1 #ifndef CYGONCE_VAR_CACHE_H
2 #define CYGONCE_VAR_CACHE_H
4 //=============================================================================
8 // HAL variant cache control API
10 //=============================================================================
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43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
49 // Purpose: Cache control API
50 // Description: The macros defined here provide the HAL APIs for handling
51 // cache control operations.
53 // #include <cyg/hal/hal_cache.h>
57 //####DESCRIPTIONEND####
59 //=============================================================================
61 #include <pkgconf/system.h>
62 #include <pkgconf/hal.h>
63 #include <cyg/infra/cyg_type.h>
64 #include <cyg/hal/hal_io.h> // HAL_READ/WRITE macros
66 #include <cyg/hal/plf_cache.h> // Platform cache definitions
68 #include CYGBLD_HAL_CPU_MODULES_H // cache module specs
70 #include <cyg/hal/sh_regs.h> // CYGARC_REG_ definitions
72 //-----------------------------------------------------------------------------
73 // Cache dimensions - one unified cache
75 #define HAL_CACHE_UNIFIED
77 #define HAL_UCACHE_SIZE CYGARC_SH_MOD_CAC_SIZE
78 #define HAL_UCACHE_LINE_SIZE CYGARC_SH_MOD_CAC_LINE_SIZE
79 #define HAL_UCACHE_WAYS CYGARC_SH_MOD_CAC_WAYS
81 // Cache addressing information
82 #define CYGARC_REG_CACHE_ADDRESS_BASE CYGARC_SH_MOD_CAC_ADDRESS_BASE
83 #define CYGARC_REG_CACHE_ADDRESS_TOP CYGARC_SH_MOD_CAC_ADDRESS_TOP
84 #define CYGARC_REG_CACHE_ADDRESS_STEP CYGARC_SH_MOD_CAC_ADDRESS_STEP
86 // Writing this to a cache address entry forces a flush of the line if
88 #define CYGARC_REG_CACHE_ADDRESS_FLUSH CYGARC_SH_MOD_CAC_ADDRESS_FLUSH
90 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
92 //-----------------------------------------------------------------------------
93 // Global control of cache
95 // This is all handled in assembly (see variant.S) due to a requirement about
96 // not fiddling the cache from cachable memory.
98 externC void cyg_hal_cache_enable(void);
99 externC void cyg_hal_cache_disable(void);
100 externC void cyg_hal_cache_invalidate_all(void);
101 externC void cyg_hal_cache_sync(void);
102 externC void cyg_hal_cache_sync_region(cyg_haladdress base,
103 cyg_haladdrword len);
104 externC void cyg_hal_cache_write_mode(int mode);
107 #define HAL_UCACHE_ENABLE() cyg_hal_cache_enable()
110 #define HAL_UCACHE_DISABLE() cyg_hal_cache_disable()
112 // Invalidate the entire cache
113 #define HAL_UCACHE_INVALIDATE_ALL() cyg_hal_cache_invalidate_all()
115 // Synchronize the contents of the cache with memory.
116 #define HAL_UCACHE_SYNC() cyg_hal_cache_sync()
118 // Query the state of the cache (does not affect the caching)
119 #define HAL_UCACHE_IS_ENABLED(_state_) \
122 HAL_READ_UINT32(CYGARC_REG_CCR, _tmp); \
123 (_state_) = (_tmp & CYGARC_REG_CCR_CE) ? 1 : 0; \
126 // Set the cache refill burst size
127 //#define HAL_UCACHE_BURST_SIZE(_size_)
129 // Set the cache write mode
130 #define HAL_UCACHE_WRITE_MODE( _mode_ ) \
133 if (HAL_UCACHE_WRITETHRU_MODE == _mode_) \
134 _m_ = CYGARC_REG_CCR_WT; \
136 _m_ = CYGARC_REG_CCR_CB; \
137 cyg_hal_cache_write_mode(_m_); \
140 #define HAL_UCACHE_WRITETHRU_MODE 0
141 #define HAL_UCACHE_WRITEBACK_MODE 1
143 // This macro allows the client to specify separate modes for the two
145 #define HAL_UCACHE_WRITE_MODE_SH( _mode_ ) cyg_hal_cache_write_mode(_mode_)
147 // Load the contents of the given address range into the cache
148 // and then lock the cache so that it stays there.
149 //#define HAL_UCACHE_LOCK(_base_, _size_)
151 // Undo a previous lock operation
152 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
154 // Unlock entire cache
155 //#define HAL_UCACHE_UNLOCK_ALL()
157 //-----------------------------------------------------------------------------
158 // Cache line control
160 // Allocate cache lines for the given address range without reading its
161 // contents from memory.
162 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
164 // Write dirty cache lines to memory and invalidate the cache entries
165 // for the given address range.
166 #define HAL_UCACHE_FLUSH( _base_ , _size_ ) \
167 cyg_hal_cache_sync_region((cyg_haladdress) _base_, (cyg_haladdrword)_size_)
169 // Invalidate cache lines in the given range without writing to memory.
170 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
172 // Write dirty cache lines to memory for the given address range.
173 //#define HAL_UCACHE_STORE( _base_ , _size_ )
176 // Preread the given range into the cache with the intention of reading
178 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
180 // Preread the given range into the cache with the intention of writing
182 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
184 // Allocate and zero the cache lines associated with the given range.
185 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
188 //-----------------------------------------------------------------------------
189 // Data and instruction cache macros map onto the both-cache macros
191 //-----------------------------------------------------------------------------
192 // Global control of data cache
194 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
195 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
196 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
197 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
199 // Enable the data cache
200 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
202 // Disable the data cache
203 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
205 // Invalidate the entire cache
206 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
208 // Synchronize the contents of the cache with memory.
209 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
211 // Query the state of the data cache
212 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
214 // Set the data cache refill burst size
215 //#define HAL_DCACHE_BURST_SIZE(_size_)
217 // Set the data cache write mode
218 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
220 //#define HAL_DCACHE_WRITETHRU_MODE 0
221 //#define HAL_DCACHE_WRITEBACK_MODE 1
223 // Load the contents of the given address range into the data cache
224 // and then lock the cache so that it stays there.
225 //#define HAL_DCACHE_LOCK(_base_, _size_)
227 // Undo a previous lock operation
228 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
230 // Unlock entire cache
231 //#define HAL_DCACHE_UNLOCK_ALL()
233 //-----------------------------------------------------------------------------
234 // Data cache line control
236 // Allocate cache lines for the given address range without reading its
237 // contents from memory.
238 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
240 // Write dirty cache lines to memory and invalidate the cache entries
241 // for the given address range.
242 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_, _size_ )
244 // Invalidate cache lines in the given range without writing to memory.
245 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
247 // Write dirty cache lines to memory for the given address range.
248 //#define HAL_DCACHE_STORE( _base_ , _size_ )
250 // Preread the given range into the cache with the intention of reading
252 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
254 // Preread the given range into the cache with the intention of writing
256 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
258 // Allocate and zero the cache lines associated with the given range.
259 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
261 //-----------------------------------------------------------------------------
262 // Global control of Instruction cache
264 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
265 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
266 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
267 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
269 // Enable the instruction cache
270 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
272 // Disable the instruction cache
273 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
275 // Invalidate the entire cache
276 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
279 // Synchronize the contents of the cache with memory.
280 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
282 // Query the state of the instruction cache
283 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
285 // Set the instruction cache refill burst size
286 //#define HAL_ICACHE_BURST_SIZE(_size_)
288 // Load the contents of the given address range into the instruction cache
289 // and then lock the cache so that it stays there.
291 //#define HAL_ICACHE_LOCK(_base_, _size_)
293 // Undo a previous lock operation
294 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
296 // Unlock entire cache
297 //#define HAL_ICACHE_UNLOCK_ALL()
299 //-----------------------------------------------------------------------------
300 // Instruction cache line control
302 // Invalidate cache lines in the given range without writing to memory.
303 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
305 //-----------------------------------------------------------------------------
306 #endif // ifndef CYGONCE_VAR_CACHE_H
307 // End of var_cache.h