1 //=============================================================================
5 // PFC (pin function controller) Module register definitions
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 // or inline functions from this file, or you compile this file and link it
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30 // License. However the source code for this file must still be made available
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
47 //####DESCRIPTIONEND####
49 //=============================================================================
51 #define CYGARC_REG_PACR 0xa4000100 // port A control
52 #define CYGARC_REG_PBCR 0xa4000102 // port B control
53 #define CYGARC_REG_PCCR 0xa4000104 // port C control
54 #define CYGARC_REG_PDCR 0xa4000106 // port D control
55 #define CYGARC_REG_PECR 0xa4000108 // port E control
56 #define CYGARC_REG_PFCR 0xa400010a // port F control
57 #define CYGARC_REG_PGCR 0xa400010c // port G control
58 #define CYGARC_REG_PHCR 0xa400010e // port H control
59 #define CYGARC_REG_PJCR 0xa4000110 // port J control
60 #define CYGARC_REG_PKCR 0xa4000112 // port K control
61 #define CYGARC_REG_PLCR 0xa4000114 // port L control
62 #define CYGARC_REG_SCPCR 0xa4000116 // SC port control
64 #define CYGARC_REG_PADR 0xa4000120 // port A data
65 #define CYGARC_REG_PBDR 0xa4000122 // port B data
66 #define CYGARC_REG_PCDR 0xa4000124 // port C data
67 #define CYGARC_REG_PDDR 0xa4000126 // port D data
68 #define CYGARC_REG_PEDR 0xa4000128 // port E data
69 #define CYGARC_REG_PFDR 0xa400012a // port F data
70 #define CYGARC_REG_PGDR 0xa400012c // port G data
71 #define CYGARC_REG_PHDR 0xa400012e // port H data
72 #define CYGARC_REG_PJDR 0xa4000130 // port J data
73 #define CYGARC_REG_PKDR 0xa4000132 // port K data
74 #define CYGARC_REG_PLDR 0xa4000134 // port L data
75 #define CYGARC_REG_SCPDR 0xa4000136 // SC port data
79 #define CYGARC_REG_PCCR_PC7_MASK 0xc000
80 #define CYGARC_REG_PCCR_PC7_shift 14
81 #define CYGARC_REG_PCCR_PC6_MASK 0x3000
82 #define CYGARC_REG_PCCR_PC6_shift 12
83 #define CYGARC_REG_PCCR_PC5_MASK 0x0c00
84 #define CYGARC_REG_PCCR_PC5_shift 10
85 #define CYGARC_REG_PCCR_PC4_MASK 0x0300
86 #define CYGARC_REG_PCCR_PC4_shift 8
87 #define CYGARC_REG_PCCR_PC3_MASK 0x00c0
88 #define CYGARC_REG_PCCR_PC3_shift 6
89 #define CYGARC_REG_PCCR_PC2_MASK 0x0030
90 #define CYGARC_REG_PCCR_PC2_shift 4
91 #define CYGARC_REG_PCCR_PC1_MASK 0x000c
92 #define CYGARC_REG_PCCR_PC1_shift 2
93 #define CYGARC_REG_PCCR_PC0_MASK 0x0003
94 #define CYGARC_REG_PCCR_PC0_shift 0
96 #define CYGARC_REG_PCCR_MD_OTHER 0x0
97 #define CYGARC_REG_PCCR_MD_OUT 0x1
98 #define CYGARC_REG_PCCR_MD_IN_ON 0x2
99 #define CYGARC_REG_PCCR_MD_IN_OFF 0x3
101 #define CYGARC_REG_PCDR_PC7DT 0x80
102 #define CYGARC_REG_PCDR_PC6DT 0x40
103 #define CYGARC_REG_PCDR_PC5DT 0x20
104 #define CYGARC_REG_PCDR_PC4DT 0x10
105 #define CYGARC_REG_PCDR_PC3DT 0x08
106 #define CYGARC_REG_PCDR_PC2DT 0x04
107 #define CYGARC_REG_PCDR_PC1DT 0x02
108 #define CYGARC_REG_PCDR_PC0DT 0x01