1 ##==========================================================================
5 ## SH4 variant assembly code
7 ##==========================================================================
8 #####ECOSGPLCOPYRIGHTBEGIN####
9 ## -------------------------------------------
10 ## This file is part of eCos, the Embedded Configurable Operating System.
11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 ## eCos is free software; you can redistribute it and/or modify it under
14 ## the terms of the GNU General Public License as published by the Free
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17 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 ## You should have received a copy of the GNU General Public License along
23 ## with eCos; if not, write to the Free Software Foundation, Inc.,
24 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 ## As a special exception, if other files instantiate templates or use macros
27 ## or inline functions from this file, or you compile this file and link it
28 ## with other works to produce a work based on this file, this file does not
29 ## by itself cause the resulting work to be covered by the GNU General Public
30 ## License. However the source code for this file must still be made available
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37 ## at http://sources.redhat.com/ecos/ecos-license/
38 ## -------------------------------------------
39 #####ECOSGPLCOPYRIGHTEND####
40 ##==========================================================================
41 #######DESCRIPTIONBEGIN####
44 ## Contributors: jskov
46 ## Purpose: SH4 misc assembly code
47 ######DESCRIPTIONEND####
49 ##==========================================================================
51 #include <pkgconf/hal.h>
52 #include <pkgconf/hal_sh.h>
54 #include <cyg/hal/sh_regs.h>
55 #include <cyg/hal/sh4_offsets.inc>
57 #include <cyg/hal/arch.inc>
58 #include <cyg/hal/hal_intr.h>
60 #---------------------------------------------------------------------------
62 # These need to be written in assembly to ensure they do not rely on data
63 # in cachable space (i.e., code must use registers exclusively, not the stack).
65 # This macro must be used at the top of each cache function. It ensures
66 # that the code gets executed from a shadow region where caching is disabled
68 .macro GOTO_NONCACHED_SHADOW
80 .macro RETURN_FROM_NONCACHED_SHADOW
81 nop ! Wait for 8 instructions
82 nop ! before jumping to a non-P2
93 FUNC_START(cyg_hal_dcache_enable)
95 mov.l $nCYGARC_REG_CCR,r1
97 mov #CYGARC_REG_CCR_OCE,r2
100 RETURN_FROM_NONCACHED_SHADOW
102 FUNC_START(cyg_hal_dcache_disable)
103 GOTO_NONCACHED_SHADOW
104 mov.l $nCYGARC_REG_CCR,r1
106 mov #CYGARC_REG_CCR_OCE,r2
110 RETURN_FROM_NONCACHED_SHADOW
112 FUNC_START(cyg_hal_dcache_invalidate_all)
113 GOTO_NONCACHED_SHADOW
114 mov.l $nCYGARC_REG_CCR,r1
116 mov #CYGARC_REG_CCR_OCI,r2
119 RETURN_FROM_NONCACHED_SHADOW
121 FUNC_START(cyg_hal_dcache_sync)
122 GOTO_NONCACHED_SHADOW
123 mov.l $CYGARC_REG_DCACHE_ADDRESS_FLUSH,r0
124 mov.l $CYGARC_REG_DCACHE_ADDRESS_BASE,r1
125 mov.l $CYGARC_REG_DCACHE_ADDRESS_TOP,r2
126 mov.l $CYGARC_REG_DCACHE_ADDRESS_STEP,r3
131 add r3,r1 ! delay slot!
133 RETURN_FROM_NONCACHED_SHADOW
136 $CYGARC_REG_DCACHE_ADDRESS_FLUSH:
137 .long CYGARC_REG_DCACHE_ADDRESS_FLUSH
138 $CYGARC_REG_DCACHE_ADDRESS_BASE:
139 .long CYGARC_REG_DCACHE_ADDRESS_BASE
140 $CYGARC_REG_DCACHE_ADDRESS_TOP:
141 .long CYGARC_REG_DCACHE_ADDRESS_TOP
142 $CYGARC_REG_DCACHE_ADDRESS_STEP:
143 .long CYGARC_REG_DCACHE_ADDRESS_STEP
148 FUNC_START(cyg_hal_dcache_sync_region)
149 GOTO_NONCACHED_SHADOW
150 1: ocbp @r4 ! operand cache block purge
151 add #CYGARC_SH_MOD_DCAC_ADDRESS_STEP,r4
152 add #-CYGARC_SH_MOD_DCAC_ADDRESS_STEP,r5
155 RETURN_FROM_NONCACHED_SHADOW
157 FUNC_START(cyg_hal_dcache_write_mode)
158 GOTO_NONCACHED_SHADOW
159 # Mode argument in r4.
160 # Read current state and mask out the two caching mode bits
161 mov.l $nCYGARC_REG_CCR,r1
163 mov #CYGARC_REG_CCR_CB|CYGARC_REG_CCR_WT,r2
167 # Or in the new settings and restore to CCR
170 RETURN_FROM_NONCACHED_SHADOW
172 FUNC_START(cyg_hal_icache_enable)
173 GOTO_NONCACHED_SHADOW
174 mov.l $nCYGARC_REG_CCR,r1
176 mov.l $nCYGARC_REG_CCR_ICE,r2
179 RETURN_FROM_NONCACHED_SHADOW
181 FUNC_START(cyg_hal_icache_disable)
182 GOTO_NONCACHED_SHADOW
183 mov.l $nCYGARC_REG_CCR,r1
185 mov.l $nCYGARC_REG_CCR_ICE,r2
189 RETURN_FROM_NONCACHED_SHADOW
191 FUNC_START(cyg_hal_icache_invalidate_all)
192 GOTO_NONCACHED_SHADOW
193 mov.l $nCYGARC_REG_CCR,r1
195 mov.l $nCYGARC_REG_CCR_ICI,r2
198 RETURN_FROM_NONCACHED_SHADOW
202 .long 0x1fffffff ! mask off top 3 bits
204 .long 0xa0000000 ! base of non-cachable memory
207 $nCYGARC_REG_CCR_ICE:
208 .long CYGARC_REG_CCR_ICE
209 $nCYGARC_REG_CCR_ICI:
210 .long CYGARC_REG_CCR_ICI
215 SYM_DEF(cyg_hal_ILVL_table)
216 # The first entries in the table have static priorities.
219 .byte 0xf // Reserved
235 .byte 0xf // Reserved
237 # The rest of the table consists of programmable levels, maintained
238 # by the HAL_INTERRUPT_SET_LEVEL macro.
239 # These default to the highest level so that a spurious
240 # interrupt cause the IPL to be suddenly lowered to allow all
241 # interrupts. This should give a better chance at tracking down
243 .rept (CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_INTERRUPT_RESERVED_3E0)
247 # All interrupts are masked initally. Set to 1 to enable.
248 SYM_DEF(cyg_hal_IMASK_table)
249 .rept (CYGNUM_HAL_ISR_MAX)