1 #ifndef CYGONCE_HAL_PLF_INTR_H
2 #define CYGONCE_HAL_PLF_INTR_H
4 //==========================================================================
8 // Platform specific Interrupt and clock support
10 //==========================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // Copyright (C) 2003 Nick Garnett
17 // eCos is free software; you can redistribute it and/or modify it under
18 // the terms of the GNU General Public License as published by the Free
19 // Software Foundation; either version 2 or (at your option) any later version.
21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 // You should have received a copy of the GNU General Public License along
27 // with eCos; if not, write to the Free Software Foundation, Inc.,
28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
35 // in accordance with section (3) of the GNU General Public License.
37 // This exception does not invalidate any other reasons why a work based on
38 // this file might be covered by the GNU General Public License.
40 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
41 // at http://sources.redhat.com/ecos/ecos-license/
42 // -------------------------------------------
43 //####ECOSGPLCOPYRIGHTEND####
44 //==========================================================================
45 //#####DESCRIPTIONBEGIN####
48 // Contributors: nickg
50 // Purpose: Define Interrupt support
51 // Description: The macros defined here provide the HAL APIs for handling
52 // interrupts and the clock for the SuperH SH4-202 MicroDev
55 // #include <cyg/hal/plf_intr.h>
59 //####DESCRIPTIONEND####
61 //==========================================================================
63 #include <pkgconf/hal.h>
65 //----------------------------------------------------------------------------
66 // External interrupts.
68 #define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_LVL3
70 //----------------------------------------------------------------------------
71 // FPGA Interrupt controller
74 #define FPGA_INTC_BASE 0xA6110000ul /* INTC base address on CPU-board FPGA */
75 #define FPGA_INTENB_REG (FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
76 #define FPGA_INTDSB_REG (FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
77 #define FPGA_INTENB_MASK(n) (1ul<<(n)) /* Interupt mask to enable Ethernet on INTC in CPU-board FPGA */
78 #define FPGA_INTPRI_REG(n) (FPGA_INTC_BASE+0x10+((n)/8)*8) /* Interrupt Priority Register on INTC on CPU-board FPGA */
79 #define FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* FPGA_INTPRI_LEVEL(int_number, int_level) */
80 #define FPGA_INTPRI_MASK(n) (FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
82 #define FPGA_ETHERNET_INT (18) /* Interrupt number for Ethernet in INTC on CPU-board FPGA */
83 #define ETHERNET_INT_PRIORITY (0xc) /* Interrupt Priority of Ethenet IRQ */
85 //----------------------------------------------------------------------------
86 // Interrupt configuration extension macros
88 #define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level) \
89 case CYGNUM_HAL_INTERRUPT_ETH: \
91 volatile cyg_uint32* const intEnableReg = (cyg_uint32*)FPGA_INTENB_REG; \
92 volatile cyg_uint32* const intDisableReg = (cyg_uint32*)FPGA_INTDSB_REG; \
95 *intEnableReg |= FPGA_INTENB_MASK(FPGA_ETHERNET_INT); \
97 *intDisableReg |= FPGA_INTENB_MASK(FPGA_ETHERNET_INT); \
100 case CYGNUM_HAL_INTERRUPT_NMI: \
102 case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL2: \
104 case CYGNUM_HAL_INTERRUPT_LVL4 ... CYGNUM_HAL_INTERRUPT_LVL14: \
105 /* Cannot change levels */ \
108 //----------------------------------------------------------------------------
110 // Block interrupts and cause an exception. This forces a reset.
112 #define HAL_PLATFORM_RESET() \
113 asm volatile ("ldc %0,sr;trapa #0x00;" : : "r" (CYGARC_REG_SR_BL))
115 #define HAL_PLATFORM_RESET_ENTRY 0x80000000
117 //--------------------------------------------------------------------------
118 #endif // ifndef CYGONCE_HAL_PLF_INTR_H