1 //=============================================================================
5 // SPARClite Architecture sim-specific private variables
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
46 // Purpose: private vars for SPARClite sim.
48 //####DESCRIPTIONEND####
50 //=============================================================================
53 #include <pkgconf/system.h>
54 #include <pkgconf/hal.h>
55 #include <pkgconf/hal_sparclite.h>
56 #include <pkgconf/hal_sparclite_sleb.h>
58 #include <cyg/infra/cyg_type.h>
59 #include <cyg/hal/hal_intr.h>
60 #include <cyg/hal/hal_arch.h>
63 #include <pkgconf/kernel.h> // CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
66 #include <cyg/hal/hal_clock.h>
68 // ------------------------------------------------------------------------
69 // Clock static to keep period recorded.
70 cyg_int32 cyg_hal_sparclite_clock_period = 0;
72 /* Address of clock switch */
73 #define CLKSW_ADDR 0x01000003
75 #define HAL_SPARC_86940_TIMER1_CONTROL_INIT ( \
77 HAL_SPARC_86940_TCR_CLKPRS | \
78 HAL_SPARC_86940_TCR_OUTLOW )
79 // Disable, CLKSEL=prescale(2), periodic interrupts, gate 0
80 // and lower the output: OUTCTL = 2
82 #define HAL_SPARC_86940_TIMER1_CONTROL_ENABLE ( \
83 HAL_SPARC_86940_TCR_CE | \
84 HAL_SPARC_86940_TCR_CLKPRS | \
85 HAL_SPARC_86940_TCR_OUTSAME )
86 // Enable + .... and no change to the output: OUTCTL = 0
88 void hal_clock_initialize( cyg_uint32 p )
92 HAL_DISABLE_INTERRUPTS( ints );
94 HAL_SPARC_86940_TIMER1_CONTROL_WRITE(
95 HAL_SPARC_86940_TIMER1_CONTROL_INIT ); // Make sure it's disabled
97 // Clear any pending interrupts:
98 HAL_INTERRUPT_ACKNOWLEDGE( CYGNUM_HAL_INTERRUPT_RTC );
100 clk = *(unsigned char *)CLKSW_ADDR;
104 /* could be 10 - 62 MHz */
105 clk = (clk & 0x3f); /* in MHz */
106 // BUT the 86940 is internally clocked at half that speed (page 20 RHS)
108 // so the clock is now the number of system ticks we want per counter
110 HAL_SPARC_86940_TIMER1_PRESCALER_WRITE(
111 0 /* internal clock */ |
112 HAL_SPARC_86940_PRS_ODIV1 |
114 // should give 1MHz on the externally visible counter...
115 HAL_SPARC_86940_TIMER1_CONTROL_WRITE(
116 HAL_SPARC_86940_TIMER1_CONTROL_INIT );
117 HAL_SPARC_86940_TIMER1_RELOAD_WRITE( p );
118 HAL_SPARC_86940_TIMER1_CONTROL_WRITE(
119 HAL_SPARC_86940_TIMER1_CONTROL_ENABLE );
120 HAL_SPARC_86940_TIMER1_RELOAD_WRITE( p );
121 cyg_hal_sparclite_clock_period = p;
122 HAL_RESTORE_INTERRUPTS( ints );
125 // ------------------------------------------------------------------------
127 #ifdef CYG_HAL_USE_ROM_MONITOR_CYGMON
128 #include <cyg/hal/hal_cygm.h> // CygMon vector table & layout
130 static struct { int eCosV, CygMonV; } setup[] = {
131 { CYGNUM_HAL_VECTOR_OTHERS , BSP_EXC_TRAP },
132 { CYGNUM_HAL_VECTOR_FETCH_ABORT , BSP_EXC_IACCESS },
133 { CYGNUM_HAL_VECTOR_ILLEGAL_OP , BSP_EXC_ILL },
134 { CYGNUM_HAL_VECTOR_PRIV_OP , BSP_EXC_IPRIV },
135 { CYGNUM_HAL_VECTOR_UNALIGNED , BSP_EXC_ALIGN },
136 { CYGNUM_HAL_VECTOR_DATA_ABORT , BSP_EXC_DACCESS },
139 #endif // CYG_HAL_USE_ROM_MONITOR_CYGMON
141 // ------------------------------------------------------------------------
142 // Board specific startups.
144 extern void hal_board_prestart( void );
145 extern void hal_board_poststart( void );
147 #define SLEB_LED (*(volatile char *)(0x02000003))
149 #define LED( _x_ ) SLEB_LED = (char)(0xff & ~(_x_))
151 void hal_board_prestart( void )
156 // Disable default clocks &c
157 HAL_SPARC_86940_TIMER1_PRESCALER_WRITE( 1 ); // as if at reset
158 HAL_SPARC_86940_TIMER1_CONTROL_WRITE( 0 ); // as if at reset
160 #ifdef CYG_HAL_USE_ROM_MONITOR_CYGMON
161 // then initialize our vectors to point to (or bounce to)
162 // CygMon's equivalent functionality.
164 extern void hal_user_trap_to_cygmon_vsr( void );
165 extern void hal_nofpcp_trap_to_cygmon_vsr( void );
166 extern void hal_nmi_handler( void );
169 HAL_VSR_SET( CYGNUM_HAL_VECTOR_USER_TRAP,
170 (CYG_ADDRESS)hal_user_trap_to_cygmon_vsr, NULL );
172 HAL_VSR_SET( CYGNUM_HAL_VECTOR_NOFPCP,
173 (CYG_ADDRESS)hal_nofpcp_trap_to_cygmon_vsr, NULL );
175 for ( i = 0; i < sizeof(setup)/sizeof(setup[0]); i++ )
176 HAL_VSR_SET( setup[i].eCosV,
177 CYGMON_VECTOR_TABLE[ setup[i].CygMonV ], NULL );
179 // Just point this one straight though, and unmask it.
180 // That way CygMon looks after ^Cs itself.
181 HAL_VSR_SET( CYGNUM_HAL_VECTOR_INTERRUPT_10,
182 CYGMON_VECTOR_TABLE[ BSP_EXC_INT10 ], NULL );
183 HAL_INTERRUPT_UNMASK( CYGNUM_HAL_VECTOR_INTERRUPT_10 );
185 // Just point this one straight though, and unmask it.
186 // That way CygMon looks after the Ethernet itself.
187 HAL_VSR_SET( CYGNUM_HAL_VECTOR_INTERRUPT_14,
188 CYGMON_VECTOR_TABLE[ BSP_EXC_INT14 ], NULL );
189 HAL_INTERRUPT_UNMASK( CYGNUM_HAL_VECTOR_INTERRUPT_14 );
191 // Install handler for the NMI button on the board
192 HAL_VSR_SET( CYGNUM_HAL_VECTOR_INTERRUPT_15,
193 (CYG_ADDRESS)hal_nmi_handler, NULL );
194 HAL_INTERRUPT_UNMASK( CYGNUM_HAL_VECTOR_INTERRUPT_15 );
198 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
200 extern void patch_dbg_syscalls(void * vector);
201 patch_dbg_syscalls( (void *)CYGMON_VECTOR_TABLE );
203 #endif // CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
206 #endif // CYG_HAL_USE_ROM_MONITOR_CYGMON
211 void hal_board_poststart( void )
214 HAL_ENABLE_INTERRUPTS();