packages/hal/synth/arch/v2_0/include/hal_intr.h

   1 #ifndef CYGONCE_HAL_HAL_INTR_H
   2 #define CYGONCE_HAL_HAL_INTR_H
   3
   4 //==========================================================================
   5 //
   6 //      hal_intr.h
   7 //
   8 //      HAL Interrupt and clock support
   9 //
  10 //==========================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
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  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
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  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
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  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //==========================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):    proven
  47 // Contributors: proven, jskov, pjo, nickg, bartv
  48 // Date:         1999-02-20
  49 // Purpose:      Define Interrupt support
  50 // Description:  The macros defined here provide the HAL APIs for handling
  51 //               interrupts and the clock.
  52 //
  53 // Usage:
  54 //               #include <cyg/hal/hal_intr.h>
  55 //               ...
  56 //
  57 //####DESCRIPTIONEND####
  58 //
  59 //==========================================================================
  60
  61 // Interrupt and exception handling in the synthetic target is very much
  62 // tied up with POSIX signal handling.
  63 //
  64 // There are two interrupt sources to consider. The system clock is
  65 // provided most conveniently by a timer signal SIGALRM. All other
  66 // interrupts are handled by communication with the auxiliary program
  67 // and involve SIGIO. The model that is actually presented to
  68 // higher-level code is a single VSR, and 32 ISRs. ISR 0 is
  69 // arbitrarily assigned to the clock. The remaining 31 ISRs correspond
  70 // to devices managed through the auxiliary, effectively providing an
  71 // interrupt controller. A single VSR suffices because it is passed
  72 // the signal number as argument.
  73 //
  74 // Exceptions also correspond to signals, but are not handled through
  75 // the same VSR: slightly different processing is needed for
  76 // interrupts vs. exceptions, for example the latter does not involve
  77 // calling interrupt_end(). The exceptions of interest are SIGILL,
  78 // SIGBUS, SIGFPE, and SIGSEGV. SIGBUS and SIGSEGV are treated as a
  79 // single exception. Obviously there are other signals but they do not
  80 // have obvious meanings in the context of the synthetic target. NOTE:
  81 // SIGSTKFLT may be needed as well at some point.
  82
  83 #define CYGNUM_HAL_INTERRUPT_RTC        0
  84 #define CYGNUM_HAL_ISR_MIN              0
  85 #define CYGNUM_HAL_ISR_MAX              31
  86 #define CYGNUM_HAL_ISR_COUNT            (CYGNUM_HAL_ISR_MAX + 1)
  87
  88 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION        0
  89 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS                1
  90 #define CYGNUM_HAL_EXCEPTION_FPU                        2
  91
  92 #define CYGNUM_HAL_EXCEPTION_MIN        0
  93 #define CYGNUM_HAL_EXCEPTION_MAX        CYGNUM_HAL_EXCEPTION_FPU
  94 #define CYGNUM_HAL_EXCEPTION_COUNT      (CYGNUM_HAL_EXCEPTION_MAX + 1)
  95
  96 #define CYGNUM_HAL_VECTOR_SIGNAL        0
  97 #define CYGNUM_HAL_VSR_MIN              0
  98 #define CYGNUM_HAL_VSR_MAX              CYGNUM_HAL_VECTOR_SIGNAL
  99 #define CYGNUM_HAL_VSR_COUNT            (CYGNUM_HAL_VSR_MAX + 1)
 100
 101 // These #include's cannot happen until after the above are defined.
 102 // There are dependencies on e.g. CYGNUM_HAL_EXCEPTION_COUNT.
 103 // Basic data types
 104 #include <cyg/infra/cyg_type.h>
 105
 106 // cyg_vector_t etc., supplied either by the kernel or the common HAL
 107 #include <cyg/hal/drv_api.h>
 108
 109 // Nearly all interrupt state control happens via functions. This
 110 // facilitates debugging, for example it is easier to set breakpoints
 111 // that way, at the cost of performance. However performance is not a
 112 // critical issue for the synthetic target, Instead it is intended to
 113 // facilitate application development, and hence debugability has a
 114 // higher priority. There is one exception: the sequence
 115 // disable_interrupts() followed by restore_interrupts() occurs
 116 // frequently and is worth some inlining.
 117 //
 118 // Note: some of the details such as the existence of a global
 119 // variable hal_interrupts_enabled are known to the context switch
 120 // code in the variant HAL.
 121 typedef cyg_bool_t          CYG_INTERRUPT_STATE;
 122 externC volatile cyg_bool_t hal_interrupts_enabled;
 123 externC void                hal_enable_interrupts(void);
 124 externC cyg_bool_t          hal_interrupt_in_use(cyg_vector_t);
 125 externC void                hal_interrupt_attach(cyg_vector_t, cyg_ISR_t*, CYG_ADDRWORD, CYG_ADDRESS);
 126 externC void                hal_interrupt_detach(cyg_vector_t, cyg_ISR_t*);
 127 externC void                (*hal_vsr_get(cyg_vector_t))(void);
 128 externC void                hal_vsr_set(cyg_vector_t, void (*)(void), void (**)(void));
 129 externC void                hal_interrupt_mask(cyg_vector_t);
 130 externC void                hal_interrupt_unmask(cyg_vector_t);
 131 externC void                hal_interrupt_acknowledge(cyg_vector_t);
 132 externC void                hal_interrupt_configure(cyg_vector_t, cyg_bool_t, cyg_bool_t);
 133 externC void                hal_interrupt_set_level(cyg_vector_t, cyg_priority_t);
 134
 135
 136 #define HAL_ENABLE_INTERRUPTS()                 \
 137     CYG_MACRO_START                             \
 138     hal_enable_interrupts();                    \
 139     CYG_MACRO_END
 140
 141 #define HAL_DISABLE_INTERRUPTS(_old_)           \
 142     CYG_MACRO_START                             \
 143     _old_ = hal_interrupts_enabled;             \
 144     hal_interrupts_enabled = false;             \
 145     CYG_MACRO_END
 146
 147 #define HAL_RESTORE_INTERRUPTS(_old_)           \
 148     CYG_MACRO_START                             \
 149     if (!_old_) {                               \
 150         hal_interrupts_enabled = false;         \
 151     } else if (!hal_interrupts_enabled) {       \
 152         hal_enable_interrupts();                \
 153     }                                           \
 154     CYG_MACRO_END
 155
 156 #define HAL_QUERY_INTERRUPTS(_old_)             \
 157     CYG_MACRO_START                             \
 158     _old_ = hal_interrupts_enabled;             \
 159     CYG_MACRO_END
 160
 161 #define HAL_TRANSLATE_VECTOR(_vector_, _index_) \
 162     CYG_MACRO_START                             \
 163     (_index_) = (_vector_);                     \
 164     CYG_MACRO_END
 165
 166 #define HAL_INTERRUPT_IN_USE(_vector_, _state_)                         \
 167     CYG_MACRO_START                                                     \
 168     (_state_) = hal_interrupt_in_use(_vector_);                         \
 169     CYG_MACRO_END
 170
 171 #define HAL_INTERRUPT_ATTACH(_vector_, _isr_, _data_, _object_ )        \
 172     CYG_MACRO_START                                                     \
 173     hal_interrupt_attach(_vector_, _isr_, (CYG_ADDRWORD) _data_, (CYG_ADDRESS) _object_); \
 174     CYG_MACRO_END
 175
 176 #define HAL_INTERRUPT_DETACH(_vector_, _isr_)                           \
 177     CYG_MACRO_START                                                     \
 178     hal_interrupt_detach(_vector_, _isr_);                              \
 179     CYG_MACRO_END
 180
 181 #define HAL_VSR_GET(_vector_, _vsr_)                                    \
 182     CYG_MACRO_START                                                     \
 183     (*_vsr_) = hal_vsr_get(_vector_);                                   \
 184     CYG_MACRO_END
 185
 186 #define HAL_VSR_SET(_vector_, _vsr_, _poldvsr_)                         \
 187     CYG_MACRO_START                                                     \
 188     hal_vsr_set(_vector_, _vsr_, _poldvsr_);                            \
 189     CYG_MACRO_END
 190
 191 #define HAL_INTERRUPT_MASK(_vector_)            \
 192     CYG_MACRO_START                             \
 193     hal_interrupt_mask(_vector_);               \
 194     CYG_MACRO_END
 195
 196 #define HAL_INTERRUPT_UNMASK(_vector_)          \
 197     CYG_MACRO_START                             \
 198     hal_interrupt_unmask(_vector_);             \
 199     CYG_MACRO_END
 200
 201 #define HAL_INTERRUPT_ACKNOWLEDGE(_vector_)     \
 202     CYG_MACRO_START                             \
 203     hal_interrupt_acknowledge(_vector_);        \
 204     CYG_MACRO_END
 205
 206 #define HAL_INTERRUPT_CONFIGURE(_vector_, _level_, _up_)        \
 207     CYG_MACRO_START                                             \
 208     hal_interrupt_configure(_vector_, _level_, _up_);           \
 209     CYG_MACRO_END
 210
 211 #define HAL_INTERRUPT_SET_LEVEL(_vector_, _level_)              \
 212     CYG_MACRO_START                                             \
 213     hal_interrupt_set_level(_vector_, _level_);                 \
 214     CYG_MACRO_END
 215
 216 // Additional data exported by the synthetic target interrupt handling
 217 // subsystem. These two variables correspond to typical interrupt
 218 // status and mask registers.
 219 extern volatile cyg_uint32   synth_pending_isrs;
 220 extern volatile cyg_uint32   synth_masked_isrs;
 221
 222 // ----------------------------------------------------------------------------
 223 // The clock support
 224 externC void            hal_clock_initialize(cyg_uint32);
 225 externC cyg_uint32      hal_clock_read(void);
 226
 227 #define HAL_CLOCK_INITIALIZE( _period_ )                        \
 228     CYG_MACRO_START                                             \
 229     hal_clock_initialize(_period_);                             \
 230     CYG_MACRO_END
 231
 232 // No special action is needed for reset.
 233 #define HAL_CLOCK_RESET( _vector_, _period_ )                   \
 234     CYG_EMPTY_STATEMENT
 235
 236 #define HAL_CLOCK_READ(_pvalue_)                                \
 237     CYG_MACRO_START                                             \
 238     *(_pvalue_) = hal_clock_read();                             \
 239     CYG_MACRO_END
 240
 241 // ----------------------------------------------------------------------------
 242 // HAL_DELAY_US() support. The macro is provided by the processor-specific
 243 // HAL, but the bogomips rating is provided by the architectural code.
 244 extern int hal_bogomips;
 245 #include <cyg/hal/var_intr.h>
 246
 247 // ----------------------------------------------------------------------------
 248 // Resetting the Synth target is not possible, but existing the process is.
 249 externC void            cyg_hal_sys_exit(int);
 250 #define HAL_PLATFORM_RESET()                                    \
 251     CYG_MACRO_START                                             \
 252     cyg_hal_sys_exit(0);                                        \
 253     CYG_MACRO_END
 254
 255 // ----------------------------------------------------------------------------
 256 // Test case exit support.
 257 #define CYGHWR_TEST_PROGRAM_EXIT()                              \
 258     CYG_MACRO_START                                             \
 259     cyg_hal_sys_exit(0);                                        \
 260     CYG_MACRO_END
 261 //---------------------------------------------------------------------------
 262 #endif // ifndef CYGONCE_HAL_HAL_INTR_H
 263 // End of hal_intr.h