1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 /*=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: gthomas, jlarmour
49 // Purpose: NEC CEB/V850 platform specific support routines
51 // Usage: #include <cyg/hal/hal_platform_setup.h>
53 //####DESCRIPTIONEND####
55 //===========================================================================*/
57 #include <pkgconf/system.h> // System-wide configuration info
58 #include <pkgconf/hal.h> // Architecture independent configuration
59 #include <cyg/hal/v850_common.h>
60 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
63 movhi hi(\addr),r0,\reg
64 movea lo(\addr),\reg,\reg
67 .macro PLATFORM_SETUP1
68 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
69 movhi hi(V850_REGS),r0,r6
71 // set bus control signals
73 st.b r1,lo(V850_REG_SYC)[r6]
75 // Internal RAM, internal ROM and I/O - no wait states, regardless
76 // of the setting of DWC
77 // External RAM is 70ns, External ROM is 120ns. Therefore...
78 #if CYGHWR_HAL_V85X_CPU_FREQ < 14285714
79 // External RAM - 0 wait states
81 #elif CYGHWR_HAL_V85X_CPU_FREQ < 28571428
82 // External RAM - 1 wait state
84 #elif CYGHWR_HAL_V85X_CPU_FREQ < 42857142
85 // External RAM - 2 wait states
88 // External RAM - 3 wait states
91 #if CYGHWR_HAL_V85X_CPU_FREQ < 8333333
92 // External ROM - 0 wait states
94 #elif CYGHWR_HAL_V85X_CPU_FREQ < 16666667
95 // External ROM - 1 wait states
97 #elif CYGHWR_HAL_V85X_CPU_FREQ < 25000000
98 // External ROM - 2 wait states
101 // External ROM - 3 wait states
104 st.h r1,lo(V850_REG_DWC)[r6]
106 // Internal RAM, ROM, I/O - always 0 idle regardless of the setting
108 // External RAM - 0 idle
109 // External ROM - 0 idle
111 st.h r1,lo(V850_REG_BCC)[r6]
113 // No INTs on rising edge
115 st.b r1,lo(V850_REG_EGP0)[r6]
117 // enable INTP0 (serial) IRQ only, set for falling edge
119 st.b r1,lo(V850_REG_EGN0)[r6]
121 // Port 1 mode: set serial DSR, RXD and CTS as inputs, and others
124 st.b r1,lo(V850_REG_PM1)[r6]
126 // Port 3 mode: SW2 read port: set to all input
128 st.b r1,lo(V850_REG_PM3)[r6]
130 // Set serial port control inputs (DSR, RXD, CTS) to 1
131 // FIXME Why? Also I don't get why the top two bits are set.
133 st.b r1,lo(V850_REG_P1)[r6]
135 // Enable all outputs for 7-segment LED
137 st.b r1,lo(V850_REG_PM10)[r6]
141 st.b r1,lo(V850_REG_P10)[r6]
143 // Init serial port 0 baud rate to divide clock down to 9600 baud
144 // by setting baud count here
145 // This may seem unnecessary, but setting up the serial allows
146 // us to do diag output before HAL diag is initialized. The values
147 // are clock dependent however, but this is only for debug so we
150 st.b r1,lo(V850_REG_BRGC0)[r6]
154 st.b r1,lo(V850_REG_BRGMC00)[r6]
156 // set serial 0 to enable tx/rx and 8-N-1
158 st.b r1,lo(V850_REG_ASIM0)[r6]
160 // disable reception of serial interrupts, and set serial interrupt
161 // priority to level 7 (lowest)
163 st.b r1,lo(V850_REG_STIC0)[r6]
165 // Memory expansion mode - set to 4MB
166 // We could probably set this to 256K (MM==0x4), but there seems
169 st.b r1,lo(V850_REG_MM)[r6]
171 // Setting the PCC register is tricky - it is a "specific register"
172 // We set the CPU clock to full speed
174 ori CYGARC_PSW_NP,r7,r8
177 st.b r1,lo(V850_REG_PRCMD)[r6]
178 st.b r1,lo(V850_REG_PCC)[r6]
188 /*---------------------------------------------------------------------------*/
189 /* end of hal_platform_setup.h */
190 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */