2 * Mediated virtual PCI serial host device driver
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 * Author: Neo Jia <cjia@nvidia.com>
6 * Kirti Wankhede <kwankhede@nvidia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Sample driver that creates mdev device that simulates serial port over PCI
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/kernel.h>
22 #include <linux/poll.h>
23 #include <linux/slab.h>
24 #include <linux/cdev.h>
25 #include <linux/sched.h>
26 #include <linux/wait.h>
27 #include <linux/uuid.h>
28 #include <linux/vfio.h>
29 #include <linux/iommu.h>
30 #include <linux/sysfs.h>
31 #include <linux/ctype.h>
32 #include <linux/file.h>
33 #include <linux/mdev.h>
34 #include <linux/pci.h>
35 #include <linux/serial.h>
36 #include <uapi/linux/serial_reg.h>
37 #include <linux/eventfd.h>
42 #define VERSION_STRING "0.1"
43 #define DRIVER_AUTHOR "NVIDIA Corporation"
45 #define MTTY_CLASS_NAME "mtty"
47 #define MTTY_NAME "mtty"
49 #define MTTY_STRING_LEN 16
51 #define MTTY_CONFIG_SPACE_SIZE 0xff
52 #define MTTY_IO_BAR_SIZE 0x8
53 #define MTTY_MMIO_BAR_SIZE 0x100000
55 #define STORE_LE16(addr, val) (*(u16 *)addr = val)
56 #define STORE_LE32(addr, val) (*(u32 *)addr = val)
58 #define MAX_FIFO_SIZE 16
60 #define CIRCULAR_BUF_INC_IDX(idx) (idx = (idx + 1) & (MAX_FIFO_SIZE - 1))
62 #define MTTY_VFIO_PCI_OFFSET_SHIFT 40
64 #define MTTY_VFIO_PCI_OFFSET_TO_INDEX(off) (off >> MTTY_VFIO_PCI_OFFSET_SHIFT)
65 #define MTTY_VFIO_PCI_INDEX_TO_OFFSET(index) \
66 ((u64)(index) << MTTY_VFIO_PCI_OFFSET_SHIFT)
67 #define MTTY_VFIO_PCI_OFFSET_MASK \
68 (((u64)(1) << MTTY_VFIO_PCI_OFFSET_SHIFT) - 1)
77 struct class *vd_class;
83 struct mdev_region_info {
90 #if defined(DEBUG_REGS)
91 const char *wr_reg[] = {
102 const char *rd_reg[] = {
114 /* loop back buffer */
116 u8 fifo[MAX_FIFO_SIZE];
122 u8 uart_reg[8]; /* 8 registers */
123 struct rxtx rxtx; /* loop back buffer */
127 u8 fcr; /* FIFO control register */
129 u8 intr_trigger_level; /* interrupt trigger level */
132 /* State of each mdev device */
135 struct eventfd_ctx *intx_evtfd;
136 struct eventfd_ctx *msi_evtfd;
139 struct mutex ops_lock;
140 struct mdev_device *mdev;
141 struct mdev_region_info region_info[VFIO_PCI_NUM_REGIONS];
142 u32 bar_mask[VFIO_PCI_NUM_REGIONS];
143 struct list_head next;
144 struct serial_port s[2];
145 struct mutex rxtx_lock;
146 struct vfio_device_info dev_info;
150 struct mutex mdev_list_lock;
151 struct list_head mdev_devices_list;
153 static const struct file_operations vd_fops = {
154 .owner = THIS_MODULE,
157 /* function prototypes */
159 static int mtty_trigger_interrupt(uuid_le uuid);
161 /* Helper functions */
162 static struct mdev_state *find_mdev_state_by_uuid(uuid_le uuid)
164 struct mdev_state *mds;
166 list_for_each_entry(mds, &mdev_devices_list, next) {
167 if (uuid_le_cmp(mds->mdev->uuid, uuid) == 0)
174 void dump_buffer(char *buf, uint32_t count)
179 pr_info("Buffer:\n");
180 for (i = 0; i < count; i++) {
181 pr_info("%2x ", *(buf + i));
182 if ((i + 1) % 16 == 0)
188 static void mtty_create_config_space(struct mdev_state *mdev_state)
191 STORE_LE32((u32 *) &mdev_state->vconfig[0x0], 0x32534348);
193 /* Control: I/O+, Mem-, BusMaster- */
194 STORE_LE16((u16 *) &mdev_state->vconfig[0x4], 0x0001);
196 /* Status: capabilities list absent */
197 STORE_LE16((u16 *) &mdev_state->vconfig[0x6], 0x0200);
200 mdev_state->vconfig[0x8] = 0x10;
202 /* programming interface class : 16550-compatible serial controller */
203 mdev_state->vconfig[0x9] = 0x02;
206 mdev_state->vconfig[0xa] = 0x00;
208 /* Base class : Simple Communication controllers */
209 mdev_state->vconfig[0xb] = 0x07;
211 /* base address registers */
213 STORE_LE32((u32 *) &mdev_state->vconfig[0x10], 0x000001);
214 mdev_state->bar_mask[0] = ~(MTTY_IO_BAR_SIZE) + 1;
216 if (mdev_state->nr_ports == 2) {
218 STORE_LE32((u32 *) &mdev_state->vconfig[0x14], 0x000001);
219 mdev_state->bar_mask[1] = ~(MTTY_IO_BAR_SIZE) + 1;
223 STORE_LE32((u32 *) &mdev_state->vconfig[0x2c], 0x32534348);
225 mdev_state->vconfig[0x34] = 0x00; /* Cap Ptr */
226 mdev_state->vconfig[0x3d] = 0x01; /* interrupt pin (INTA#) */
228 /* Vendor specific data */
229 mdev_state->vconfig[0x40] = 0x23;
230 mdev_state->vconfig[0x43] = 0x80;
231 mdev_state->vconfig[0x44] = 0x23;
232 mdev_state->vconfig[0x48] = 0x23;
233 mdev_state->vconfig[0x4c] = 0x23;
235 mdev_state->vconfig[0x60] = 0x50;
236 mdev_state->vconfig[0x61] = 0x43;
237 mdev_state->vconfig[0x62] = 0x49;
238 mdev_state->vconfig[0x63] = 0x20;
239 mdev_state->vconfig[0x64] = 0x53;
240 mdev_state->vconfig[0x65] = 0x65;
241 mdev_state->vconfig[0x66] = 0x72;
242 mdev_state->vconfig[0x67] = 0x69;
243 mdev_state->vconfig[0x68] = 0x61;
244 mdev_state->vconfig[0x69] = 0x6c;
245 mdev_state->vconfig[0x6a] = 0x2f;
246 mdev_state->vconfig[0x6b] = 0x55;
247 mdev_state->vconfig[0x6c] = 0x41;
248 mdev_state->vconfig[0x6d] = 0x52;
249 mdev_state->vconfig[0x6e] = 0x54;
252 static void handle_pci_cfg_write(struct mdev_state *mdev_state, u16 offset,
253 char *buf, u32 count)
255 u32 cfg_addr, bar_mask, bar_index = 0;
258 case 0x04: /* device control */
259 case 0x06: /* device status */
262 case 0x3c: /* interrupt line */
263 mdev_state->vconfig[0x3c] = buf[0];
267 * Interrupt Pin is hardwired to INTA.
268 * This field is write protected by hardware
271 case 0x10: /* BAR0 */
272 case 0x14: /* BAR1 */
275 else if (offset == 0x14)
278 if ((mdev_state->nr_ports == 1) && (bar_index == 1)) {
279 STORE_LE32(&mdev_state->vconfig[offset], 0);
283 cfg_addr = *(u32 *)buf;
284 pr_info("BAR%d addr 0x%x\n", bar_index, cfg_addr);
286 if (cfg_addr == 0xffffffff) {
287 bar_mask = mdev_state->bar_mask[bar_index];
288 cfg_addr = (cfg_addr & bar_mask);
291 cfg_addr |= (mdev_state->vconfig[offset] & 0x3ul);
292 STORE_LE32(&mdev_state->vconfig[offset], cfg_addr);
294 case 0x18: /* BAR2 */
295 case 0x1c: /* BAR3 */
296 case 0x20: /* BAR4 */
297 STORE_LE32(&mdev_state->vconfig[offset], 0);
300 pr_info("PCI config write @0x%x of %d bytes not handled\n",
306 static void handle_bar_write(unsigned int index, struct mdev_state *mdev_state,
307 u16 offset, char *buf, u32 count)
311 /* Handle data written by guest */
314 /* if DLAB set, data is LSB of divisor */
315 if (mdev_state->s[index].dlab) {
316 mdev_state->s[index].divisor |= data;
320 mutex_lock(&mdev_state->rxtx_lock);
322 /* save in TX buffer */
323 if (mdev_state->s[index].rxtx.count <
324 mdev_state->s[index].max_fifo_size) {
325 mdev_state->s[index].rxtx.fifo[
326 mdev_state->s[index].rxtx.head] = data;
327 mdev_state->s[index].rxtx.count++;
328 CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.head);
329 mdev_state->s[index].overrun = false;
332 * Trigger interrupt if receive data interrupt is
333 * enabled and fifo reached trigger level
335 if ((mdev_state->s[index].uart_reg[UART_IER] &
337 (mdev_state->s[index].rxtx.count ==
338 mdev_state->s[index].intr_trigger_level)) {
339 /* trigger interrupt */
340 #if defined(DEBUG_INTR)
341 pr_err("Serial port %d: Fifo level trigger\n",
344 mtty_trigger_interrupt(mdev_state->mdev->uuid);
347 #if defined(DEBUG_INTR)
348 pr_err("Serial port %d: Buffer Overflow\n", index);
350 mdev_state->s[index].overrun = true;
353 * Trigger interrupt if receiver line status interrupt
356 if (mdev_state->s[index].uart_reg[UART_IER] &
358 mtty_trigger_interrupt(mdev_state->mdev->uuid);
360 mutex_unlock(&mdev_state->rxtx_lock);
364 /* if DLAB set, data is MSB of divisor */
365 if (mdev_state->s[index].dlab)
366 mdev_state->s[index].divisor |= (u16)data << 8;
368 mdev_state->s[index].uart_reg[offset] = data;
369 mutex_lock(&mdev_state->rxtx_lock);
370 if ((data & UART_IER_THRI) &&
371 (mdev_state->s[index].rxtx.head ==
372 mdev_state->s[index].rxtx.tail)) {
373 #if defined(DEBUG_INTR)
374 pr_err("Serial port %d: IER_THRI write\n",
377 mtty_trigger_interrupt(mdev_state->mdev->uuid);
380 mutex_unlock(&mdev_state->rxtx_lock);
386 mdev_state->s[index].fcr = data;
388 mutex_lock(&mdev_state->rxtx_lock);
389 if (data & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT)) {
390 /* clear loop back FIFO */
391 mdev_state->s[index].rxtx.count = 0;
392 mdev_state->s[index].rxtx.head = 0;
393 mdev_state->s[index].rxtx.tail = 0;
395 mutex_unlock(&mdev_state->rxtx_lock);
397 switch (data & UART_FCR_TRIGGER_MASK) {
398 case UART_FCR_TRIGGER_1:
399 mdev_state->s[index].intr_trigger_level = 1;
402 case UART_FCR_TRIGGER_4:
403 mdev_state->s[index].intr_trigger_level = 4;
406 case UART_FCR_TRIGGER_8:
407 mdev_state->s[index].intr_trigger_level = 8;
410 case UART_FCR_TRIGGER_14:
411 mdev_state->s[index].intr_trigger_level = 14;
416 * Set trigger level to 1 otherwise or implement timer with
417 * timeout of 4 characters and on expiring that timer set
418 * Recevice data timeout in IIR register
420 mdev_state->s[index].intr_trigger_level = 1;
421 if (data & UART_FCR_ENABLE_FIFO)
422 mdev_state->s[index].max_fifo_size = MAX_FIFO_SIZE;
424 mdev_state->s[index].max_fifo_size = 1;
425 mdev_state->s[index].intr_trigger_level = 1;
431 if (data & UART_LCR_DLAB) {
432 mdev_state->s[index].dlab = true;
433 mdev_state->s[index].divisor = 0;
435 mdev_state->s[index].dlab = false;
437 mdev_state->s[index].uart_reg[offset] = data;
441 mdev_state->s[index].uart_reg[offset] = data;
443 if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
444 (data & UART_MCR_OUT2)) {
445 #if defined(DEBUG_INTR)
446 pr_err("Serial port %d: MCR_OUT2 write\n", index);
448 mtty_trigger_interrupt(mdev_state->mdev->uuid);
451 if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
452 (data & (UART_MCR_RTS | UART_MCR_DTR))) {
453 #if defined(DEBUG_INTR)
454 pr_err("Serial port %d: MCR RTS/DTR write\n", index);
456 mtty_trigger_interrupt(mdev_state->mdev->uuid);
466 mdev_state->s[index].uart_reg[offset] = data;
474 static void handle_bar_read(unsigned int index, struct mdev_state *mdev_state,
475 u16 offset, char *buf, u32 count)
477 /* Handle read requests by guest */
480 /* if DLAB set, data is LSB of divisor */
481 if (mdev_state->s[index].dlab) {
482 *buf = (u8)mdev_state->s[index].divisor;
486 mutex_lock(&mdev_state->rxtx_lock);
487 /* return data in tx buffer */
488 if (mdev_state->s[index].rxtx.head !=
489 mdev_state->s[index].rxtx.tail) {
490 *buf = mdev_state->s[index].rxtx.fifo[
491 mdev_state->s[index].rxtx.tail];
492 mdev_state->s[index].rxtx.count--;
493 CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.tail);
496 if (mdev_state->s[index].rxtx.head ==
497 mdev_state->s[index].rxtx.tail) {
499 * Trigger interrupt if tx buffer empty interrupt is
500 * enabled and fifo is empty
502 #if defined(DEBUG_INTR)
503 pr_err("Serial port %d: Buffer Empty\n", index);
505 if (mdev_state->s[index].uart_reg[UART_IER] &
507 mtty_trigger_interrupt(mdev_state->mdev->uuid);
509 mutex_unlock(&mdev_state->rxtx_lock);
514 if (mdev_state->s[index].dlab) {
515 *buf = (u8)(mdev_state->s[index].divisor >> 8);
518 *buf = mdev_state->s[index].uart_reg[offset] & 0x0f;
523 u8 ier = mdev_state->s[index].uart_reg[UART_IER];
526 mutex_lock(&mdev_state->rxtx_lock);
527 /* Interrupt priority 1: Parity, overrun, framing or break */
528 if ((ier & UART_IER_RLSI) && mdev_state->s[index].overrun)
529 *buf |= UART_IIR_RLSI;
531 /* Interrupt priority 2: Fifo trigger level reached */
532 if ((ier & UART_IER_RDI) &&
533 (mdev_state->s[index].rxtx.count ==
534 mdev_state->s[index].intr_trigger_level))
535 *buf |= UART_IIR_RDI;
537 /* Interrupt priotiry 3: transmitter holding register empty */
538 if ((ier & UART_IER_THRI) &&
539 (mdev_state->s[index].rxtx.head ==
540 mdev_state->s[index].rxtx.tail))
541 *buf |= UART_IIR_THRI;
543 /* Interrupt priotiry 4: Modem status: CTS, DSR, RI or DCD */
544 if ((ier & UART_IER_MSI) &&
545 (mdev_state->s[index].uart_reg[UART_MCR] &
546 (UART_MCR_RTS | UART_MCR_DTR)))
547 *buf |= UART_IIR_MSI;
549 /* bit0: 0=> interrupt pending, 1=> no interrupt is pending */
551 *buf = UART_IIR_NO_INT;
553 /* set bit 6 & 7 to be 16550 compatible */
555 mutex_unlock(&mdev_state->rxtx_lock);
561 *buf = mdev_state->s[index].uart_reg[offset];
568 mutex_lock(&mdev_state->rxtx_lock);
569 /* atleast one char in FIFO */
570 if (mdev_state->s[index].rxtx.head !=
571 mdev_state->s[index].rxtx.tail)
574 /* if FIFO overrun */
575 if (mdev_state->s[index].overrun)
578 /* transmit FIFO empty and tramsitter empty */
579 if (mdev_state->s[index].rxtx.head ==
580 mdev_state->s[index].rxtx.tail)
581 lsr |= UART_LSR_TEMT | UART_LSR_THRE;
583 mutex_unlock(&mdev_state->rxtx_lock);
588 *buf = UART_MSR_DSR | UART_MSR_DDSR | UART_MSR_DCD;
590 mutex_lock(&mdev_state->rxtx_lock);
591 /* if AFE is 1 and FIFO have space, set CTS bit */
592 if (mdev_state->s[index].uart_reg[UART_MCR] &
594 if (mdev_state->s[index].rxtx.count <
595 mdev_state->s[index].max_fifo_size)
596 *buf |= UART_MSR_CTS | UART_MSR_DCTS;
598 *buf |= UART_MSR_CTS | UART_MSR_DCTS;
599 mutex_unlock(&mdev_state->rxtx_lock);
604 *buf = mdev_state->s[index].uart_reg[offset];
612 static void mdev_read_base(struct mdev_state *mdev_state)
615 u32 start_lo, start_hi;
618 pos = PCI_BASE_ADDRESS_0;
620 for (index = 0; index <= VFIO_PCI_BAR5_REGION_INDEX; index++) {
622 if (!mdev_state->region_info[index].size)
625 start_lo = (*(u32 *)(mdev_state->vconfig + pos)) &
626 PCI_BASE_ADDRESS_MEM_MASK;
627 mem_type = (*(u32 *)(mdev_state->vconfig + pos)) &
628 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
631 case PCI_BASE_ADDRESS_MEM_TYPE_64:
632 start_hi = (*(u32 *)(mdev_state->vconfig + pos + 4));
635 case PCI_BASE_ADDRESS_MEM_TYPE_32:
636 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
637 /* 1M mem BAR treated as 32-bit BAR */
639 /* mem unknown type treated as 32-bit BAR */
644 mdev_state->region_info[index].start = ((u64)start_hi << 32) |
649 static ssize_t mdev_access(struct mdev_device *mdev, char *buf, size_t count,
650 loff_t pos, bool is_write)
652 struct mdev_state *mdev_state;
660 mdev_state = mdev_get_drvdata(mdev);
662 pr_err("%s mdev_state not found\n", __func__);
666 mutex_lock(&mdev_state->ops_lock);
668 index = MTTY_VFIO_PCI_OFFSET_TO_INDEX(pos);
669 offset = pos & MTTY_VFIO_PCI_OFFSET_MASK;
671 case VFIO_PCI_CONFIG_REGION_INDEX:
674 pr_info("%s: PCI config space %s at offset 0x%llx\n",
675 __func__, is_write ? "write" : "read", offset);
678 dump_buffer(buf, count);
679 handle_pci_cfg_write(mdev_state, offset, buf, count);
681 memcpy(buf, (mdev_state->vconfig + offset), count);
682 dump_buffer(buf, count);
687 case VFIO_PCI_BAR0_REGION_INDEX ... VFIO_PCI_BAR5_REGION_INDEX:
688 if (!mdev_state->region_info[index].start)
689 mdev_read_base(mdev_state);
692 dump_buffer(buf, count);
694 #if defined(DEBUG_REGS)
695 pr_info("%s: BAR%d WR @0x%llx %s val:0x%02x dlab:%d\n",
696 __func__, index, offset, wr_reg[offset],
697 (u8)*buf, mdev_state->s[index].dlab);
699 handle_bar_write(index, mdev_state, offset, buf, count);
701 handle_bar_read(index, mdev_state, offset, buf, count);
702 dump_buffer(buf, count);
704 #if defined(DEBUG_REGS)
705 pr_info("%s: BAR%d RD @0x%llx %s val:0x%02x dlab:%d\n",
706 __func__, index, offset, rd_reg[offset],
707 (u8)*buf, mdev_state->s[index].dlab);
721 mutex_unlock(&mdev_state->ops_lock);
726 int mtty_create(struct kobject *kobj, struct mdev_device *mdev)
728 struct mdev_state *mdev_state;
729 char name[MTTY_STRING_LEN];
735 for (i = 0; i < 2; i++) {
736 snprintf(name, MTTY_STRING_LEN, "%s-%d",
737 dev_driver_string(mdev->parent->dev), i + 1);
738 if (!strcmp(kobj->name, name)) {
747 mdev_state = kzalloc(sizeof(struct mdev_state), GFP_KERNEL);
748 if (mdev_state == NULL)
751 mdev_state->nr_ports = nr_ports;
752 mdev_state->irq_index = -1;
753 mdev_state->s[0].max_fifo_size = MAX_FIFO_SIZE;
754 mdev_state->s[1].max_fifo_size = MAX_FIFO_SIZE;
755 mutex_init(&mdev_state->rxtx_lock);
756 mdev_state->vconfig = kzalloc(MTTY_CONFIG_SPACE_SIZE, GFP_KERNEL);
758 if (mdev_state->vconfig == NULL) {
763 mutex_init(&mdev_state->ops_lock);
764 mdev_state->mdev = mdev;
765 mdev_set_drvdata(mdev, mdev_state);
767 mtty_create_config_space(mdev_state);
769 mutex_lock(&mdev_list_lock);
770 list_add(&mdev_state->next, &mdev_devices_list);
771 mutex_unlock(&mdev_list_lock);
776 int mtty_remove(struct mdev_device *mdev)
778 struct mdev_state *mds, *tmp_mds;
779 struct mdev_state *mdev_state = mdev_get_drvdata(mdev);
782 mutex_lock(&mdev_list_lock);
783 list_for_each_entry_safe(mds, tmp_mds, &mdev_devices_list, next) {
784 if (mdev_state == mds) {
785 list_del(&mdev_state->next);
786 mdev_set_drvdata(mdev, NULL);
787 kfree(mdev_state->vconfig);
793 mutex_unlock(&mdev_list_lock);
798 int mtty_reset(struct mdev_device *mdev)
800 struct mdev_state *mdev_state;
805 mdev_state = mdev_get_drvdata(mdev);
809 pr_info("%s: called\n", __func__);
814 ssize_t mtty_read(struct mdev_device *mdev, char __user *buf, size_t count,
817 unsigned int done = 0;
823 if (count >= 4 && !(*ppos % 4)) {
826 ret = mdev_access(mdev, (char *)&val, sizeof(val),
831 if (copy_to_user(buf, &val, sizeof(val)))
835 } else if (count >= 2 && !(*ppos % 2)) {
838 ret = mdev_access(mdev, (char *)&val, sizeof(val),
843 if (copy_to_user(buf, &val, sizeof(val)))
850 ret = mdev_access(mdev, (char *)&val, sizeof(val),
855 if (copy_to_user(buf, &val, sizeof(val)))
873 ssize_t mtty_write(struct mdev_device *mdev, const char __user *buf,
874 size_t count, loff_t *ppos)
876 unsigned int done = 0;
882 if (count >= 4 && !(*ppos % 4)) {
885 if (copy_from_user(&val, buf, sizeof(val)))
888 ret = mdev_access(mdev, (char *)&val, sizeof(val),
894 } else if (count >= 2 && !(*ppos % 2)) {
897 if (copy_from_user(&val, buf, sizeof(val)))
900 ret = mdev_access(mdev, (char *)&val, sizeof(val),
909 if (copy_from_user(&val, buf, sizeof(val)))
912 ret = mdev_access(mdev, (char *)&val, sizeof(val),
930 static int mtty_set_irqs(struct mdev_device *mdev, uint32_t flags,
931 unsigned int index, unsigned int start,
932 unsigned int count, void *data)
935 struct mdev_state *mdev_state;
940 mdev_state = mdev_get_drvdata(mdev);
944 mutex_lock(&mdev_state->ops_lock);
946 case VFIO_PCI_INTX_IRQ_INDEX:
947 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) {
948 case VFIO_IRQ_SET_ACTION_MASK:
949 case VFIO_IRQ_SET_ACTION_UNMASK:
951 case VFIO_IRQ_SET_ACTION_TRIGGER:
953 if (flags & VFIO_IRQ_SET_DATA_NONE) {
954 pr_info("%s: disable INTx\n", __func__);
955 if (mdev_state->intx_evtfd)
956 eventfd_ctx_put(mdev_state->intx_evtfd);
960 if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
961 int fd = *(int *)data;
964 struct eventfd_ctx *evt;
966 evt = eventfd_ctx_fdget(fd);
971 mdev_state->intx_evtfd = evt;
972 mdev_state->irq_fd = fd;
973 mdev_state->irq_index = index;
981 case VFIO_PCI_MSI_IRQ_INDEX:
982 switch (flags & VFIO_IRQ_SET_ACTION_TYPE_MASK) {
983 case VFIO_IRQ_SET_ACTION_MASK:
984 case VFIO_IRQ_SET_ACTION_UNMASK:
986 case VFIO_IRQ_SET_ACTION_TRIGGER:
987 if (flags & VFIO_IRQ_SET_DATA_NONE) {
988 if (mdev_state->msi_evtfd)
989 eventfd_ctx_put(mdev_state->msi_evtfd);
990 pr_info("%s: disable MSI\n", __func__);
991 mdev_state->irq_index = VFIO_PCI_INTX_IRQ_INDEX;
994 if (flags & VFIO_IRQ_SET_DATA_EVENTFD) {
995 int fd = *(int *)data;
996 struct eventfd_ctx *evt;
1001 if (mdev_state->msi_evtfd)
1004 evt = eventfd_ctx_fdget(fd);
1009 mdev_state->msi_evtfd = evt;
1010 mdev_state->irq_fd = fd;
1011 mdev_state->irq_index = index;
1016 case VFIO_PCI_MSIX_IRQ_INDEX:
1017 pr_info("%s: MSIX_IRQ\n", __func__);
1019 case VFIO_PCI_ERR_IRQ_INDEX:
1020 pr_info("%s: ERR_IRQ\n", __func__);
1022 case VFIO_PCI_REQ_IRQ_INDEX:
1023 pr_info("%s: REQ_IRQ\n", __func__);
1027 mutex_unlock(&mdev_state->ops_lock);
1031 static int mtty_trigger_interrupt(uuid_le uuid)
1034 struct mdev_state *mdev_state;
1036 mdev_state = find_mdev_state_by_uuid(uuid);
1039 pr_info("%s: mdev not found\n", __func__);
1043 if ((mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX) &&
1044 (!mdev_state->msi_evtfd))
1046 else if ((mdev_state->irq_index == VFIO_PCI_INTX_IRQ_INDEX) &&
1047 (!mdev_state->intx_evtfd)) {
1048 pr_info("%s: Intr eventfd not found\n", __func__);
1052 if (mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX)
1053 ret = eventfd_signal(mdev_state->msi_evtfd, 1);
1055 ret = eventfd_signal(mdev_state->intx_evtfd, 1);
1057 #if defined(DEBUG_INTR)
1058 pr_info("Intx triggered\n");
1061 pr_err("%s: eventfd signal failed (%d)\n", __func__, ret);
1066 int mtty_get_region_info(struct mdev_device *mdev,
1067 struct vfio_region_info *region_info,
1068 u16 *cap_type_id, void **cap_type)
1070 unsigned int size = 0;
1071 struct mdev_state *mdev_state;
1077 mdev_state = mdev_get_drvdata(mdev);
1081 mutex_lock(&mdev_state->ops_lock);
1082 bar_index = region_info->index;
1084 switch (bar_index) {
1085 case VFIO_PCI_CONFIG_REGION_INDEX:
1086 size = MTTY_CONFIG_SPACE_SIZE;
1088 case VFIO_PCI_BAR0_REGION_INDEX:
1089 size = MTTY_IO_BAR_SIZE;
1091 case VFIO_PCI_BAR1_REGION_INDEX:
1092 if (mdev_state->nr_ports == 2)
1093 size = MTTY_IO_BAR_SIZE;
1100 mdev_state->region_info[bar_index].size = size;
1101 mdev_state->region_info[bar_index].vfio_offset =
1102 MTTY_VFIO_PCI_INDEX_TO_OFFSET(bar_index);
1104 region_info->size = size;
1105 region_info->offset = MTTY_VFIO_PCI_INDEX_TO_OFFSET(bar_index);
1106 region_info->flags = VFIO_REGION_INFO_FLAG_READ |
1107 VFIO_REGION_INFO_FLAG_WRITE;
1108 mutex_unlock(&mdev_state->ops_lock);
1112 int mtty_get_irq_info(struct mdev_device *mdev, struct vfio_irq_info *irq_info)
1114 switch (irq_info->index) {
1115 case VFIO_PCI_INTX_IRQ_INDEX:
1116 case VFIO_PCI_MSI_IRQ_INDEX:
1117 case VFIO_PCI_REQ_IRQ_INDEX:
1124 irq_info->flags = VFIO_IRQ_INFO_EVENTFD;
1125 irq_info->count = 1;
1127 if (irq_info->index == VFIO_PCI_INTX_IRQ_INDEX)
1128 irq_info->flags |= (VFIO_IRQ_INFO_MASKABLE |
1129 VFIO_IRQ_INFO_AUTOMASKED);
1131 irq_info->flags |= VFIO_IRQ_INFO_NORESIZE;
1136 int mtty_get_device_info(struct mdev_device *mdev,
1137 struct vfio_device_info *dev_info)
1139 dev_info->flags = VFIO_DEVICE_FLAGS_PCI;
1140 dev_info->num_regions = VFIO_PCI_NUM_REGIONS;
1141 dev_info->num_irqs = VFIO_PCI_NUM_IRQS;
1146 static long mtty_ioctl(struct mdev_device *mdev, unsigned int cmd,
1150 unsigned long minsz;
1151 struct mdev_state *mdev_state;
1156 mdev_state = mdev_get_drvdata(mdev);
1161 case VFIO_DEVICE_GET_INFO:
1163 struct vfio_device_info info;
1165 minsz = offsetofend(struct vfio_device_info, num_irqs);
1167 if (copy_from_user(&info, (void __user *)arg, minsz))
1170 if (info.argsz < minsz)
1173 ret = mtty_get_device_info(mdev, &info);
1177 memcpy(&mdev_state->dev_info, &info, sizeof(info));
1179 return copy_to_user((void __user *)arg, &info, minsz);
1181 case VFIO_DEVICE_GET_REGION_INFO:
1183 struct vfio_region_info info;
1184 u16 cap_type_id = 0;
1185 void *cap_type = NULL;
1187 minsz = offsetofend(struct vfio_region_info, offset);
1189 if (copy_from_user(&info, (void __user *)arg, minsz))
1192 if (info.argsz < minsz)
1195 ret = mtty_get_region_info(mdev, &info, &cap_type_id,
1200 return copy_to_user((void __user *)arg, &info, minsz);
1203 case VFIO_DEVICE_GET_IRQ_INFO:
1205 struct vfio_irq_info info;
1207 minsz = offsetofend(struct vfio_irq_info, count);
1209 if (copy_from_user(&info, (void __user *)arg, minsz))
1212 if ((info.argsz < minsz) ||
1213 (info.index >= mdev_state->dev_info.num_irqs))
1216 ret = mtty_get_irq_info(mdev, &info);
1220 if (info.count == -1)
1223 return copy_to_user((void __user *)arg, &info, minsz);
1225 case VFIO_DEVICE_SET_IRQS:
1227 struct vfio_irq_set hdr;
1228 u8 *data = NULL, *ptr = NULL;
1229 size_t data_size = 0;
1231 minsz = offsetofend(struct vfio_irq_set, count);
1233 if (copy_from_user(&hdr, (void __user *)arg, minsz))
1236 ret = vfio_set_irqs_validate_and_prepare(&hdr,
1237 mdev_state->dev_info.num_irqs,
1244 ptr = data = memdup_user((void __user *)(arg + minsz),
1247 return PTR_ERR(data);
1250 ret = mtty_set_irqs(mdev, hdr.flags, hdr.index, hdr.start,
1256 case VFIO_DEVICE_RESET:
1257 return mtty_reset(mdev);
1262 int mtty_open(struct mdev_device *mdev)
1264 pr_info("%s\n", __func__);
1268 void mtty_close(struct mdev_device *mdev)
1270 pr_info("%s\n", __func__);
1274 sample_mtty_dev_show(struct device *dev, struct device_attribute *attr,
1277 return sprintf(buf, "This is phy device\n");
1280 static DEVICE_ATTR_RO(sample_mtty_dev);
1282 static struct attribute *mtty_dev_attrs[] = {
1283 &dev_attr_sample_mtty_dev.attr,
1287 static const struct attribute_group mtty_dev_group = {
1289 .attrs = mtty_dev_attrs,
1292 const struct attribute_group *mtty_dev_groups[] = {
1298 sample_mdev_dev_show(struct device *dev, struct device_attribute *attr,
1301 struct mdev_device *mdev = to_mdev_device(dev);
1304 return sprintf(buf, "This is MDEV %s\n", dev_name(&mdev->dev));
1306 return sprintf(buf, "\n");
1309 static DEVICE_ATTR_RO(sample_mdev_dev);
1311 static struct attribute *mdev_dev_attrs[] = {
1312 &dev_attr_sample_mdev_dev.attr,
1316 static const struct attribute_group mdev_dev_group = {
1318 .attrs = mdev_dev_attrs,
1321 const struct attribute_group *mdev_dev_groups[] = {
1327 name_show(struct kobject *kobj, struct device *dev, char *buf)
1329 char name[MTTY_STRING_LEN];
1331 const char *name_str[2] = {"Single port serial", "Dual port serial"};
1333 for (i = 0; i < 2; i++) {
1334 snprintf(name, MTTY_STRING_LEN, "%s-%d",
1335 dev_driver_string(dev), i + 1);
1336 if (!strcmp(kobj->name, name))
1337 return sprintf(buf, "%s\n", name_str[i]);
1343 MDEV_TYPE_ATTR_RO(name);
1346 available_instances_show(struct kobject *kobj, struct device *dev, char *buf)
1348 char name[MTTY_STRING_LEN];
1350 struct mdev_state *mds;
1351 int ports = 0, used = 0;
1353 for (i = 0; i < 2; i++) {
1354 snprintf(name, MTTY_STRING_LEN, "%s-%d",
1355 dev_driver_string(dev), i + 1);
1356 if (!strcmp(kobj->name, name)) {
1365 list_for_each_entry(mds, &mdev_devices_list, next)
1366 used += mds->nr_ports;
1368 return sprintf(buf, "%d\n", (MAX_MTTYS - used)/ports);
1371 MDEV_TYPE_ATTR_RO(available_instances);
1374 static ssize_t device_api_show(struct kobject *kobj, struct device *dev,
1377 return sprintf(buf, "%s\n", VFIO_DEVICE_API_PCI_STRING);
1380 MDEV_TYPE_ATTR_RO(device_api);
1382 static struct attribute *mdev_types_attrs[] = {
1383 &mdev_type_attr_name.attr,
1384 &mdev_type_attr_device_api.attr,
1385 &mdev_type_attr_available_instances.attr,
1389 static struct attribute_group mdev_type_group1 = {
1391 .attrs = mdev_types_attrs,
1394 static struct attribute_group mdev_type_group2 = {
1396 .attrs = mdev_types_attrs,
1399 struct attribute_group *mdev_type_groups[] = {
1405 struct parent_ops mdev_fops = {
1406 .owner = THIS_MODULE,
1407 .dev_attr_groups = mtty_dev_groups,
1408 .mdev_attr_groups = mdev_dev_groups,
1409 .supported_type_groups = mdev_type_groups,
1410 .create = mtty_create,
1411 .remove = mtty_remove,
1413 .release = mtty_close,
1415 .write = mtty_write,
1416 .ioctl = mtty_ioctl,
1419 static void mtty_device_release(struct device *dev)
1421 dev_dbg(dev, "mtty: released\n");
1424 static int __init mtty_dev_init(void)
1428 pr_info("mtty_dev: %s\n", __func__);
1430 memset(&mtty_dev, 0, sizeof(mtty_dev));
1432 idr_init(&mtty_dev.vd_idr);
1434 ret = alloc_chrdev_region(&mtty_dev.vd_devt, 0, MINORMASK, MTTY_NAME);
1437 pr_err("Error: failed to register mtty_dev, err:%d\n", ret);
1441 cdev_init(&mtty_dev.vd_cdev, &vd_fops);
1442 cdev_add(&mtty_dev.vd_cdev, mtty_dev.vd_devt, MINORMASK);
1444 pr_info("major_number:%d\n", MAJOR(mtty_dev.vd_devt));
1446 mtty_dev.vd_class = class_create(THIS_MODULE, MTTY_CLASS_NAME);
1448 if (IS_ERR(mtty_dev.vd_class)) {
1449 pr_err("Error: failed to register mtty_dev class\n");
1453 mtty_dev.dev.class = mtty_dev.vd_class;
1454 mtty_dev.dev.release = mtty_device_release;
1455 dev_set_name(&mtty_dev.dev, "%s", MTTY_NAME);
1457 ret = device_register(&mtty_dev.dev);
1461 if (mdev_register_device(&mtty_dev.dev, &mdev_fops) != 0)
1464 mutex_init(&mdev_list_lock);
1465 INIT_LIST_HEAD(&mdev_devices_list);
1471 device_unregister(&mtty_dev.dev);
1473 class_destroy(mtty_dev.vd_class);
1476 cdev_del(&mtty_dev.vd_cdev);
1477 unregister_chrdev_region(mtty_dev.vd_devt, MINORMASK);
1483 static void __exit mtty_dev_exit(void)
1485 mtty_dev.dev.bus = NULL;
1486 mdev_unregister_device(&mtty_dev.dev);
1488 device_unregister(&mtty_dev.dev);
1489 idr_destroy(&mtty_dev.vd_idr);
1490 cdev_del(&mtty_dev.vd_cdev);
1491 unregister_chrdev_region(mtty_dev.vd_devt, MINORMASK);
1492 class_destroy(mtty_dev.vd_class);
1493 mtty_dev.vd_class = NULL;
1494 pr_info("mtty_dev: Unloaded!\n");
1497 module_init(mtty_dev_init)
1498 module_exit(mtty_dev_exit)
1500 MODULE_LICENSE("GPL v2");
1501 MODULE_INFO(supported, "Test driver that simulate serial port over PCI");
1502 MODULE_VERSION(VERSION_STRING);
1503 MODULE_AUTHOR(DRIVER_AUTHOR);