2 * dice_stream.c - a part of driver for DICE based devices
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 * Copyright (c) 2014 Takashi Sakamoto <o-takashi@sakamocchi.jp>
7 * Licensed under the terms of the GNU General Public License, version 2.
12 #define CALLBACK_TIMEOUT 200
13 #define NOTIFICATION_TIMEOUT_MS (2 * MSEC_PER_SEC)
15 const unsigned int snd_dice_rates[SND_DICE_RATES_COUNT] = {
29 * This operation has an effect to synchronize GLOBAL_STATUS/GLOBAL_SAMPLE_RATE
30 * to GLOBAL_STATUS. Especially, just after powering on, these are different.
32 static int ensure_phase_lock(struct snd_dice *dice)
37 err = snd_dice_transaction_read_global(dice, GLOBAL_CLOCK_SELECT,
42 if (completion_done(&dice->clock_accepted))
43 reinit_completion(&dice->clock_accepted);
45 err = snd_dice_transaction_write_global(dice, GLOBAL_CLOCK_SELECT,
50 if (wait_for_completion_timeout(&dice->clock_accepted,
51 msecs_to_jiffies(NOTIFICATION_TIMEOUT_MS)) == 0)
57 static void release_resources(struct snd_dice *dice,
58 struct fw_iso_resources *resources)
62 /* Reset channel number */
63 channel = cpu_to_be32((u32)-1);
64 if (resources == &dice->tx_resources)
65 snd_dice_transaction_write_tx(dice, TX_ISOCHRONOUS,
66 &channel, sizeof(channel));
68 snd_dice_transaction_write_rx(dice, RX_ISOCHRONOUS,
69 &channel, sizeof(channel));
71 fw_iso_resources_free(resources);
74 static int keep_resources(struct snd_dice *dice,
75 struct fw_iso_resources *resources,
76 unsigned int max_payload_bytes)
81 err = fw_iso_resources_allocate(resources, max_payload_bytes,
82 fw_parent_device(dice->unit)->max_speed);
86 /* Set channel number */
87 channel = cpu_to_be32(resources->channel);
88 if (resources == &dice->tx_resources)
89 err = snd_dice_transaction_write_tx(dice, TX_ISOCHRONOUS,
90 &channel, sizeof(channel));
92 err = snd_dice_transaction_write_rx(dice, RX_ISOCHRONOUS,
93 &channel, sizeof(channel));
95 release_resources(dice, resources);
100 static void stop_stream(struct snd_dice *dice, struct amdtp_stream *stream)
102 amdtp_stream_pcm_abort(stream);
103 amdtp_stream_stop(stream);
105 if (stream == &dice->tx_stream)
106 release_resources(dice, &dice->tx_resources);
108 release_resources(dice, &dice->rx_resources);
111 static int start_stream(struct snd_dice *dice, struct amdtp_stream *stream,
114 struct fw_iso_resources *resources;
116 unsigned int i, pcm_chs, midi_ports;
117 bool double_pcm_frames;
120 if (stream == &dice->tx_stream) {
121 resources = &dice->tx_resources;
122 err = snd_dice_transaction_read_tx(dice, TX_NUMBER_AUDIO,
125 resources = &dice->rx_resources;
126 err = snd_dice_transaction_read_rx(dice, RX_NUMBER_AUDIO,
133 pcm_chs = be32_to_cpu(reg[0]);
134 midi_ports = be32_to_cpu(reg[1]);
137 * At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in
138 * one data block of AMDTP packet. Thus sampling transfer frequency is
139 * a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are
140 * transferred on AMDTP packets at 96 kHz. Two successive samples of a
141 * channel are stored consecutively in the packet. This quirk is called
143 * For this quirk, blocking mode is required and PCM buffer size should
144 * be aligned to SYT_INTERVAL.
146 double_pcm_frames = rate > 96000;
147 if (double_pcm_frames) {
152 err = amdtp_am824_set_parameters(stream, rate, pcm_chs, midi_ports,
157 if (double_pcm_frames) {
160 for (i = 0; i < pcm_chs; i++) {
161 amdtp_am824_set_pcm_position(stream, i, i * 2);
162 amdtp_am824_set_pcm_position(stream, i + pcm_chs,
167 err = keep_resources(dice, resources,
168 amdtp_stream_get_max_payload(stream));
170 dev_err(&dice->unit->device,
171 "fail to keep isochronous resources\n");
175 err = amdtp_stream_start(stream, resources->channel,
176 fw_parent_device(dice->unit)->max_speed);
178 release_resources(dice, resources);
183 static int get_sync_mode(struct snd_dice *dice, enum cip_flags *sync_mode)
188 err = snd_dice_transaction_get_clock_source(dice, &source);
193 /* So-called 'SYT Match' modes, sync_to_syt value of packets received */
194 case CLOCK_SOURCE_ARX4: /* in 4th stream */
195 case CLOCK_SOURCE_ARX3: /* in 3rd stream */
196 case CLOCK_SOURCE_ARX2: /* in 2nd stream */
199 case CLOCK_SOURCE_ARX1: /* in 1st stream, which this driver uses */
203 *sync_mode = CIP_SYNC_TO_DEVICE;
210 int snd_dice_stream_start_duplex(struct snd_dice *dice, unsigned int rate)
212 struct amdtp_stream *master, *slave;
213 unsigned int curr_rate;
214 enum cip_flags sync_mode;
217 if (dice->substreams_counter == 0)
220 err = get_sync_mode(dice, &sync_mode);
223 if (sync_mode == CIP_SYNC_TO_DEVICE) {
224 master = &dice->tx_stream;
225 slave = &dice->rx_stream;
227 master = &dice->rx_stream;
228 slave = &dice->tx_stream;
231 /* Some packet queueing errors. */
232 if (amdtp_streaming_error(master) || amdtp_streaming_error(slave))
233 stop_stream(dice, master);
235 /* Stop stream if rate is different. */
236 err = snd_dice_transaction_get_rate(dice, &curr_rate);
238 dev_err(&dice->unit->device,
239 "fail to get sampling rate\n");
244 if (rate != curr_rate) {
249 if (!amdtp_stream_running(master)) {
250 stop_stream(dice, slave);
251 snd_dice_transaction_clear_enable(dice);
253 amdtp_stream_set_sync(sync_mode, master, slave);
255 err = ensure_phase_lock(dice);
257 dev_err(&dice->unit->device,
258 "fail to ensure phase lock\n");
262 /* Start both streams. */
263 err = start_stream(dice, master, rate);
265 dev_err(&dice->unit->device,
266 "fail to start AMDTP master stream\n");
269 err = start_stream(dice, slave, rate);
271 dev_err(&dice->unit->device,
272 "fail to start AMDTP slave stream\n");
273 stop_stream(dice, master);
276 err = snd_dice_transaction_set_enable(dice);
278 dev_err(&dice->unit->device,
279 "fail to enable interface\n");
280 stop_stream(dice, master);
281 stop_stream(dice, slave);
285 /* Wait first callbacks */
286 if (!amdtp_stream_wait_callback(master, CALLBACK_TIMEOUT) ||
287 !amdtp_stream_wait_callback(slave, CALLBACK_TIMEOUT)) {
288 snd_dice_transaction_clear_enable(dice);
289 stop_stream(dice, master);
290 stop_stream(dice, slave);
298 void snd_dice_stream_stop_duplex(struct snd_dice *dice)
300 if (dice->substreams_counter > 0)
303 snd_dice_transaction_clear_enable(dice);
305 stop_stream(dice, &dice->tx_stream);
306 stop_stream(dice, &dice->rx_stream);
309 static int init_stream(struct snd_dice *dice, struct amdtp_stream *stream)
312 struct fw_iso_resources *resources;
313 enum amdtp_stream_direction dir;
315 if (stream == &dice->tx_stream) {
316 resources = &dice->tx_resources;
317 dir = AMDTP_IN_STREAM;
319 resources = &dice->rx_resources;
320 dir = AMDTP_OUT_STREAM;
323 err = fw_iso_resources_init(resources, dice->unit);
326 resources->channels_mask = 0x00000000ffffffffuLL;
328 err = amdtp_am824_init(stream, dice->unit, dir, CIP_BLOCKING);
330 amdtp_stream_destroy(stream);
331 fw_iso_resources_destroy(resources);
338 * This function should be called before starting streams or after stopping
341 static void destroy_stream(struct snd_dice *dice, struct amdtp_stream *stream)
343 struct fw_iso_resources *resources;
345 if (stream == &dice->tx_stream)
346 resources = &dice->tx_resources;
348 resources = &dice->rx_resources;
350 amdtp_stream_destroy(stream);
351 fw_iso_resources_destroy(resources);
354 int snd_dice_stream_init_duplex(struct snd_dice *dice)
358 dice->substreams_counter = 0;
360 err = init_stream(dice, &dice->tx_stream);
364 err = init_stream(dice, &dice->rx_stream);
366 destroy_stream(dice, &dice->tx_stream);
371 void snd_dice_stream_destroy_duplex(struct snd_dice *dice)
373 snd_dice_transaction_clear_enable(dice);
375 destroy_stream(dice, &dice->tx_stream);
376 destroy_stream(dice, &dice->rx_stream);
378 dice->substreams_counter = 0;
381 void snd_dice_stream_update_duplex(struct snd_dice *dice)
384 * On a bus reset, the DICE firmware disables streaming and then goes
385 * off contemplating its own navel for hundreds of milliseconds before
386 * it can react to any of our attempts to reenable streaming. This
387 * means that we lose synchronization anyway, so we force our streams
388 * to stop so that the application can restart them in an orderly
391 dice->global_enabled = false;
393 stop_stream(dice, &dice->rx_stream);
394 stop_stream(dice, &dice->tx_stream);
396 fw_iso_resources_update(&dice->rx_resources);
397 fw_iso_resources_update(&dice->tx_resources);
400 static void dice_lock_changed(struct snd_dice *dice)
402 dice->dev_lock_changed = true;
403 wake_up(&dice->hwdep_wait);
406 int snd_dice_stream_lock_try(struct snd_dice *dice)
410 spin_lock_irq(&dice->lock);
412 if (dice->dev_lock_count < 0) {
417 if (dice->dev_lock_count++ == 0)
418 dice_lock_changed(dice);
421 spin_unlock_irq(&dice->lock);
425 void snd_dice_stream_lock_release(struct snd_dice *dice)
427 spin_lock_irq(&dice->lock);
429 if (WARN_ON(dice->dev_lock_count <= 0))
432 if (--dice->dev_lock_count == 0)
433 dice_lock_changed(dice);
435 spin_unlock_irq(&dice->lock);