2 * TC Applied Technologies Digital Interface Communications Engine driver
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 * Licensed under the terms of the GNU General Public License, version 2.
8 #include <linux/compat.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/firewire.h>
13 #include <linux/firewire-constants.h>
14 #include <linux/jiffies.h>
15 #include <linux/module.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/mutex.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
20 #include <linux/wait.h>
21 #include <sound/control.h>
22 #include <sound/core.h>
23 #include <sound/firewire.h>
24 #include <sound/hwdep.h>
25 #include <sound/initval.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
29 #include "iso-resources.h"
31 #include "dice-interface.h"
35 struct snd_card *card;
39 unsigned int global_offset;
40 unsigned int rx_offset;
41 unsigned int clock_caps;
42 unsigned int rx_channels[3];
43 unsigned int rx_midi_ports[3];
44 struct fw_address_handler notification_handler;
46 int dev_lock_count; /* > 0 driver, < 0 userspace */
47 bool dev_lock_changed;
49 struct completion clock_accepted;
50 wait_queue_head_t hwdep_wait;
51 u32 notification_bits;
52 struct fw_iso_resources resources;
53 struct amdtp_out_stream stream;
56 MODULE_DESCRIPTION("DICE driver");
57 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
58 MODULE_LICENSE("GPL v2");
60 static const unsigned int dice_rates[] = {
73 static unsigned int rate_index_to_mode(unsigned int rate_index)
75 return ((int)rate_index - 1) / 2;
78 static void dice_lock_changed(struct dice *dice)
80 dice->dev_lock_changed = true;
81 wake_up(&dice->hwdep_wait);
84 static int dice_try_lock(struct dice *dice)
88 spin_lock_irq(&dice->lock);
90 if (dice->dev_lock_count < 0) {
95 if (dice->dev_lock_count++ == 0)
96 dice_lock_changed(dice);
100 spin_unlock_irq(&dice->lock);
105 static void dice_unlock(struct dice *dice)
107 spin_lock_irq(&dice->lock);
109 if (WARN_ON(dice->dev_lock_count <= 0))
112 if (--dice->dev_lock_count == 0)
113 dice_lock_changed(dice);
116 spin_unlock_irq(&dice->lock);
119 static inline u64 global_address(struct dice *dice, unsigned int offset)
121 return DICE_PRIVATE_SPACE + dice->global_offset + offset;
125 static inline u64 rx_address(struct dice *dice, unsigned int offset)
127 return DICE_PRIVATE_SPACE + dice->rx_offset + offset;
130 static int dice_owner_set(struct dice *dice)
132 struct fw_device *device = fw_parent_device(dice->unit);
136 buffer = kmalloc(2 * 8, GFP_KERNEL);
141 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
142 buffer[1] = cpu_to_be64(
143 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
144 dice->notification_handler.offset);
146 dice->owner_generation = device->generation;
147 smp_rmb(); /* node_id vs. generation */
148 err = snd_fw_transaction(dice->unit,
149 TCODE_LOCK_COMPARE_SWAP,
150 global_address(dice, GLOBAL_OWNER),
152 FW_FIXED_GENERATION |
153 dice->owner_generation);
156 if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
157 dev_err(&dice->unit->device,
158 "device is already in use\n");
163 if (err != -EAGAIN || ++errors >= 3)
174 static int dice_owner_update(struct dice *dice)
176 struct fw_device *device = fw_parent_device(dice->unit);
180 if (dice->owner_generation == -1)
183 buffer = kmalloc(2 * 8, GFP_KERNEL);
187 buffer[0] = cpu_to_be64(OWNER_NO_OWNER);
188 buffer[1] = cpu_to_be64(
189 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
190 dice->notification_handler.offset);
192 dice->owner_generation = device->generation;
193 smp_rmb(); /* node_id vs. generation */
194 err = snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
195 global_address(dice, GLOBAL_OWNER),
197 FW_FIXED_GENERATION | dice->owner_generation);
200 if (buffer[0] != cpu_to_be64(OWNER_NO_OWNER)) {
201 dev_err(&dice->unit->device,
202 "device is already in use\n");
205 } else if (err == -EAGAIN) {
206 err = 0; /* try again later */
212 dice->owner_generation = -1;
217 static void dice_owner_clear(struct dice *dice)
219 struct fw_device *device = fw_parent_device(dice->unit);
222 buffer = kmalloc(2 * 8, GFP_KERNEL);
226 buffer[0] = cpu_to_be64(
227 ((u64)device->card->node_id << OWNER_NODE_SHIFT) |
228 dice->notification_handler.offset);
229 buffer[1] = cpu_to_be64(OWNER_NO_OWNER);
230 snd_fw_transaction(dice->unit, TCODE_LOCK_COMPARE_SWAP,
231 global_address(dice, GLOBAL_OWNER),
232 buffer, 2 * 8, FW_QUIET |
233 FW_FIXED_GENERATION | dice->owner_generation);
237 dice->owner_generation = -1;
240 static int dice_enable_set(struct dice *dice)
245 value = cpu_to_be32(1);
246 err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
247 global_address(dice, GLOBAL_ENABLE),
249 FW_FIXED_GENERATION | dice->owner_generation);
253 dice->global_enabled = true;
258 static void dice_enable_clear(struct dice *dice)
262 if (!dice->global_enabled)
266 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
267 global_address(dice, GLOBAL_ENABLE),
268 &value, 4, FW_QUIET |
269 FW_FIXED_GENERATION | dice->owner_generation);
271 dice->global_enabled = false;
274 static void dice_notification(struct fw_card *card, struct fw_request *request,
275 int tcode, int destination, int source,
276 int generation, unsigned long long offset,
277 void *data, size_t length, void *callback_data)
279 struct dice *dice = callback_data;
283 if (tcode != TCODE_WRITE_QUADLET_REQUEST) {
284 fw_send_response(card, request, RCODE_TYPE_ERROR);
287 if ((offset & 3) != 0) {
288 fw_send_response(card, request, RCODE_ADDRESS_ERROR);
292 bits = be32_to_cpup(data);
294 spin_lock_irqsave(&dice->lock, flags);
295 dice->notification_bits |= bits;
296 spin_unlock_irqrestore(&dice->lock, flags);
298 fw_send_response(card, request, RCODE_COMPLETE);
300 if (bits & NOTIFY_CLOCK_ACCEPTED)
301 complete(&dice->clock_accepted);
302 wake_up(&dice->hwdep_wait);
305 static int dice_open(struct snd_pcm_substream *substream)
307 static const struct snd_pcm_hardware hardware = {
308 .info = SNDRV_PCM_INFO_MMAP |
309 SNDRV_PCM_INFO_MMAP_VALID |
310 SNDRV_PCM_INFO_BATCH |
311 SNDRV_PCM_INFO_INTERLEAVED |
312 SNDRV_PCM_INFO_BLOCK_TRANSFER,
313 .formats = AMDTP_OUT_PCM_FORMAT_BITS,
314 .buffer_bytes_max = 16 * 1024 * 1024,
315 .period_bytes_min = 1,
316 .period_bytes_max = UINT_MAX,
318 .periods_max = UINT_MAX,
320 struct dice *dice = substream->private_data;
321 struct snd_pcm_runtime *runtime = substream->runtime;
322 __be32 clock_sel, data[2];
323 unsigned int rate_index, number_audio, number_midi;
326 err = dice_try_lock(dice);
330 err = snd_fw_transaction(dice->unit, TCODE_READ_QUADLET_REQUEST,
331 global_address(dice, GLOBAL_CLOCK_SELECT),
335 rate_index = (be32_to_cpu(clock_sel) & CLOCK_RATE_MASK)
337 if (rate_index >= ARRAY_SIZE(dice_rates)) {
342 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
343 rx_address(dice, RX_NUMBER_AUDIO),
347 number_audio = be32_to_cpu(data[0]);
348 number_midi = be32_to_cpu(data[1]);
350 runtime->hw = hardware;
352 runtime->hw.rates = snd_pcm_rate_to_rate_bit(dice_rates[rate_index]);
353 snd_pcm_limit_hw_rates(runtime);
355 runtime->hw.channels_min = number_audio;
356 runtime->hw.channels_max = number_audio;
358 amdtp_out_stream_set_parameters(&dice->stream, dice_rates[rate_index],
359 number_audio, number_midi);
361 err = snd_pcm_hw_constraint_step(runtime, 0,
362 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
363 amdtp_syt_intervals[rate_index]);
366 err = snd_pcm_hw_constraint_step(runtime, 0,
367 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
368 amdtp_syt_intervals[rate_index]);
372 err = snd_pcm_hw_constraint_minmax(runtime,
373 SNDRV_PCM_HW_PARAM_PERIOD_TIME,
378 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
390 static int dice_close(struct snd_pcm_substream *substream)
392 struct dice *dice = substream->private_data;
399 static int dice_stream_start_packets(struct dice *dice)
403 if (amdtp_out_stream_running(&dice->stream))
406 err = amdtp_out_stream_start(&dice->stream, dice->resources.channel,
407 fw_parent_device(dice->unit)->max_speed);
411 err = dice_enable_set(dice);
413 amdtp_out_stream_stop(&dice->stream);
420 static int dice_stream_start(struct dice *dice)
425 if (!dice->resources.allocated) {
426 err = fw_iso_resources_allocate(&dice->resources,
427 amdtp_out_stream_get_max_payload(&dice->stream),
428 fw_parent_device(dice->unit)->max_speed);
432 channel = cpu_to_be32(dice->resources.channel);
433 err = snd_fw_transaction(dice->unit,
434 TCODE_WRITE_QUADLET_REQUEST,
435 rx_address(dice, RX_ISOCHRONOUS),
441 err = dice_stream_start_packets(dice);
448 channel = cpu_to_be32((u32)-1);
449 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
450 rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
452 fw_iso_resources_free(&dice->resources);
457 static void dice_stream_stop_packets(struct dice *dice)
459 if (amdtp_out_stream_running(&dice->stream)) {
460 dice_enable_clear(dice);
461 amdtp_out_stream_stop(&dice->stream);
465 static void dice_stream_stop(struct dice *dice)
469 dice_stream_stop_packets(dice);
471 if (!dice->resources.allocated)
474 channel = cpu_to_be32((u32)-1);
475 snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
476 rx_address(dice, RX_ISOCHRONOUS), &channel, 4, 0);
478 fw_iso_resources_free(&dice->resources);
481 static int dice_change_rate(struct dice *dice, unsigned int clock_rate)
486 INIT_COMPLETION(dice->clock_accepted);
488 value = cpu_to_be32(clock_rate | CLOCK_SOURCE_ARX1);
489 err = snd_fw_transaction(dice->unit, TCODE_WRITE_QUADLET_REQUEST,
490 global_address(dice, GLOBAL_CLOCK_SELECT),
495 wait_for_completion_timeout(&dice->clock_accepted,
496 msecs_to_jiffies(100));
501 static int dice_hw_params(struct snd_pcm_substream *substream,
502 struct snd_pcm_hw_params *hw_params)
504 struct dice *dice = substream->private_data;
507 mutex_lock(&dice->mutex);
508 dice_stream_stop(dice);
509 mutex_unlock(&dice->mutex);
511 err = snd_pcm_lib_alloc_vmalloc_buffer(substream,
512 params_buffer_bytes(hw_params));
516 amdtp_out_stream_set_pcm_format(&dice->stream,
517 params_format(hw_params));
525 static int dice_hw_free(struct snd_pcm_substream *substream)
527 struct dice *dice = substream->private_data;
529 mutex_lock(&dice->mutex);
530 dice_stream_stop(dice);
531 mutex_unlock(&dice->mutex);
533 return snd_pcm_lib_free_vmalloc_buffer(substream);
536 static int dice_prepare(struct snd_pcm_substream *substream)
538 struct dice *dice = substream->private_data;
541 mutex_lock(&dice->mutex);
543 if (amdtp_out_streaming_error(&dice->stream))
544 dice_stream_stop_packets(dice);
546 err = dice_stream_start(dice);
548 mutex_unlock(&dice->mutex);
552 mutex_unlock(&dice->mutex);
554 amdtp_out_stream_pcm_prepare(&dice->stream);
559 static int dice_trigger(struct snd_pcm_substream *substream, int cmd)
561 struct dice *dice = substream->private_data;
562 struct snd_pcm_substream *pcm;
565 case SNDRV_PCM_TRIGGER_START:
568 case SNDRV_PCM_TRIGGER_STOP:
574 amdtp_out_stream_pcm_trigger(&dice->stream, pcm);
579 static snd_pcm_uframes_t dice_pointer(struct snd_pcm_substream *substream)
581 struct dice *dice = substream->private_data;
583 return amdtp_out_stream_pcm_pointer(&dice->stream);
586 static int dice_create_pcm(struct dice *dice)
588 static struct snd_pcm_ops ops = {
591 .ioctl = snd_pcm_lib_ioctl,
592 .hw_params = dice_hw_params,
593 .hw_free = dice_hw_free,
594 .prepare = dice_prepare,
595 .trigger = dice_trigger,
596 .pointer = dice_pointer,
597 .page = snd_pcm_lib_get_vmalloc_page,
598 .mmap = snd_pcm_lib_mmap_vmalloc,
603 err = snd_pcm_new(dice->card, "DICE", 0, 1, 0, &pcm);
606 pcm->private_data = dice;
607 strcpy(pcm->name, dice->card->shortname);
608 pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->ops = &ops;
613 static long dice_hwdep_read(struct snd_hwdep *hwdep, char __user *buf,
614 long count, loff_t *offset)
616 struct dice *dice = hwdep->private_data;
618 union snd_firewire_event event;
620 spin_lock_irq(&dice->lock);
622 while (!dice->dev_lock_changed && dice->notification_bits == 0) {
623 prepare_to_wait(&dice->hwdep_wait, &wait, TASK_INTERRUPTIBLE);
624 spin_unlock_irq(&dice->lock);
626 finish_wait(&dice->hwdep_wait, &wait);
627 if (signal_pending(current))
629 spin_lock_irq(&dice->lock);
632 memset(&event, 0, sizeof(event));
633 if (dice->dev_lock_changed) {
634 event.lock_status.type = SNDRV_FIREWIRE_EVENT_LOCK_STATUS;
635 event.lock_status.status = dice->dev_lock_count > 0;
636 dice->dev_lock_changed = false;
638 count = min(count, (long)sizeof(event.lock_status));
640 event.dice_notification.type = SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION;
641 event.dice_notification.notification = dice->notification_bits;
642 dice->notification_bits = 0;
644 count = min(count, (long)sizeof(event.dice_notification));
647 spin_unlock_irq(&dice->lock);
649 if (copy_to_user(buf, &event, count))
655 static unsigned int dice_hwdep_poll(struct snd_hwdep *hwdep, struct file *file,
658 struct dice *dice = hwdep->private_data;
661 poll_wait(file, &dice->hwdep_wait, wait);
663 spin_lock_irq(&dice->lock);
664 if (dice->dev_lock_changed || dice->notification_bits != 0)
665 events = POLLIN | POLLRDNORM;
668 spin_unlock_irq(&dice->lock);
673 static int dice_hwdep_get_info(struct dice *dice, void __user *arg)
675 struct fw_device *dev = fw_parent_device(dice->unit);
676 struct snd_firewire_get_info info;
678 memset(&info, 0, sizeof(info));
679 info.type = SNDRV_FIREWIRE_TYPE_DICE;
680 info.card = dev->card->index;
681 *(__be32 *)&info.guid[0] = cpu_to_be32(dev->config_rom[3]);
682 *(__be32 *)&info.guid[4] = cpu_to_be32(dev->config_rom[4]);
683 strlcpy(info.device_name, dev_name(&dev->device),
684 sizeof(info.device_name));
686 if (copy_to_user(arg, &info, sizeof(info)))
692 static int dice_hwdep_lock(struct dice *dice)
696 spin_lock_irq(&dice->lock);
698 if (dice->dev_lock_count == 0) {
699 dice->dev_lock_count = -1;
705 spin_unlock_irq(&dice->lock);
710 static int dice_hwdep_unlock(struct dice *dice)
714 spin_lock_irq(&dice->lock);
716 if (dice->dev_lock_count == -1) {
717 dice->dev_lock_count = 0;
723 spin_unlock_irq(&dice->lock);
728 static int dice_hwdep_release(struct snd_hwdep *hwdep, struct file *file)
730 struct dice *dice = hwdep->private_data;
732 spin_lock_irq(&dice->lock);
733 if (dice->dev_lock_count == -1)
734 dice->dev_lock_count = 0;
735 spin_unlock_irq(&dice->lock);
740 static int dice_hwdep_ioctl(struct snd_hwdep *hwdep, struct file *file,
741 unsigned int cmd, unsigned long arg)
743 struct dice *dice = hwdep->private_data;
746 case SNDRV_FIREWIRE_IOCTL_GET_INFO:
747 return dice_hwdep_get_info(dice, (void __user *)arg);
748 case SNDRV_FIREWIRE_IOCTL_LOCK:
749 return dice_hwdep_lock(dice);
750 case SNDRV_FIREWIRE_IOCTL_UNLOCK:
751 return dice_hwdep_unlock(dice);
758 static int dice_hwdep_compat_ioctl(struct snd_hwdep *hwdep, struct file *file,
759 unsigned int cmd, unsigned long arg)
761 return dice_hwdep_ioctl(hwdep, file, cmd,
762 (unsigned long)compat_ptr(arg));
765 #define dice_hwdep_compat_ioctl NULL
768 static int dice_create_hwdep(struct dice *dice)
770 static const struct snd_hwdep_ops ops = {
771 .read = dice_hwdep_read,
772 .release = dice_hwdep_release,
773 .poll = dice_hwdep_poll,
774 .ioctl = dice_hwdep_ioctl,
775 .ioctl_compat = dice_hwdep_compat_ioctl,
777 struct snd_hwdep *hwdep;
780 err = snd_hwdep_new(dice->card, "DICE", 0, &hwdep);
783 strcpy(hwdep->name, "DICE");
784 hwdep->iface = SNDRV_HWDEP_IFACE_FW_DICE;
786 hwdep->private_data = dice;
787 hwdep->exclusive = true;
792 static void dice_card_free(struct snd_card *card)
794 struct dice *dice = card->private_data;
796 amdtp_out_stream_destroy(&dice->stream);
797 fw_core_remove_address_handler(&dice->notification_handler);
798 mutex_destroy(&dice->mutex);
801 #define DICE_CATEGORY_ID 0x04
803 static int dice_interface_check(struct fw_unit *unit)
805 static const int min_values[10] = {
812 struct fw_device *device = fw_parent_device(unit);
813 struct fw_csr_iterator it;
814 int key, value, vendor = -1, model = -1, err;
816 __be32 pointers[ARRAY_SIZE(min_values)];
820 * Check that GUID and unit directory are constructed according to DICE
821 * rules, i.e., that the specifier ID is the GUID's OUI, and that the
822 * GUID chip ID consists of the 8-bit DICE category ID, the 10-bit
823 * product ID, and a 22-bit serial number.
825 fw_csr_iterator_init(&it, unit->directory);
826 while (fw_csr_iterator_next(&it, &key, &value)) {
828 case CSR_SPECIFIER_ID:
836 if (device->config_rom[3] != ((vendor << 8) | DICE_CATEGORY_ID) ||
837 device->config_rom[4] >> 22 != model)
841 * Check that the sub address spaces exist and are located inside the
842 * private address space. The minimum values are chosen so that all
843 * minimally required registers are included.
845 err = snd_fw_transaction(unit, TCODE_READ_BLOCK_REQUEST,
847 pointers, sizeof(pointers), 0);
850 for (i = 0; i < ARRAY_SIZE(pointers); ++i) {
851 value = be32_to_cpu(pointers[i]);
852 if (value < min_values[i] || value >= 0x40000)
857 * Check that the implemented DICE driver specification major version
860 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
862 be32_to_cpu(pointers[0]) * 4 + GLOBAL_VERSION,
866 if ((version & cpu_to_be32(0xff000000)) != cpu_to_be32(0x01000000)) {
867 dev_err(&unit->device,
868 "unknown DICE version: 0x%08x\n", be32_to_cpu(version));
875 static int highest_supported_mode_rate(struct dice *dice, unsigned int mode)
879 for (i = ARRAY_SIZE(dice_rates) - 1; i >= 0; --i)
880 if ((dice->clock_caps & (1 << i)) &&
881 rate_index_to_mode(i) == mode)
887 static int dice_read_mode_params(struct dice *dice, unsigned int mode)
892 rate_index = highest_supported_mode_rate(dice, mode);
893 if (rate_index < 0) {
894 dice->rx_channels[mode] = 0;
895 dice->rx_midi_ports[mode] = 0;
899 err = dice_change_rate(dice, rate_index << CLOCK_RATE_SHIFT);
903 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
904 rx_address(dice, RX_NUMBER_AUDIO),
909 dice->rx_channels[mode] = be32_to_cpu(values[0]);
910 dice->rx_midi_ports[mode] = be32_to_cpu(values[1]);
915 static int dice_read_params(struct dice *dice)
921 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
923 pointers, sizeof(pointers), 0);
927 dice->global_offset = be32_to_cpu(pointers[0]) * 4;
928 dice->rx_offset = be32_to_cpu(pointers[4]) * 4;
930 /* some very old firmwares don't tell about their clock support */
931 if (be32_to_cpu(pointers[1]) * 4 >= GLOBAL_CLOCK_CAPABILITIES + 4) {
932 err = snd_fw_transaction(
933 dice->unit, TCODE_READ_QUADLET_REQUEST,
934 global_address(dice, GLOBAL_CLOCK_CAPABILITIES),
938 dice->clock_caps = be32_to_cpu(value);
940 /* this should be supported by any device */
941 dice->clock_caps = CLOCK_CAP_RATE_44100 |
942 CLOCK_CAP_RATE_48000 |
943 CLOCK_CAP_SOURCE_ARX1 |
944 CLOCK_CAP_SOURCE_INTERNAL;
947 for (mode = 2; mode >= 0; --mode) {
948 err = dice_read_mode_params(dice, mode);
956 static void dice_card_strings(struct dice *dice)
958 struct snd_card *card = dice->card;
959 struct fw_device *dev = fw_parent_device(dice->unit);
960 char vendor[32], model[32];
964 strcpy(card->driver, "DICE");
966 strcpy(card->shortname, "DICE");
967 BUILD_BUG_ON(NICK_NAME_SIZE < sizeof(card->shortname));
968 err = snd_fw_transaction(dice->unit, TCODE_READ_BLOCK_REQUEST,
969 global_address(dice, GLOBAL_NICK_NAME),
970 card->shortname, sizeof(card->shortname), 0);
972 /* DICE strings are returned in "always-wrong" endianness */
973 BUILD_BUG_ON(sizeof(card->shortname) % 4 != 0);
974 for (i = 0; i < sizeof(card->shortname); i += 4)
975 swab32s((u32 *)&card->shortname[i]);
976 card->shortname[sizeof(card->shortname) - 1] = '\0';
980 fw_csr_string(dev->config_rom + 5, CSR_VENDOR, vendor, sizeof(vendor));
982 fw_csr_string(dice->unit->directory, CSR_MODEL, model, sizeof(model));
983 snprintf(card->longname, sizeof(card->longname),
984 "%s %s (serial %u) at %s, S%d",
985 vendor, model, dev->config_rom[4] & 0x3fffff,
986 dev_name(&dice->unit->device), 100 << dev->max_speed);
988 strcpy(card->mixername, "DICE");
991 static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
993 struct snd_card *card;
998 err = dice_interface_check(unit);
1002 err = snd_card_create(-1, NULL, THIS_MODULE, sizeof(*dice), &card);
1005 snd_card_set_dev(card, &unit->device);
1007 dice = card->private_data;
1009 spin_lock_init(&dice->lock);
1010 mutex_init(&dice->mutex);
1012 init_completion(&dice->clock_accepted);
1013 init_waitqueue_head(&dice->hwdep_wait);
1015 dice->notification_handler.length = 4;
1016 dice->notification_handler.address_callback = dice_notification;
1017 dice->notification_handler.callback_data = dice;
1018 err = fw_core_add_address_handler(&dice->notification_handler,
1019 &fw_high_memory_region);
1023 err = dice_owner_set(dice);
1025 goto err_notification_handler;
1027 err = dice_read_params(dice);
1031 err = fw_iso_resources_init(&dice->resources, unit);
1034 dice->resources.channels_mask = 0x00000000ffffffffuLL;
1036 err = amdtp_out_stream_init(&dice->stream, unit,
1037 CIP_BLOCKING | CIP_HI_DUALWIRE);
1041 card->private_free = dice_card_free;
1043 dice_card_strings(dice);
1045 err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
1046 global_address(dice, GLOBAL_CLOCK_SELECT),
1050 clock_sel &= cpu_to_be32(~CLOCK_SOURCE_MASK);
1051 clock_sel |= cpu_to_be32(CLOCK_SOURCE_ARX1);
1052 err = snd_fw_transaction(unit, TCODE_WRITE_QUADLET_REQUEST,
1053 global_address(dice, GLOBAL_CLOCK_SELECT),
1058 err = dice_create_pcm(dice);
1062 err = dice_create_hwdep(dice);
1066 err = snd_card_register(card);
1070 dev_set_drvdata(&unit->device, dice);
1075 fw_iso_resources_destroy(&dice->resources);
1077 dice_owner_clear(dice);
1078 err_notification_handler:
1079 fw_core_remove_address_handler(&dice->notification_handler);
1081 mutex_destroy(&dice->mutex);
1083 snd_card_free(card);
1087 static void dice_remove(struct fw_unit *unit)
1089 struct dice *dice = dev_get_drvdata(&unit->device);
1091 amdtp_out_stream_pcm_abort(&dice->stream);
1093 snd_card_disconnect(dice->card);
1095 mutex_lock(&dice->mutex);
1097 dice_stream_stop(dice);
1098 dice_owner_clear(dice);
1100 mutex_unlock(&dice->mutex);
1102 snd_card_free_when_closed(dice->card);
1105 static void dice_bus_reset(struct fw_unit *unit)
1107 struct dice *dice = dev_get_drvdata(&unit->device);
1110 * On a bus reset, the DICE firmware disables streaming and then goes
1111 * off contemplating its own navel for hundreds of milliseconds before
1112 * it can react to any of our attempts to reenable streaming. This
1113 * means that we lose synchronization anyway, so we force our streams
1114 * to stop so that the application can restart them in an orderly
1117 amdtp_out_stream_pcm_abort(&dice->stream);
1119 mutex_lock(&dice->mutex);
1121 dice->global_enabled = false;
1122 dice_stream_stop_packets(dice);
1124 dice_owner_update(dice);
1126 fw_iso_resources_update(&dice->resources);
1128 mutex_unlock(&dice->mutex);
1131 #define DICE_INTERFACE 0x000001
1133 static const struct ieee1394_device_id dice_id_table[] = {
1135 .match_flags = IEEE1394_MATCH_VERSION,
1136 .version = DICE_INTERFACE,
1140 MODULE_DEVICE_TABLE(ieee1394, dice_id_table);
1142 static struct fw_driver dice_driver = {
1144 .owner = THIS_MODULE,
1145 .name = KBUILD_MODNAME,
1146 .bus = &fw_bus_type,
1148 .probe = dice_probe,
1149 .update = dice_bus_reset,
1150 .remove = dice_remove,
1151 .id_table = dice_id_table,
1154 static int __init alsa_dice_init(void)
1156 return driver_register(&dice_driver.driver);
1159 static void __exit alsa_dice_exit(void)
1161 driver_unregister(&dice_driver.driver);
1164 module_init(alsa_dice_init);
1165 module_exit(alsa_dice_exit);