sound/hda/hdac_controller.c

   1 /*
   2  * HD-audio controller helpers
   3  */
   4
   5 #include <linux/kernel.h>
   6 #include <linux/delay.h>
   7 #include <linux/export.h>
   8 #include <sound/core.h>
   9 #include <sound/hdaudio.h>
  10 #include <sound/hda_register.h>
  11
  12 /* clear CORB read pointer properly */
  13 static void azx_clear_corbrp(struct hdac_bus *bus)
  14 {
  15         int timeout;
  16
  17         for (timeout = 1000; timeout > 0; timeout--) {
  18                 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
  19                         break;
  20                 udelay(1);
  21         }
  22         if (timeout <= 0)
  23                 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
  24                         snd_hdac_chip_readw(bus, CORBRP));
  25
  26         snd_hdac_chip_writew(bus, CORBRP, 0);
  27         for (timeout = 1000; timeout > 0; timeout--) {
  28                 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
  29                         break;
  30                 udelay(1);
  31         }
  32         if (timeout <= 0)
  33                 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
  34                         snd_hdac_chip_readw(bus, CORBRP));
  35 }
  36
  37 /**
  38  * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
  39  * @bus: HD-audio core bus
  40  */
  41 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
  42 {
  43         spin_lock_irq(&bus->reg_lock);
  44         /* CORB set up */
  45         bus->corb.addr = bus->rb.addr;
  46         bus->corb.buf = (__le32 *)bus->rb.area;
  47         snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
  48         snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
  49
  50         /* set the corb size to 256 entries (ULI requires explicitly) */
  51         snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
  52         /* set the corb write pointer to 0 */
  53         snd_hdac_chip_writew(bus, CORBWP, 0);
  54
  55         /* reset the corb hw read pointer */
  56         snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
  57         if (!bus->corbrp_self_clear)
  58                 azx_clear_corbrp(bus);
  59
  60         /* enable corb dma */
  61         snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
  62
  63         /* RIRB set up */
  64         bus->rirb.addr = bus->rb.addr + 2048;
  65         bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
  66         bus->rirb.wp = bus->rirb.rp = 0;
  67         memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
  68         snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
  69         snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
  70
  71         /* set the rirb size to 256 entries (ULI requires explicitly) */
  72         snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
  73         /* reset the rirb hw write pointer */
  74         snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
  75         /* set N=1, get RIRB response interrupt for new entry */
  76         snd_hdac_chip_writew(bus, RINTCNT, 1);
  77         /* enable rirb dma and response irq */
  78         snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
  79         spin_unlock_irq(&bus->reg_lock);
  80 }
  81 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
  82
  83 /* wait for cmd dmas till they are stopped */
  84 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
  85 {
  86         unsigned long timeout;
  87
  88         timeout = jiffies + msecs_to_jiffies(100);
  89         while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
  90                 && time_before(jiffies, timeout))
  91                 udelay(10);
  92
  93         timeout = jiffies + msecs_to_jiffies(100);
  94         while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
  95                 && time_before(jiffies, timeout))
  96                 udelay(10);
  97 }
  98
  99 /**
 100  * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
 101  * @bus: HD-audio core bus
 102  */
 103 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
 104 {
 105         spin_lock_irq(&bus->reg_lock);
 106         /* disable ringbuffer DMAs */
 107         snd_hdac_chip_writeb(bus, RIRBCTL, 0);
 108         snd_hdac_chip_writeb(bus, CORBCTL, 0);
 109         spin_unlock_irq(&bus->reg_lock);
 110
 111         hdac_wait_for_cmd_dmas(bus);
 112
 113         spin_lock_irq(&bus->reg_lock);
 114         /* disable unsolicited responses */
 115         snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
 116         spin_unlock_irq(&bus->reg_lock);
 117 }
 118 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
 119
 120 static unsigned int azx_command_addr(u32 cmd)
 121 {
 122         unsigned int addr = cmd >> 28;
 123
 124         if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
 125                 addr = 0;
 126         return addr;
 127 }
 128
 129 /**
 130  * snd_hdac_bus_send_cmd - send a command verb via CORB
 131  * @bus: HD-audio core bus
 132  * @val: encoded verb value to send
 133  *
 134  * Returns zero for success or a negative error code.
 135  */
 136 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
 137 {
 138         unsigned int addr = azx_command_addr(val);
 139         unsigned int wp, rp;
 140
 141         spin_lock_irq(&bus->reg_lock);
 142
 143         bus->last_cmd[azx_command_addr(val)] = val;
 144
 145         /* add command to corb */
 146         wp = snd_hdac_chip_readw(bus, CORBWP);
 147         if (wp == 0xffff) {
 148                 /* something wrong, controller likely turned to D3 */
 149                 spin_unlock_irq(&bus->reg_lock);
 150                 return -EIO;
 151         }
 152         wp++;
 153         wp %= AZX_MAX_CORB_ENTRIES;
 154
 155         rp = snd_hdac_chip_readw(bus, CORBRP);
 156         if (wp == rp) {
 157                 /* oops, it's full */
 158                 spin_unlock_irq(&bus->reg_lock);
 159                 return -EAGAIN;
 160         }
 161
 162         bus->rirb.cmds[addr]++;
 163         bus->corb.buf[wp] = cpu_to_le32(val);
 164         snd_hdac_chip_writew(bus, CORBWP, wp);
 165
 166         spin_unlock_irq(&bus->reg_lock);
 167
 168         return 0;
 169 }
 170 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
 171
 172 #define AZX_RIRB_EX_UNSOL_EV    (1<<4)
 173
 174 /**
 175  * snd_hdac_bus_update_rirb - retrieve RIRB entries
 176  * @bus: HD-audio core bus
 177  *
 178  * Usually called from interrupt handler.
 179  */
 180 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
 181 {
 182         unsigned int rp, wp;
 183         unsigned int addr;
 184         u32 res, res_ex;
 185
 186         wp = snd_hdac_chip_readw(bus, RIRBWP);
 187         if (wp == 0xffff) {
 188                 /* something wrong, controller likely turned to D3 */
 189                 return;
 190         }
 191
 192         if (wp == bus->rirb.wp)
 193                 return;
 194         bus->rirb.wp = wp;
 195
 196         while (bus->rirb.rp != wp) {
 197                 bus->rirb.rp++;
 198                 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
 199
 200                 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 201                 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
 202                 res = le32_to_cpu(bus->rirb.buf[rp]);
 203                 addr = res_ex & 0xf;
 204                 if (addr >= HDA_MAX_CODECS) {
 205                         dev_err(bus->dev,
 206                                 "spurious response %#x:%#x, rp = %d, wp = %d",
 207                                 res, res_ex, bus->rirb.rp, wp);
 208                         snd_BUG();
 209                 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
 210                         snd_hdac_bus_queue_event(bus, res, res_ex);
 211                 else if (bus->rirb.cmds[addr]) {
 212                         bus->rirb.res[addr] = res;
 213                         bus->rirb.cmds[addr]--;
 214                 } else {
 215                         dev_err_ratelimited(bus->dev,
 216                                 "spurious response %#x:%#x, last cmd=%#08x\n",
 217                                 res, res_ex, bus->last_cmd[addr]);
 218                 }
 219         }
 220 }
 221 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
 222
 223 /**
 224  * snd_hdac_bus_get_response - receive a response via RIRB
 225  * @bus: HD-audio core bus
 226  * @addr: codec address
 227  * @res: pointer to store the value, NULL when not needed
 228  *
 229  * Returns zero if a value is read, or a negative error code.
 230  */
 231 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
 232                               unsigned int *res)
 233 {
 234         unsigned long timeout;
 235         unsigned long loopcounter;
 236
 237         timeout = jiffies + msecs_to_jiffies(1000);
 238
 239         for (loopcounter = 0;; loopcounter++) {
 240                 spin_lock_irq(&bus->reg_lock);
 241                 if (!bus->rirb.cmds[addr]) {
 242                         if (res)
 243                                 *res = bus->rirb.res[addr]; /* the last value */
 244                         spin_unlock_irq(&bus->reg_lock);
 245                         return 0;
 246                 }
 247                 spin_unlock_irq(&bus->reg_lock);
 248                 if (time_after(jiffies, timeout))
 249                         break;
 250                 if (loopcounter > 3000)
 251                         msleep(2); /* temporary workaround */
 252                 else {
 253                         udelay(10);
 254                         cond_resched();
 255                 }
 256         }
 257
 258         return -EIO;
 259 }
 260 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
 261
 262 #define HDAC_MAX_CAPS 10
 263 /**
 264  * snd_hdac_bus_parse_capabilities - parse capability structure
 265  * @bus: the pointer to bus object
 266  *
 267  * Returns 0 if successful, or a negative error code.
 268  */
 269 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
 270 {
 271         unsigned int cur_cap;
 272         unsigned int offset;
 273         unsigned int counter = 0;
 274
 275         offset = snd_hdac_chip_readw(bus, LLCH);
 276
 277         /* Lets walk the linked capabilities list */
 278         do {
 279                 cur_cap = _snd_hdac_chip_readl(bus, offset);
 280
 281                 dev_dbg(bus->dev, "Capability version: 0x%x\n",
 282                         (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF);
 283
 284                 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
 285                         (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
 286
 287                 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
 288                 case AZX_ML_CAP_ID:
 289                         dev_dbg(bus->dev, "Found ML capability\n");
 290                         bus->mlcap = bus->remap_addr + offset;
 291                         break;
 292
 293                 case AZX_GTS_CAP_ID:
 294                         dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
 295                         bus->gtscap = bus->remap_addr + offset;
 296                         break;
 297
 298                 case AZX_PP_CAP_ID:
 299                         /* PP capability found, the Audio DSP is present */
 300                         dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
 301                         bus->ppcap = bus->remap_addr + offset;
 302                         break;
 303
 304                 case AZX_SPB_CAP_ID:
 305                         /* SPIB capability found, handler function */
 306                         dev_dbg(bus->dev, "Found SPB capability\n");
 307                         bus->spbcap = bus->remap_addr + offset;
 308                         break;
 309
 310                 case AZX_DRSM_CAP_ID:
 311                         /* DMA resume  capability found, handler function */
 312                         dev_dbg(bus->dev, "Found DRSM capability\n");
 313                         bus->drsmcap = bus->remap_addr + offset;
 314                         break;
 315
 316                 default:
 317                         dev_dbg(bus->dev, "Unknown capability %d\n", cur_cap);
 318                         break;
 319                 }
 320
 321                 counter++;
 322
 323                 if (counter > HDAC_MAX_CAPS) {
 324                         dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
 325                         break;
 326                 }
 327
 328                 /* read the offset of next capability */
 329                 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
 330
 331         } while (offset);
 332
 333         return 0;
 334 }
 335 EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities);
 336
 337 /*
 338  * Lowlevel interface
 339  */
 340
 341 /**
 342  * snd_hdac_bus_enter_link_reset - enter link reset
 343  * @bus: HD-audio core bus
 344  *
 345  * Enter to the link reset state.
 346  */
 347 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
 348 {
 349         unsigned long timeout;
 350
 351         /* reset controller */
 352         snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
 353
 354         timeout = jiffies + msecs_to_jiffies(100);
 355         while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
 356                time_before(jiffies, timeout))
 357                 usleep_range(500, 1000);
 358 }
 359 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
 360
 361 /**
 362  * snd_hdac_bus_exit_link_reset - exit link reset
 363  * @bus: HD-audio core bus
 364  *
 365  * Exit from the link reset state.
 366  */
 367 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
 368 {
 369         unsigned long timeout;
 370
 371         snd_hdac_chip_updateb(bus, GCTL, 0, AZX_GCTL_RESET);
 372
 373         timeout = jiffies + msecs_to_jiffies(100);
 374         while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
 375                 usleep_range(500, 1000);
 376 }
 377 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
 378
 379 /* reset codec link */
 380 static int azx_reset(struct hdac_bus *bus, bool full_reset)
 381 {
 382         if (!full_reset)
 383                 goto skip_reset;
 384
 385         /* clear STATESTS */
 386         snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
 387
 388         /* reset controller */
 389         snd_hdac_bus_enter_link_reset(bus);
 390
 391         /* delay for >= 100us for codec PLL to settle per spec
 392          * Rev 0.9 section 5.5.1
 393          */
 394         usleep_range(500, 1000);
 395
 396         /* Bring controller out of reset */
 397         snd_hdac_bus_exit_link_reset(bus);
 398
 399         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 400         usleep_range(1000, 1200);
 401
 402  skip_reset:
 403         /* check to see if controller is ready */
 404         if (!snd_hdac_chip_readb(bus, GCTL)) {
 405                 dev_dbg(bus->dev, "azx_reset: controller not ready!\n");
 406                 return -EBUSY;
 407         }
 408
 409         /* Accept unsolicited responses */
 410         snd_hdac_chip_updatel(bus, GCTL, 0, AZX_GCTL_UNSOL);
 411
 412         /* detect codecs */
 413         if (!bus->codec_mask) {
 414                 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
 415                 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
 416         }
 417
 418         return 0;
 419 }
 420
 421 /* enable interrupts */
 422 static void azx_int_enable(struct hdac_bus *bus)
 423 {
 424         /* enable controller CIE and GIE */
 425         snd_hdac_chip_updatel(bus, INTCTL, 0, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
 426 }
 427
 428 /* disable interrupts */
 429 static void azx_int_disable(struct hdac_bus *bus)
 430 {
 431         struct hdac_stream *azx_dev;
 432
 433         /* disable interrupts in stream descriptor */
 434         list_for_each_entry(azx_dev, &bus->stream_list, list)
 435                 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
 436
 437         /* disable SIE for all streams */
 438         snd_hdac_chip_writeb(bus, INTCTL, 0);
 439
 440         /* disable controller CIE and GIE */
 441         snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
 442 }
 443
 444 /* clear interrupts */
 445 static void azx_int_clear(struct hdac_bus *bus)
 446 {
 447         struct hdac_stream *azx_dev;
 448
 449         /* clear stream status */
 450         list_for_each_entry(azx_dev, &bus->stream_list, list)
 451                 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
 452
 453         /* clear STATESTS */
 454         snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
 455
 456         /* clear rirb status */
 457         snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
 458
 459         /* clear int status */
 460         snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
 461 }
 462
 463 /**
 464  * snd_hdac_bus_init_chip - reset and start the controller registers
 465  * @bus: HD-audio core bus
 466  * @full_reset: Do full reset
 467  */
 468 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
 469 {
 470         if (bus->chip_init)
 471                 return false;
 472
 473         /* reset controller */
 474         azx_reset(bus, full_reset);
 475
 476         /* initialize interrupts */
 477         azx_int_clear(bus);
 478         azx_int_enable(bus);
 479
 480         /* initialize the codec command I/O */
 481         snd_hdac_bus_init_cmd_io(bus);
 482
 483         /* program the position buffer */
 484         if (bus->use_posbuf && bus->posbuf.addr) {
 485                 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
 486                 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
 487         }
 488
 489         bus->chip_init = true;
 490         return true;
 491 }
 492 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
 493
 494 /**
 495  * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
 496  * @bus: HD-audio core bus
 497  */
 498 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
 499 {
 500         if (!bus->chip_init)
 501                 return;
 502
 503         /* disable interrupts */
 504         azx_int_disable(bus);
 505         azx_int_clear(bus);
 506
 507         /* disable CORB/RIRB */
 508         snd_hdac_bus_stop_cmd_io(bus);
 509
 510         /* disable position buffer */
 511         if (bus->posbuf.addr) {
 512                 snd_hdac_chip_writel(bus, DPLBASE, 0);
 513                 snd_hdac_chip_writel(bus, DPUBASE, 0);
 514         }
 515
 516         bus->chip_init = false;
 517 }
 518 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
 519
 520 /**
 521  * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
 522  * @bus: HD-audio core bus
 523  * @status: INTSTS register value
 524  * @ask: callback to be called for woken streams
 525  *
 526  * Returns the bits of handled streams, or zero if no stream is handled.
 527  */
 528 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
 529                                     void (*ack)(struct hdac_bus *,
 530                                                 struct hdac_stream *))
 531 {
 532         struct hdac_stream *azx_dev;
 533         u8 sd_status;
 534         int handled = 0;
 535
 536         list_for_each_entry(azx_dev, &bus->stream_list, list) {
 537                 if (status & azx_dev->sd_int_sta_mask) {
 538                         sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
 539                         snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
 540                         handled |= 1 << azx_dev->index;
 541                         if (!azx_dev->substream || !azx_dev->running ||
 542                             !(sd_status & SD_INT_COMPLETE))
 543                                 continue;
 544                         if (ack)
 545                                 ack(bus, azx_dev);
 546                 }
 547         }
 548         return handled;
 549 }
 550 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
 551
 552 /**
 553  * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
 554  * @bus: HD-audio core bus
 555  *
 556  * Call this after assigning the all streams.
 557  * Returns zero for success, or a negative error code.
 558  */
 559 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
 560 {
 561         struct hdac_stream *s;
 562         int num_streams = 0;
 563         int err;
 564
 565         list_for_each_entry(s, &bus->stream_list, list) {
 566                 /* allocate memory for the BDL for each stream */
 567                 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
 568                                                    BDL_SIZE, &s->bdl);
 569                 num_streams++;
 570                 if (err < 0)
 571                         return -ENOMEM;
 572         }
 573
 574         if (WARN_ON(!num_streams))
 575                 return -EINVAL;
 576         /* allocate memory for the position buffer */
 577         err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
 578                                            num_streams * 8, &bus->posbuf);
 579         if (err < 0)
 580                 return -ENOMEM;
 581         list_for_each_entry(s, &bus->stream_list, list)
 582                 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
 583
 584         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 585         return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
 586                                             PAGE_SIZE, &bus->rb);
 587 }
 588 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
 589
 590 /**
 591  * snd_hdac_bus_free_stream_pages - release BDL and other buffers
 592  * @bus: HD-audio core bus
 593  */
 594 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
 595 {
 596         struct hdac_stream *s;
 597
 598         list_for_each_entry(s, &bus->stream_list, list) {
 599                 if (s->bdl.area)
 600                         bus->io_ops->dma_free_pages(bus, &s->bdl);
 601         }
 602
 603         if (bus->rb.area)
 604                 bus->io_ops->dma_free_pages(bus, &bus->rb);
 605         if (bus->posbuf.area)
 606                 bus->io_ops->dma_free_pages(bus, &bus->posbuf);
 607 }
 608 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);