sound/oss/ad1848.c

   1 /*
   2  * sound/oss/ad1848.c
   3  *
   4  * The low level driver for the AD1848/CS4248 codec chip which
   5  * is used for example in the MS Sound System.
   6  *
   7  * The CS4231 which is used in the GUS MAX and some other cards is
   8  * upwards compatible with AD1848 and this driver is able to drive it.
   9  *
  10  * CS4231A and AD1845 are upward compatible with CS4231. However
  11  * the new features of these chips are different.
  12  *
  13  * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
  14  * CS4232A is an improved version of CS4232.
  15  *
  16  *
  17  *
  18  * Copyright (C) by Hannu Savolainen 1993-1997
  19  *
  20  * OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
  21  * Version 2 (June 1991). See the "COPYING" file distributed with this software
  22  * for more info.
  23  *
  24  *
  25  * Thomas Sailer        : ioctl code reworked (vmalloc/vfree removed)
  26  *                        general sleep/wakeup clean up.
  27  * Alan Cox             : reformatted. Fixed SMP bugs. Moved to kernel alloc/free
  28  *                        of irqs. Use dev_id.
  29  * Christoph Hellwig    : adapted to module_init/module_exit
  30  * Aki Laukkanen        : added power management support
  31  * Arnaldo C. de Melo   : added missing restore_flags in ad1848_resume
  32  * Miguel Freitas       : added ISA PnP support
  33  * Alan Cox             : Added CS4236->4239 identification
  34  * Daniel T. Cobra      : Alernate config/mixer for later chips
  35  * Alan Cox             : Merged chip idents and config code
  36  *
  37  * TODO
  38  *              APM save restore assist code on IBM thinkpad
  39  *
  40  * Status:
  41  *              Tested. Believed fully functional.
  42  */
  43
  44 #include <linux/init.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/module.h>
  47 #include <linux/stddef.h>
  48 #include <linux/slab.h>
  49 #include <linux/isapnp.h>
  50 #include <linux/pnp.h>
  51 #include <linux/spinlock.h>
  52
  53 #include "sound_config.h"
  54
  55 #include "ad1848.h"
  56 #include "ad1848_mixer.h"
  57
  58 typedef struct
  59 {
  60         spinlock_t      lock;
  61         int             base;
  62         int             irq;
  63         int             dma1, dma2;
  64         int             dual_dma;       /* 1, when two DMA channels allocated */
  65         int             subtype;
  66         unsigned char   MCE_bit;
  67         unsigned char   saved_regs[64]; /* Includes extended register space */
  68         int             debug_flag;
  69
  70         int             audio_flags;
  71         int             record_dev, playback_dev;
  72
  73         int             xfer_count;
  74         int             audio_mode;
  75         int             open_mode;
  76         int             intr_active;
  77         char           *chip_name, *name;
  78         int             model;
  79 #define MD_1848         1
  80 #define MD_4231         2
  81 #define MD_4231A        3
  82 #define MD_1845         4
  83 #define MD_4232         5
  84 #define MD_C930         6
  85 #define MD_IWAVE        7
  86 #define MD_4235         8 /* Crystal Audio CS4235  */
  87 #define MD_1845_SSCAPE  9 /* Ensoniq Soundscape PNP*/
  88 #define MD_4236         10 /* 4236 and higher */
  89 #define MD_42xB         11 /* CS 42xB */
  90 #define MD_4239         12 /* CS4239 */
  91
  92         /* Mixer parameters */
  93         int             recmask;
  94         int             supported_devices, orig_devices;
  95         int             supported_rec_devices, orig_rec_devices;
  96         int            *levels;
  97         short           mixer_reroute[32];
  98         int             dev_no;
  99         volatile unsigned long timer_ticks;
 100         int             timer_running;
 101         int             irq_ok;
 102         mixer_ents     *mix_devices;
 103         int             mixer_output_port;
 104 } ad1848_info;
 105
 106 typedef struct ad1848_port_info
 107 {
 108         int             open_mode;
 109         int             speed;
 110         unsigned char   speed_bits;
 111         int             channels;
 112         int             audio_format;
 113         unsigned char   format_bits;
 114 }
 115 ad1848_port_info;
 116
 117 static struct address_info cfg;
 118 static int nr_ad1848_devs;
 119
 120 static bool deskpro_xl;
 121 static bool deskpro_m;
 122 static bool soundpro;
 123
 124 static volatile signed char irq2dev[17] = {
 125         -1, -1, -1, -1, -1, -1, -1, -1,
 126         -1, -1, -1, -1, -1, -1, -1, -1, -1
 127 };
 128
 129 #ifndef EXCLUDE_TIMERS
 130 static int timer_installed = -1;
 131 #endif
 132
 133 static int loaded;
 134
 135 static int ad_format_mask[13 /*devc->model */ ] =
 136 {
 137         0,
 138         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
 139         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 140         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 141         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,       /* AD1845 */
 142         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 143         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 144         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 145         AFMT_U8 | AFMT_S16_LE /* CS4235 */,
 146         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW        /* Ensoniq Soundscape*/,
 147         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 148         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
 149         AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM
 150 };
 151
 152 static ad1848_info adev_info[MAX_AUDIO_DEV];
 153
 154 #define io_Index_Addr(d)        ((d)->base)
 155 #define io_Indexed_Data(d)      ((d)->base+1)
 156 #define io_Status(d)            ((d)->base+2)
 157 #define io_Polled_IO(d)         ((d)->base+3)
 158
 159 static struct {
 160      unsigned char flags;
 161 #define CAP_F_TIMER 0x01
 162 } capabilities [10 /*devc->model */ ] = {
 163      {0}
 164     ,{0}           /* MD_1848  */
 165     ,{CAP_F_TIMER} /* MD_4231  */
 166     ,{CAP_F_TIMER} /* MD_4231A */
 167     ,{CAP_F_TIMER} /* MD_1845  */
 168     ,{CAP_F_TIMER} /* MD_4232  */
 169     ,{0}           /* MD_C930  */
 170     ,{CAP_F_TIMER} /* MD_IWAVE */
 171     ,{0}           /* MD_4235  */
 172     ,{CAP_F_TIMER} /* MD_1845_SSCAPE */
 173 };
 174
 175 #ifdef CONFIG_PNP
 176 static int isapnp       = 1;
 177 static int isapnpjump;
 178 static bool reverse;
 179
 180 static int audio_activated;
 181 #else
 182 static int isapnp;
 183 #endif
 184
 185
 186
 187 static int      ad1848_open(int dev, int mode);
 188 static void     ad1848_close(int dev);
 189 static void     ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
 190 static void     ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
 191 static int      ad1848_prepare_for_output(int dev, int bsize, int bcount);
 192 static int      ad1848_prepare_for_input(int dev, int bsize, int bcount);
 193 static void     ad1848_halt(int dev);
 194 static void     ad1848_halt_input(int dev);
 195 static void     ad1848_halt_output(int dev);
 196 static void     ad1848_trigger(int dev, int bits);
 197 static irqreturn_t adintr(int irq, void *dev_id);
 198
 199 #ifndef EXCLUDE_TIMERS
 200 static int ad1848_tmr_install(int dev);
 201 static void ad1848_tmr_reprogram(int dev);
 202 #endif
 203
 204 static int ad_read(ad1848_info * devc, int reg)
 205 {
 206         int x;
 207         int timeout = 900000;
 208
 209         while (timeout > 0 && inb(devc->base) == 0x80)  /*Are we initializing */
 210                 timeout--;
 211
 212         if(reg < 32)
 213         {
 214                 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 215                 x = inb(io_Indexed_Data(devc));
 216         }
 217         else
 218         {
 219                 int xreg, xra;
 220
 221                 xreg = (reg & 0xff) - 32;
 222                 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
 223                 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 224                 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
 225                 x = inb(io_Indexed_Data(devc));
 226         }
 227
 228         return x;
 229 }
 230
 231 static void ad_write(ad1848_info * devc, int reg, int data)
 232 {
 233         int timeout = 900000;
 234
 235         while (timeout > 0 && inb(devc->base) == 0x80)  /* Are we initializing */
 236                 timeout--;
 237
 238         if(reg < 32)
 239         {
 240                 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 241                 outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
 242         }
 243         else
 244         {
 245                 int xreg, xra;
 246
 247                 xreg = (reg & 0xff) - 32;
 248                 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
 249                 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
 250                 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
 251                 outb((unsigned char) (data & 0xff), io_Indexed_Data(devc));
 252         }
 253 }
 254
 255 static void wait_for_calibration(ad1848_info * devc)
 256 {
 257         int timeout = 0;
 258
 259         /*
 260          * Wait until the auto calibration process has finished.
 261          *
 262          * 1)       Wait until the chip becomes ready (reads don't return 0x80).
 263          * 2)       Wait until the ACI bit of I11 gets on and then off.
 264          */
 265
 266         timeout = 100000;
 267         while (timeout > 0 && inb(devc->base) == 0x80)
 268                 timeout--;
 269         if (inb(devc->base) & 0x80)
 270                 printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");
 271
 272         timeout = 100;
 273         while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
 274                 timeout--;
 275         if (!(ad_read(devc, 11) & 0x20))
 276                 return;
 277
 278         timeout = 80000;
 279         while (timeout > 0 && (ad_read(devc, 11) & 0x20))
 280                 timeout--;
 281         if (ad_read(devc, 11) & 0x20)
 282                 if ((devc->model != MD_1845) && (devc->model != MD_1845_SSCAPE))
 283                         printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
 284 }
 285
 286 static void ad_mute(ad1848_info * devc)
 287 {
 288         int i;
 289         unsigned char prev;
 290
 291         /*
 292          * Save old register settings and mute output channels
 293          */
 294
 295         for (i = 6; i < 8; i++)
 296         {
 297                 prev = devc->saved_regs[i] = ad_read(devc, i);
 298         }
 299
 300 }
 301
 302 static void ad_unmute(ad1848_info * devc)
 303 {
 304 }
 305
 306 static void ad_enter_MCE(ad1848_info * devc)
 307 {
 308         int timeout = 1000;
 309         unsigned short prev;
 310
 311         while (timeout > 0 && inb(devc->base) == 0x80)  /*Are we initializing */
 312                 timeout--;
 313
 314         devc->MCE_bit = 0x40;
 315         prev = inb(io_Index_Addr(devc));
 316         if (prev & 0x40)
 317         {
 318                 return;
 319         }
 320         outb((devc->MCE_bit), io_Index_Addr(devc));
 321 }
 322
 323 static void ad_leave_MCE(ad1848_info * devc)
 324 {
 325         unsigned char prev, acal;
 326         int timeout = 1000;
 327
 328         while (timeout > 0 && inb(devc->base) == 0x80)  /*Are we initializing */
 329                 timeout--;
 330
 331         acal = ad_read(devc, 9);
 332
 333         devc->MCE_bit = 0x00;
 334         prev = inb(io_Index_Addr(devc));
 335         outb((0x00), io_Index_Addr(devc));      /* Clear the MCE bit */
 336
 337         if ((prev & 0x40) == 0) /* Not in MCE mode */
 338         {
 339                 return;
 340         }
 341         outb((0x00), io_Index_Addr(devc));      /* Clear the MCE bit */
 342         if (acal & 0x08)        /* Auto calibration is enabled */
 343                 wait_for_calibration(devc);
 344 }
 345
 346 static int ad1848_set_recmask(ad1848_info * devc, int mask)
 347 {
 348         unsigned char   recdev;
 349         int             i, n;
 350         unsigned long flags;
 351
 352         mask &= devc->supported_rec_devices;
 353
 354         /* Rename the mixer bits if necessary */
 355         for (i = 0; i < 32; i++)
 356         {
 357                 if (devc->mixer_reroute[i] != i)
 358                 {
 359                         if (mask & (1 << i))
 360                         {
 361                                 mask &= ~(1 << i);
 362                                 mask |= (1 << devc->mixer_reroute[i]);
 363                         }
 364                 }
 365         }
 366
 367         n = 0;
 368         for (i = 0; i < 32; i++)        /* Count selected device bits */
 369                 if (mask & (1 << i))
 370                         n++;
 371
 372         spin_lock_irqsave(&devc->lock,flags);
 373         if (!soundpro) {
 374                 if (n == 0)
 375                         mask = SOUND_MASK_MIC;
 376                 else if (n != 1) {      /* Too many devices selected */
 377                         mask &= ~devc->recmask; /* Filter out active settings */
 378
 379                         n = 0;
 380                         for (i = 0; i < 32; i++)        /* Count selected device bits */
 381                                 if (mask & (1 << i))
 382                                         n++;
 383
 384                         if (n != 1)
 385                                 mask = SOUND_MASK_MIC;
 386                 }
 387                 switch (mask) {
 388                 case SOUND_MASK_MIC:
 389                         recdev = 2;
 390                         break;
 391
 392                 case SOUND_MASK_LINE:
 393                 case SOUND_MASK_LINE3:
 394                         recdev = 0;
 395                         break;
 396
 397                 case SOUND_MASK_CD:
 398                 case SOUND_MASK_LINE1:
 399                         recdev = 1;
 400                         break;
 401
 402                 case SOUND_MASK_IMIX:
 403                         recdev = 3;
 404                         break;
 405
 406                 default:
 407                         mask = SOUND_MASK_MIC;
 408                         recdev = 2;
 409                 }
 410
 411                 recdev <<= 6;
 412                 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
 413                 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
 414         } else { /* soundpro */
 415                 unsigned char val;
 416                 int set_rec_bit;
 417                 int j;
 418
 419                 for (i = 0; i < 32; i++) {      /* For each bit */
 420                         if ((devc->supported_rec_devices & (1 << i)) == 0)
 421                                 continue;       /* Device not supported */
 422
 423                         for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
 424                                 if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
 425                                         continue;
 426
 427                                 /*
 428                                  * This is tricky:
 429                                  * set_rec_bit becomes 1 if the corresponding bit in mask is set
 430                                  * then it gets flipped if the polarity is inverse
 431                                  */
 432                                 set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;
 433
 434                                 val = ad_read(devc, devc->mix_devices[i][j].recreg);
 435                                 val &= ~(1 << devc->mix_devices[i][j].recpos);
 436                                 val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
 437                                 ad_write(devc, devc->mix_devices[i][j].recreg, val);
 438                         }
 439                 }
 440         }
 441         spin_unlock_irqrestore(&devc->lock,flags);
 442
 443         /* Rename the mixer bits back if necessary */
 444         for (i = 0; i < 32; i++)
 445         {
 446                 if (devc->mixer_reroute[i] != i)
 447                 {
 448                         if (mask & (1 << devc->mixer_reroute[i]))
 449                         {
 450                                 mask &= ~(1 << devc->mixer_reroute[i]);
 451                                 mask |= (1 << i);
 452                         }
 453                 }
 454         }
 455         devc->recmask = mask;
 456         return mask;
 457 }
 458
 459 static void oss_change_bits(ad1848_info *devc, unsigned char *regval,
 460                         unsigned char *muteval, int dev, int chn, int newval)
 461 {
 462         unsigned char mask;
 463         int shift;
 464         int mute;
 465         int mutemask;
 466         int set_mute_bit;
 467
 468         set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;
 469
 470         if (devc->mix_devices[dev][chn].polarity == 1)  /* Reverse */
 471                 newval = 100 - newval;
 472
 473         mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
 474         shift = devc->mix_devices[dev][chn].bitpos;
 475
 476         if (devc->mix_devices[dev][chn].mutepos == 8)
 477         {                       /* if there is no mute bit */
 478                 mute = 0;       /* No mute bit; do nothing special */
 479                 mutemask = ~0;  /* No mute bit; do nothing special */
 480         }
 481         else
 482         {
 483                 mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
 484                 mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
 485         }
 486
 487         newval = (int) ((newval * mask) + 50) / 100;    /* Scale it */
 488         *regval &= ~(mask << shift);                    /* Clear bits */
 489         *regval |= (newval & mask) << shift;            /* Set new value */
 490
 491         *muteval &= mutemask;
 492         *muteval |= mute;
 493 }
 494
 495 static int ad1848_mixer_get(ad1848_info * devc, int dev)
 496 {
 497         if (!((1 << dev) & devc->supported_devices))
 498                 return -EINVAL;
 499
 500         dev = devc->mixer_reroute[dev];
 501
 502         return devc->levels[dev];
 503 }
 504
 505 static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
 506 {
 507         int regoffs, muteregoffs;
 508         unsigned char val, muteval;
 509         unsigned long flags;
 510
 511         regoffs = devc->mix_devices[dev][channel].regno;
 512         muteregoffs = devc->mix_devices[dev][channel].mutereg;
 513         val = ad_read(devc, regoffs);
 514
 515         if (muteregoffs != regoffs) {
 516                 muteval = ad_read(devc, muteregoffs);
 517                 oss_change_bits(devc, &val, &muteval, dev, channel, value);
 518         }
 519         else
 520                 oss_change_bits(devc, &val, &val, dev, channel, value);
 521
 522         spin_lock_irqsave(&devc->lock,flags);
 523         ad_write(devc, regoffs, val);
 524         devc->saved_regs[regoffs] = val;
 525         if (muteregoffs != regoffs) {
 526                 ad_write(devc, muteregoffs, muteval);
 527                 devc->saved_regs[muteregoffs] = muteval;
 528         }
 529         spin_unlock_irqrestore(&devc->lock,flags);
 530 }
 531
 532 static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
 533 {
 534         int left = value & 0x000000ff;
 535         int right = (value & 0x0000ff00) >> 8;
 536         int retvol;
 537
 538         if (dev > 31)
 539                 return -EINVAL;
 540
 541         if (!(devc->supported_devices & (1 << dev)))
 542                 return -EINVAL;
 543
 544         dev = devc->mixer_reroute[dev];
 545
 546         if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
 547                 return -EINVAL;
 548
 549         if (left > 100)
 550                 left = 100;
 551         if (right > 100)
 552                 right = 100;
 553
 554         if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)       /* Mono control */
 555                 right = left;
 556
 557         retvol = left | (right << 8);
 558
 559         /* Scale volumes */
 560         left = mix_cvt[left];
 561         right = mix_cvt[right];
 562
 563         devc->levels[dev] = retvol;
 564
 565         /*
 566          * Set the left channel
 567          */
 568         ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);
 569
 570         /*
 571          * Set the right channel
 572          */
 573         if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
 574                 goto out;
 575         ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);
 576
 577  out:
 578         return retvol;
 579 }
 580
 581 static void ad1848_mixer_reset(ad1848_info * devc)
 582 {
 583         int i;
 584         char name[32];
 585         unsigned long flags;
 586
 587         devc->mix_devices = &(ad1848_mix_devices[0]);
 588
 589         sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);
 590
 591         for (i = 0; i < 32; i++)
 592                 devc->mixer_reroute[i] = i;
 593
 594         devc->supported_rec_devices = MODE1_REC_DEVICES;
 595
 596         switch (devc->model)
 597         {
 598                 case MD_4231:
 599                 case MD_4231A:
 600                 case MD_1845:
 601                 case MD_1845_SSCAPE:
 602                         devc->supported_devices = MODE2_MIXER_DEVICES;
 603                         break;
 604
 605                 case MD_C930:
 606                         devc->supported_devices = C930_MIXER_DEVICES;
 607                         devc->mix_devices = &(c930_mix_devices[0]);
 608                         break;
 609
 610                 case MD_IWAVE:
 611                         devc->supported_devices = MODE3_MIXER_DEVICES;
 612                         devc->mix_devices = &(iwave_mix_devices[0]);
 613                         break;
 614
 615                 case MD_42xB:
 616                 case MD_4239:
 617                         devc->mix_devices = &(cs42xb_mix_devices[0]);
 618                         devc->supported_devices = MODE3_MIXER_DEVICES;
 619                         break;
 620                 case MD_4232:
 621                 case MD_4235:
 622                 case MD_4236:
 623                         devc->supported_devices = MODE3_MIXER_DEVICES;
 624                         break;
 625
 626                 case MD_1848:
 627                         if (soundpro) {
 628                                 devc->supported_devices = SPRO_MIXER_DEVICES;
 629                                 devc->supported_rec_devices = SPRO_REC_DEVICES;
 630                                 devc->mix_devices = &(spro_mix_devices[0]);
 631                                 break;
 632                         }
 633
 634                 default:
 635                         devc->supported_devices = MODE1_MIXER_DEVICES;
 636         }
 637
 638         devc->orig_devices = devc->supported_devices;
 639         devc->orig_rec_devices = devc->supported_rec_devices;
 640
 641         devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);
 642
 643         for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
 644         {
 645                 if (devc->supported_devices & (1 << i))
 646                         ad1848_mixer_set(devc, i, devc->levels[i]);
 647         }
 648
 649         ad1848_set_recmask(devc, SOUND_MASK_MIC);
 650
 651         devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
 652
 653         spin_lock_irqsave(&devc->lock,flags);
 654         if (!soundpro) {
 655                 if (devc->mixer_output_port & AUDIO_SPEAKER)
 656                         ad_write(devc, 26, ad_read(devc, 26) & ~0x40);  /* Unmute mono out */
 657                 else
 658                         ad_write(devc, 26, ad_read(devc, 26) | 0x40);   /* Mute mono out */
 659         } else {
 660                 /*
 661                  * From the "wouldn't it be nice if the mixer API had (better)
 662                  * support for custom stuff" category
 663                  */
 664                 /* Enable surround mode and SB16 mixer */
 665                 ad_write(devc, 16, 0x60);
 666         }
 667         spin_unlock_irqrestore(&devc->lock,flags);
 668 }
 669
 670 static int ad1848_mixer_ioctl(int dev, unsigned int cmd, void __user *arg)
 671 {
 672         ad1848_info *devc = mixer_devs[dev]->devc;
 673         int val;
 674
 675         if (cmd == SOUND_MIXER_PRIVATE1)
 676         {
 677                 if (get_user(val, (int __user *)arg))
 678                         return -EFAULT;
 679
 680                 if (val != 0xffff)
 681                 {
 682                         unsigned long flags;
 683                         val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
 684                         devc->mixer_output_port = val;
 685                         val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT;        /* Always on */
 686                         devc->mixer_output_port = val;
 687                         spin_lock_irqsave(&devc->lock,flags);
 688                         if (val & AUDIO_SPEAKER)
 689                                 ad_write(devc, 26, ad_read(devc, 26) & ~0x40);  /* Unmute mono out */
 690                         else
 691                                 ad_write(devc, 26, ad_read(devc, 26) | 0x40);           /* Mute mono out */
 692                         spin_unlock_irqrestore(&devc->lock,flags);
 693                 }
 694                 val = devc->mixer_output_port;
 695                 return put_user(val, (int __user *)arg);
 696         }
 697         if (cmd == SOUND_MIXER_PRIVATE2)
 698         {
 699                 if (get_user(val, (int __user *)arg))
 700                         return -EFAULT;
 701                 return(ad1848_control(AD1848_MIXER_REROUTE, val));
 702         }
 703         if (((cmd >> 8) & 0xff) == 'M')
 704         {
 705                 if (_SIOC_DIR(cmd) & _SIOC_WRITE)
 706                 {
 707                         switch (cmd & 0xff)
 708                         {
 709                                 case SOUND_MIXER_RECSRC:
 710                                         if (get_user(val, (int __user *)arg))
 711                                                 return -EFAULT;
 712                                         val = ad1848_set_recmask(devc, val);
 713                                         break;
 714
 715                                 default:
 716                                         if (get_user(val, (int __user *)arg))
 717                                                 return -EFAULT;
 718                                         val = ad1848_mixer_set(devc, cmd & 0xff, val);
 719                                         break;
 720                         }
 721                         return put_user(val, (int __user *)arg);
 722                 }
 723                 else
 724                 {
 725                         switch (cmd & 0xff)
 726                         {
 727                                 /*
 728                                  * Return parameters
 729                                  */
 730
 731                                 case SOUND_MIXER_RECSRC:
 732                                         val = devc->recmask;
 733                                         break;
 734
 735                                 case SOUND_MIXER_DEVMASK:
 736                                         val = devc->supported_devices;
 737                                         break;
 738
 739                                 case SOUND_MIXER_STEREODEVS:
 740                                         val = devc->supported_devices;
 741                                         if (devc->model != MD_C930)
 742                                                 val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
 743                                         break;
 744
 745                                 case SOUND_MIXER_RECMASK:
 746                                         val = devc->supported_rec_devices;
 747                                         break;
 748
 749                                 case SOUND_MIXER_CAPS:
 750                                         val=SOUND_CAP_EXCL_INPUT;
 751                                         break;
 752
 753                                 default:
 754                                         val = ad1848_mixer_get(devc, cmd & 0xff);
 755                                         break;
 756                         }
 757                         return put_user(val, (int __user *)arg);
 758                 }
 759         }
 760         else
 761                 return -EINVAL;
 762 }
 763
 764 static int ad1848_set_speed(int dev, int arg)
 765 {
 766         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
 767         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
 768
 769         /*
 770          * The sampling speed is encoded in the least significant nibble of I8. The
 771          * LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
 772          * three bits select the divisor (indirectly):
 773          *
 774          * The available speeds are in the following table. Keep the speeds in
 775          * the increasing order.
 776          */
 777         typedef struct
 778         {
 779                 int             speed;
 780                 unsigned char   bits;
 781         }
 782         speed_struct;
 783
 784         static speed_struct speed_table[] =
 785         {
 786                 {5510, (0 << 1) | 1},
 787                 {5510, (0 << 1) | 1},
 788                 {6620, (7 << 1) | 1},
 789                 {8000, (0 << 1) | 0},
 790                 {9600, (7 << 1) | 0},
 791                 {11025, (1 << 1) | 1},
 792                 {16000, (1 << 1) | 0},
 793                 {18900, (2 << 1) | 1},
 794                 {22050, (3 << 1) | 1},
 795                 {27420, (2 << 1) | 0},
 796                 {32000, (3 << 1) | 0},
 797                 {33075, (6 << 1) | 1},
 798                 {37800, (4 << 1) | 1},
 799                 {44100, (5 << 1) | 1},
 800                 {48000, (6 << 1) | 0}
 801         };
 802
 803         int i, n, selected = -1;
 804
 805         n = sizeof(speed_table) / sizeof(speed_struct);
 806
 807         if (arg <= 0)
 808                 return portc->speed;
 809
 810         if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)    /* AD1845 has different timer than others */
 811         {
 812                 if (arg < 4000)
 813                         arg = 4000;
 814                 if (arg > 50000)
 815                         arg = 50000;
 816
 817                 portc->speed = arg;
 818                 portc->speed_bits = speed_table[3].bits;
 819                 return portc->speed;
 820         }
 821         if (arg < speed_table[0].speed)
 822                 selected = 0;
 823         if (arg > speed_table[n - 1].speed)
 824                 selected = n - 1;
 825
 826         for (i = 1 /*really */ ; selected == -1 && i < n; i++)
 827         {
 828                 if (speed_table[i].speed == arg)
 829                         selected = i;
 830                 else if (speed_table[i].speed > arg)
 831                 {
 832                         int diff1, diff2;
 833
 834                         diff1 = arg - speed_table[i - 1].speed;
 835                         diff2 = speed_table[i].speed - arg;
 836
 837                         if (diff1 < diff2)
 838                                 selected = i - 1;
 839                         else
 840                                 selected = i;
 841                 }
 842         }
 843         if (selected == -1)
 844         {
 845                 printk(KERN_WARNING "ad1848: Can't find speed???\n");
 846                 selected = 3;
 847         }
 848         portc->speed = speed_table[selected].speed;
 849         portc->speed_bits = speed_table[selected].bits;
 850         return portc->speed;
 851 }
 852
 853 static short ad1848_set_channels(int dev, short arg)
 854 {
 855         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
 856
 857         if (arg != 1 && arg != 2)
 858                 return portc->channels;
 859
 860         portc->channels = arg;
 861         return arg;
 862 }
 863
 864 static unsigned int ad1848_set_bits(int dev, unsigned int arg)
 865 {
 866         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
 867         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
 868
 869         static struct format_tbl
 870         {
 871                   int             format;
 872                   unsigned char   bits;
 873         }
 874         format2bits[] =
 875         {
 876                 {
 877                         0, 0
 878                 }
 879                 ,
 880                 {
 881                         AFMT_MU_LAW, 1
 882                 }
 883                 ,
 884                 {
 885                         AFMT_A_LAW, 3
 886                 }
 887                 ,
 888                 {
 889                         AFMT_IMA_ADPCM, 5
 890                 }
 891                 ,
 892                 {
 893                         AFMT_U8, 0
 894                 }
 895                 ,
 896                 {
 897                         AFMT_S16_LE, 2
 898                 }
 899                 ,
 900                 {
 901                         AFMT_S16_BE, 6
 902                 }
 903                 ,
 904                 {
 905                         AFMT_S8, 0
 906                 }
 907                 ,
 908                 {
 909                         AFMT_U16_LE, 0
 910                 }
 911                 ,
 912                 {
 913                         AFMT_U16_BE, 0
 914                 }
 915         };
 916         int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
 917
 918         if (arg == 0)
 919                 return portc->audio_format;
 920
 921         if (!(arg & ad_format_mask[devc->model]))
 922                 arg = AFMT_U8;
 923
 924         portc->audio_format = arg;
 925
 926         for (i = 0; i < n; i++)
 927                 if (format2bits[i].format == arg)
 928                 {
 929                         if ((portc->format_bits = format2bits[i].bits) == 0)
 930                                 return portc->audio_format = AFMT_U8;           /* Was not supported */
 931
 932                         return arg;
 933                 }
 934         /* Still hanging here. Something must be terribly wrong */
 935         portc->format_bits = 0;
 936         return portc->audio_format = AFMT_U8;
 937 }
 938
 939 static struct audio_driver ad1848_audio_driver =
 940 {
 941         .owner                  = THIS_MODULE,
 942         .open                   = ad1848_open,
 943         .close                  = ad1848_close,
 944         .output_block           = ad1848_output_block,
 945         .start_input            = ad1848_start_input,
 946         .prepare_for_input      = ad1848_prepare_for_input,
 947         .prepare_for_output     = ad1848_prepare_for_output,
 948         .halt_io                = ad1848_halt,
 949         .halt_input             = ad1848_halt_input,
 950         .halt_output            = ad1848_halt_output,
 951         .trigger                = ad1848_trigger,
 952         .set_speed              = ad1848_set_speed,
 953         .set_bits               = ad1848_set_bits,
 954         .set_channels           = ad1848_set_channels
 955 };
 956
 957 static struct mixer_operations ad1848_mixer_operations =
 958 {
 959         .owner  = THIS_MODULE,
 960         .id     = "SOUNDPORT",
 961         .name   = "AD1848/CS4248/CS4231",
 962         .ioctl  = ad1848_mixer_ioctl
 963 };
 964
 965 static int ad1848_open(int dev, int mode)
 966 {
 967         ad1848_info    *devc;
 968         ad1848_port_info *portc;
 969         unsigned long   flags;
 970
 971         if (dev < 0 || dev >= num_audiodevs)
 972                 return -ENXIO;
 973
 974         devc = (ad1848_info *) audio_devs[dev]->devc;
 975         portc = (ad1848_port_info *) audio_devs[dev]->portc;
 976
 977         /* here we don't have to protect against intr */
 978         spin_lock(&devc->lock);
 979         if (portc->open_mode || (devc->open_mode & mode))
 980         {
 981                 spin_unlock(&devc->lock);
 982                 return -EBUSY;
 983         }
 984         devc->dual_dma = 0;
 985
 986         if (audio_devs[dev]->flags & DMA_DUPLEX)
 987         {
 988                 devc->dual_dma = 1;
 989         }
 990         devc->intr_active = 0;
 991         devc->audio_mode = 0;
 992         devc->open_mode |= mode;
 993         portc->open_mode = mode;
 994         spin_unlock(&devc->lock);
 995         ad1848_trigger(dev, 0);
 996
 997         if (mode & OPEN_READ)
 998                 devc->record_dev = dev;
 999         if (mode & OPEN_WRITE)
1000                 devc->playback_dev = dev;
1001 /*
1002  * Mute output until the playback really starts. This decreases clicking (hope so).
1003  */
1004         spin_lock_irqsave(&devc->lock,flags);
1005         ad_mute(devc);
1006         spin_unlock_irqrestore(&devc->lock,flags);
1007
1008         return 0;
1009 }
1010
1011 static void ad1848_close(int dev)
1012 {
1013         unsigned long   flags;
1014         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1015         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1016
1017         devc->intr_active = 0;
1018         ad1848_halt(dev);
1019
1020         spin_lock_irqsave(&devc->lock,flags);
1021
1022         devc->audio_mode = 0;
1023         devc->open_mode &= ~portc->open_mode;
1024         portc->open_mode = 0;
1025
1026         ad_unmute(devc);
1027         spin_unlock_irqrestore(&devc->lock,flags);
1028 }
1029
1030 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
1031 {
1032         unsigned long   flags, cnt;
1033         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1034         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1035
1036         cnt = count;
1037
1038         if (portc->audio_format == AFMT_IMA_ADPCM)
1039         {
1040                 cnt /= 4;
1041         }
1042         else
1043         {
1044                 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))  /* 16 bit data */
1045                         cnt >>= 1;
1046         }
1047         if (portc->channels > 1)
1048                 cnt >>= 1;
1049         cnt--;
1050
1051         if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1052             intrflag &&
1053             cnt == devc->xfer_count)
1054         {
1055                 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1056                 devc->intr_active = 1;
1057                 return; /*
1058                          * Auto DMA mode on. No need to react
1059                          */
1060         }
1061         spin_lock_irqsave(&devc->lock,flags);
1062
1063         ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1064         ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1065
1066         devc->xfer_count = cnt;
1067         devc->audio_mode |= PCM_ENABLE_OUTPUT;
1068         devc->intr_active = 1;
1069         spin_unlock_irqrestore(&devc->lock,flags);
1070 }
1071
1072 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
1073 {
1074         unsigned long   flags, cnt;
1075         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1076         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1077
1078         cnt = count;
1079         if (portc->audio_format == AFMT_IMA_ADPCM)
1080         {
1081                 cnt /= 4;
1082         }
1083         else
1084         {
1085                 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE))  /* 16 bit data */
1086                         cnt >>= 1;
1087         }
1088         if (portc->channels > 1)
1089                 cnt >>= 1;
1090         cnt--;
1091
1092         if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1093                 intrflag &&
1094                 cnt == devc->xfer_count)
1095         {
1096                 devc->audio_mode |= PCM_ENABLE_INPUT;
1097                 devc->intr_active = 1;
1098                 return; /*
1099                          * Auto DMA mode on. No need to react
1100                          */
1101         }
1102         spin_lock_irqsave(&devc->lock,flags);
1103
1104         if (devc->model == MD_1848)
1105         {
1106                   ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1107                   ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1108         }
1109         else
1110         {
1111                   ad_write(devc, 31, (unsigned char) (cnt & 0xff));
1112                   ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
1113         }
1114
1115         ad_unmute(devc);
1116
1117         devc->xfer_count = cnt;
1118         devc->audio_mode |= PCM_ENABLE_INPUT;
1119         devc->intr_active = 1;
1120         spin_unlock_irqrestore(&devc->lock,flags);
1121 }
1122
1123 static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
1124 {
1125         int             timeout;
1126         unsigned char   fs, old_fs, tmp = 0;
1127         unsigned long   flags;
1128         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1129         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1130
1131         ad_mute(devc);
1132
1133         spin_lock_irqsave(&devc->lock,flags);
1134         fs = portc->speed_bits | (portc->format_bits << 5);
1135
1136         if (portc->channels > 1)
1137                 fs |= 0x10;
1138
1139         ad_enter_MCE(devc);     /* Enables changes to the format select reg */
1140
1141         if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
1142         {
1143                 fs &= 0xf0;     /* Mask off the rate select bits */
1144
1145                 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1146                 ad_write(devc, 23, portc->speed & 0xff);        /* Speed LSB */
1147         }
1148         old_fs = ad_read(devc, 8);
1149
1150         if (devc->model == MD_4232 || devc->model >= MD_4236)
1151         {
1152                 tmp = ad_read(devc, 16);
1153                 ad_write(devc, 16, tmp | 0x30);
1154         }
1155         if (devc->model == MD_IWAVE)
1156                 ad_write(devc, 17, 0xc2);       /* Disable variable frequency select */
1157
1158         ad_write(devc, 8, fs);
1159
1160         /*
1161          * Write to I8 starts resynchronization. Wait until it completes.
1162          */
1163
1164         timeout = 0;
1165         while (timeout < 100 && inb(devc->base) != 0x80)
1166                 timeout++;
1167         timeout = 0;
1168         while (timeout < 10000 && inb(devc->base) == 0x80)
1169                 timeout++;
1170
1171         if (devc->model >= MD_4232)
1172                 ad_write(devc, 16, tmp & ~0x30);
1173
1174         ad_leave_MCE(devc);     /*
1175                                  * Starts the calibration process.
1176                                  */
1177         spin_unlock_irqrestore(&devc->lock,flags);
1178         devc->xfer_count = 0;
1179
1180 #ifndef EXCLUDE_TIMERS
1181         if (dev == timer_installed && devc->timer_running)
1182                 if ((fs & 0x01) != (old_fs & 0x01))
1183                 {
1184                         ad1848_tmr_reprogram(dev);
1185                 }
1186 #endif
1187         ad1848_halt_output(dev);
1188         return 0;
1189 }
1190
1191 static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
1192 {
1193         int timeout;
1194         unsigned char fs, old_fs, tmp = 0;
1195         unsigned long flags;
1196         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1197         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1198
1199         if (devc->audio_mode)
1200                 return 0;
1201
1202         spin_lock_irqsave(&devc->lock,flags);
1203         fs = portc->speed_bits | (portc->format_bits << 5);
1204
1205         if (portc->channels > 1)
1206                 fs |= 0x10;
1207
1208         ad_enter_MCE(devc);     /* Enables changes to the format select reg */
1209
1210         if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE))        /* Use alternate speed select registers */
1211         {
1212                 fs &= 0xf0;     /* Mask off the rate select bits */
1213
1214                 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1215                 ad_write(devc, 23, portc->speed & 0xff);        /* Speed LSB */
1216         }
1217         if (devc->model == MD_4232)
1218         {
1219                 tmp = ad_read(devc, 16);
1220                 ad_write(devc, 16, tmp | 0x30);
1221         }
1222         if (devc->model == MD_IWAVE)
1223                 ad_write(devc, 17, 0xc2);       /* Disable variable frequency select */
1224
1225         /*
1226          * If mode >= 2 (CS4231), set I28. It's the capture format register.
1227          */
1228
1229         if (devc->model != MD_1848)
1230         {
1231                 old_fs = ad_read(devc, 28);
1232                 ad_write(devc, 28, fs);
1233
1234                 /*
1235                  * Write to I28 starts resynchronization. Wait until it completes.
1236                  */
1237
1238                 timeout = 0;
1239                 while (timeout < 100 && inb(devc->base) != 0x80)
1240                         timeout++;
1241
1242                 timeout = 0;
1243                 while (timeout < 10000 && inb(devc->base) == 0x80)
1244                         timeout++;
1245
1246                 if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
1247                 {
1248                         /*
1249                          * CS4231 compatible devices don't have separate sampling rate selection
1250                          * register for recording an playback. The I8 register is shared so we have to
1251                          * set the speed encoding bits of it too.
1252                          */
1253                         unsigned char   tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);
1254
1255                         ad_write(devc, 8, tmp);
1256                         /*
1257                          * Write to I8 starts resynchronization. Wait until it completes.
1258                          */
1259                         timeout = 0;
1260                         while (timeout < 100 && inb(devc->base) != 0x80)
1261                                 timeout++;
1262
1263                         timeout = 0;
1264                         while (timeout < 10000 && inb(devc->base) == 0x80)
1265                                 timeout++;
1266                 }
1267         }
1268         else
1269         {                       /* For AD1848 set I8. */
1270
1271                 old_fs = ad_read(devc, 8);
1272                 ad_write(devc, 8, fs);
1273                 /*
1274                  * Write to I8 starts resynchronization. Wait until it completes.
1275                  */
1276                 timeout = 0;
1277                 while (timeout < 100 && inb(devc->base) != 0x80)
1278                         timeout++;
1279                 timeout = 0;
1280                 while (timeout < 10000 && inb(devc->base) == 0x80)
1281                         timeout++;
1282         }
1283
1284         if (devc->model == MD_4232)
1285                 ad_write(devc, 16, tmp & ~0x30);
1286
1287         ad_leave_MCE(devc);     /*
1288                                  * Starts the calibration process.
1289                                  */
1290         spin_unlock_irqrestore(&devc->lock,flags);
1291         devc->xfer_count = 0;
1292
1293 #ifndef EXCLUDE_TIMERS
1294         if (dev == timer_installed && devc->timer_running)
1295         {
1296                 if ((fs & 0x01) != (old_fs & 0x01))
1297                 {
1298                         ad1848_tmr_reprogram(dev);
1299                 }
1300         }
1301 #endif
1302         ad1848_halt_input(dev);
1303         return 0;
1304 }
1305
1306 static void ad1848_halt(int dev)
1307 {
1308         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1309         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1310
1311         unsigned char   bits = ad_read(devc, 9);
1312
1313         if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
1314                 ad1848_halt_output(dev);
1315
1316         if (bits & 0x02 && (portc->open_mode & OPEN_READ))
1317                 ad1848_halt_input(dev);
1318         devc->audio_mode = 0;
1319 }
1320
1321 static void ad1848_halt_input(int dev)
1322 {
1323         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1324         unsigned long   flags;
1325
1326         if (!(ad_read(devc, 9) & 0x02))
1327                 return;         /* Capture not enabled */
1328
1329         spin_lock_irqsave(&devc->lock,flags);
1330
1331         ad_mute(devc);
1332
1333         {
1334                 int             tmout;
1335
1336                 if(!isa_dma_bridge_buggy)
1337                         disable_dma(audio_devs[dev]->dmap_in->dma);
1338
1339                 for (tmout = 0; tmout < 100000; tmout++)
1340                         if (ad_read(devc, 11) & 0x10)
1341                                 break;
1342                 ad_write(devc, 9, ad_read(devc, 9) & ~0x02);    /* Stop capture */
1343
1344                 if(!isa_dma_bridge_buggy)
1345                         enable_dma(audio_devs[dev]->dmap_in->dma);
1346                 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1347         }
1348
1349         outb(0, io_Status(devc));       /* Clear interrupt status */
1350         outb(0, io_Status(devc));       /* Clear interrupt status */
1351
1352         devc->audio_mode &= ~PCM_ENABLE_INPUT;
1353
1354         spin_unlock_irqrestore(&devc->lock,flags);
1355 }
1356
1357 static void ad1848_halt_output(int dev)
1358 {
1359         ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1360         unsigned long flags;
1361
1362         if (!(ad_read(devc, 9) & 0x01))
1363                 return;         /* Playback not enabled */
1364
1365         spin_lock_irqsave(&devc->lock,flags);
1366
1367         ad_mute(devc);
1368         {
1369                 int             tmout;
1370
1371                 if(!isa_dma_bridge_buggy)
1372                         disable_dma(audio_devs[dev]->dmap_out->dma);
1373
1374                 for (tmout = 0; tmout < 100000; tmout++)
1375                         if (ad_read(devc, 11) & 0x10)
1376                                 break;
1377                 ad_write(devc, 9, ad_read(devc, 9) & ~0x01);    /* Stop playback */
1378
1379                 if(!isa_dma_bridge_buggy)
1380                        enable_dma(audio_devs[dev]->dmap_out->dma);
1381
1382                 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1383         }
1384
1385         outb((0), io_Status(devc));     /* Clear interrupt status */
1386         outb((0), io_Status(devc));     /* Clear interrupt status */
1387
1388         devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1389
1390         spin_unlock_irqrestore(&devc->lock,flags);
1391 }
1392
1393 static void ad1848_trigger(int dev, int state)
1394 {
1395         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
1396         ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1397         unsigned long   flags;
1398         unsigned char   tmp, old;
1399
1400         spin_lock_irqsave(&devc->lock,flags);
1401         state &= devc->audio_mode;
1402
1403         tmp = old = ad_read(devc, 9);
1404
1405         if (portc->open_mode & OPEN_READ)
1406         {
1407                   if (state & PCM_ENABLE_INPUT)
1408                           tmp |= 0x02;
1409                   else
1410                           tmp &= ~0x02;
1411         }
1412         if (portc->open_mode & OPEN_WRITE)
1413         {
1414                 if (state & PCM_ENABLE_OUTPUT)
1415                         tmp |= 0x01;
1416                 else
1417                         tmp &= ~0x01;
1418         }
1419         /* ad_mute(devc); */
1420         if (tmp != old)
1421         {
1422                   ad_write(devc, 9, tmp);
1423                   ad_unmute(devc);
1424         }
1425         spin_unlock_irqrestore(&devc->lock,flags);
1426 }
1427
1428 static void ad1848_init_hw(ad1848_info * devc)
1429 {
1430         int i;
1431         int *init_values;
1432
1433         /*
1434          * Initial values for the indirect registers of CS4248/AD1848.
1435          */
1436         static int      init_values_a[] =
1437         {
1438                 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1439                 0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1440
1441         /* Positions 16 to 31 just for CS4231/2 and ad1845 */
1442                 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1443                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1444         };
1445
1446         static int      init_values_b[] =
1447         {
1448                 /*
1449                    Values for the newer chips
1450                    Some of the register initialization values were changed. In
1451                    order to get rid of the click that preceded PCM playback,
1452                    calibration was disabled on the 10th byte. On that same byte,
1453                    dual DMA was enabled; on the 11th byte, ADC dithering was
1454                    enabled, since that is theoretically desirable; on the 13th
1455                    byte, Mode 3 was selected, to enable access to extended
1456                    registers.
1457                  */
1458                 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1459                 0x00, 0x00, 0x06, 0x00, 0xe0, 0x01, 0x00, 0x00,
1460                 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1461                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1462         };
1463
1464         /*
1465          *      Select initialisation data
1466          */
1467
1468         init_values = init_values_a;
1469         if(devc->model >= MD_4236)
1470                 init_values = init_values_b;
1471
1472         for (i = 0; i < 16; i++)
1473                 ad_write(devc, i, init_values[i]);
1474
1475
1476         ad_mute(devc);          /* Initialize some variables */
1477         ad_unmute(devc);        /* Leave it unmuted now */
1478
1479         if (devc->model > MD_1848)
1480         {
1481                 if (devc->model == MD_1845_SSCAPE)
1482                         ad_write(devc, 12, ad_read(devc, 12) | 0x50);
1483                 else
1484                         ad_write(devc, 12, ad_read(devc, 12) | 0x40);           /* Mode2 = enabled */
1485
1486                 if (devc->model == MD_IWAVE)
1487                         ad_write(devc, 12, 0x6c);       /* Select codec mode 3 */
1488
1489                 if (devc->model != MD_1845_SSCAPE)
1490                         for (i = 16; i < 32; i++)
1491                                 ad_write(devc, i, init_values[i]);
1492
1493                 if (devc->model == MD_IWAVE)
1494                         ad_write(devc, 16, 0x30);       /* Playback and capture counters enabled */
1495         }
1496         if (devc->model > MD_1848)
1497         {
1498                 if (devc->audio_flags & DMA_DUPLEX)
1499                         ad_write(devc, 9, ad_read(devc, 9) & ~0x04);    /* Dual DMA mode */
1500                 else
1501                         ad_write(devc, 9, ad_read(devc, 9) | 0x04);     /* Single DMA mode */
1502
1503                 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
1504                         ad_write(devc, 27, ad_read(devc, 27) | 0x08);           /* Alternate freq select enabled */
1505
1506                 if (devc->model == MD_IWAVE)
1507                 {               /* Some magic Interwave specific initialization */
1508                         ad_write(devc, 12, 0x6c);       /* Select codec mode 3 */
1509                         ad_write(devc, 16, 0x30);       /* Playback and capture counters enabled */
1510                         ad_write(devc, 17, 0xc2);       /* Alternate feature enable */
1511                 }
1512         }
1513         else
1514         {
1515                   devc->audio_flags &= ~DMA_DUPLEX;
1516                   ad_write(devc, 9, ad_read(devc, 9) | 0x04);   /* Single DMA mode */
1517                   if (soundpro)
1518                           ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1519         }
1520
1521         outb((0), io_Status(devc));     /* Clear pending interrupts */
1522
1523         /*
1524          * Toggle the MCE bit. It completes the initialization phase.
1525          */
1526
1527         ad_enter_MCE(devc);     /* In case the bit was off */
1528         ad_leave_MCE(devc);
1529
1530         ad1848_mixer_reset(devc);
1531 }
1532
1533 int ad1848_detect(struct resource *ports, int *ad_flags, int *osp)
1534 {
1535         unsigned char tmp;
1536         ad1848_info *devc = &adev_info[nr_ad1848_devs];
1537         unsigned char tmp1 = 0xff, tmp2 = 0xff;
1538         int optiC930 = 0;       /* OPTi 82C930 flag */
1539         int interwave = 0;
1540         int ad1847_flag = 0;
1541         int cs4248_flag = 0;
1542         int sscape_flag = 0;
1543         int io_base = ports->start;
1544
1545         int i;
1546
1547         DDB(printk("ad1848_detect(%x)\n", io_base));
1548
1549         if (ad_flags)
1550         {
1551                 if (*ad_flags == 0x12345678)
1552                 {
1553                         interwave = 1;
1554                         *ad_flags = 0;
1555                 }
1556
1557                 if (*ad_flags == 0x87654321)
1558                 {
1559                         sscape_flag = 1;
1560                         *ad_flags = 0;
1561                 }
1562
1563                 if (*ad_flags == 0x12345677)
1564                 {
1565                     cs4248_flag = 1;
1566                     *ad_flags = 0;
1567                 }
1568         }
1569         if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1570         {
1571                 printk(KERN_ERR "ad1848 - Too many audio devices\n");
1572                 return 0;
1573         }
1574         spin_lock_init(&devc->lock);
1575         devc->base = io_base;
1576         devc->irq_ok = 0;
1577         devc->timer_running = 0;
1578         devc->MCE_bit = 0x40;
1579         devc->irq = 0;
1580         devc->open_mode = 0;
1581         devc->chip_name = devc->name = "AD1848";
1582         devc->model = MD_1848;  /* AD1848 or CS4248 */
1583         devc->levels = NULL;
1584         devc->debug_flag = 0;
1585
1586         /*
1587          * Check that the I/O address is in use.
1588          *
1589          * The bit 0x80 of the base I/O port is known to be 0 after the
1590          * chip has performed its power on initialization. Just assume
1591          * this has happened before the OS is starting.
1592          *
1593          * If the I/O address is unused, it typically returns 0xff.
1594          */
1595
1596         if (inb(devc->base) == 0xff)
1597         {
1598                 DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
1599         }
1600
1601         /*
1602          * Wait for the device to stop initialization
1603          */
1604
1605         DDB(printk("ad1848_detect() - step 0\n"));
1606
1607         for (i = 0; i < 10000000; i++)
1608         {
1609                 unsigned char   x = inb(devc->base);
1610
1611                 if (x == 0xff || !(x & 0x80))
1612                         break;
1613         }
1614
1615         DDB(printk("ad1848_detect() - step A\n"));
1616
1617         if (inb(devc->base) == 0x80)    /* Not ready. Let's wait */
1618                 ad_leave_MCE(devc);
1619
1620         if ((inb(devc->base) & 0x80) != 0x00)   /* Not a AD1848 */
1621         {
1622                 DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
1623                 return 0;
1624         }
1625
1626         /*
1627          * Test if it's possible to change contents of the indirect registers.
1628          * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1629          * so try to avoid using it.
1630          */
1631
1632         DDB(printk("ad1848_detect() - step B\n"));
1633         ad_write(devc, 0, 0xaa);
1634         ad_write(devc, 1, 0x45);        /* 0x55 with bit 0x10 clear */
1635
1636         if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
1637         {
1638                 if (tmp2 == 0x65)       /* AD1847 has couple of bits hardcoded to 1 */
1639                         ad1847_flag = 1;
1640                 else
1641                 {
1642                         DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1643                         return 0;
1644                 }
1645         }
1646         DDB(printk("ad1848_detect() - step C\n"));
1647         ad_write(devc, 0, 0x45);
1648         ad_write(devc, 1, 0xaa);
1649
1650         if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
1651         {
1652                 if (tmp2 == 0x8a)       /* AD1847 has few bits hardcoded to 1 */
1653                         ad1847_flag = 1;
1654                 else
1655                 {
1656                         DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1657                         return 0;
1658                 }
1659         }
1660
1661         /*
1662          * The indirect register I12 has some read only bits. Let's
1663          * try to change them.
1664          */
1665
1666         DDB(printk("ad1848_detect() - step D\n"));
1667         tmp = ad_read(devc, 12);
1668         ad_write(devc, 12, (~tmp) & 0x0f);
1669
1670         if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
1671         {
1672                 DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
1673                 return 0;
1674         }
1675
1676         /*
1677          * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1678          *   0x01=RevB and 0x0A=RevC.
1679          */
1680
1681         /*
1682          * The original AD1848/CS4248 has just 15 indirect registers. This means
1683          * that I0 and I16 should return the same value (etc.).
1684          * However this doesn't work with CS4248. Actually it seems to be impossible
1685          * to detect if the chip is a CS4231 or CS4248.
1686          * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1687          * with CS4231.
1688          */
1689
1690         /*
1691          * OPTi 82C930 has mode2 control bit in another place. This test will fail
1692          * with it. Accept this situation as a possible indication of this chip.
1693          */
1694
1695         DDB(printk("ad1848_detect() - step F\n"));
1696         ad_write(devc, 12, 0);  /* Mode2=disabled */
1697
1698         for (i = 0; i < 16; i++)
1699         {
1700                 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
1701                 {
1702                         DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
1703                         if (!ad1847_flag)
1704                                 optiC930 = 1;
1705                         break;
1706                 }
1707         }
1708
1709         /*
1710          * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1711          * The bit 0x80 is always 1 in CS4248 and CS4231.
1712          */
1713
1714         DDB(printk("ad1848_detect() - step G\n"));
1715
1716         if (ad_flags && *ad_flags == 400)
1717                 *ad_flags = 0;
1718         else
1719                 ad_write(devc, 12, 0x40);       /* Set mode2, clear 0x80 */
1720
1721
1722         if (ad_flags)
1723                 *ad_flags = 0;
1724
1725         tmp1 = ad_read(devc, 12);
1726         if (tmp1 & 0x80)
1727         {
1728                 if (ad_flags)
1729                         *ad_flags |= AD_F_CS4248;
1730
1731                 devc->chip_name = "CS4248";     /* Our best knowledge just now */
1732         }
1733         if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
1734         {
1735                 /*
1736                  *      CS4231 detected - is it?
1737                  *
1738                  *      Verify that setting I0 doesn't change I16.
1739                  */
1740
1741                 DDB(printk("ad1848_detect() - step H\n"));
1742                 ad_write(devc, 16, 0);  /* Set I16 to known value */
1743
1744                 ad_write(devc, 0, 0x45);
1745                 if ((tmp1 = ad_read(devc, 16)) != 0x45) /* No change -> CS4231? */
1746                 {
1747                         ad_write(devc, 0, 0xaa);
1748                         if ((tmp1 = ad_read(devc, 16)) == 0xaa) /* Rotten bits? */
1749                         {
1750                                 DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
1751                                 return 0;
1752                         }
1753
1754                         /*
1755                          * Verify that some bits of I25 are read only.
1756                          */
1757
1758                         DDB(printk("ad1848_detect() - step I\n"));
1759                         tmp1 = ad_read(devc, 25);       /* Original bits */
1760                         ad_write(devc, 25, ~tmp1);      /* Invert all bits */
1761                         if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
1762                         {
1763                                 int id;
1764
1765                                 /*
1766                                  *      It's at least CS4231
1767                                  */
1768
1769                                 devc->chip_name = "CS4231";
1770                                 devc->model = MD_4231;
1771
1772                                 /*
1773                                  * It could be an AD1845 or CS4231A as well.
1774                                  * CS4231 and AD1845 report the same revision info in I25
1775                                  * while the CS4231A reports different.
1776                                  */
1777
1778                                 id = ad_read(devc, 25);
1779                                 if ((id & 0xe7) == 0x80)        /* Device busy??? */
1780                                         id = ad_read(devc, 25);
1781                                 if ((id & 0xe7) == 0x80)        /* Device still busy??? */
1782                                         id = ad_read(devc, 25);
1783                                 DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));
1784
1785                                 if ((id & 0xe7) == 0x80) {
1786                                         /*
1787                                          * It must be a CS4231 or AD1845. The register I23 of
1788                                          * CS4231 is undefined and it appears to be read only.
1789                                          * AD1845 uses I23 for setting sample rate. Assume
1790                                          * the chip is AD1845 if I23 is changeable.
1791                                          */
1792
1793                                         unsigned char   tmp = ad_read(devc, 23);
1794                                         ad_write(devc, 23, ~tmp);
1795
1796                                         if (interwave)
1797                                         {
1798                                                 devc->model = MD_IWAVE;
1799                                                 devc->chip_name = "IWave";
1800                                         }
1801                                         else if (ad_read(devc, 23) != tmp)      /* AD1845 ? */
1802                                         {
1803                                                 devc->chip_name = "AD1845";
1804                                                 devc->model = MD_1845;
1805                                         }
1806                                         else if (cs4248_flag)
1807                                         {
1808                                                 if (ad_flags)
1809                                                           *ad_flags |= AD_F_CS4248;
1810                                                 devc->chip_name = "CS4248";
1811                                                 devc->model = MD_1848;
1812                                                 ad_write(devc, 12, ad_read(devc, 12) & ~0x40);  /* Mode2 off */
1813                                         }
1814                                         ad_write(devc, 23, tmp);        /* Restore */
1815                                 }
1816                                 else
1817                                 {
1818                                         switch (id & 0x1f) {
1819                                         case 3: /* CS4236/CS4235/CS42xB/CS4239 */
1820                                                 {
1821                                                         int xid;
1822                                                         ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
1823                                                         ad_write(devc, 23, 0x9c); /* select extended register 25 */
1824                                                         xid = inb(io_Indexed_Data(devc));
1825                                                         ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
1826                                                         switch (xid & 0x1f)
1827                                                         {
1828                                                                 case 0x00:
1829                                                                         devc->chip_name = "CS4237B(B)";
1830                                                                         devc->model = MD_42xB;
1831                                                                         break;
1832                                                                 case 0x08:
1833                                                                         /* Seems to be a 4238 ?? */
1834                                                                         devc->chip_name = "CS4238";
1835                                                                         devc->model = MD_42xB;
1836                                                                         break;
1837                                                                 case 0x09:
1838                                                                         devc->chip_name = "CS4238B";
1839                                                                         devc->model = MD_42xB;
1840                                                                         break;
1841                                                                 case 0x0b:
1842                                                                         devc->chip_name = "CS4236B";
1843                                                                         devc->model = MD_4236;
1844                                                                         break;
1845                                                                 case 0x10:
1846                                                                         devc->chip_name = "CS4237B";
1847                                                                         devc->model = MD_42xB;
1848                                                                         break;
1849                                                                 case 0x1d:
1850                                                                         devc->chip_name = "CS4235";
1851                                                                         devc->model = MD_4235;
1852                                                                         break;
1853                                                                 case 0x1e:
1854                                                                         devc->chip_name = "CS4239";
1855                                                                         devc->model = MD_4239;
1856                                                                         break;
1857                                                                 default:
1858                                                                         printk("Chip ident is %X.\n", xid&0x1F);
1859                                                                         devc->chip_name = "CS42xx";
1860                                                                         devc->model = MD_4232;
1861                                                                         break;
1862                                                         }
1863                                                 }
1864                                                 break;
1865
1866                                         case 2: /* CS4232/CS4232A */
1867                                                 devc->chip_name = "CS4232";
1868                                                 devc->model = MD_4232;
1869                                                 break;
1870
1871                                         case 0:
1872                                                 if ((id & 0xe0) == 0xa0)
1873                                                 {
1874                                                         devc->chip_name = "CS4231A";
1875                                                         devc->model = MD_4231A;
1876                                                 }
1877                                                 else
1878                                                 {
1879                                                         devc->chip_name = "CS4321";
1880                                                         devc->model = MD_4231;
1881                                                 }
1882                                                 break;
1883
1884                                         default: /* maybe */
1885                                                 DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
1886                                                 if (optiC930)
1887                                                 {
1888                                                         devc->chip_name = "82C930";
1889                                                         devc->model = MD_C930;
1890                                                 }
1891                                                 else
1892                                                 {
1893                                                         devc->chip_name = "CS4231";
1894                                                         devc->model = MD_4231;
1895                                                 }
1896                                         }
1897                                 }
1898                         }
1899                         ad_write(devc, 25, tmp1);       /* Restore bits */
1900
1901                         DDB(printk("ad1848_detect() - step K\n"));
1902                 }
1903         } else if (tmp1 == 0x0a) {
1904                 /*
1905                  * Is it perhaps a SoundPro CMI8330?
1906                  * If so, then we should be able to change indirect registers
1907                  * greater than I15 after activating MODE2, even though reading
1908                  * back I12 does not show it.
1909                  */
1910
1911                 /*
1912                  * Let's try comparing register values
1913                  */
1914                 for (i = 0; i < 16; i++) {
1915                         if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1916                                 DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
1917                                 soundpro = 1;
1918                                 devc->chip_name = "SoundPro CMI 8330";
1919                                 break;
1920                         }
1921                 }
1922         }
1923
1924         DDB(printk("ad1848_detect() - step L\n"));
1925         if (ad_flags)
1926         {
1927                   if (devc->model != MD_1848)
1928                           *ad_flags |= AD_F_CS4231;
1929         }
1930         DDB(printk("ad1848_detect() - Detected OK\n"));
1931
1932         if (devc->model == MD_1848 && ad1847_flag)
1933                 devc->chip_name = "AD1847";
1934
1935
1936         if (sscape_flag == 1)
1937                 devc->model = MD_1845_SSCAPE;
1938
1939         return 1;
1940 }
1941
1942 int ad1848_init (char *name, struct resource *ports, int irq, int dma_playback,
1943                 int dma_capture, int share_dma, int *osp, struct module *owner)
1944 {
1945         /*
1946          * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1947          *   so that this driver doesn't need to allocate/deallocate it.
1948          *   The actually used IRQ is ABS(irq).
1949          */
1950
1951         int my_dev;
1952         char dev_name[100];
1953         int e;
1954
1955         ad1848_info  *devc = &adev_info[nr_ad1848_devs];
1956
1957         ad1848_port_info *portc = NULL;
1958
1959         devc->irq = (irq > 0) ? irq : 0;
1960         devc->open_mode = 0;
1961         devc->timer_ticks = 0;
1962         devc->dma1 = dma_playback;
1963         devc->dma2 = dma_capture;
1964         devc->subtype = cfg.card_subtype;
1965         devc->audio_flags = DMA_AUTOMODE;
1966         devc->playback_dev = devc->record_dev = 0;
1967         if (name != NULL)
1968                 devc->name = name;
1969
1970         if (name != NULL && name[0] != 0)
1971                 sprintf(dev_name,
1972                         "%s (%s)", name, devc->chip_name);
1973         else
1974                 sprintf(dev_name,
1975                         "Generic audio codec (%s)", devc->chip_name);
1976
1977         rename_region(ports, devc->name);
1978
1979         conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);
1980
1981         if (devc->model == MD_1848 || devc->model == MD_C930)
1982                 devc->audio_flags |= DMA_HARDSTOP;
1983
1984         if (devc->model > MD_1848)
1985         {
1986                 if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
1987                         devc->audio_flags &= ~DMA_DUPLEX;
1988                 else
1989                         devc->audio_flags |= DMA_DUPLEX;
1990         }
1991
1992         portc = kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
1993         if(portc==NULL) {
1994                 release_region(devc->base, 4);
1995                 return -1;
1996         }
1997
1998         if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
1999                                              dev_name,
2000                                              &ad1848_audio_driver,
2001                                              sizeof(struct audio_driver),
2002                                              devc->audio_flags,
2003                                              ad_format_mask[devc->model],
2004                                              devc,
2005                                              dma_playback,
2006                                              dma_capture)) < 0)
2007         {
2008                 release_region(devc->base, 4);
2009                 kfree(portc);
2010                 return -1;
2011         }
2012
2013         audio_devs[my_dev]->portc = portc;
2014         audio_devs[my_dev]->mixer_dev = -1;
2015         if (owner)
2016                 audio_devs[my_dev]->d->owner = owner;
2017         memset((char *) portc, 0, sizeof(*portc));
2018
2019         nr_ad1848_devs++;
2020
2021         ad1848_init_hw(devc);
2022
2023         if (irq > 0)
2024         {
2025                 devc->dev_no = my_dev;
2026                 if (request_irq(devc->irq, adintr, 0, devc->name,
2027                                 (void *)(long)my_dev) < 0)
2028                 {
2029                         printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
2030                         /* Don't free it either then.. */
2031                         devc->irq = 0;
2032                 }
2033                 if (capabilities[devc->model].flags & CAP_F_TIMER)
2034                 {
2035 #ifndef CONFIG_SMP
2036                         int x;
2037                         unsigned char tmp = ad_read(devc, 16);
2038 #endif
2039
2040                         devc->timer_ticks = 0;
2041
2042                         ad_write(devc, 21, 0x00);       /* Timer MSB */
2043                         ad_write(devc, 20, 0x10);       /* Timer LSB */
2044 #ifndef CONFIG_SMP
2045                         ad_write(devc, 16, tmp | 0x40); /* Enable timer */
2046                         for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
2047                         ad_write(devc, 16, tmp & ~0x40);        /* Disable timer */
2048
2049                         if (devc->timer_ticks == 0)
2050                                 printk(KERN_WARNING "ad1848: Interrupt test failed (IRQ%d)\n", irq);
2051                         else
2052                         {
2053                                 DDB(printk("Interrupt test OK\n"));
2054                                 devc->irq_ok = 1;
2055                         }
2056 #else
2057                         devc->irq_ok = 1;
2058 #endif
2059                 }
2060                 else
2061                         devc->irq_ok = 1;       /* Couldn't test. assume it's OK */
2062         } else if (irq < 0)
2063                 irq2dev[-irq] = devc->dev_no = my_dev;
2064
2065 #ifndef EXCLUDE_TIMERS
2066         if ((capabilities[devc->model].flags & CAP_F_TIMER) &&
2067             devc->irq_ok)
2068                 ad1848_tmr_install(my_dev);
2069 #endif
2070
2071         if (!share_dma)
2072         {
2073                 if (sound_alloc_dma(dma_playback, devc->name))
2074                         printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_playback);
2075
2076                 if (dma_capture != dma_playback)
2077                         if (sound_alloc_dma(dma_capture, devc->name))
2078                                 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_capture);
2079         }
2080
2081         if ((e = sound_install_mixer(MIXER_DRIVER_VERSION,
2082                                      dev_name,
2083                                      &ad1848_mixer_operations,
2084                                      sizeof(struct mixer_operations),
2085                                      devc)) >= 0)
2086         {
2087                 audio_devs[my_dev]->mixer_dev = e;
2088                 if (owner)
2089                         mixer_devs[e]->owner = owner;
2090         }
2091         return my_dev;
2092 }
2093
2094 int ad1848_control(int cmd, int arg)
2095 {
2096         ad1848_info *devc;
2097         unsigned long flags;
2098
2099         if (nr_ad1848_devs < 1)
2100                 return -ENODEV;
2101
2102         devc = &adev_info[nr_ad1848_devs - 1];
2103
2104         switch (cmd)
2105         {
2106                 case AD1848_SET_XTAL:   /* Change clock frequency of AD1845 (only ) */
2107                         if (devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
2108                                 return -EINVAL;
2109                         spin_lock_irqsave(&devc->lock,flags);
2110                         ad_enter_MCE(devc);
2111                         ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
2112                         ad_leave_MCE(devc);
2113                         spin_unlock_irqrestore(&devc->lock,flags);
2114                         break;
2115
2116                 case AD1848_MIXER_REROUTE:
2117                 {
2118                         int o = (arg >> 8) & 0xff;
2119                         int n = arg & 0xff;
2120
2121                         if (o < 0 || o >= SOUND_MIXER_NRDEVICES)
2122                                 return -EINVAL;
2123
2124                         if (!(devc->supported_devices & (1 << o)) &&
2125                             !(devc->supported_rec_devices & (1 << o)))
2126                                 return -EINVAL;
2127
2128                         if (n == SOUND_MIXER_NONE)
2129                         {       /* Just hide this control */
2130                                 ad1848_mixer_set(devc, o, 0);   /* Shut up it */
2131                                 devc->supported_devices &= ~(1 << o);
2132                                 devc->supported_rec_devices &= ~(1 << o);
2133                                 break;
2134                         }
2135
2136                         /* Make the mixer control identified by o to appear as n */
2137                         if (n < 0 || n >= SOUND_MIXER_NRDEVICES)
2138                                 return -EINVAL;
2139
2140                         devc->mixer_reroute[n] = o;     /* Rename the control */
2141                         if (devc->supported_devices & (1 << o))
2142                                 devc->supported_devices |= (1 << n);
2143                         if (devc->supported_rec_devices & (1 << o))
2144                                 devc->supported_rec_devices |= (1 << n);
2145
2146                         devc->supported_devices &= ~(1 << o);
2147                         devc->supported_rec_devices &= ~(1 << o);
2148                 }
2149                 break;
2150         }
2151         return 0;
2152 }
2153
2154 void ad1848_unload(int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
2155 {
2156         int i, mixer, dev = 0;
2157         ad1848_info *devc = NULL;
2158
2159         for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
2160         {
2161                 if (adev_info[i].base == io_base)
2162                 {
2163                         devc = &adev_info[i];
2164                         dev = devc->dev_no;
2165                 }
2166         }
2167
2168         if (devc != NULL)
2169         {
2170                 kfree(audio_devs[dev]->portc);
2171                 release_region(devc->base, 4);
2172
2173                 if (!share_dma)
2174                 {
2175                         if (devc->irq > 0) /* There is no point in freeing irq, if it wasn't allocated */
2176                                 free_irq(devc->irq, (void *)(long)devc->dev_no);
2177
2178                         sound_free_dma(dma_playback);
2179
2180                         if (dma_playback != dma_capture)
2181                                 sound_free_dma(dma_capture);
2182
2183                 }
2184                 mixer = audio_devs[devc->dev_no]->mixer_dev;
2185                 if(mixer>=0)
2186                         sound_unload_mixerdev(mixer);
2187
2188                 nr_ad1848_devs--;
2189                 for ( ; i < nr_ad1848_devs ; i++)
2190                         adev_info[i] = adev_info[i+1];
2191         }
2192         else
2193                 printk(KERN_ERR "ad1848: Can't find device to be unloaded. Base=%x\n", io_base);
2194 }
2195
2196 static irqreturn_t adintr(int irq, void *dev_id)
2197 {
2198         unsigned char status;
2199         ad1848_info *devc;
2200         int dev;
2201         int alt_stat = 0xff;
2202         unsigned char c930_stat = 0;
2203         int cnt = 0;
2204
2205         dev = (long)dev_id;
2206         devc = (ad1848_info *) audio_devs[dev]->devc;
2207
2208 interrupt_again:                /* Jump back here if int status doesn't reset */
2209
2210         status = inb(io_Status(devc));
2211
2212         if (status == 0x80)
2213                 printk(KERN_DEBUG "adintr: Why?\n");
2214         if (devc->model == MD_1848)
2215                 outb((0), io_Status(devc));     /* Clear interrupt status */
2216
2217         if (status & 0x01)
2218         {
2219                 if (devc->model == MD_C930)
2220                 {               /* 82C930 has interrupt status register in MAD16 register MC11 */
2221
2222                         spin_lock(&devc->lock);
2223
2224                         /* 0xe0e is C930 address port
2225                          * 0xe0f is C930 data port
2226                          */
2227                         outb(11, 0xe0e);
2228                         c930_stat = inb(0xe0f);
2229                         outb((~c930_stat), 0xe0f);
2230
2231                         spin_unlock(&devc->lock);
2232
2233                         alt_stat = (c930_stat << 2) & 0x30;
2234                 }
2235                 else if (devc->model != MD_1848)
2236                 {
2237                         spin_lock(&devc->lock);
2238                         alt_stat = ad_read(devc, 24);
2239                         ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat);      /* Selective ack */
2240                         spin_unlock(&devc->lock);
2241                 }
2242
2243                 if ((devc->open_mode & OPEN_READ) && (devc->audio_mode & PCM_ENABLE_INPUT) && (alt_stat & 0x20))
2244                 {
2245                         DMAbuf_inputintr(devc->record_dev);
2246                 }
2247                 if ((devc->open_mode & OPEN_WRITE) && (devc->audio_mode & PCM_ENABLE_OUTPUT) &&
2248                       (alt_stat & 0x10))
2249                 {
2250                         DMAbuf_outputintr(devc->playback_dev, 1);
2251                 }
2252                 if (devc->model != MD_1848 && (alt_stat & 0x40))        /* Timer interrupt */
2253                 {
2254                         devc->timer_ticks++;
2255 #ifndef EXCLUDE_TIMERS
2256                         if (timer_installed == dev && devc->timer_running)
2257                                 sound_timer_interrupt();
2258 #endif
2259                 }
2260         }
2261 /*
2262  * Sometimes playback or capture interrupts occur while a timer interrupt
2263  * is being handled. The interrupt will not be retriggered if we don't
2264  * handle it now. Check if an interrupt is still pending and restart
2265  * the handler in this case.
2266  */
2267         if (inb(io_Status(devc)) & 0x01 && cnt++ < 4)
2268         {
2269                   goto interrupt_again;
2270         }
2271         return IRQ_HANDLED;
2272 }
2273
2274 /*
2275  *      Experimental initialization sequence for the integrated sound system
2276  *      of the Compaq Deskpro M.
2277  */
2278
2279 static int init_deskpro_m(struct address_info *hw_config)
2280 {
2281         unsigned char   tmp;
2282
2283         if ((tmp = inb(0xc44)) == 0xff)
2284         {
2285                 DDB(printk("init_deskpro_m: Dead port 0xc44\n"));
2286                 return 0;
2287         }
2288
2289         outb(0x10, 0xc44);
2290         outb(0x40, 0xc45);
2291         outb(0x00, 0xc46);
2292         outb(0xe8, 0xc47);
2293         outb(0x14, 0xc44);
2294         outb(0x40, 0xc45);
2295         outb(0x00, 0xc46);
2296         outb(0xe8, 0xc47);
2297         outb(0x10, 0xc44);
2298
2299         return 1;
2300 }
2301
2302 /*
2303  *      Experimental initialization sequence for the integrated sound system
2304  *      of Compaq Deskpro XL.
2305  */
2306
2307 static int init_deskpro(struct address_info *hw_config)
2308 {
2309         unsigned char   tmp;
2310
2311         if ((tmp = inb(0xc44)) == 0xff)
2312         {
2313                 DDB(printk("init_deskpro: Dead port 0xc44\n"));
2314                 return 0;
2315         }
2316         outb((tmp | 0x04), 0xc44);      /* Select bank 1 */
2317         if (inb(0xc44) != 0x04)
2318         {
2319                 DDB(printk("init_deskpro: Invalid bank1 signature in port 0xc44\n"));
2320                 return 0;
2321         }
2322         /*
2323          * OK. It looks like a Deskpro so let's proceed.
2324          */
2325
2326         /*
2327          * I/O port 0xc44 Audio configuration register.
2328          *
2329          * bits 0xc0:   Audio revision bits
2330          *              0x00 = Compaq Business Audio
2331          *              0x40 = MS Sound System Compatible (reset default)
2332          *              0x80 = Reserved
2333          *              0xc0 = Reserved
2334          * bit 0x20:    No Wait State Enable
2335          *              0x00 = Disabled (reset default, DMA mode)
2336          *              0x20 = Enabled (programmed I/O mode)
2337          * bit 0x10:    MS Sound System Decode Enable
2338          *              0x00 = Decoding disabled (reset default)
2339          *              0x10 = Decoding enabled
2340          * bit 0x08:    FM Synthesis Decode Enable
2341          *              0x00 = Decoding Disabled (reset default)
2342          *              0x08 = Decoding enabled
2343          * bit 0x04     Bank select
2344          *              0x00 = Bank 0
2345          *              0x04 = Bank 1
2346          * bits 0x03    MSS Base address
2347          *              0x00 = 0x530 (reset default)
2348          *              0x01 = 0x604
2349          *              0x02 = 0xf40
2350          *              0x03 = 0xe80
2351          */
2352
2353 #ifdef DEBUGXL
2354         /* Debug printing */
2355         printk("Port 0xc44 (before): ");
2356         outb((tmp & ~0x04), 0xc44);
2357         printk("%02x ", inb(0xc44));
2358         outb((tmp | 0x04), 0xc44);
2359         printk("%02x\n", inb(0xc44));
2360 #endif
2361
2362         /* Set bank 1 of the register */
2363         tmp = 0x58;             /* MSS Mode, MSS&FM decode enabled */
2364
2365         switch (hw_config->io_base)
2366         {
2367                 case 0x530:
2368                         tmp |= 0x00;
2369                         break;
2370                 case 0x604:
2371                         tmp |= 0x01;
2372                         break;
2373                 case 0xf40:
2374                         tmp |= 0x02;
2375                         break;
2376                 case 0xe80:
2377                         tmp |= 0x03;
2378                         break;
2379                 default:
2380                         DDB(printk("init_deskpro: Invalid MSS port %x\n", hw_config->io_base));
2381                         return 0;
2382         }
2383         outb((tmp & ~0x04), 0xc44);     /* Write to bank=0 */
2384
2385 #ifdef DEBUGXL
2386         /* Debug printing */
2387         printk("Port 0xc44 (after): ");
2388         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2389         printk("%02x ", inb(0xc44));
2390         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2391         printk("%02x\n", inb(0xc44));
2392 #endif
2393
2394         /*
2395          * I/O port 0xc45 FM Address Decode/MSS ID Register.
2396          *
2397          * bank=0, bits 0xfe:   FM synthesis Decode Compare bits 7:1 (default=0x88)
2398          * bank=0, bit 0x01:    SBIC Power Control Bit
2399          *                      0x00 = Powered up
2400          *                      0x01 = Powered down
2401          * bank=1, bits 0xfc:   MSS ID (default=0x40)
2402          */
2403
2404 #ifdef DEBUGXL
2405         /* Debug printing */
2406         printk("Port 0xc45 (before): ");
2407         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2408         printk("%02x ", inb(0xc45));
2409         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2410         printk("%02x\n", inb(0xc45));
2411 #endif
2412
2413         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2414         outb((0x88), 0xc45);    /* FM base 7:0 = 0x88 */
2415         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2416         outb((0x10), 0xc45);    /* MSS ID = 0x10 (MSS port returns 0x04) */
2417
2418 #ifdef DEBUGXL
2419         /* Debug printing */
2420         printk("Port 0xc45 (after): ");
2421         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2422         printk("%02x ", inb(0xc45));
2423         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2424         printk("%02x\n", inb(0xc45));
2425 #endif
2426
2427
2428         /*
2429          * I/O port 0xc46 FM Address Decode/Address ASIC Revision Register.
2430          *
2431          * bank=0, bits 0xff:   FM synthesis Decode Compare bits 15:8 (default=0x03)
2432          * bank=1, bits 0xff:   Audio addressing ASIC id
2433          */
2434
2435 #ifdef DEBUGXL
2436         /* Debug printing */
2437         printk("Port 0xc46 (before): ");
2438         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2439         printk("%02x ", inb(0xc46));
2440         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2441         printk("%02x\n", inb(0xc46));
2442 #endif
2443
2444         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2445         outb((0x03), 0xc46);    /* FM base 15:8 = 0x03 */
2446         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2447         outb((0x11), 0xc46);    /* ASIC ID = 0x11 */
2448
2449 #ifdef DEBUGXL
2450         /* Debug printing */
2451         printk("Port 0xc46 (after): ");
2452         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2453         printk("%02x ", inb(0xc46));
2454         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2455         printk("%02x\n", inb(0xc46));
2456 #endif
2457
2458         /*
2459          * I/O port 0xc47 FM Address Decode Register.
2460          *
2461          * bank=0, bits 0xff:   Decode enable selection for various FM address bits
2462          * bank=1, bits 0xff:   Reserved
2463          */
2464
2465 #ifdef DEBUGXL
2466         /* Debug printing */
2467         printk("Port 0xc47 (before): ");
2468         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2469         printk("%02x ", inb(0xc47));
2470         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2471         printk("%02x\n", inb(0xc47));
2472 #endif
2473
2474         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2475         outb((0x7c), 0xc47);    /* FM decode enable bits = 0x7c */
2476         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2477         outb((0x00), 0xc47);    /* Reserved bank1 = 0x00 */
2478
2479 #ifdef DEBUGXL
2480         /* Debug printing */
2481         printk("Port 0xc47 (after): ");
2482         outb((tmp & ~0x04), 0xc44);     /* Select bank=0 */
2483         printk("%02x ", inb(0xc47));
2484         outb((tmp | 0x04), 0xc44);      /* Select bank=1 */
2485         printk("%02x\n", inb(0xc47));
2486 #endif
2487
2488         /*
2489          * I/O port 0xc6f = Audio Disable Function Register
2490          */
2491
2492 #ifdef DEBUGXL
2493         printk("Port 0xc6f (before) = %02x\n", inb(0xc6f));
2494 #endif
2495
2496         outb((0x80), 0xc6f);
2497
2498 #ifdef DEBUGXL
2499         printk("Port 0xc6f (after) = %02x\n", inb(0xc6f));
2500 #endif
2501
2502         return 1;
2503 }
2504
2505 int probe_ms_sound(struct address_info *hw_config, struct resource *ports)
2506 {
2507         unsigned char   tmp;
2508
2509         DDB(printk("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
2510
2511         if (hw_config->card_subtype == 1)       /* Has no IRQ/DMA registers */
2512         {
2513                 /* check_opl3(0x388, hw_config); */
2514                 return ad1848_detect(ports, NULL, hw_config->osp);
2515         }
2516
2517         if (deskpro_xl && hw_config->card_subtype == 2) /* Compaq Deskpro XL */
2518         {
2519                 if (!init_deskpro(hw_config))
2520                         return 0;
2521         }
2522
2523         if (deskpro_m)  /* Compaq Deskpro M */
2524         {
2525                 if (!init_deskpro_m(hw_config))
2526                         return 0;
2527         }
2528
2529         /*
2530            * Check if the IO port returns valid signature. The original MS Sound
2531            * system returns 0x04 while some cards (AudioTrix Pro for example)
2532            * return 0x00 or 0x0f.
2533          */
2534
2535         if ((tmp = inb(hw_config->io_base + 3)) == 0xff)        /* Bus float */
2536         {
2537                   int             ret;
2538
2539                   DDB(printk("I/O address is inactive (%x)\n", tmp));
2540                   if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
2541                           return 0;
2542                   return 1;
2543         }
2544         DDB(printk("MSS signature = %x\n", tmp & 0x3f));
2545         if ((tmp & 0x3f) != 0x04 &&
2546             (tmp & 0x3f) != 0x0f &&
2547             (tmp & 0x3f) != 0x00)
2548         {
2549                 int ret;
2550
2551                 MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3)));
2552                 DDB(printk("Trying to detect codec anyway but IRQ/DMA may not work\n"));
2553                 if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
2554                         return 0;
2555
2556                 hw_config->card_subtype = 1;
2557                 return 1;
2558         }
2559         if ((hw_config->irq != 5)  &&
2560             (hw_config->irq != 7)  &&
2561             (hw_config->irq != 9)  &&
2562             (hw_config->irq != 10) &&
2563             (hw_config->irq != 11) &&
2564             (hw_config->irq != 12))
2565         {
2566                 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2567                 return 0;
2568         }
2569         if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
2570         {
2571                   printk(KERN_ERR "MSS: Bad DMA %d\n", hw_config->dma);
2572                   return 0;
2573         }
2574         /*
2575          * Check that DMA0 is not in use with a 8 bit board.
2576          */
2577
2578         if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80)
2579         {
2580                 printk(KERN_ERR "MSS: Can't use DMA0 with a 8 bit card/slot\n");
2581                 return 0;
2582         }
2583         if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80)
2584         {
2585                 printk(KERN_ERR "MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
2586                 return 0;
2587         }
2588         return ad1848_detect(ports, NULL, hw_config->osp);
2589 }
2590
2591 void attach_ms_sound(struct address_info *hw_config, struct resource *ports, struct module *owner)
2592 {
2593         static signed char interrupt_bits[12] =
2594         {
2595                 -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20
2596         };
2597         signed char     bits;
2598         char            dma2_bit = 0;
2599
2600         static char     dma_bits[4] =
2601         {
2602                 1, 2, 0, 3
2603         };
2604
2605         int config_port = hw_config->io_base + 0;
2606         int version_port = hw_config->io_base + 3;
2607         int dma = hw_config->dma;
2608         int dma2 = hw_config->dma2;
2609
2610         if (hw_config->card_subtype == 1)       /* Has no IRQ/DMA registers */
2611         {
2612                 hw_config->slots[0] = ad1848_init("MS Sound System", ports,
2613                                                     hw_config->irq,
2614                                                     hw_config->dma,
2615                                                     hw_config->dma2, 0,
2616                                                     hw_config->osp,
2617                                                     owner);
2618                 return;
2619         }
2620         /*
2621          * Set the IRQ and DMA addresses.
2622          */
2623
2624         bits = interrupt_bits[hw_config->irq];
2625         if (bits == -1)
2626         {
2627                 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2628                 release_region(ports->start, 4);
2629                 release_region(ports->start - 4, 4);
2630                 return;
2631         }
2632         outb((bits | 0x40), config_port);
2633         if ((inb(version_port) & 0x40) == 0)
2634                 printk(KERN_ERR "[MSS: IRQ Conflict?]\n");
2635
2636 /*
2637  * Handle the capture DMA channel
2638  */
2639
2640         if (dma2 != -1 && dma2 != dma)
2641         {
2642                 if (!((dma == 0 && dma2 == 1) ||
2643                         (dma == 1 && dma2 == 0) ||
2644                         (dma == 3 && dma2 == 0)))
2645                 {       /* Unsupported combination. Try to swap channels */
2646                         int tmp = dma;
2647
2648                         dma = dma2;
2649                         dma2 = tmp;
2650                 }
2651                 if ((dma == 0 && dma2 == 1) ||
2652                         (dma == 1 && dma2 == 0) ||
2653                         (dma == 3 && dma2 == 0))
2654                 {
2655                         dma2_bit = 0x04;        /* Enable capture DMA */
2656                 }
2657                 else
2658                 {
2659                         printk(KERN_WARNING "MSS: Invalid capture DMA\n");
2660                         dma2 = dma;
2661                 }
2662         }
2663         else
2664         {
2665                 dma2 = dma;
2666         }
2667
2668         hw_config->dma = dma;
2669         hw_config->dma2 = dma2;
2670
2671         outb((bits | dma_bits[dma] | dma2_bit), config_port);   /* Write IRQ+DMA setup */
2672
2673         hw_config->slots[0] = ad1848_init("MS Sound System", ports,
2674                                           hw_config->irq,
2675                                           dma, dma2, 0,
2676                                           hw_config->osp,
2677                                           THIS_MODULE);
2678 }
2679
2680 void unload_ms_sound(struct address_info *hw_config)
2681 {
2682         ad1848_unload(hw_config->io_base + 4,
2683                       hw_config->irq,
2684                       hw_config->dma,
2685                       hw_config->dma2, 0);
2686         sound_unload_audiodev(hw_config->slots[0]);
2687         release_region(hw_config->io_base, 4);
2688 }
2689
2690 #ifndef EXCLUDE_TIMERS
2691
2692 /*
2693  * Timer stuff (for /dev/music).
2694  */
2695
2696 static unsigned int current_interval;
2697
2698 static unsigned int ad1848_tmr_start(int dev, unsigned int usecs)
2699 {
2700         unsigned long   flags;
2701         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
2702         unsigned long   xtal_nsecs;     /* nanoseconds per xtal oscillator tick */
2703         unsigned long   divider;
2704
2705         spin_lock_irqsave(&devc->lock,flags);
2706
2707         /*
2708          * Length of the timer interval (in nanoseconds) depends on the
2709          * selected crystal oscillator. Check this from bit 0x01 of I8.
2710          *
2711          * AD1845 has just one oscillator which has cycle time of 10.050 us
2712          * (when a 24.576 MHz xtal oscillator is used).
2713          *
2714          * Convert requested interval to nanoseconds before computing
2715          * the timer divider.
2716          */
2717
2718         if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
2719                 xtal_nsecs = 10050;
2720         else if (ad_read(devc, 8) & 0x01)
2721                 xtal_nsecs = 9920;
2722         else
2723                 xtal_nsecs = 9969;
2724
2725         divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
2726
2727         if (divider < 100)      /* Don't allow shorter intervals than about 1ms */
2728                 divider = 100;
2729
2730         if (divider > 65535)    /* Overflow check */
2731                 divider = 65535;
2732
2733         ad_write(devc, 21, (divider >> 8) & 0xff);      /* Set upper bits */
2734         ad_write(devc, 20, divider & 0xff);     /* Set lower bits */
2735         ad_write(devc, 16, ad_read(devc, 16) | 0x40);   /* Start the timer */
2736         devc->timer_running = 1;
2737         spin_unlock_irqrestore(&devc->lock,flags);
2738
2739         return current_interval = (divider * xtal_nsecs + 500) / 1000;
2740 }
2741
2742 static void ad1848_tmr_reprogram(int dev)
2743 {
2744         /*
2745          *    Audio driver has changed sampling rate so that a different xtal
2746          *      oscillator was selected. We have to reprogram the timer rate.
2747          */
2748
2749         ad1848_tmr_start(dev, current_interval);
2750         sound_timer_syncinterval(current_interval);
2751 }
2752
2753 static void ad1848_tmr_disable(int dev)
2754 {
2755         unsigned long   flags;
2756         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
2757
2758         spin_lock_irqsave(&devc->lock,flags);
2759         ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
2760         devc->timer_running = 0;
2761         spin_unlock_irqrestore(&devc->lock,flags);
2762 }
2763
2764 static void ad1848_tmr_restart(int dev)
2765 {
2766         unsigned long   flags;
2767         ad1848_info    *devc = (ad1848_info *) audio_devs[dev]->devc;
2768
2769         if (current_interval == 0)
2770                 return;
2771
2772         spin_lock_irqsave(&devc->lock,flags);
2773         ad_write(devc, 16, ad_read(devc, 16) | 0x40);
2774         devc->timer_running = 1;
2775         spin_unlock_irqrestore(&devc->lock,flags);
2776 }
2777
2778 static struct sound_lowlev_timer ad1848_tmr =
2779 {
2780         0,
2781         2,
2782         ad1848_tmr_start,
2783         ad1848_tmr_disable,
2784         ad1848_tmr_restart
2785 };
2786
2787 static int ad1848_tmr_install(int dev)
2788 {
2789         if (timer_installed != -1)
2790                 return 0;       /* Don't install another timer */
2791
2792         timer_installed = ad1848_tmr.dev = dev;
2793         sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);
2794
2795         return 1;
2796 }
2797 #endif /* EXCLUDE_TIMERS */
2798
2799 EXPORT_SYMBOL(ad1848_detect);
2800 EXPORT_SYMBOL(ad1848_init);
2801 EXPORT_SYMBOL(ad1848_unload);
2802 EXPORT_SYMBOL(ad1848_control);
2803 EXPORT_SYMBOL(probe_ms_sound);
2804 EXPORT_SYMBOL(attach_ms_sound);
2805 EXPORT_SYMBOL(unload_ms_sound);
2806
2807 static int __initdata io = -1;
2808 static int __initdata irq = -1;
2809 static int __initdata dma = -1;
2810 static int __initdata dma2 = -1;
2811 static int __initdata type = 0;
2812
2813 module_param(io, int, 0);               /* I/O for a raw AD1848 card */
2814 module_param(irq, int, 0);              /* IRQ to use */
2815 module_param(dma, int, 0);              /* First DMA channel */
2816 module_param(dma2, int, 0);             /* Second DMA channel */
2817 module_param(type, int, 0);             /* Card type */
2818 module_param(deskpro_xl, bool, 0);      /* Special magic for Deskpro XL boxen */
2819 module_param(deskpro_m, bool, 0);       /* Special magic for Deskpro M box */
2820 module_param(soundpro, bool, 0);        /* More special magic for SoundPro chips */
2821
2822 #ifdef CONFIG_PNP
2823 module_param(isapnp, int, 0);
2824 module_param(isapnpjump, int, 0);
2825 module_param(reverse, bool, 0);
2826 MODULE_PARM_DESC(isapnp,        "When set to 0, Plug & Play support will be disabled");
2827 MODULE_PARM_DESC(isapnpjump,    "Jumps to a specific slot in the driver's PnP table. Use the source, Luke.");
2828 MODULE_PARM_DESC(reverse,       "When set to 1, will reverse ISAPnP search order");
2829
2830 static struct pnp_dev   *ad1848_dev  = NULL;
2831
2832 /* Please add new entries at the end of the table */
2833 static struct {
2834         char *name;
2835         unsigned short  card_vendor, card_device,
2836                         vendor, function;
2837         short mss_io, irq, dma, dma2;   /* index into isapnp table */
2838         int type;
2839 } ad1848_isapnp_list[] __initdata = {
2840         {"CMI 8330 SoundPRO",
2841                 ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2842                 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001),
2843                 0, 0, 0,-1, 0},
2844         {"CS4232 based card",
2845                 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2846                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000),
2847                 0, 0, 0, 1, 0},
2848         {"CS4232 based card",
2849                 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2850                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100),
2851                 0, 0, 0, 1, 0},
2852         {"OPL3-SA2 WSS mode",
2853                 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2854                 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021),
2855                 1, 0, 0, 1, 1},
2856         {"Advanced Gravis InterWave Audio",
2857                 ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2858                 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000),
2859                 0, 0, 0, 1, 0},
2860         {NULL}
2861 };
2862
2863 #ifdef MODULE
2864 static struct isapnp_device_id id_table[] = {
2865         {       ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2866                 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001), 0 },
2867         {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2868                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000), 0 },
2869         {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2870                 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100), 0 },
2871         /* The main driver for this card is opl3sa2
2872         {       ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2873                 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021), 0 },
2874         */
2875         {       ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2876                 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000), 0 },
2877         {0}
2878 };
2879
2880 MODULE_DEVICE_TABLE(isapnp, id_table);
2881 #endif
2882
2883 static struct pnp_dev *activate_dev(char *devname, char *resname, struct pnp_dev *dev)
2884 {
2885         int err;
2886
2887         err = pnp_device_attach(dev);
2888         if (err < 0)
2889                 return(NULL);
2890
2891         if((err = pnp_activate_dev(dev)) < 0) {
2892                 printk(KERN_ERR "ad1848: %s %s config failed (out of resources?)[%d]\n", devname, resname, err);
2893
2894                 pnp_device_detach(dev);
2895
2896                 return(NULL);
2897         }
2898         audio_activated = 1;
2899         return(dev);
2900 }
2901
2902 static struct pnp_dev __init *ad1848_init_generic(struct pnp_card *bus,
2903                                 struct address_info *hw_config, int slot)
2904 {
2905
2906         /* Configure Audio device */
2907         if((ad1848_dev = pnp_find_dev(bus, ad1848_isapnp_list[slot].vendor, ad1848_isapnp_list[slot].function, NULL)))
2908         {
2909                 if((ad1848_dev = activate_dev(ad1848_isapnp_list[slot].name, "ad1848", ad1848_dev)))
2910                 {
2911                         hw_config->io_base      = pnp_port_start(ad1848_dev, ad1848_isapnp_list[slot].mss_io);
2912                         hw_config->irq          = pnp_irq(ad1848_dev, ad1848_isapnp_list[slot].irq);
2913                         hw_config->dma          = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma);
2914                         if(ad1848_isapnp_list[slot].dma2 != -1)
2915                                 hw_config->dma2 = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma2);
2916                         else
2917                                 hw_config->dma2 = -1;
2918                         hw_config->card_subtype = ad1848_isapnp_list[slot].type;
2919                 } else
2920                         return(NULL);
2921         } else
2922                 return(NULL);
2923
2924         return(ad1848_dev);
2925 }
2926
2927 static int __init ad1848_isapnp_init(struct address_info *hw_config, struct pnp_card *bus, int slot)
2928 {
2929         char *busname = bus->name[0] ? bus->name : ad1848_isapnp_list[slot].name;
2930
2931         /* Initialize this baby. */
2932
2933         if(ad1848_init_generic(bus, hw_config, slot)) {
2934                 /* We got it. */
2935
2936                 printk(KERN_NOTICE "ad1848: PnP reports '%s' at i/o %#x, irq %d, dma %d, %d\n",
2937                        busname,
2938                        hw_config->io_base, hw_config->irq, hw_config->dma,
2939                        hw_config->dma2);
2940                 return 1;
2941         }
2942         return 0;
2943 }
2944
2945 static int __init ad1848_isapnp_probe(struct address_info *hw_config)
2946 {
2947         static int first = 1;
2948         int i;
2949
2950         /* Count entries in sb_isapnp_list */
2951         for (i = 0; ad1848_isapnp_list[i].card_vendor != 0; i++);
2952         i--;
2953
2954         /* Check and adjust isapnpjump */
2955         if( isapnpjump < 0 || isapnpjump > i) {
2956                 isapnpjump = reverse ? i : 0;
2957                 printk(KERN_ERR "ad1848: Valid range for isapnpjump is 0-%d. Adjusted to %d.\n", i, isapnpjump);
2958         }
2959
2960         if(!first || !reverse)
2961                 i = isapnpjump;
2962         first = 0;
2963         while(ad1848_isapnp_list[i].card_vendor != 0) {
2964                 static struct pnp_card *bus = NULL;
2965
2966                 while ((bus = pnp_find_card(
2967                                 ad1848_isapnp_list[i].card_vendor,
2968                                 ad1848_isapnp_list[i].card_device,
2969                                 bus))) {
2970
2971                         if(ad1848_isapnp_init(hw_config, bus, i)) {
2972                                 isapnpjump = i; /* start next search from here */
2973                                 return 0;
2974                         }
2975                 }
2976                 i += reverse ? -1 : 1;
2977         }
2978
2979         return -ENODEV;
2980 }
2981 #endif
2982
2983
2984 static int __init init_ad1848(void)
2985 {
2986         printk(KERN_INFO "ad1848/cs4248 codec driver Copyright (C) by Hannu Savolainen 1993-1996\n");
2987
2988 #ifdef CONFIG_PNP
2989         if(isapnp && (ad1848_isapnp_probe(&cfg) < 0) ) {
2990                 printk(KERN_NOTICE "ad1848: No ISAPnP cards found, trying standard ones...\n");
2991                 isapnp = 0;
2992         }
2993 #endif
2994
2995         if(io != -1) {
2996                 struct resource *ports;
2997                 if( isapnp == 0 )
2998                 {
2999                         if(irq == -1 || dma == -1) {
3000                                 printk(KERN_WARNING "ad1848: must give I/O , IRQ and DMA.\n");
3001                                 return -EINVAL;
3002                         }
3003
3004                         cfg.irq = irq;
3005                         cfg.io_base = io;
3006                         cfg.dma = dma;
3007                         cfg.dma2 = dma2;
3008                         cfg.card_subtype = type;
3009                 }
3010
3011                 ports = request_region(io + 4, 4, "ad1848");
3012
3013                 if (!ports)
3014                         return -EBUSY;
3015
3016                 if (!request_region(io, 4, "WSS config")) {
3017                         release_region(io + 4, 4);
3018                         return -EBUSY;
3019                 }
3020
3021                 if (!probe_ms_sound(&cfg, ports)) {
3022                         release_region(io + 4, 4);
3023                         release_region(io, 4);
3024                         return -ENODEV;
3025                 }
3026                 attach_ms_sound(&cfg, ports, THIS_MODULE);
3027                 loaded = 1;
3028         }
3029         return 0;
3030 }
3031
3032 static void __exit cleanup_ad1848(void)
3033 {
3034         if(loaded)
3035                 unload_ms_sound(&cfg);
3036
3037 #ifdef CONFIG_PNP
3038         if(ad1848_dev){
3039                 if(audio_activated)
3040                         pnp_device_detach(ad1848_dev);
3041         }
3042 #endif
3043 }
3044
3045 module_init(init_ad1848);
3046 module_exit(cleanup_ad1848);
3047
3048 #ifndef MODULE
3049 static int __init setup_ad1848(char *str)
3050 {
3051         /* io, irq, dma, dma2, type */
3052         int ints[6];
3053
3054         str = get_options(str, ARRAY_SIZE(ints), ints);
3055
3056         io      = ints[1];
3057         irq     = ints[2];
3058         dma     = ints[3];
3059         dma2    = ints[4];
3060         type    = ints[5];
3061
3062         return 1;
3063 }
3064
3065 __setup("ad1848=", setup_ad1848);
3066 #endif
3067 MODULE_LICENSE("GPL");