4 * The low level driver for the AD1848/CS4248 codec chip which
5 * is used for example in the MS Sound System.
7 * The CS4231 which is used in the GUS MAX and some other cards is
8 * upwards compatible with AD1848 and this driver is able to drive it.
10 * CS4231A and AD1845 are upward compatible with CS4231. However
11 * the new features of these chips are different.
13 * CS4232 is a PnP audio chip which contains a CS4231A (and SB, MPU).
14 * CS4232A is an improved version of CS4232.
18 * Copyright (C) by Hannu Savolainen 1993-1997
20 * OSS/Free for Linux is distributed under the GNU GENERAL PUBLIC LICENSE (GPL)
21 * Version 2 (June 1991). See the "COPYING" file distributed with this software
25 * Thomas Sailer : ioctl code reworked (vmalloc/vfree removed)
26 * general sleep/wakeup clean up.
27 * Alan Cox : reformatted. Fixed SMP bugs. Moved to kernel alloc/free
28 * of irqs. Use dev_id.
29 * Christoph Hellwig : adapted to module_init/module_exit
30 * Aki Laukkanen : added power management support
31 * Arnaldo C. de Melo : added missing restore_flags in ad1848_resume
32 * Miguel Freitas : added ISA PnP support
33 * Alan Cox : Added CS4236->4239 identification
34 * Daniel T. Cobra : Alernate config/mixer for later chips
35 * Alan Cox : Merged chip idents and config code
38 * APM save restore assist code on IBM thinkpad
41 * Tested. Believed fully functional.
44 #include <linux/init.h>
45 #include <linux/interrupt.h>
46 #include <linux/module.h>
47 #include <linux/stddef.h>
48 #include <linux/slab.h>
49 #include <linux/isapnp.h>
50 #include <linux/pnp.h>
51 #include <linux/spinlock.h>
55 #include "sound_config.h"
58 #include "ad1848_mixer.h"
66 int dual_dma; /* 1, when two DMA channels allocated */
68 unsigned char MCE_bit;
69 unsigned char saved_regs[64]; /* Includes extended register space */
73 int record_dev, playback_dev;
79 char *chip_name, *name;
88 #define MD_4235 8 /* Crystal Audio CS4235 */
89 #define MD_1845_SSCAPE 9 /* Ensoniq Soundscape PNP*/
90 #define MD_4236 10 /* 4236 and higher */
91 #define MD_42xB 11 /* CS 42xB */
92 #define MD_4239 12 /* CS4239 */
94 /* Mixer parameters */
96 int supported_devices, orig_devices;
97 int supported_rec_devices, orig_rec_devices;
99 short mixer_reroute[32];
101 volatile unsigned long timer_ticks;
104 mixer_ents *mix_devices;
105 int mixer_output_port;
108 typedef struct ad1848_port_info
112 unsigned char speed_bits;
115 unsigned char format_bits;
119 static struct address_info cfg;
120 static int nr_ad1848_devs;
122 static int deskpro_xl;
123 static int deskpro_m;
126 static volatile signed char irq2dev[17] = {
127 -1, -1, -1, -1, -1, -1, -1, -1,
128 -1, -1, -1, -1, -1, -1, -1, -1, -1
131 #ifndef EXCLUDE_TIMERS
132 static int timer_installed = -1;
137 static int ad_format_mask[13 /*devc->model */ ] =
140 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW,
141 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
142 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
143 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW, /* AD1845 */
144 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
145 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
146 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
147 AFMT_U8 | AFMT_S16_LE /* CS4235 */,
148 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW /* Ensoniq Soundscape*/,
149 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
150 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM,
151 AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW | AFMT_S16_BE | AFMT_IMA_ADPCM
154 static ad1848_info adev_info[MAX_AUDIO_DEV];
156 #define io_Index_Addr(d) ((d)->base)
157 #define io_Indexed_Data(d) ((d)->base+1)
158 #define io_Status(d) ((d)->base+2)
159 #define io_Polled_IO(d) ((d)->base+3)
163 #define CAP_F_TIMER 0x01
164 } capabilities [10 /*devc->model */ ] = {
167 ,{CAP_F_TIMER} /* MD_4231 */
168 ,{CAP_F_TIMER} /* MD_4231A */
169 ,{CAP_F_TIMER} /* MD_1845 */
170 ,{CAP_F_TIMER} /* MD_4232 */
172 ,{CAP_F_TIMER} /* MD_IWAVE */
174 ,{CAP_F_TIMER} /* MD_1845_SSCAPE */
178 static int isapnp = 1;
179 static int isapnpjump;
182 static int audio_activated;
189 static int ad1848_open(int dev, int mode);
190 static void ad1848_close(int dev);
191 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag);
192 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag);
193 static int ad1848_prepare_for_output(int dev, int bsize, int bcount);
194 static int ad1848_prepare_for_input(int dev, int bsize, int bcount);
195 static void ad1848_halt(int dev);
196 static void ad1848_halt_input(int dev);
197 static void ad1848_halt_output(int dev);
198 static void ad1848_trigger(int dev, int bits);
199 static irqreturn_t adintr(int irq, void *dev_id);
201 #ifndef EXCLUDE_TIMERS
202 static int ad1848_tmr_install(int dev);
203 static void ad1848_tmr_reprogram(int dev);
206 static int ad_read(ad1848_info * devc, int reg)
209 int timeout = 900000;
211 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
216 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
217 x = inb(io_Indexed_Data(devc));
223 xreg = (reg & 0xff) - 32;
224 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
225 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
226 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
227 x = inb(io_Indexed_Data(devc));
233 static void ad_write(ad1848_info * devc, int reg, int data)
235 int timeout = 900000;
237 while (timeout > 0 && inb(devc->base) == 0x80) /* Are we initializing */
242 outb(((unsigned char) (reg & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
243 outb(((unsigned char) (data & 0xff)), io_Indexed_Data(devc));
249 xreg = (reg & 0xff) - 32;
250 xra = (((xreg & 0x0f) << 4) & 0xf0) | 0x08 | ((xreg & 0x10) >> 2);
251 outb(((unsigned char) (23 & 0xff) | devc->MCE_bit), io_Index_Addr(devc));
252 outb(((unsigned char) (xra & 0xff)), io_Indexed_Data(devc));
253 outb((unsigned char) (data & 0xff), io_Indexed_Data(devc));
257 static void wait_for_calibration(ad1848_info * devc)
262 * Wait until the auto calibration process has finished.
264 * 1) Wait until the chip becomes ready (reads don't return 0x80).
265 * 2) Wait until the ACI bit of I11 gets on and then off.
269 while (timeout > 0 && inb(devc->base) == 0x80)
271 if (inb(devc->base) & 0x80)
272 printk(KERN_WARNING "ad1848: Auto calibration timed out(1).\n");
275 while (timeout > 0 && !(ad_read(devc, 11) & 0x20))
277 if (!(ad_read(devc, 11) & 0x20))
281 while (timeout > 0 && (ad_read(devc, 11) & 0x20))
283 if (ad_read(devc, 11) & 0x20)
284 if ((devc->model != MD_1845) && (devc->model != MD_1845_SSCAPE))
285 printk(KERN_WARNING "ad1848: Auto calibration timed out(3).\n");
288 static void ad_mute(ad1848_info * devc)
294 * Save old register settings and mute output channels
297 for (i = 6; i < 8; i++)
299 prev = devc->saved_regs[i] = ad_read(devc, i);
304 static void ad_unmute(ad1848_info * devc)
308 static void ad_enter_MCE(ad1848_info * devc)
313 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
316 devc->MCE_bit = 0x40;
317 prev = inb(io_Index_Addr(devc));
322 outb((devc->MCE_bit), io_Index_Addr(devc));
325 static void ad_leave_MCE(ad1848_info * devc)
327 unsigned char prev, acal;
330 while (timeout > 0 && inb(devc->base) == 0x80) /*Are we initializing */
333 acal = ad_read(devc, 9);
335 devc->MCE_bit = 0x00;
336 prev = inb(io_Index_Addr(devc));
337 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
339 if ((prev & 0x40) == 0) /* Not in MCE mode */
343 outb((0x00), io_Index_Addr(devc)); /* Clear the MCE bit */
344 if (acal & 0x08) /* Auto calibration is enabled */
345 wait_for_calibration(devc);
348 static int ad1848_set_recmask(ad1848_info * devc, int mask)
350 unsigned char recdev;
354 mask &= devc->supported_rec_devices;
356 /* Rename the mixer bits if necessary */
357 for (i = 0; i < 32; i++)
359 if (devc->mixer_reroute[i] != i)
364 mask |= (1 << devc->mixer_reroute[i]);
370 for (i = 0; i < 32; i++) /* Count selected device bits */
374 spin_lock_irqsave(&devc->lock,flags);
377 mask = SOUND_MASK_MIC;
378 else if (n != 1) { /* Too many devices selected */
379 mask &= ~devc->recmask; /* Filter out active settings */
382 for (i = 0; i < 32; i++) /* Count selected device bits */
387 mask = SOUND_MASK_MIC;
394 case SOUND_MASK_LINE:
395 case SOUND_MASK_LINE3:
400 case SOUND_MASK_LINE1:
404 case SOUND_MASK_IMIX:
409 mask = SOUND_MASK_MIC;
414 ad_write(devc, 0, (ad_read(devc, 0) & 0x3f) | recdev);
415 ad_write(devc, 1, (ad_read(devc, 1) & 0x3f) | recdev);
416 } else { /* soundpro */
421 for (i = 0; i < 32; i++) { /* For each bit */
422 if ((devc->supported_rec_devices & (1 << i)) == 0)
423 continue; /* Device not supported */
425 for (j = LEFT_CHN; j <= RIGHT_CHN; j++) {
426 if (devc->mix_devices[i][j].nbits == 0) /* Inexistent channel */
431 * set_rec_bit becomes 1 if the corresponding bit in mask is set
432 * then it gets flipped if the polarity is inverse
434 set_rec_bit = ((mask & (1 << i)) != 0) ^ devc->mix_devices[i][j].recpol;
436 val = ad_read(devc, devc->mix_devices[i][j].recreg);
437 val &= ~(1 << devc->mix_devices[i][j].recpos);
438 val |= (set_rec_bit << devc->mix_devices[i][j].recpos);
439 ad_write(devc, devc->mix_devices[i][j].recreg, val);
443 spin_unlock_irqrestore(&devc->lock,flags);
445 /* Rename the mixer bits back if necessary */
446 for (i = 0; i < 32; i++)
448 if (devc->mixer_reroute[i] != i)
450 if (mask & (1 << devc->mixer_reroute[i]))
452 mask &= ~(1 << devc->mixer_reroute[i]);
457 devc->recmask = mask;
461 static void change_bits(ad1848_info * devc, unsigned char *regval,
462 unsigned char *muteval, int dev, int chn, int newval)
470 set_mute_bit = (newval == 0) ^ devc->mix_devices[dev][chn].mutepol;
472 if (devc->mix_devices[dev][chn].polarity == 1) /* Reverse */
473 newval = 100 - newval;
475 mask = (1 << devc->mix_devices[dev][chn].nbits) - 1;
476 shift = devc->mix_devices[dev][chn].bitpos;
478 if (devc->mix_devices[dev][chn].mutepos == 8)
479 { /* if there is no mute bit */
480 mute = 0; /* No mute bit; do nothing special */
481 mutemask = ~0; /* No mute bit; do nothing special */
485 mute = (set_mute_bit << devc->mix_devices[dev][chn].mutepos);
486 mutemask = ~(1 << devc->mix_devices[dev][chn].mutepos);
489 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */
490 *regval &= ~(mask << shift); /* Clear bits */
491 *regval |= (newval & mask) << shift; /* Set new value */
493 *muteval &= mutemask;
497 static int ad1848_mixer_get(ad1848_info * devc, int dev)
499 if (!((1 << dev) & devc->supported_devices))
502 dev = devc->mixer_reroute[dev];
504 return devc->levels[dev];
507 static void ad1848_mixer_set_channel(ad1848_info *devc, int dev, int value, int channel)
509 int regoffs, muteregoffs;
510 unsigned char val, muteval;
513 regoffs = devc->mix_devices[dev][channel].regno;
514 muteregoffs = devc->mix_devices[dev][channel].mutereg;
515 val = ad_read(devc, regoffs);
517 if (muteregoffs != regoffs) {
518 muteval = ad_read(devc, muteregoffs);
519 change_bits(devc, &val, &muteval, dev, channel, value);
522 change_bits(devc, &val, &val, dev, channel, value);
524 spin_lock_irqsave(&devc->lock,flags);
525 ad_write(devc, regoffs, val);
526 devc->saved_regs[regoffs] = val;
527 if (muteregoffs != regoffs) {
528 ad_write(devc, muteregoffs, muteval);
529 devc->saved_regs[muteregoffs] = muteval;
531 spin_unlock_irqrestore(&devc->lock,flags);
534 static int ad1848_mixer_set(ad1848_info * devc, int dev, int value)
536 int left = value & 0x000000ff;
537 int right = (value & 0x0000ff00) >> 8;
543 if (!(devc->supported_devices & (1 << dev)))
546 dev = devc->mixer_reroute[dev];
548 if (devc->mix_devices[dev][LEFT_CHN].nbits == 0)
556 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0) /* Mono control */
559 retvol = left | (right << 8);
562 left = mix_cvt[left];
563 right = mix_cvt[right];
565 devc->levels[dev] = retvol;
568 * Set the left channel
570 ad1848_mixer_set_channel(devc, dev, left, LEFT_CHN);
573 * Set the right channel
575 if (devc->mix_devices[dev][RIGHT_CHN].nbits == 0)
577 ad1848_mixer_set_channel(devc, dev, right, RIGHT_CHN);
583 static void ad1848_mixer_reset(ad1848_info * devc)
589 devc->mix_devices = &(ad1848_mix_devices[0]);
591 sprintf(name, "%s_%d", devc->chip_name, nr_ad1848_devs);
593 for (i = 0; i < 32; i++)
594 devc->mixer_reroute[i] = i;
596 devc->supported_rec_devices = MODE1_REC_DEVICES;
604 devc->supported_devices = MODE2_MIXER_DEVICES;
608 devc->supported_devices = C930_MIXER_DEVICES;
609 devc->mix_devices = &(c930_mix_devices[0]);
613 devc->supported_devices = MODE3_MIXER_DEVICES;
614 devc->mix_devices = &(iwave_mix_devices[0]);
619 devc->mix_devices = &(cs42xb_mix_devices[0]);
620 devc->supported_devices = MODE3_MIXER_DEVICES;
625 devc->supported_devices = MODE3_MIXER_DEVICES;
630 devc->supported_devices = SPRO_MIXER_DEVICES;
631 devc->supported_rec_devices = SPRO_REC_DEVICES;
632 devc->mix_devices = &(spro_mix_devices[0]);
637 devc->supported_devices = MODE1_MIXER_DEVICES;
640 devc->orig_devices = devc->supported_devices;
641 devc->orig_rec_devices = devc->supported_rec_devices;
643 devc->levels = load_mixer_volumes(name, default_mixer_levels, 1);
645 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
647 if (devc->supported_devices & (1 << i))
648 ad1848_mixer_set(devc, i, devc->levels[i]);
651 ad1848_set_recmask(devc, SOUND_MASK_MIC);
653 devc->mixer_output_port = devc->levels[31] | AUDIO_HEADPHONE | AUDIO_LINE_OUT;
655 spin_lock_irqsave(&devc->lock,flags);
657 if (devc->mixer_output_port & AUDIO_SPEAKER)
658 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
660 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
663 * From the "wouldn't it be nice if the mixer API had (better)
664 * support for custom stuff" category
666 /* Enable surround mode and SB16 mixer */
667 ad_write(devc, 16, 0x60);
669 spin_unlock_irqrestore(&devc->lock,flags);
672 static int ad1848_mixer_ioctl(int dev, unsigned int cmd, void __user *arg)
674 ad1848_info *devc = mixer_devs[dev]->devc;
677 if (cmd == SOUND_MIXER_PRIVATE1)
679 if (get_user(val, (int __user *)arg))
685 val &= (AUDIO_SPEAKER | AUDIO_HEADPHONE | AUDIO_LINE_OUT);
686 devc->mixer_output_port = val;
687 val |= AUDIO_HEADPHONE | AUDIO_LINE_OUT; /* Always on */
688 devc->mixer_output_port = val;
689 spin_lock_irqsave(&devc->lock,flags);
690 if (val & AUDIO_SPEAKER)
691 ad_write(devc, 26, ad_read(devc, 26) & ~0x40); /* Unmute mono out */
693 ad_write(devc, 26, ad_read(devc, 26) | 0x40); /* Mute mono out */
694 spin_unlock_irqrestore(&devc->lock,flags);
696 val = devc->mixer_output_port;
697 return put_user(val, (int __user *)arg);
699 if (cmd == SOUND_MIXER_PRIVATE2)
701 if (get_user(val, (int __user *)arg))
703 return(ad1848_control(AD1848_MIXER_REROUTE, val));
705 if (((cmd >> 8) & 0xff) == 'M')
707 if (_SIOC_DIR(cmd) & _SIOC_WRITE)
711 case SOUND_MIXER_RECSRC:
712 if (get_user(val, (int __user *)arg))
714 val = ad1848_set_recmask(devc, val);
718 if (get_user(val, (int __user *)arg))
720 val = ad1848_mixer_set(devc, cmd & 0xff, val);
723 return put_user(val, (int __user *)arg);
733 case SOUND_MIXER_RECSRC:
737 case SOUND_MIXER_DEVMASK:
738 val = devc->supported_devices;
741 case SOUND_MIXER_STEREODEVS:
742 val = devc->supported_devices;
743 if (devc->model != MD_C930)
744 val &= ~(SOUND_MASK_SPEAKER | SOUND_MASK_IMIX);
747 case SOUND_MIXER_RECMASK:
748 val = devc->supported_rec_devices;
751 case SOUND_MIXER_CAPS:
752 val=SOUND_CAP_EXCL_INPUT;
756 val = ad1848_mixer_get(devc, cmd & 0xff);
759 return put_user(val, (int __user *)arg);
766 static int ad1848_set_speed(int dev, int arg)
768 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
769 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
772 * The sampling speed is encoded in the least significant nibble of I8. The
773 * LSB selects the clock source (0=24.576 MHz, 1=16.9344 MHz) and other
774 * three bits select the divisor (indirectly):
776 * The available speeds are in the following table. Keep the speeds in
777 * the increasing order.
786 static speed_struct speed_table[] =
788 {5510, (0 << 1) | 1},
789 {5510, (0 << 1) | 1},
790 {6620, (7 << 1) | 1},
791 {8000, (0 << 1) | 0},
792 {9600, (7 << 1) | 0},
793 {11025, (1 << 1) | 1},
794 {16000, (1 << 1) | 0},
795 {18900, (2 << 1) | 1},
796 {22050, (3 << 1) | 1},
797 {27420, (2 << 1) | 0},
798 {32000, (3 << 1) | 0},
799 {33075, (6 << 1) | 1},
800 {37800, (4 << 1) | 1},
801 {44100, (5 << 1) | 1},
802 {48000, (6 << 1) | 0}
805 int i, n, selected = -1;
807 n = sizeof(speed_table) / sizeof(speed_struct);
812 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* AD1845 has different timer than others */
820 portc->speed_bits = speed_table[3].bits;
823 if (arg < speed_table[0].speed)
825 if (arg > speed_table[n - 1].speed)
828 for (i = 1 /*really */ ; selected == -1 && i < n; i++)
830 if (speed_table[i].speed == arg)
832 else if (speed_table[i].speed > arg)
836 diff1 = arg - speed_table[i - 1].speed;
837 diff2 = speed_table[i].speed - arg;
847 printk(KERN_WARNING "ad1848: Can't find speed???\n");
850 portc->speed = speed_table[selected].speed;
851 portc->speed_bits = speed_table[selected].bits;
855 static short ad1848_set_channels(int dev, short arg)
857 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
859 if (arg != 1 && arg != 2)
860 return portc->channels;
862 portc->channels = arg;
866 static unsigned int ad1848_set_bits(int dev, unsigned int arg)
868 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
869 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
871 static struct format_tbl
918 int i, n = sizeof(format2bits) / sizeof(struct format_tbl);
921 return portc->audio_format;
923 if (!(arg & ad_format_mask[devc->model]))
926 portc->audio_format = arg;
928 for (i = 0; i < n; i++)
929 if (format2bits[i].format == arg)
931 if ((portc->format_bits = format2bits[i].bits) == 0)
932 return portc->audio_format = AFMT_U8; /* Was not supported */
936 /* Still hanging here. Something must be terribly wrong */
937 portc->format_bits = 0;
938 return portc->audio_format = AFMT_U8;
941 static struct audio_driver ad1848_audio_driver =
943 .owner = THIS_MODULE,
945 .close = ad1848_close,
946 .output_block = ad1848_output_block,
947 .start_input = ad1848_start_input,
948 .prepare_for_input = ad1848_prepare_for_input,
949 .prepare_for_output = ad1848_prepare_for_output,
950 .halt_io = ad1848_halt,
951 .halt_input = ad1848_halt_input,
952 .halt_output = ad1848_halt_output,
953 .trigger = ad1848_trigger,
954 .set_speed = ad1848_set_speed,
955 .set_bits = ad1848_set_bits,
956 .set_channels = ad1848_set_channels
959 static struct mixer_operations ad1848_mixer_operations =
961 .owner = THIS_MODULE,
963 .name = "AD1848/CS4248/CS4231",
964 .ioctl = ad1848_mixer_ioctl
967 static int ad1848_open(int dev, int mode)
970 ad1848_port_info *portc;
973 if (dev < 0 || dev >= num_audiodevs)
976 devc = (ad1848_info *) audio_devs[dev]->devc;
977 portc = (ad1848_port_info *) audio_devs[dev]->portc;
979 /* here we don't have to protect against intr */
980 spin_lock(&devc->lock);
981 if (portc->open_mode || (devc->open_mode & mode))
983 spin_unlock(&devc->lock);
988 if (audio_devs[dev]->flags & DMA_DUPLEX)
992 devc->intr_active = 0;
993 devc->audio_mode = 0;
994 devc->open_mode |= mode;
995 portc->open_mode = mode;
996 spin_unlock(&devc->lock);
997 ad1848_trigger(dev, 0);
999 if (mode & OPEN_READ)
1000 devc->record_dev = dev;
1001 if (mode & OPEN_WRITE)
1002 devc->playback_dev = dev;
1004 * Mute output until the playback really starts. This decreases clicking (hope so).
1006 spin_lock_irqsave(&devc->lock,flags);
1008 spin_unlock_irqrestore(&devc->lock,flags);
1013 static void ad1848_close(int dev)
1015 unsigned long flags;
1016 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1017 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1019 DEB(printk("ad1848_close(void)\n"));
1021 devc->intr_active = 0;
1024 spin_lock_irqsave(&devc->lock,flags);
1026 devc->audio_mode = 0;
1027 devc->open_mode &= ~portc->open_mode;
1028 portc->open_mode = 0;
1031 spin_unlock_irqrestore(&devc->lock,flags);
1034 static void ad1848_output_block(int dev, unsigned long buf, int count, int intrflag)
1036 unsigned long flags, cnt;
1037 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1038 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1042 if (portc->audio_format == AFMT_IMA_ADPCM)
1048 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
1051 if (portc->channels > 1)
1055 if ((devc->audio_mode & PCM_ENABLE_OUTPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1057 cnt == devc->xfer_count)
1059 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1060 devc->intr_active = 1;
1062 * Auto DMA mode on. No need to react
1065 spin_lock_irqsave(&devc->lock,flags);
1067 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1068 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1070 devc->xfer_count = cnt;
1071 devc->audio_mode |= PCM_ENABLE_OUTPUT;
1072 devc->intr_active = 1;
1073 spin_unlock_irqrestore(&devc->lock,flags);
1076 static void ad1848_start_input(int dev, unsigned long buf, int count, int intrflag)
1078 unsigned long flags, cnt;
1079 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1080 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1083 if (portc->audio_format == AFMT_IMA_ADPCM)
1089 if (portc->audio_format & (AFMT_S16_LE | AFMT_S16_BE)) /* 16 bit data */
1092 if (portc->channels > 1)
1096 if ((devc->audio_mode & PCM_ENABLE_INPUT) && (audio_devs[dev]->flags & DMA_AUTOMODE) &&
1098 cnt == devc->xfer_count)
1100 devc->audio_mode |= PCM_ENABLE_INPUT;
1101 devc->intr_active = 1;
1103 * Auto DMA mode on. No need to react
1106 spin_lock_irqsave(&devc->lock,flags);
1108 if (devc->model == MD_1848)
1110 ad_write(devc, 15, (unsigned char) (cnt & 0xff));
1111 ad_write(devc, 14, (unsigned char) ((cnt >> 8) & 0xff));
1115 ad_write(devc, 31, (unsigned char) (cnt & 0xff));
1116 ad_write(devc, 30, (unsigned char) ((cnt >> 8) & 0xff));
1121 devc->xfer_count = cnt;
1122 devc->audio_mode |= PCM_ENABLE_INPUT;
1123 devc->intr_active = 1;
1124 spin_unlock_irqrestore(&devc->lock,flags);
1127 static int ad1848_prepare_for_output(int dev, int bsize, int bcount)
1130 unsigned char fs, old_fs, tmp = 0;
1131 unsigned long flags;
1132 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1133 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1137 spin_lock_irqsave(&devc->lock,flags);
1138 fs = portc->speed_bits | (portc->format_bits << 5);
1140 if (portc->channels > 1)
1143 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1145 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE) /* Use alternate speed select registers */
1147 fs &= 0xf0; /* Mask off the rate select bits */
1149 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1150 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1152 old_fs = ad_read(devc, 8);
1154 if (devc->model == MD_4232 || devc->model >= MD_4236)
1156 tmp = ad_read(devc, 16);
1157 ad_write(devc, 16, tmp | 0x30);
1159 if (devc->model == MD_IWAVE)
1160 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1162 ad_write(devc, 8, fs);
1165 * Write to I8 starts resynchronization. Wait until it completes.
1169 while (timeout < 100 && inb(devc->base) != 0x80)
1172 while (timeout < 10000 && inb(devc->base) == 0x80)
1175 if (devc->model >= MD_4232)
1176 ad_write(devc, 16, tmp & ~0x30);
1178 ad_leave_MCE(devc); /*
1179 * Starts the calibration process.
1181 spin_unlock_irqrestore(&devc->lock,flags);
1182 devc->xfer_count = 0;
1184 #ifndef EXCLUDE_TIMERS
1185 if (dev == timer_installed && devc->timer_running)
1186 if ((fs & 0x01) != (old_fs & 0x01))
1188 ad1848_tmr_reprogram(dev);
1191 ad1848_halt_output(dev);
1195 static int ad1848_prepare_for_input(int dev, int bsize, int bcount)
1198 unsigned char fs, old_fs, tmp = 0;
1199 unsigned long flags;
1200 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1201 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1203 if (devc->audio_mode)
1206 spin_lock_irqsave(&devc->lock,flags);
1207 fs = portc->speed_bits | (portc->format_bits << 5);
1209 if (portc->channels > 1)
1212 ad_enter_MCE(devc); /* Enables changes to the format select reg */
1214 if ((devc->model == MD_1845) || (devc->model == MD_1845_SSCAPE)) /* Use alternate speed select registers */
1216 fs &= 0xf0; /* Mask off the rate select bits */
1218 ad_write(devc, 22, (portc->speed >> 8) & 0xff); /* Speed MSB */
1219 ad_write(devc, 23, portc->speed & 0xff); /* Speed LSB */
1221 if (devc->model == MD_4232)
1223 tmp = ad_read(devc, 16);
1224 ad_write(devc, 16, tmp | 0x30);
1226 if (devc->model == MD_IWAVE)
1227 ad_write(devc, 17, 0xc2); /* Disable variable frequency select */
1230 * If mode >= 2 (CS4231), set I28. It's the capture format register.
1233 if (devc->model != MD_1848)
1235 old_fs = ad_read(devc, 28);
1236 ad_write(devc, 28, fs);
1239 * Write to I28 starts resynchronization. Wait until it completes.
1243 while (timeout < 100 && inb(devc->base) != 0x80)
1247 while (timeout < 10000 && inb(devc->base) == 0x80)
1250 if (devc->model != MD_1848 && devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
1253 * CS4231 compatible devices don't have separate sampling rate selection
1254 * register for recording an playback. The I8 register is shared so we have to
1255 * set the speed encoding bits of it too.
1257 unsigned char tmp = portc->speed_bits | (ad_read(devc, 8) & 0xf0);
1259 ad_write(devc, 8, tmp);
1261 * Write to I8 starts resynchronization. Wait until it completes.
1264 while (timeout < 100 && inb(devc->base) != 0x80)
1268 while (timeout < 10000 && inb(devc->base) == 0x80)
1273 { /* For AD1848 set I8. */
1275 old_fs = ad_read(devc, 8);
1276 ad_write(devc, 8, fs);
1278 * Write to I8 starts resynchronization. Wait until it completes.
1281 while (timeout < 100 && inb(devc->base) != 0x80)
1284 while (timeout < 10000 && inb(devc->base) == 0x80)
1288 if (devc->model == MD_4232)
1289 ad_write(devc, 16, tmp & ~0x30);
1291 ad_leave_MCE(devc); /*
1292 * Starts the calibration process.
1294 spin_unlock_irqrestore(&devc->lock,flags);
1295 devc->xfer_count = 0;
1297 #ifndef EXCLUDE_TIMERS
1298 if (dev == timer_installed && devc->timer_running)
1300 if ((fs & 0x01) != (old_fs & 0x01))
1302 ad1848_tmr_reprogram(dev);
1306 ad1848_halt_input(dev);
1310 static void ad1848_halt(int dev)
1312 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1313 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1315 unsigned char bits = ad_read(devc, 9);
1317 if (bits & 0x01 && (portc->open_mode & OPEN_WRITE))
1318 ad1848_halt_output(dev);
1320 if (bits & 0x02 && (portc->open_mode & OPEN_READ))
1321 ad1848_halt_input(dev);
1322 devc->audio_mode = 0;
1325 static void ad1848_halt_input(int dev)
1327 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1328 unsigned long flags;
1330 if (!(ad_read(devc, 9) & 0x02))
1331 return; /* Capture not enabled */
1333 spin_lock_irqsave(&devc->lock,flags);
1340 if(!isa_dma_bridge_buggy)
1341 disable_dma(audio_devs[dev]->dmap_in->dma);
1343 for (tmout = 0; tmout < 100000; tmout++)
1344 if (ad_read(devc, 11) & 0x10)
1346 ad_write(devc, 9, ad_read(devc, 9) & ~0x02); /* Stop capture */
1348 if(!isa_dma_bridge_buggy)
1349 enable_dma(audio_devs[dev]->dmap_in->dma);
1350 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1353 outb(0, io_Status(devc)); /* Clear interrupt status */
1354 outb(0, io_Status(devc)); /* Clear interrupt status */
1356 devc->audio_mode &= ~PCM_ENABLE_INPUT;
1358 spin_unlock_irqrestore(&devc->lock,flags);
1361 static void ad1848_halt_output(int dev)
1363 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1364 unsigned long flags;
1366 if (!(ad_read(devc, 9) & 0x01))
1367 return; /* Playback not enabled */
1369 spin_lock_irqsave(&devc->lock,flags);
1375 if(!isa_dma_bridge_buggy)
1376 disable_dma(audio_devs[dev]->dmap_out->dma);
1378 for (tmout = 0; tmout < 100000; tmout++)
1379 if (ad_read(devc, 11) & 0x10)
1381 ad_write(devc, 9, ad_read(devc, 9) & ~0x01); /* Stop playback */
1383 if(!isa_dma_bridge_buggy)
1384 enable_dma(audio_devs[dev]->dmap_out->dma);
1386 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1389 outb((0), io_Status(devc)); /* Clear interrupt status */
1390 outb((0), io_Status(devc)); /* Clear interrupt status */
1392 devc->audio_mode &= ~PCM_ENABLE_OUTPUT;
1394 spin_unlock_irqrestore(&devc->lock,flags);
1397 static void ad1848_trigger(int dev, int state)
1399 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
1400 ad1848_port_info *portc = (ad1848_port_info *) audio_devs[dev]->portc;
1401 unsigned long flags;
1402 unsigned char tmp, old;
1404 spin_lock_irqsave(&devc->lock,flags);
1405 state &= devc->audio_mode;
1407 tmp = old = ad_read(devc, 9);
1409 if (portc->open_mode & OPEN_READ)
1411 if (state & PCM_ENABLE_INPUT)
1416 if (portc->open_mode & OPEN_WRITE)
1418 if (state & PCM_ENABLE_OUTPUT)
1423 /* ad_mute(devc); */
1426 ad_write(devc, 9, tmp);
1429 spin_unlock_irqrestore(&devc->lock,flags);
1432 static void ad1848_init_hw(ad1848_info * devc)
1438 * Initial values for the indirect registers of CS4248/AD1848.
1440 static int init_values_a[] =
1442 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1443 0x00, 0x0c, 0x02, 0x00, 0x8a, 0x01, 0x00, 0x00,
1445 /* Positions 16 to 31 just for CS4231/2 and ad1845 */
1446 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1447 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1450 static int init_values_b[] =
1453 Values for the newer chips
1454 Some of the register initialization values were changed. In
1455 order to get rid of the click that preceded PCM playback,
1456 calibration was disabled on the 10th byte. On that same byte,
1457 dual DMA was enabled; on the 11th byte, ADC dithering was
1458 enabled, since that is theoretically desirable; on the 13th
1459 byte, Mode 3 was selected, to enable access to extended
1462 0xa8, 0xa8, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00,
1463 0x00, 0x00, 0x06, 0x00, 0xe0, 0x01, 0x00, 0x00,
1464 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x1f, 0x40,
1465 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1469 * Select initialisation data
1472 init_values = init_values_a;
1473 if(devc->model >= MD_4236)
1474 init_values = init_values_b;
1476 for (i = 0; i < 16; i++)
1477 ad_write(devc, i, init_values[i]);
1480 ad_mute(devc); /* Initialize some variables */
1481 ad_unmute(devc); /* Leave it unmuted now */
1483 if (devc->model > MD_1848)
1485 if (devc->model == MD_1845_SSCAPE)
1486 ad_write(devc, 12, ad_read(devc, 12) | 0x50);
1488 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1490 if (devc->model == MD_IWAVE)
1491 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1493 if (devc->model != MD_1845_SSCAPE)
1494 for (i = 16; i < 32; i++)
1495 ad_write(devc, i, init_values[i]);
1497 if (devc->model == MD_IWAVE)
1498 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1500 if (devc->model > MD_1848)
1502 if (devc->audio_flags & DMA_DUPLEX)
1503 ad_write(devc, 9, ad_read(devc, 9) & ~0x04); /* Dual DMA mode */
1505 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1507 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
1508 ad_write(devc, 27, ad_read(devc, 27) | 0x08); /* Alternate freq select enabled */
1510 if (devc->model == MD_IWAVE)
1511 { /* Some magic Interwave specific initialization */
1512 ad_write(devc, 12, 0x6c); /* Select codec mode 3 */
1513 ad_write(devc, 16, 0x30); /* Playback and capture counters enabled */
1514 ad_write(devc, 17, 0xc2); /* Alternate feature enable */
1519 devc->audio_flags &= ~DMA_DUPLEX;
1520 ad_write(devc, 9, ad_read(devc, 9) | 0x04); /* Single DMA mode */
1522 ad_write(devc, 12, ad_read(devc, 12) | 0x40); /* Mode2 = enabled */
1525 outb((0), io_Status(devc)); /* Clear pending interrupts */
1528 * Toggle the MCE bit. It completes the initialization phase.
1531 ad_enter_MCE(devc); /* In case the bit was off */
1534 ad1848_mixer_reset(devc);
1537 int ad1848_detect(struct resource *ports, int *ad_flags, int *osp)
1540 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1541 unsigned char tmp1 = 0xff, tmp2 = 0xff;
1542 int optiC930 = 0; /* OPTi 82C930 flag */
1544 int ad1847_flag = 0;
1545 int cs4248_flag = 0;
1546 int sscape_flag = 0;
1547 int io_base = ports->start;
1551 DDB(printk("ad1848_detect(%x)\n", io_base));
1555 if (*ad_flags == 0x12345678)
1561 if (*ad_flags == 0x87654321)
1567 if (*ad_flags == 0x12345677)
1573 if (nr_ad1848_devs >= MAX_AUDIO_DEV)
1575 printk(KERN_ERR "ad1848 - Too many audio devices\n");
1578 spin_lock_init(&devc->lock);
1579 devc->base = io_base;
1581 devc->timer_running = 0;
1582 devc->MCE_bit = 0x40;
1584 devc->open_mode = 0;
1585 devc->chip_name = devc->name = "AD1848";
1586 devc->model = MD_1848; /* AD1848 or CS4248 */
1587 devc->levels = NULL;
1588 devc->debug_flag = 0;
1591 * Check that the I/O address is in use.
1593 * The bit 0x80 of the base I/O port is known to be 0 after the
1594 * chip has performed its power on initialization. Just assume
1595 * this has happened before the OS is starting.
1597 * If the I/O address is unused, it typically returns 0xff.
1600 if (inb(devc->base) == 0xff)
1602 DDB(printk("ad1848_detect: The base I/O address appears to be dead\n"));
1606 * Wait for the device to stop initialization
1609 DDB(printk("ad1848_detect() - step 0\n"));
1611 for (i = 0; i < 10000000; i++)
1613 unsigned char x = inb(devc->base);
1615 if (x == 0xff || !(x & 0x80))
1619 DDB(printk("ad1848_detect() - step A\n"));
1621 if (inb(devc->base) == 0x80) /* Not ready. Let's wait */
1624 if ((inb(devc->base) & 0x80) != 0x00) /* Not a AD1848 */
1626 DDB(printk("ad1848 detect error - step A (%02x)\n", (int) inb(devc->base)));
1631 * Test if it's possible to change contents of the indirect registers.
1632 * Registers 0 and 1 are ADC volume registers. The bit 0x10 is read only
1633 * so try to avoid using it.
1636 DDB(printk("ad1848_detect() - step B\n"));
1637 ad_write(devc, 0, 0xaa);
1638 ad_write(devc, 1, 0x45); /* 0x55 with bit 0x10 clear */
1640 if ((tmp1 = ad_read(devc, 0)) != 0xaa || (tmp2 = ad_read(devc, 1)) != 0x45)
1642 if (tmp2 == 0x65) /* AD1847 has couple of bits hardcoded to 1 */
1646 DDB(printk("ad1848 detect error - step B (%x/%x)\n", tmp1, tmp2));
1650 DDB(printk("ad1848_detect() - step C\n"));
1651 ad_write(devc, 0, 0x45);
1652 ad_write(devc, 1, 0xaa);
1654 if ((tmp1 = ad_read(devc, 0)) != 0x45 || (tmp2 = ad_read(devc, 1)) != 0xaa)
1656 if (tmp2 == 0x8a) /* AD1847 has few bits hardcoded to 1 */
1660 DDB(printk("ad1848 detect error - step C (%x/%x)\n", tmp1, tmp2));
1666 * The indirect register I12 has some read only bits. Let's
1667 * try to change them.
1670 DDB(printk("ad1848_detect() - step D\n"));
1671 tmp = ad_read(devc, 12);
1672 ad_write(devc, 12, (~tmp) & 0x0f);
1674 if ((tmp & 0x0f) != ((tmp1 = ad_read(devc, 12)) & 0x0f))
1676 DDB(printk("ad1848 detect error - step D (%x)\n", tmp1));
1681 * NOTE! Last 4 bits of the reg I12 tell the chip revision.
1682 * 0x01=RevB and 0x0A=RevC.
1686 * The original AD1848/CS4248 has just 15 indirect registers. This means
1687 * that I0 and I16 should return the same value (etc.).
1688 * However this doesn't work with CS4248. Actually it seems to be impossible
1689 * to detect if the chip is a CS4231 or CS4248.
1690 * Ensure that the Mode2 enable bit of I12 is 0. Otherwise this test fails
1695 * OPTi 82C930 has mode2 control bit in another place. This test will fail
1696 * with it. Accept this situation as a possible indication of this chip.
1699 DDB(printk("ad1848_detect() - step F\n"));
1700 ad_write(devc, 12, 0); /* Mode2=disabled */
1702 for (i = 0; i < 16; i++)
1704 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16)))
1706 DDB(printk("ad1848 detect step F(%d/%x/%x) - OPTi chip???\n", i, tmp1, tmp2));
1714 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit (0x40).
1715 * The bit 0x80 is always 1 in CS4248 and CS4231.
1718 DDB(printk("ad1848_detect() - step G\n"));
1720 if (ad_flags && *ad_flags == 400)
1723 ad_write(devc, 12, 0x40); /* Set mode2, clear 0x80 */
1729 tmp1 = ad_read(devc, 12);
1733 *ad_flags |= AD_F_CS4248;
1735 devc->chip_name = "CS4248"; /* Our best knowledge just now */
1737 if (optiC930 || (tmp1 & 0xc0) == (0x80 | 0x40))
1740 * CS4231 detected - is it?
1742 * Verify that setting I0 doesn't change I16.
1745 DDB(printk("ad1848_detect() - step H\n"));
1746 ad_write(devc, 16, 0); /* Set I16 to known value */
1748 ad_write(devc, 0, 0x45);
1749 if ((tmp1 = ad_read(devc, 16)) != 0x45) /* No change -> CS4231? */
1751 ad_write(devc, 0, 0xaa);
1752 if ((tmp1 = ad_read(devc, 16)) == 0xaa) /* Rotten bits? */
1754 DDB(printk("ad1848 detect error - step H(%x)\n", tmp1));
1759 * Verify that some bits of I25 are read only.
1762 DDB(printk("ad1848_detect() - step I\n"));
1763 tmp1 = ad_read(devc, 25); /* Original bits */
1764 ad_write(devc, 25, ~tmp1); /* Invert all bits */
1765 if ((ad_read(devc, 25) & 0xe7) == (tmp1 & 0xe7))
1770 * It's at least CS4231
1773 devc->chip_name = "CS4231";
1774 devc->model = MD_4231;
1777 * It could be an AD1845 or CS4231A as well.
1778 * CS4231 and AD1845 report the same revision info in I25
1779 * while the CS4231A reports different.
1782 id = ad_read(devc, 25);
1783 if ((id & 0xe7) == 0x80) /* Device busy??? */
1784 id = ad_read(devc, 25);
1785 if ((id & 0xe7) == 0x80) /* Device still busy??? */
1786 id = ad_read(devc, 25);
1787 DDB(printk("ad1848_detect() - step J (%02x/%02x)\n", id, ad_read(devc, 25)));
1789 if ((id & 0xe7) == 0x80) {
1791 * It must be a CS4231 or AD1845. The register I23 of
1792 * CS4231 is undefined and it appears to be read only.
1793 * AD1845 uses I23 for setting sample rate. Assume
1794 * the chip is AD1845 if I23 is changeable.
1797 unsigned char tmp = ad_read(devc, 23);
1798 ad_write(devc, 23, ~tmp);
1802 devc->model = MD_IWAVE;
1803 devc->chip_name = "IWave";
1805 else if (ad_read(devc, 23) != tmp) /* AD1845 ? */
1807 devc->chip_name = "AD1845";
1808 devc->model = MD_1845;
1810 else if (cs4248_flag)
1813 *ad_flags |= AD_F_CS4248;
1814 devc->chip_name = "CS4248";
1815 devc->model = MD_1848;
1816 ad_write(devc, 12, ad_read(devc, 12) & ~0x40); /* Mode2 off */
1818 ad_write(devc, 23, tmp); /* Restore */
1822 switch (id & 0x1f) {
1823 case 3: /* CS4236/CS4235/CS42xB/CS4239 */
1826 ad_write(devc, 12, ad_read(devc, 12) | 0x60); /* switch to mode 3 */
1827 ad_write(devc, 23, 0x9c); /* select extended register 25 */
1828 xid = inb(io_Indexed_Data(devc));
1829 ad_write(devc, 12, ad_read(devc, 12) & ~0x60); /* back to mode 0 */
1833 devc->chip_name = "CS4237B(B)";
1834 devc->model = MD_42xB;
1837 /* Seems to be a 4238 ?? */
1838 devc->chip_name = "CS4238";
1839 devc->model = MD_42xB;
1842 devc->chip_name = "CS4238B";
1843 devc->model = MD_42xB;
1846 devc->chip_name = "CS4236B";
1847 devc->model = MD_4236;
1850 devc->chip_name = "CS4237B";
1851 devc->model = MD_42xB;
1854 devc->chip_name = "CS4235";
1855 devc->model = MD_4235;
1858 devc->chip_name = "CS4239";
1859 devc->model = MD_4239;
1862 printk("Chip ident is %X.\n", xid&0x1F);
1863 devc->chip_name = "CS42xx";
1864 devc->model = MD_4232;
1870 case 2: /* CS4232/CS4232A */
1871 devc->chip_name = "CS4232";
1872 devc->model = MD_4232;
1876 if ((id & 0xe0) == 0xa0)
1878 devc->chip_name = "CS4231A";
1879 devc->model = MD_4231A;
1883 devc->chip_name = "CS4321";
1884 devc->model = MD_4231;
1888 default: /* maybe */
1889 DDB(printk("ad1848: I25 = %02x/%02x\n", ad_read(devc, 25), ad_read(devc, 25) & 0xe7));
1892 devc->chip_name = "82C930";
1893 devc->model = MD_C930;
1897 devc->chip_name = "CS4231";
1898 devc->model = MD_4231;
1903 ad_write(devc, 25, tmp1); /* Restore bits */
1905 DDB(printk("ad1848_detect() - step K\n"));
1907 } else if (tmp1 == 0x0a) {
1909 * Is it perhaps a SoundPro CMI8330?
1910 * If so, then we should be able to change indirect registers
1911 * greater than I15 after activating MODE2, even though reading
1912 * back I12 does not show it.
1916 * Let's try comparing register values
1918 for (i = 0; i < 16; i++) {
1919 if ((tmp1 = ad_read(devc, i)) != (tmp2 = ad_read(devc, i + 16))) {
1920 DDB(printk("ad1848 detect step H(%d/%x/%x) - SoundPro chip?\n", i, tmp1, tmp2));
1922 devc->chip_name = "SoundPro CMI 8330";
1928 DDB(printk("ad1848_detect() - step L\n"));
1931 if (devc->model != MD_1848)
1932 *ad_flags |= AD_F_CS4231;
1934 DDB(printk("ad1848_detect() - Detected OK\n"));
1936 if (devc->model == MD_1848 && ad1847_flag)
1937 devc->chip_name = "AD1847";
1940 if (sscape_flag == 1)
1941 devc->model = MD_1845_SSCAPE;
1946 int ad1848_init (char *name, struct resource *ports, int irq, int dma_playback,
1947 int dma_capture, int share_dma, int *osp, struct module *owner)
1950 * NOTE! If irq < 0, there is another driver which has allocated the IRQ
1951 * so that this driver doesn't need to allocate/deallocate it.
1952 * The actually used IRQ is ABS(irq).
1959 ad1848_info *devc = &adev_info[nr_ad1848_devs];
1961 ad1848_port_info *portc = NULL;
1963 devc->irq = (irq > 0) ? irq : 0;
1964 devc->open_mode = 0;
1965 devc->timer_ticks = 0;
1966 devc->dma1 = dma_playback;
1967 devc->dma2 = dma_capture;
1968 devc->subtype = cfg.card_subtype;
1969 devc->audio_flags = DMA_AUTOMODE;
1970 devc->playback_dev = devc->record_dev = 0;
1974 if (name != NULL && name[0] != 0)
1976 "%s (%s)", name, devc->chip_name);
1979 "Generic audio codec (%s)", devc->chip_name);
1981 rename_region(ports, devc->name);
1983 conf_printf2(dev_name, devc->base, devc->irq, dma_playback, dma_capture);
1985 if (devc->model == MD_1848 || devc->model == MD_C930)
1986 devc->audio_flags |= DMA_HARDSTOP;
1988 if (devc->model > MD_1848)
1990 if (devc->dma1 == devc->dma2 || devc->dma2 == -1 || devc->dma1 == -1)
1991 devc->audio_flags &= ~DMA_DUPLEX;
1993 devc->audio_flags |= DMA_DUPLEX;
1996 portc = kmalloc(sizeof(ad1848_port_info), GFP_KERNEL);
1998 release_region(devc->base, 4);
2002 if ((my_dev = sound_install_audiodrv(AUDIO_DRIVER_VERSION,
2004 &ad1848_audio_driver,
2005 sizeof(struct audio_driver),
2007 ad_format_mask[devc->model],
2012 release_region(devc->base, 4);
2017 audio_devs[my_dev]->portc = portc;
2018 audio_devs[my_dev]->mixer_dev = -1;
2020 audio_devs[my_dev]->d->owner = owner;
2021 memset((char *) portc, 0, sizeof(*portc));
2025 ad1848_init_hw(devc);
2029 devc->dev_no = my_dev;
2030 if (request_irq(devc->irq, adintr, 0, devc->name,
2031 (void *)(long)my_dev) < 0)
2033 printk(KERN_WARNING "ad1848: Unable to allocate IRQ\n");
2034 /* Don't free it either then.. */
2037 if (capabilities[devc->model].flags & CAP_F_TIMER)
2041 unsigned char tmp = ad_read(devc, 16);
2044 devc->timer_ticks = 0;
2046 ad_write(devc, 21, 0x00); /* Timer MSB */
2047 ad_write(devc, 20, 0x10); /* Timer LSB */
2049 ad_write(devc, 16, tmp | 0x40); /* Enable timer */
2050 for (x = 0; x < 100000 && devc->timer_ticks == 0; x++);
2051 ad_write(devc, 16, tmp & ~0x40); /* Disable timer */
2053 if (devc->timer_ticks == 0)
2054 printk(KERN_WARNING "ad1848: Interrupt test failed (IRQ%d)\n", irq);
2057 DDB(printk("Interrupt test OK\n"));
2065 devc->irq_ok = 1; /* Couldn't test. assume it's OK */
2067 irq2dev[-irq] = devc->dev_no = my_dev;
2069 #ifndef EXCLUDE_TIMERS
2070 if ((capabilities[devc->model].flags & CAP_F_TIMER) &&
2072 ad1848_tmr_install(my_dev);
2077 if (sound_alloc_dma(dma_playback, devc->name))
2078 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_playback);
2080 if (dma_capture != dma_playback)
2081 if (sound_alloc_dma(dma_capture, devc->name))
2082 printk(KERN_WARNING "ad1848.c: Can't allocate DMA%d\n", dma_capture);
2085 if ((e = sound_install_mixer(MIXER_DRIVER_VERSION,
2087 &ad1848_mixer_operations,
2088 sizeof(struct mixer_operations),
2091 audio_devs[my_dev]->mixer_dev = e;
2093 mixer_devs[e]->owner = owner;
2098 int ad1848_control(int cmd, int arg)
2101 unsigned long flags;
2103 if (nr_ad1848_devs < 1)
2106 devc = &adev_info[nr_ad1848_devs - 1];
2110 case AD1848_SET_XTAL: /* Change clock frequency of AD1845 (only ) */
2111 if (devc->model != MD_1845 && devc->model != MD_1845_SSCAPE)
2113 spin_lock_irqsave(&devc->lock,flags);
2115 ad_write(devc, 29, (ad_read(devc, 29) & 0x1f) | (arg << 5));
2117 spin_unlock_irqrestore(&devc->lock,flags);
2120 case AD1848_MIXER_REROUTE:
2122 int o = (arg >> 8) & 0xff;
2125 if (o < 0 || o >= SOUND_MIXER_NRDEVICES)
2128 if (!(devc->supported_devices & (1 << o)) &&
2129 !(devc->supported_rec_devices & (1 << o)))
2132 if (n == SOUND_MIXER_NONE)
2133 { /* Just hide this control */
2134 ad1848_mixer_set(devc, o, 0); /* Shut up it */
2135 devc->supported_devices &= ~(1 << o);
2136 devc->supported_rec_devices &= ~(1 << o);
2140 /* Make the mixer control identified by o to appear as n */
2141 if (n < 0 || n >= SOUND_MIXER_NRDEVICES)
2144 devc->mixer_reroute[n] = o; /* Rename the control */
2145 if (devc->supported_devices & (1 << o))
2146 devc->supported_devices |= (1 << n);
2147 if (devc->supported_rec_devices & (1 << o))
2148 devc->supported_rec_devices |= (1 << n);
2150 devc->supported_devices &= ~(1 << o);
2151 devc->supported_rec_devices &= ~(1 << o);
2158 void ad1848_unload(int io_base, int irq, int dma_playback, int dma_capture, int share_dma)
2160 int i, mixer, dev = 0;
2161 ad1848_info *devc = NULL;
2163 for (i = 0; devc == NULL && i < nr_ad1848_devs; i++)
2165 if (adev_info[i].base == io_base)
2167 devc = &adev_info[i];
2174 kfree(audio_devs[dev]->portc);
2175 release_region(devc->base, 4);
2179 if (devc->irq > 0) /* There is no point in freeing irq, if it wasn't allocated */
2180 free_irq(devc->irq, (void *)(long)devc->dev_no);
2182 sound_free_dma(dma_playback);
2184 if (dma_playback != dma_capture)
2185 sound_free_dma(dma_capture);
2188 mixer = audio_devs[devc->dev_no]->mixer_dev;
2190 sound_unload_mixerdev(mixer);
2193 for ( ; i < nr_ad1848_devs ; i++)
2194 adev_info[i] = adev_info[i+1];
2197 printk(KERN_ERR "ad1848: Can't find device to be unloaded. Base=%x\n", io_base);
2200 static irqreturn_t adintr(int irq, void *dev_id)
2202 unsigned char status;
2205 int alt_stat = 0xff;
2206 unsigned char c930_stat = 0;
2210 devc = (ad1848_info *) audio_devs[dev]->devc;
2212 interrupt_again: /* Jump back here if int status doesn't reset */
2214 status = inb(io_Status(devc));
2217 printk(KERN_DEBUG "adintr: Why?\n");
2218 if (devc->model == MD_1848)
2219 outb((0), io_Status(devc)); /* Clear interrupt status */
2223 if (devc->model == MD_C930)
2224 { /* 82C930 has interrupt status register in MAD16 register MC11 */
2226 spin_lock(&devc->lock);
2228 /* 0xe0e is C930 address port
2229 * 0xe0f is C930 data port
2232 c930_stat = inb(0xe0f);
2233 outb((~c930_stat), 0xe0f);
2235 spin_unlock(&devc->lock);
2237 alt_stat = (c930_stat << 2) & 0x30;
2239 else if (devc->model != MD_1848)
2241 spin_lock(&devc->lock);
2242 alt_stat = ad_read(devc, 24);
2243 ad_write(devc, 24, ad_read(devc, 24) & ~alt_stat); /* Selective ack */
2244 spin_unlock(&devc->lock);
2247 if ((devc->open_mode & OPEN_READ) && (devc->audio_mode & PCM_ENABLE_INPUT) && (alt_stat & 0x20))
2249 DMAbuf_inputintr(devc->record_dev);
2251 if ((devc->open_mode & OPEN_WRITE) && (devc->audio_mode & PCM_ENABLE_OUTPUT) &&
2254 DMAbuf_outputintr(devc->playback_dev, 1);
2256 if (devc->model != MD_1848 && (alt_stat & 0x40)) /* Timer interrupt */
2258 devc->timer_ticks++;
2259 #ifndef EXCLUDE_TIMERS
2260 if (timer_installed == dev && devc->timer_running)
2261 sound_timer_interrupt();
2266 * Sometimes playback or capture interrupts occur while a timer interrupt
2267 * is being handled. The interrupt will not be retriggered if we don't
2268 * handle it now. Check if an interrupt is still pending and restart
2269 * the handler in this case.
2271 if (inb(io_Status(devc)) & 0x01 && cnt++ < 4)
2273 goto interrupt_again;
2279 * Experimental initialization sequence for the integrated sound system
2280 * of the Compaq Deskpro M.
2283 static int init_deskpro_m(struct address_info *hw_config)
2287 if ((tmp = inb(0xc44)) == 0xff)
2289 DDB(printk("init_deskpro_m: Dead port 0xc44\n"));
2307 * Experimental initialization sequence for the integrated sound system
2308 * of Compaq Deskpro XL.
2311 static int init_deskpro(struct address_info *hw_config)
2315 if ((tmp = inb(0xc44)) == 0xff)
2317 DDB(printk("init_deskpro: Dead port 0xc44\n"));
2320 outb((tmp | 0x04), 0xc44); /* Select bank 1 */
2321 if (inb(0xc44) != 0x04)
2323 DDB(printk("init_deskpro: Invalid bank1 signature in port 0xc44\n"));
2327 * OK. It looks like a Deskpro so let's proceed.
2331 * I/O port 0xc44 Audio configuration register.
2333 * bits 0xc0: Audio revision bits
2334 * 0x00 = Compaq Business Audio
2335 * 0x40 = MS Sound System Compatible (reset default)
2338 * bit 0x20: No Wait State Enable
2339 * 0x00 = Disabled (reset default, DMA mode)
2340 * 0x20 = Enabled (programmed I/O mode)
2341 * bit 0x10: MS Sound System Decode Enable
2342 * 0x00 = Decoding disabled (reset default)
2343 * 0x10 = Decoding enabled
2344 * bit 0x08: FM Synthesis Decode Enable
2345 * 0x00 = Decoding Disabled (reset default)
2346 * 0x08 = Decoding enabled
2347 * bit 0x04 Bank select
2350 * bits 0x03 MSS Base address
2351 * 0x00 = 0x530 (reset default)
2358 /* Debug printing */
2359 printk("Port 0xc44 (before): ");
2360 outb((tmp & ~0x04), 0xc44);
2361 printk("%02x ", inb(0xc44));
2362 outb((tmp | 0x04), 0xc44);
2363 printk("%02x\n", inb(0xc44));
2366 /* Set bank 1 of the register */
2367 tmp = 0x58; /* MSS Mode, MSS&FM decode enabled */
2369 switch (hw_config->io_base)
2384 DDB(printk("init_deskpro: Invalid MSS port %x\n", hw_config->io_base));
2387 outb((tmp & ~0x04), 0xc44); /* Write to bank=0 */
2390 /* Debug printing */
2391 printk("Port 0xc44 (after): ");
2392 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2393 printk("%02x ", inb(0xc44));
2394 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2395 printk("%02x\n", inb(0xc44));
2399 * I/O port 0xc45 FM Address Decode/MSS ID Register.
2401 * bank=0, bits 0xfe: FM synthesis Decode Compare bits 7:1 (default=0x88)
2402 * bank=0, bit 0x01: SBIC Power Control Bit
2404 * 0x01 = Powered down
2405 * bank=1, bits 0xfc: MSS ID (default=0x40)
2409 /* Debug printing */
2410 printk("Port 0xc45 (before): ");
2411 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2412 printk("%02x ", inb(0xc45));
2413 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2414 printk("%02x\n", inb(0xc45));
2417 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2418 outb((0x88), 0xc45); /* FM base 7:0 = 0x88 */
2419 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2420 outb((0x10), 0xc45); /* MSS ID = 0x10 (MSS port returns 0x04) */
2423 /* Debug printing */
2424 printk("Port 0xc45 (after): ");
2425 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2426 printk("%02x ", inb(0xc45));
2427 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2428 printk("%02x\n", inb(0xc45));
2433 * I/O port 0xc46 FM Address Decode/Address ASIC Revision Register.
2435 * bank=0, bits 0xff: FM synthesis Decode Compare bits 15:8 (default=0x03)
2436 * bank=1, bits 0xff: Audio addressing ASIC id
2440 /* Debug printing */
2441 printk("Port 0xc46 (before): ");
2442 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2443 printk("%02x ", inb(0xc46));
2444 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2445 printk("%02x\n", inb(0xc46));
2448 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2449 outb((0x03), 0xc46); /* FM base 15:8 = 0x03 */
2450 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2451 outb((0x11), 0xc46); /* ASIC ID = 0x11 */
2454 /* Debug printing */
2455 printk("Port 0xc46 (after): ");
2456 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2457 printk("%02x ", inb(0xc46));
2458 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2459 printk("%02x\n", inb(0xc46));
2463 * I/O port 0xc47 FM Address Decode Register.
2465 * bank=0, bits 0xff: Decode enable selection for various FM address bits
2466 * bank=1, bits 0xff: Reserved
2470 /* Debug printing */
2471 printk("Port 0xc47 (before): ");
2472 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2473 printk("%02x ", inb(0xc47));
2474 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2475 printk("%02x\n", inb(0xc47));
2478 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2479 outb((0x7c), 0xc47); /* FM decode enable bits = 0x7c */
2480 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2481 outb((0x00), 0xc47); /* Reserved bank1 = 0x00 */
2484 /* Debug printing */
2485 printk("Port 0xc47 (after): ");
2486 outb((tmp & ~0x04), 0xc44); /* Select bank=0 */
2487 printk("%02x ", inb(0xc47));
2488 outb((tmp | 0x04), 0xc44); /* Select bank=1 */
2489 printk("%02x\n", inb(0xc47));
2493 * I/O port 0xc6f = Audio Disable Function Register
2497 printk("Port 0xc6f (before) = %02x\n", inb(0xc6f));
2500 outb((0x80), 0xc6f);
2503 printk("Port 0xc6f (after) = %02x\n", inb(0xc6f));
2509 int probe_ms_sound(struct address_info *hw_config, struct resource *ports)
2513 DDB(printk("Entered probe_ms_sound(%x, %d)\n", hw_config->io_base, hw_config->card_subtype));
2515 if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
2517 /* check_opl3(0x388, hw_config); */
2518 return ad1848_detect(ports, NULL, hw_config->osp);
2521 if (deskpro_xl && hw_config->card_subtype == 2) /* Compaq Deskpro XL */
2523 if (!init_deskpro(hw_config))
2527 if (deskpro_m) /* Compaq Deskpro M */
2529 if (!init_deskpro_m(hw_config))
2534 * Check if the IO port returns valid signature. The original MS Sound
2535 * system returns 0x04 while some cards (AudioTrix Pro for example)
2536 * return 0x00 or 0x0f.
2539 if ((tmp = inb(hw_config->io_base + 3)) == 0xff) /* Bus float */
2543 DDB(printk("I/O address is inactive (%x)\n", tmp));
2544 if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
2548 DDB(printk("MSS signature = %x\n", tmp & 0x3f));
2549 if ((tmp & 0x3f) != 0x04 &&
2550 (tmp & 0x3f) != 0x0f &&
2551 (tmp & 0x3f) != 0x00)
2555 MDB(printk(KERN_ERR "No MSS signature detected on port 0x%x (0x%x)\n", hw_config->io_base, (int) inb(hw_config->io_base + 3)));
2556 DDB(printk("Trying to detect codec anyway but IRQ/DMA may not work\n"));
2557 if (!(ret = ad1848_detect(ports, NULL, hw_config->osp)))
2560 hw_config->card_subtype = 1;
2563 if ((hw_config->irq != 5) &&
2564 (hw_config->irq != 7) &&
2565 (hw_config->irq != 9) &&
2566 (hw_config->irq != 10) &&
2567 (hw_config->irq != 11) &&
2568 (hw_config->irq != 12))
2570 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2573 if (hw_config->dma != 0 && hw_config->dma != 1 && hw_config->dma != 3)
2575 printk(KERN_ERR "MSS: Bad DMA %d\n", hw_config->dma);
2579 * Check that DMA0 is not in use with a 8 bit board.
2582 if (hw_config->dma == 0 && inb(hw_config->io_base + 3) & 0x80)
2584 printk(KERN_ERR "MSS: Can't use DMA0 with a 8 bit card/slot\n");
2587 if (hw_config->irq > 7 && hw_config->irq != 9 && inb(hw_config->io_base + 3) & 0x80)
2589 printk(KERN_ERR "MSS: Can't use IRQ%d with a 8 bit card/slot\n", hw_config->irq);
2592 return ad1848_detect(ports, NULL, hw_config->osp);
2595 void attach_ms_sound(struct address_info *hw_config, struct resource *ports, struct module *owner)
2597 static signed char interrupt_bits[12] =
2599 -1, -1, -1, -1, -1, 0x00, -1, 0x08, -1, 0x10, 0x18, 0x20
2604 static char dma_bits[4] =
2609 int config_port = hw_config->io_base + 0;
2610 int version_port = hw_config->io_base + 3;
2611 int dma = hw_config->dma;
2612 int dma2 = hw_config->dma2;
2614 if (hw_config->card_subtype == 1) /* Has no IRQ/DMA registers */
2616 hw_config->slots[0] = ad1848_init("MS Sound System", ports,
2625 * Set the IRQ and DMA addresses.
2628 bits = interrupt_bits[hw_config->irq];
2631 printk(KERN_ERR "MSS: Bad IRQ %d\n", hw_config->irq);
2632 release_region(ports->start, 4);
2633 release_region(ports->start - 4, 4);
2636 outb((bits | 0x40), config_port);
2637 if ((inb(version_port) & 0x40) == 0)
2638 printk(KERN_ERR "[MSS: IRQ Conflict?]\n");
2641 * Handle the capture DMA channel
2644 if (dma2 != -1 && dma2 != dma)
2646 if (!((dma == 0 && dma2 == 1) ||
2647 (dma == 1 && dma2 == 0) ||
2648 (dma == 3 && dma2 == 0)))
2649 { /* Unsupported combination. Try to swap channels */
2655 if ((dma == 0 && dma2 == 1) ||
2656 (dma == 1 && dma2 == 0) ||
2657 (dma == 3 && dma2 == 0))
2659 dma2_bit = 0x04; /* Enable capture DMA */
2663 printk(KERN_WARNING "MSS: Invalid capture DMA\n");
2672 hw_config->dma = dma;
2673 hw_config->dma2 = dma2;
2675 outb((bits | dma_bits[dma] | dma2_bit), config_port); /* Write IRQ+DMA setup */
2677 hw_config->slots[0] = ad1848_init("MS Sound System", ports,
2684 void unload_ms_sound(struct address_info *hw_config)
2686 ad1848_unload(hw_config->io_base + 4,
2689 hw_config->dma2, 0);
2690 sound_unload_audiodev(hw_config->slots[0]);
2691 release_region(hw_config->io_base, 4);
2694 #ifndef EXCLUDE_TIMERS
2697 * Timer stuff (for /dev/music).
2700 static unsigned int current_interval;
2702 static unsigned int ad1848_tmr_start(int dev, unsigned int usecs)
2704 unsigned long flags;
2705 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2706 unsigned long xtal_nsecs; /* nanoseconds per xtal oscillator tick */
2707 unsigned long divider;
2709 spin_lock_irqsave(&devc->lock,flags);
2712 * Length of the timer interval (in nanoseconds) depends on the
2713 * selected crystal oscillator. Check this from bit 0x01 of I8.
2715 * AD1845 has just one oscillator which has cycle time of 10.050 us
2716 * (when a 24.576 MHz xtal oscillator is used).
2718 * Convert requested interval to nanoseconds before computing
2719 * the timer divider.
2722 if (devc->model == MD_1845 || devc->model == MD_1845_SSCAPE)
2724 else if (ad_read(devc, 8) & 0x01)
2729 divider = (usecs * 1000 + xtal_nsecs / 2) / xtal_nsecs;
2731 if (divider < 100) /* Don't allow shorter intervals than about 1ms */
2734 if (divider > 65535) /* Overflow check */
2737 ad_write(devc, 21, (divider >> 8) & 0xff); /* Set upper bits */
2738 ad_write(devc, 20, divider & 0xff); /* Set lower bits */
2739 ad_write(devc, 16, ad_read(devc, 16) | 0x40); /* Start the timer */
2740 devc->timer_running = 1;
2741 spin_unlock_irqrestore(&devc->lock,flags);
2743 return current_interval = (divider * xtal_nsecs + 500) / 1000;
2746 static void ad1848_tmr_reprogram(int dev)
2749 * Audio driver has changed sampling rate so that a different xtal
2750 * oscillator was selected. We have to reprogram the timer rate.
2753 ad1848_tmr_start(dev, current_interval);
2754 sound_timer_syncinterval(current_interval);
2757 static void ad1848_tmr_disable(int dev)
2759 unsigned long flags;
2760 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2762 spin_lock_irqsave(&devc->lock,flags);
2763 ad_write(devc, 16, ad_read(devc, 16) & ~0x40);
2764 devc->timer_running = 0;
2765 spin_unlock_irqrestore(&devc->lock,flags);
2768 static void ad1848_tmr_restart(int dev)
2770 unsigned long flags;
2771 ad1848_info *devc = (ad1848_info *) audio_devs[dev]->devc;
2773 if (current_interval == 0)
2776 spin_lock_irqsave(&devc->lock,flags);
2777 ad_write(devc, 16, ad_read(devc, 16) | 0x40);
2778 devc->timer_running = 1;
2779 spin_unlock_irqrestore(&devc->lock,flags);
2782 static struct sound_lowlev_timer ad1848_tmr =
2791 static int ad1848_tmr_install(int dev)
2793 if (timer_installed != -1)
2794 return 0; /* Don't install another timer */
2796 timer_installed = ad1848_tmr.dev = dev;
2797 sound_timer_init(&ad1848_tmr, audio_devs[dev]->name);
2801 #endif /* EXCLUDE_TIMERS */
2803 EXPORT_SYMBOL(ad1848_detect);
2804 EXPORT_SYMBOL(ad1848_init);
2805 EXPORT_SYMBOL(ad1848_unload);
2806 EXPORT_SYMBOL(ad1848_control);
2807 EXPORT_SYMBOL(probe_ms_sound);
2808 EXPORT_SYMBOL(attach_ms_sound);
2809 EXPORT_SYMBOL(unload_ms_sound);
2811 static int __initdata io = -1;
2812 static int __initdata irq = -1;
2813 static int __initdata dma = -1;
2814 static int __initdata dma2 = -1;
2815 static int __initdata type = 0;
2817 module_param(io, int, 0); /* I/O for a raw AD1848 card */
2818 module_param(irq, int, 0); /* IRQ to use */
2819 module_param(dma, int, 0); /* First DMA channel */
2820 module_param(dma2, int, 0); /* Second DMA channel */
2821 module_param(type, int, 0); /* Card type */
2822 module_param(deskpro_xl, bool, 0); /* Special magic for Deskpro XL boxen */
2823 module_param(deskpro_m, bool, 0); /* Special magic for Deskpro M box */
2824 module_param(soundpro, bool, 0); /* More special magic for SoundPro chips */
2827 module_param(isapnp, int, 0);
2828 module_param(isapnpjump, int, 0);
2829 module_param(reverse, bool, 0);
2830 MODULE_PARM_DESC(isapnp, "When set to 0, Plug & Play support will be disabled");
2831 MODULE_PARM_DESC(isapnpjump, "Jumps to a specific slot in the driver's PnP table. Use the source, Luke.");
2832 MODULE_PARM_DESC(reverse, "When set to 1, will reverse ISAPnP search order");
2834 static struct pnp_dev *ad1848_dev = NULL;
2836 /* Please add new entries at the end of the table */
2839 unsigned short card_vendor, card_device,
2841 short mss_io, irq, dma, dma2; /* index into isapnp table */
2843 } ad1848_isapnp_list[] __initdata = {
2844 {"CMI 8330 SoundPRO",
2845 ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2846 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001),
2848 {"CS4232 based card",
2849 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2850 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000),
2852 {"CS4232 based card",
2853 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2854 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100),
2856 {"OPL3-SA2 WSS mode",
2857 ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2858 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021),
2860 {"Advanced Gravis InterWave Audio",
2861 ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2862 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000),
2867 static struct isapnp_device_id id_table[] __devinitdata = {
2868 { ISAPNP_VENDOR('C','M','I'), ISAPNP_DEVICE(0x0001),
2869 ISAPNP_VENDOR('@','@','@'), ISAPNP_FUNCTION(0x0001), 0 },
2870 { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2871 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0000), 0 },
2872 { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2873 ISAPNP_VENDOR('C','S','C'), ISAPNP_FUNCTION(0x0100), 0 },
2874 /* The main driver for this card is opl3sa2
2875 { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
2876 ISAPNP_VENDOR('Y','M','H'), ISAPNP_FUNCTION(0x0021), 0 },
2878 { ISAPNP_VENDOR('G','R','V'), ISAPNP_DEVICE(0x0001),
2879 ISAPNP_VENDOR('G','R','V'), ISAPNP_FUNCTION(0x0000), 0 },
2883 MODULE_DEVICE_TABLE(isapnp, id_table);
2885 static struct pnp_dev *activate_dev(char *devname, char *resname, struct pnp_dev *dev)
2889 err = pnp_device_attach(dev);
2893 if((err = pnp_activate_dev(dev)) < 0) {
2894 printk(KERN_ERR "ad1848: %s %s config failed (out of resources?)[%d]\n", devname, resname, err);
2896 pnp_device_detach(dev);
2900 audio_activated = 1;
2904 static struct pnp_dev __init *ad1848_init_generic(struct pnp_card *bus,
2905 struct address_info *hw_config, int slot)
2908 /* Configure Audio device */
2909 if((ad1848_dev = pnp_find_dev(bus, ad1848_isapnp_list[slot].vendor, ad1848_isapnp_list[slot].function, NULL)))
2911 if((ad1848_dev = activate_dev(ad1848_isapnp_list[slot].name, "ad1848", ad1848_dev)))
2913 hw_config->io_base = pnp_port_start(ad1848_dev, ad1848_isapnp_list[slot].mss_io);
2914 hw_config->irq = pnp_irq(ad1848_dev, ad1848_isapnp_list[slot].irq);
2915 hw_config->dma = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma);
2916 if(ad1848_isapnp_list[slot].dma2 != -1)
2917 hw_config->dma2 = pnp_dma(ad1848_dev, ad1848_isapnp_list[slot].dma2);
2919 hw_config->dma2 = -1;
2920 hw_config->card_subtype = ad1848_isapnp_list[slot].type;
2929 static int __init ad1848_isapnp_init(struct address_info *hw_config, struct pnp_card *bus, int slot)
2931 char *busname = bus->name[0] ? bus->name : ad1848_isapnp_list[slot].name;
2933 /* Initialize this baby. */
2935 if(ad1848_init_generic(bus, hw_config, slot)) {
2938 printk(KERN_NOTICE "ad1848: PnP reports '%s' at i/o %#x, irq %d, dma %d, %d\n",
2940 hw_config->io_base, hw_config->irq, hw_config->dma,
2947 static int __init ad1848_isapnp_probe(struct address_info *hw_config)
2949 static int first = 1;
2952 /* Count entries in sb_isapnp_list */
2953 for (i = 0; ad1848_isapnp_list[i].card_vendor != 0; i++);
2956 /* Check and adjust isapnpjump */
2957 if( isapnpjump < 0 || isapnpjump > i) {
2958 isapnpjump = reverse ? i : 0;
2959 printk(KERN_ERR "ad1848: Valid range for isapnpjump is 0-%d. Adjusted to %d.\n", i, isapnpjump);
2962 if(!first || !reverse)
2965 while(ad1848_isapnp_list[i].card_vendor != 0) {
2966 static struct pnp_card *bus = NULL;
2968 while ((bus = pnp_find_card(
2969 ad1848_isapnp_list[i].card_vendor,
2970 ad1848_isapnp_list[i].card_device,
2973 if(ad1848_isapnp_init(hw_config, bus, i)) {
2974 isapnpjump = i; /* start next search from here */
2978 i += reverse ? -1 : 1;
2986 static int __init init_ad1848(void)
2988 printk(KERN_INFO "ad1848/cs4248 codec driver Copyright (C) by Hannu Savolainen 1993-1996\n");
2991 if(isapnp && (ad1848_isapnp_probe(&cfg) < 0) ) {
2992 printk(KERN_NOTICE "ad1848: No ISAPnP cards found, trying standard ones...\n");
2998 struct resource *ports;
3001 if(irq == -1 || dma == -1) {
3002 printk(KERN_WARNING "ad1848: must give I/O , IRQ and DMA.\n");
3010 cfg.card_subtype = type;
3013 ports = request_region(io + 4, 4, "ad1848");
3018 if (!request_region(io, 4, "WSS config")) {
3019 release_region(io + 4, 4);
3023 if (!probe_ms_sound(&cfg, ports)) {
3024 release_region(io + 4, 4);
3025 release_region(io, 4);
3028 attach_ms_sound(&cfg, ports, THIS_MODULE);
3034 static void __exit cleanup_ad1848(void)
3037 unload_ms_sound(&cfg);
3042 pnp_device_detach(ad1848_dev);
3047 module_init(init_ad1848);
3048 module_exit(cleanup_ad1848);
3051 static int __init setup_ad1848(char *str)
3053 /* io, irq, dma, dma2, type */
3056 str = get_options(str, ARRAY_SIZE(ints), ints);
3067 __setup("ad1848=", setup_ad1848);
3069 MODULE_LICENSE("GPL");