2 * au1550_ac97.c -- Sound driver for Alchemy Au1550 MIPS Internet Edge
5 * Copyright 2004 Embedded Edge, LLC
8 * Mostly copied from the au1000.c driver and some from the
9 * PowerMac dbdma driver.
10 * We assume the processor can do memory coherent DMA.
12 * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
19 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
22 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
25 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 #include <linux/module.h>
39 #include <linux/string.h>
40 #include <linux/ioport.h>
41 #include <linux/sched.h>
42 #include <linux/delay.h>
43 #include <linux/sound.h>
44 #include <linux/slab.h>
45 #include <linux/soundcard.h>
46 #include <linux/init.h>
47 #include <linux/interrupt.h>
48 #include <linux/kernel.h>
49 #include <linux/poll.h>
50 #include <linux/bitops.h>
51 #include <linux/spinlock.h>
52 #include <linux/smp_lock.h>
53 #include <linux/ac97_codec.h>
54 #include <linux/mutex.h>
57 #include <asm/uaccess.h>
58 #include <asm/hardirq.h>
59 #include <asm/mach-au1x00/au1xxx_psc.h>
60 #include <asm/mach-au1x00/au1xxx_dbdma.h>
61 #include <asm/mach-au1x00/au1xxx.h>
63 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
66 #define POLL_COUNT 0x50000
67 #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
69 /* The number of DBDMA ring descriptors to allocate. No sense making
70 * this too large....if you can't keep up with a few you aren't likely
71 * to be able to with lots of them, either.
73 #define NUM_DBDMA_DESCRIPTORS 4
75 #define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
78 * 0 = no VRA, 1 = use VRA if codec supports it
81 module_param(vra, bool, 0);
82 MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
84 static struct au1550_state {
88 struct ac97_codec *codec;
89 unsigned codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
90 unsigned codec_ext_caps; /* AC'97 reg 28h, "Extended Audio ID" */
91 int no_vra; /* do not use VRA */
94 struct mutex open_mutex;
97 wait_queue_head_t open_wait;
101 unsigned sample_rate;
103 unsigned sample_size;
105 int dma_bytes_per_sample;
106 int user_bytes_per_sample;
116 unsigned total_bytes;
118 wait_queue_head_t wait;
120 /* redundant, but makes calculations easier */
122 unsigned dma_fragsize;
130 unsigned ossfragshift;
132 unsigned subdivision;
163 au1550_delay(int msec)
171 tmo = jiffies + (msec * HZ) / 1000;
173 tmo2 = tmo - jiffies;
176 schedule_timeout(tmo2);
181 rdcodec(struct ac97_codec *codec, u8 addr)
183 struct au1550_state *s = (struct au1550_state *)codec->private_data;
189 spin_lock_irqsave(&s->lock, flags);
191 for (i = 0; i < POLL_COUNT; i++) {
192 val = au_readl(PSC_AC97STAT);
194 if (!(val & PSC_AC97STAT_CP))
198 err("rdcodec: codec cmd pending expired!");
200 cmd = (u32)PSC_AC97CDC_INDX(addr);
201 cmd |= PSC_AC97CDC_RD; /* read command */
202 au_writel(cmd, PSC_AC97CDC);
205 /* now wait for the data
207 for (i = 0; i < POLL_COUNT; i++) {
208 val = au_readl(PSC_AC97STAT);
210 if (!(val & PSC_AC97STAT_CP))
213 if (i == POLL_COUNT) {
214 err("rdcodec: read poll expired!");
219 /* wait for command done?
221 for (i = 0; i < POLL_COUNT; i++) {
222 val = au_readl(PSC_AC97EVNT);
224 if (val & PSC_AC97EVNT_CD)
227 if (i == POLL_COUNT) {
228 err("rdcodec: read cmdwait expired!");
233 data = au_readl(PSC_AC97CDC) & 0xffff;
236 /* Clear command done event.
238 au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
242 spin_unlock_irqrestore(&s->lock, flags);
249 wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
251 struct au1550_state *s = (struct au1550_state *)codec->private_data;
256 spin_lock_irqsave(&s->lock, flags);
258 for (i = 0; i < POLL_COUNT; i++) {
259 val = au_readl(PSC_AC97STAT);
261 if (!(val & PSC_AC97STAT_CP))
265 err("wrcodec: codec cmd pending expired!");
267 cmd = (u32)PSC_AC97CDC_INDX(addr);
269 au_writel(cmd, PSC_AC97CDC);
272 for (i = 0; i < POLL_COUNT; i++) {
273 val = au_readl(PSC_AC97STAT);
275 if (!(val & PSC_AC97STAT_CP))
279 err("wrcodec: codec cmd pending expired!");
281 for (i = 0; i < POLL_COUNT; i++) {
282 val = au_readl(PSC_AC97EVNT);
284 if (val & PSC_AC97EVNT_CD)
288 err("wrcodec: read cmdwait expired!");
290 /* Clear command done event.
292 au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
295 spin_unlock_irqrestore(&s->lock, flags);
299 waitcodec(struct ac97_codec *codec)
305 /* codec_wait is used to wait for a ready state after
310 /* first poll the CODEC_READY tag bit
312 for (i = 0; i < POLL_COUNT; i++) {
313 val = au_readl(PSC_AC97STAT);
315 if (val & PSC_AC97STAT_CR)
318 if (i == POLL_COUNT) {
319 err("waitcodec: CODEC_READY poll expired!");
323 /* get AC'97 powerdown control/status register
325 temp = rdcodec(codec, AC97_POWER_CONTROL);
327 /* If anything is powered down, power'em up
332 wrcodec(codec, AC97_POWER_CONTROL, 0);
337 temp = rdcodec(codec, AC97_POWER_CONTROL);
340 /* Check if Codec REF,ANL,DAC,ADC ready
342 if ((temp & 0x7f0f) != 0x000f)
343 err("codec reg 26 status (0x%x) not ready!!", temp);
346 /* stop the ADC before calling */
348 set_adc_rate(struct au1550_state *s, unsigned rate)
350 struct dmabuf *adc = &s->dma_adc;
351 struct dmabuf *dac = &s->dma_dac;
352 unsigned adc_rate, dac_rate;
358 adc->src_factor = ((96000 / rate) + 1) >> 1;
359 adc->sample_rate = 48000 / adc->src_factor;
365 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
367 rate = rate > 48000 ? 48000 : rate;
371 wrcodec(s->codec, AC97_EXTENDED_STATUS,
372 ac97_extstat | AC97_EXTSTAT_VRA);
374 /* now write the sample rate
376 wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
378 /* read it back for actual supported rate
380 adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
382 pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
384 /* some codec's don't allow unequal DAC and ADC rates, in which case
385 * writing one rate reg actually changes both.
387 dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
388 if (dac->num_channels > 2)
389 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
390 if (dac->num_channels > 4)
391 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
393 adc->sample_rate = adc_rate;
394 dac->sample_rate = dac_rate;
397 /* stop the DAC before calling */
399 set_dac_rate(struct au1550_state *s, unsigned rate)
401 struct dmabuf *dac = &s->dma_dac;
402 struct dmabuf *adc = &s->dma_adc;
403 unsigned adc_rate, dac_rate;
409 dac->src_factor = ((96000 / rate) + 1) >> 1;
410 dac->sample_rate = 48000 / dac->src_factor;
416 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
418 rate = rate > 48000 ? 48000 : rate;
422 wrcodec(s->codec, AC97_EXTENDED_STATUS,
423 ac97_extstat | AC97_EXTSTAT_VRA);
425 /* now write the sample rate
427 wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
429 /* I don't support different sample rates for multichannel,
430 * so make these channels the same.
432 if (dac->num_channels > 2)
433 wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
434 if (dac->num_channels > 4)
435 wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
436 /* read it back for actual supported rate
438 dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
440 pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
442 /* some codec's don't allow unequal DAC and ADC rates, in which case
443 * writing one rate reg actually changes both.
445 adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
447 dac->sample_rate = dac_rate;
448 adc->sample_rate = adc_rate;
452 stop_dac(struct au1550_state *s)
454 struct dmabuf *db = &s->dma_dac;
461 spin_lock_irqsave(&s->lock, flags);
463 au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
466 /* Wait for Transmit Busy to show disabled.
469 stat = au_readl(PSC_AC97STAT);
471 } while ((stat & PSC_AC97STAT_TB) != 0);
473 au1xxx_dbdma_reset(db->dmanr);
477 spin_unlock_irqrestore(&s->lock, flags);
481 stop_adc(struct au1550_state *s)
483 struct dmabuf *db = &s->dma_adc;
490 spin_lock_irqsave(&s->lock, flags);
492 au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
495 /* Wait for Receive Busy to show disabled.
498 stat = au_readl(PSC_AC97STAT);
500 } while ((stat & PSC_AC97STAT_RB) != 0);
502 au1xxx_dbdma_reset(db->dmanr);
506 spin_unlock_irqrestore(&s->lock, flags);
511 set_xmit_slots(int num_channels)
513 u32 ac97_config, stat;
515 ac97_config = au_readl(PSC_AC97CFG);
517 ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
518 au_writel(ac97_config, PSC_AC97CFG);
521 switch (num_channels) {
522 case 6: /* stereo with surround and center/LFE,
525 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
526 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
528 case 4: /* stereo with surround, slots 3,4,7,8 */
529 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
530 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
532 case 2: /* stereo, slots 3,4 */
534 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
535 ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
538 au_writel(ac97_config, PSC_AC97CFG);
541 ac97_config |= PSC_AC97CFG_DE_ENABLE;
542 au_writel(ac97_config, PSC_AC97CFG);
545 /* Wait for Device ready.
548 stat = au_readl(PSC_AC97STAT);
550 } while ((stat & PSC_AC97STAT_DR) == 0);
554 set_recv_slots(int num_channels)
556 u32 ac97_config, stat;
558 ac97_config = au_readl(PSC_AC97CFG);
560 ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
561 au_writel(ac97_config, PSC_AC97CFG);
564 /* Always enable slots 3 and 4 (stereo). Slot 6 is
565 * optional Mic ADC, which we don't support yet.
567 ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
568 ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
570 au_writel(ac97_config, PSC_AC97CFG);
573 ac97_config |= PSC_AC97CFG_DE_ENABLE;
574 au_writel(ac97_config, PSC_AC97CFG);
577 /* Wait for Device ready.
580 stat = au_readl(PSC_AC97STAT);
582 } while ((stat & PSC_AC97STAT_DR) == 0);
585 /* Hold spinlock for both start_dac() and start_adc() calls */
587 start_dac(struct au1550_state *s)
589 struct dmabuf *db = &s->dma_dac;
594 set_xmit_slots(db->num_channels);
595 au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
597 au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
600 au1xxx_dbdma_start(db->dmanr);
606 start_adc(struct au1550_state *s)
608 struct dmabuf *db = &s->dma_adc;
614 /* Put two buffers on the ring to get things started.
616 for (i=0; i<2; i++) {
617 au1xxx_dbdma_put_dest(db->dmanr, virt_to_phys(db->nextIn),
618 db->dma_fragsize, DDMA_FLAGS_IE);
620 db->nextIn += db->dma_fragsize;
621 if (db->nextIn >= db->rawbuf + db->dmasize)
622 db->nextIn -= db->dmasize;
625 set_recv_slots(db->num_channels);
626 au1xxx_dbdma_start(db->dmanr);
627 au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
629 au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
636 prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
638 unsigned user_bytes_per_sec;
640 unsigned rate = db->sample_rate;
643 db->ready = db->mapped = 0;
644 db->buforder = 5; /* 32 * PAGE_SIZE */
645 db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
651 if (db->sample_size == 8)
653 if (db->num_channels == 1)
655 db->cnt_factor *= db->src_factor;
659 db->nextIn = db->nextOut = db->rawbuf;
661 db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
662 db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
663 2 : db->num_channels);
665 user_bytes_per_sec = rate * db->user_bytes_per_sample;
666 bufs = PAGE_SIZE << db->buforder;
667 if (db->ossfragshift) {
668 if ((1000 << db->ossfragshift) < user_bytes_per_sec)
669 db->fragshift = ld2(user_bytes_per_sec/1000);
671 db->fragshift = db->ossfragshift;
673 db->fragshift = ld2(user_bytes_per_sec / 100 /
674 (db->subdivision ? db->subdivision : 1));
675 if (db->fragshift < 3)
679 db->fragsize = 1 << db->fragshift;
680 db->dma_fragsize = db->fragsize * db->cnt_factor;
681 db->numfrag = bufs / db->dma_fragsize;
683 while (db->numfrag < 4 && db->fragshift > 3) {
685 db->fragsize = 1 << db->fragshift;
686 db->dma_fragsize = db->fragsize * db->cnt_factor;
687 db->numfrag = bufs / db->dma_fragsize;
690 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
691 db->numfrag = db->ossmaxfrags;
693 db->dmasize = db->dma_fragsize * db->numfrag;
694 memset(db->rawbuf, 0, bufs);
696 pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
697 rate, db->sample_size, db->num_channels);
698 pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
699 db->fragsize, db->cnt_factor, db->dma_fragsize);
700 pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
707 prog_dmabuf_adc(struct au1550_state *s)
710 return prog_dmabuf(s, &s->dma_adc);
715 prog_dmabuf_dac(struct au1550_state *s)
718 return prog_dmabuf(s, &s->dma_dac);
722 static void dac_dma_interrupt(int irq, void *dev_id)
724 struct au1550_state *s = (struct au1550_state *) dev_id;
725 struct dmabuf *db = &s->dma_dac;
730 ac97c_stat = au_readl(PSC_AC97STAT);
731 if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
732 pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
735 if (db->count >= db->fragsize) {
736 if (au1xxx_dbdma_put_source(db->dmanr,
737 virt_to_phys(db->nextOut), db->fragsize,
738 DDMA_FLAGS_IE) == 0) {
739 err("qcount < 2 and no ring room!");
741 db->nextOut += db->fragsize;
742 if (db->nextOut >= db->rawbuf + db->dmasize)
743 db->nextOut -= db->dmasize;
744 db->count -= db->fragsize;
745 db->total_bytes += db->dma_fragsize;
749 /* wake up anybody listening */
750 if (waitqueue_active(&db->wait))
753 spin_unlock(&s->lock);
757 static void adc_dma_interrupt(int irq, void *dev_id)
759 struct au1550_state *s = (struct au1550_state *)dev_id;
760 struct dmabuf *dp = &s->dma_adc;
766 /* Pull the buffer from the dma queue.
768 au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
770 if ((dp->count + obytes) > dp->dmasize) {
771 /* Overrun. Stop ADC and log the error
773 spin_unlock(&s->lock);
780 /* Put a new empty buffer on the destination DMA.
782 au1xxx_dbdma_put_dest(dp->dmanr, virt_to_phys(dp->nextIn),
783 dp->dma_fragsize, DDMA_FLAGS_IE);
785 dp->nextIn += dp->dma_fragsize;
786 if (dp->nextIn >= dp->rawbuf + dp->dmasize)
787 dp->nextIn -= dp->dmasize;
790 dp->total_bytes += obytes;
792 /* wake up anybody listening
794 if (waitqueue_active(&dp->wait))
797 spin_unlock(&s->lock);
801 au1550_llseek(struct file *file, loff_t offset, int origin)
808 au1550_open_mixdev(struct inode *inode, struct file *file)
810 file->private_data = &au1550_state;
815 au1550_release_mixdev(struct inode *inode, struct file *file)
821 mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
824 return codec->mixer_ioctl(codec, cmd, arg);
828 au1550_ioctl_mixdev(struct inode *inode, struct file *file,
829 unsigned int cmd, unsigned long arg)
831 struct au1550_state *s = (struct au1550_state *)file->private_data;
832 struct ac97_codec *codec = s->codec;
834 return mixdev_ioctl(codec, cmd, arg);
837 static /*const */ struct file_operations au1550_mixer_fops = {
839 llseek:au1550_llseek,
840 ioctl:au1550_ioctl_mixdev,
841 open:au1550_open_mixdev,
842 release:au1550_release_mixdev,
846 drain_dac(struct au1550_state *s, int nonblock)
851 if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
855 spin_lock_irqsave(&s->lock, flags);
856 count = s->dma_dac.count;
857 spin_unlock_irqrestore(&s->lock, flags);
858 if (count <= s->dma_dac.fragsize)
860 if (signal_pending(current))
864 tmo = 1000 * count / (s->no_vra ?
865 48000 : s->dma_dac.sample_rate);
866 tmo /= s->dma_dac.dma_bytes_per_sample;
869 if (signal_pending(current))
874 static inline u8 S16_TO_U8(s16 ch)
876 return (u8) (ch >> 8) + 0x80;
878 static inline s16 U8_TO_S16(u8 ch)
880 return (s16) (ch - 0x80) << 8;
884 * Translates user samples to dma buffer suitable for AC'97 DAC data:
885 * If mono, copy left channel to right channel in dma buffer.
886 * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
887 * If interpolating (no VRA), duplicate every audio frame src_factor times.
890 translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
894 int interp_bytes_per_sample;
896 int mono = (db->num_channels == 1);
898 s16 ch, dmasample[6];
900 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
901 /* no translation necessary, just copy
903 if (copy_from_user(dmabuf, userbuf, dmacount))
908 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
909 num_samples = dmacount / interp_bytes_per_sample;
911 for (sample = 0; sample < num_samples; sample++) {
912 if (copy_from_user(usersample, userbuf,
913 db->user_bytes_per_sample)) {
917 for (i = 0; i < db->num_channels; i++) {
918 if (db->sample_size == 8)
919 ch = U8_TO_S16(usersample[i]);
921 ch = *((s16 *) (&usersample[i * 2]));
924 dmasample[i + 1] = ch; /* right channel */
927 /* duplicate every audio frame src_factor times
929 for (i = 0; i < db->src_factor; i++)
930 memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
932 userbuf += db->user_bytes_per_sample;
933 dmabuf += interp_bytes_per_sample;
936 return num_samples * interp_bytes_per_sample;
940 * Translates AC'97 ADC samples to user buffer:
941 * If mono, send only left channel to user buffer.
942 * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
943 * If decimating (no VRA), skip over src_factor audio frames.
946 translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
950 int interp_bytes_per_sample;
952 int mono = (db->num_channels == 1);
955 if (db->sample_size == 16 && !mono && db->src_factor == 1) {
956 /* no translation necessary, just copy
958 if (copy_to_user(userbuf, dmabuf, dmacount))
963 interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
964 num_samples = dmacount / interp_bytes_per_sample;
966 for (sample = 0; sample < num_samples; sample++) {
967 for (i = 0; i < db->num_channels; i++) {
968 if (db->sample_size == 8)
970 S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
972 *((s16 *) (&usersample[i * 2])) =
973 *((s16 *) (&dmabuf[i * 2]));
976 if (copy_to_user(userbuf, usersample,
977 db->user_bytes_per_sample)) {
981 userbuf += db->user_bytes_per_sample;
982 dmabuf += interp_bytes_per_sample;
985 return num_samples * interp_bytes_per_sample;
989 * Copy audio data to/from user buffer from/to dma buffer, taking care
990 * that we wrap when reading/writing the dma buffer. Returns actual byte
991 * count written to or read from the dma buffer.
994 copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
996 char *bufptr = to_user ? db->nextOut : db->nextIn;
997 char *bufend = db->rawbuf + db->dmasize;
1000 if (bufptr + count > bufend) {
1001 int partial = (int) (bufend - bufptr);
1003 if ((cnt = translate_to_user(db, userbuf,
1004 bufptr, partial)) < 0)
1007 if ((cnt = translate_to_user(db, userbuf + partial,
1009 count - partial)) < 0)
1013 if ((cnt = translate_from_user(db, bufptr, userbuf,
1017 if ((cnt = translate_from_user(db, db->rawbuf,
1019 count - partial)) < 0)
1025 ret = translate_to_user(db, userbuf, bufptr, count);
1027 ret = translate_from_user(db, bufptr, userbuf, count);
1035 au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
1037 struct au1550_state *s = (struct au1550_state *)file->private_data;
1038 struct dmabuf *db = &s->dma_adc;
1039 DECLARE_WAITQUEUE(wait, current);
1041 unsigned long flags;
1042 int cnt, usercnt, avail;
1046 if (!access_ok(VERIFY_WRITE, buffer, count))
1050 count *= db->cnt_factor;
1052 mutex_lock(&s->sem);
1053 add_wait_queue(&db->wait, &wait);
1056 /* wait for samples in ADC dma buffer
1059 spin_lock_irqsave(&s->lock, flags);
1064 __set_current_state(TASK_INTERRUPTIBLE);
1065 spin_unlock_irqrestore(&s->lock, flags);
1067 if (file->f_flags & O_NONBLOCK) {
1072 mutex_unlock(&s->sem);
1074 if (signal_pending(current)) {
1079 mutex_lock(&s->sem);
1081 } while (avail <= 0);
1083 /* copy from nextOut to user
1085 if ((cnt = copy_dmabuf_user(db, buffer,
1087 avail : count, 1)) < 0) {
1093 spin_lock_irqsave(&s->lock, flags);
1096 if (db->nextOut >= db->rawbuf + db->dmasize)
1097 db->nextOut -= db->dmasize;
1098 spin_unlock_irqrestore(&s->lock, flags);
1101 usercnt = cnt / db->cnt_factor;
1104 } /* while (count > 0) */
1107 mutex_unlock(&s->sem);
1109 remove_wait_queue(&db->wait, &wait);
1110 set_current_state(TASK_RUNNING);
1115 au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
1117 struct au1550_state *s = (struct au1550_state *)file->private_data;
1118 struct dmabuf *db = &s->dma_dac;
1119 DECLARE_WAITQUEUE(wait, current);
1121 unsigned long flags;
1122 int cnt, usercnt, avail;
1124 pr_debug("write: count=%d\n", count);
1128 if (!access_ok(VERIFY_READ, buffer, count))
1131 count *= db->cnt_factor;
1133 mutex_lock(&s->sem);
1134 add_wait_queue(&db->wait, &wait);
1137 /* wait for space in playback buffer
1140 spin_lock_irqsave(&s->lock, flags);
1141 avail = (int) db->dmasize - db->count;
1143 __set_current_state(TASK_INTERRUPTIBLE);
1144 spin_unlock_irqrestore(&s->lock, flags);
1146 if (file->f_flags & O_NONBLOCK) {
1151 mutex_unlock(&s->sem);
1153 if (signal_pending(current)) {
1158 mutex_lock(&s->sem);
1160 } while (avail <= 0);
1162 /* copy from user to nextIn
1164 if ((cnt = copy_dmabuf_user(db, (char *) buffer,
1166 avail : count, 0)) < 0) {
1172 spin_lock_irqsave(&s->lock, flags);
1175 if (db->nextIn >= db->rawbuf + db->dmasize)
1176 db->nextIn -= db->dmasize;
1178 /* If the data is available, we want to keep two buffers
1179 * on the dma queue. If the queue count reaches zero,
1180 * we know the dma has stopped.
1182 while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
1183 if (au1xxx_dbdma_put_source(db->dmanr,
1184 virt_to_phys(db->nextOut), db->fragsize,
1185 DDMA_FLAGS_IE) == 0) {
1186 err("qcount < 2 and no ring room!");
1188 db->nextOut += db->fragsize;
1189 if (db->nextOut >= db->rawbuf + db->dmasize)
1190 db->nextOut -= db->dmasize;
1191 db->total_bytes += db->dma_fragsize;
1192 if (db->dma_qcount == 0)
1196 spin_unlock_irqrestore(&s->lock, flags);
1199 usercnt = cnt / db->cnt_factor;
1202 } /* while (count > 0) */
1205 mutex_unlock(&s->sem);
1207 remove_wait_queue(&db->wait, &wait);
1208 set_current_state(TASK_RUNNING);
1213 /* No kernel lock - we have our own spinlock */
1215 au1550_poll(struct file *file, struct poll_table_struct *wait)
1217 struct au1550_state *s = (struct au1550_state *)file->private_data;
1218 unsigned long flags;
1219 unsigned int mask = 0;
1221 if (file->f_mode & FMODE_WRITE) {
1222 if (!s->dma_dac.ready)
1224 poll_wait(file, &s->dma_dac.wait, wait);
1226 if (file->f_mode & FMODE_READ) {
1227 if (!s->dma_adc.ready)
1229 poll_wait(file, &s->dma_adc.wait, wait);
1232 spin_lock_irqsave(&s->lock, flags);
1234 if (file->f_mode & FMODE_READ) {
1235 if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
1236 mask |= POLLIN | POLLRDNORM;
1238 if (file->f_mode & FMODE_WRITE) {
1239 if (s->dma_dac.mapped) {
1240 if (s->dma_dac.count >=
1241 (signed)s->dma_dac.dma_fragsize)
1242 mask |= POLLOUT | POLLWRNORM;
1244 if ((signed) s->dma_dac.dmasize >=
1245 s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
1246 mask |= POLLOUT | POLLWRNORM;
1249 spin_unlock_irqrestore(&s->lock, flags);
1254 au1550_mmap(struct file *file, struct vm_area_struct *vma)
1256 struct au1550_state *s = (struct au1550_state *)file->private_data;
1262 mutex_lock(&s->sem);
1263 if (vma->vm_flags & VM_WRITE)
1265 else if (vma->vm_flags & VM_READ)
1271 if (vma->vm_pgoff != 0) {
1275 size = vma->vm_end - vma->vm_start;
1276 if (size > (PAGE_SIZE << db->buforder)) {
1280 if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
1281 size, vma->vm_page_prot)) {
1285 vma->vm_flags &= ~VM_IO;
1288 mutex_unlock(&s->sem);
1294 static struct ioctl_str_t {
1298 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
1299 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
1300 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
1301 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
1302 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
1303 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
1304 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
1305 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
1306 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
1307 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
1308 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
1309 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
1310 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
1311 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
1312 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
1313 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
1314 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
1315 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
1316 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
1317 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
1318 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
1319 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
1320 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
1321 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
1322 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
1323 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
1324 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
1325 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
1326 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
1327 {OSS_GETVERSION, "OSS_GETVERSION"},
1328 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
1329 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
1330 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
1331 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
1336 dma_count_done(struct dmabuf *db)
1341 return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
1346 au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
1349 struct au1550_state *s = (struct au1550_state *)file->private_data;
1350 unsigned long flags;
1351 audio_buf_info abinfo;
1354 int val, mapped, ret, diff;
1356 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1357 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1360 for (count = 0; count < ARRAY_SIZE(ioctl_str); count++) {
1361 if (ioctl_str[count].cmd == cmd)
1364 if (count < ARRAY_SIZE(ioctl_str))
1365 pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
1367 pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
1371 case OSS_GETVERSION:
1372 return put_user(SOUND_VERSION, (int *) arg);
1374 case SNDCTL_DSP_SYNC:
1375 if (file->f_mode & FMODE_WRITE)
1376 return drain_dac(s, file->f_flags & O_NONBLOCK);
1379 case SNDCTL_DSP_SETDUPLEX:
1382 case SNDCTL_DSP_GETCAPS:
1383 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
1384 DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
1386 case SNDCTL_DSP_RESET:
1387 if (file->f_mode & FMODE_WRITE) {
1390 s->dma_dac.count = s->dma_dac.total_bytes = 0;
1391 s->dma_dac.nextIn = s->dma_dac.nextOut =
1394 if (file->f_mode & FMODE_READ) {
1397 s->dma_adc.count = s->dma_adc.total_bytes = 0;
1398 s->dma_adc.nextIn = s->dma_adc.nextOut =
1403 case SNDCTL_DSP_SPEED:
1404 if (get_user(val, (int *) arg))
1407 if (file->f_mode & FMODE_READ) {
1409 set_adc_rate(s, val);
1411 if (file->f_mode & FMODE_WRITE) {
1413 set_dac_rate(s, val);
1415 if (s->open_mode & FMODE_READ)
1416 if ((ret = prog_dmabuf_adc(s)))
1418 if (s->open_mode & FMODE_WRITE)
1419 if ((ret = prog_dmabuf_dac(s)))
1422 return put_user((file->f_mode & FMODE_READ) ?
1423 s->dma_adc.sample_rate :
1424 s->dma_dac.sample_rate,
1427 case SNDCTL_DSP_STEREO:
1428 if (get_user(val, (int *) arg))
1430 if (file->f_mode & FMODE_READ) {
1432 s->dma_adc.num_channels = val ? 2 : 1;
1433 if ((ret = prog_dmabuf_adc(s)))
1436 if (file->f_mode & FMODE_WRITE) {
1438 s->dma_dac.num_channels = val ? 2 : 1;
1439 if (s->codec_ext_caps & AC97_EXT_DACS) {
1440 /* disable surround and center/lfe in AC'97
1442 u16 ext_stat = rdcodec(s->codec,
1443 AC97_EXTENDED_STATUS);
1444 wrcodec(s->codec, AC97_EXTENDED_STATUS,
1445 ext_stat | (AC97_EXTSTAT_PRI |
1449 if ((ret = prog_dmabuf_dac(s)))
1454 case SNDCTL_DSP_CHANNELS:
1455 if (get_user(val, (int *) arg))
1458 if (file->f_mode & FMODE_READ) {
1459 if (val < 0 || val > 2)
1462 s->dma_adc.num_channels = val;
1463 if ((ret = prog_dmabuf_adc(s)))
1466 if (file->f_mode & FMODE_WRITE) {
1475 if (!(s->codec_ext_caps &
1480 if ((s->codec_ext_caps &
1481 AC97_EXT_DACS) != AC97_EXT_DACS)
1490 (s->codec_ext_caps & AC97_EXT_DACS)) {
1491 /* disable surround and center/lfe
1496 AC97_EXTENDED_STATUS);
1498 AC97_EXTENDED_STATUS,
1499 ext_stat | (AC97_EXTSTAT_PRI |
1502 } else if (val >= 4) {
1503 /* enable surround, center/lfe
1508 AC97_EXTENDED_STATUS);
1509 ext_stat &= ~AC97_EXTSTAT_PRJ;
1512 ~(AC97_EXTSTAT_PRI |
1515 AC97_EXTENDED_STATUS,
1519 s->dma_dac.num_channels = val;
1520 if ((ret = prog_dmabuf_dac(s)))
1524 return put_user(val, (int *) arg);
1526 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1527 return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
1529 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
1530 if (get_user(val, (int *) arg))
1532 if (val != AFMT_QUERY) {
1533 if (file->f_mode & FMODE_READ) {
1535 if (val == AFMT_S16_LE)
1536 s->dma_adc.sample_size = 16;
1539 s->dma_adc.sample_size = 8;
1541 if ((ret = prog_dmabuf_adc(s)))
1544 if (file->f_mode & FMODE_WRITE) {
1546 if (val == AFMT_S16_LE)
1547 s->dma_dac.sample_size = 16;
1550 s->dma_dac.sample_size = 8;
1552 if ((ret = prog_dmabuf_dac(s)))
1556 if (file->f_mode & FMODE_READ)
1557 val = (s->dma_adc.sample_size == 16) ?
1558 AFMT_S16_LE : AFMT_U8;
1560 val = (s->dma_dac.sample_size == 16) ?
1561 AFMT_S16_LE : AFMT_U8;
1563 return put_user(val, (int *) arg);
1565 case SNDCTL_DSP_POST:
1568 case SNDCTL_DSP_GETTRIGGER:
1570 spin_lock_irqsave(&s->lock, flags);
1571 if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
1572 val |= PCM_ENABLE_INPUT;
1573 if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
1574 val |= PCM_ENABLE_OUTPUT;
1575 spin_unlock_irqrestore(&s->lock, flags);
1576 return put_user(val, (int *) arg);
1578 case SNDCTL_DSP_SETTRIGGER:
1579 if (get_user(val, (int *) arg))
1581 if (file->f_mode & FMODE_READ) {
1582 if (val & PCM_ENABLE_INPUT) {
1583 spin_lock_irqsave(&s->lock, flags);
1585 spin_unlock_irqrestore(&s->lock, flags);
1589 if (file->f_mode & FMODE_WRITE) {
1590 if (val & PCM_ENABLE_OUTPUT) {
1591 spin_lock_irqsave(&s->lock, flags);
1593 spin_unlock_irqrestore(&s->lock, flags);
1599 case SNDCTL_DSP_GETOSPACE:
1600 if (!(file->f_mode & FMODE_WRITE))
1602 abinfo.fragsize = s->dma_dac.fragsize;
1603 spin_lock_irqsave(&s->lock, flags);
1604 count = s->dma_dac.count;
1605 count -= dma_count_done(&s->dma_dac);
1606 spin_unlock_irqrestore(&s->lock, flags);
1609 abinfo.bytes = (s->dma_dac.dmasize - count) /
1610 s->dma_dac.cnt_factor;
1611 abinfo.fragstotal = s->dma_dac.numfrag;
1612 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1613 pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
1614 return copy_to_user((void *) arg, &abinfo,
1615 sizeof(abinfo)) ? -EFAULT : 0;
1617 case SNDCTL_DSP_GETISPACE:
1618 if (!(file->f_mode & FMODE_READ))
1620 abinfo.fragsize = s->dma_adc.fragsize;
1621 spin_lock_irqsave(&s->lock, flags);
1622 count = s->dma_adc.count;
1623 count += dma_count_done(&s->dma_adc);
1624 spin_unlock_irqrestore(&s->lock, flags);
1627 abinfo.bytes = count / s->dma_adc.cnt_factor;
1628 abinfo.fragstotal = s->dma_adc.numfrag;
1629 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1630 return copy_to_user((void *) arg, &abinfo,
1631 sizeof(abinfo)) ? -EFAULT : 0;
1633 case SNDCTL_DSP_NONBLOCK:
1634 spin_lock(&file->f_lock);
1635 file->f_flags |= O_NONBLOCK;
1636 spin_unlock(&file->f_lock);
1639 case SNDCTL_DSP_GETODELAY:
1640 if (!(file->f_mode & FMODE_WRITE))
1642 spin_lock_irqsave(&s->lock, flags);
1643 count = s->dma_dac.count;
1644 count -= dma_count_done(&s->dma_dac);
1645 spin_unlock_irqrestore(&s->lock, flags);
1648 count /= s->dma_dac.cnt_factor;
1649 return put_user(count, (int *) arg);
1651 case SNDCTL_DSP_GETIPTR:
1652 if (!(file->f_mode & FMODE_READ))
1654 spin_lock_irqsave(&s->lock, flags);
1655 cinfo.bytes = s->dma_adc.total_bytes;
1656 count = s->dma_adc.count;
1657 if (!s->dma_adc.stopped) {
1658 diff = dma_count_done(&s->dma_adc);
1660 cinfo.bytes += diff;
1661 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
1662 virt_to_phys(s->dma_adc.rawbuf);
1664 cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
1665 virt_to_phys(s->dma_adc.rawbuf);
1666 if (s->dma_adc.mapped)
1667 s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
1668 spin_unlock_irqrestore(&s->lock, flags);
1671 cinfo.blocks = count >> s->dma_adc.fragshift;
1672 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1674 case SNDCTL_DSP_GETOPTR:
1675 if (!(file->f_mode & FMODE_READ))
1677 spin_lock_irqsave(&s->lock, flags);
1678 cinfo.bytes = s->dma_dac.total_bytes;
1679 count = s->dma_dac.count;
1680 if (!s->dma_dac.stopped) {
1681 diff = dma_count_done(&s->dma_dac);
1683 cinfo.bytes += diff;
1684 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
1685 virt_to_phys(s->dma_dac.rawbuf);
1687 cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
1688 virt_to_phys(s->dma_dac.rawbuf);
1689 if (s->dma_dac.mapped)
1690 s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
1691 spin_unlock_irqrestore(&s->lock, flags);
1694 cinfo.blocks = count >> s->dma_dac.fragshift;
1695 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
1697 case SNDCTL_DSP_GETBLKSIZE:
1698 if (file->f_mode & FMODE_WRITE)
1699 return put_user(s->dma_dac.fragsize, (int *) arg);
1701 return put_user(s->dma_adc.fragsize, (int *) arg);
1703 case SNDCTL_DSP_SETFRAGMENT:
1704 if (get_user(val, (int *) arg))
1706 if (file->f_mode & FMODE_READ) {
1708 s->dma_adc.ossfragshift = val & 0xffff;
1709 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1710 if (s->dma_adc.ossfragshift < 4)
1711 s->dma_adc.ossfragshift = 4;
1712 if (s->dma_adc.ossfragshift > 15)
1713 s->dma_adc.ossfragshift = 15;
1714 if (s->dma_adc.ossmaxfrags < 4)
1715 s->dma_adc.ossmaxfrags = 4;
1716 if ((ret = prog_dmabuf_adc(s)))
1719 if (file->f_mode & FMODE_WRITE) {
1721 s->dma_dac.ossfragshift = val & 0xffff;
1722 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1723 if (s->dma_dac.ossfragshift < 4)
1724 s->dma_dac.ossfragshift = 4;
1725 if (s->dma_dac.ossfragshift > 15)
1726 s->dma_dac.ossfragshift = 15;
1727 if (s->dma_dac.ossmaxfrags < 4)
1728 s->dma_dac.ossmaxfrags = 4;
1729 if ((ret = prog_dmabuf_dac(s)))
1734 case SNDCTL_DSP_SUBDIVIDE:
1735 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1736 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1738 if (get_user(val, (int *) arg))
1740 if (val != 1 && val != 2 && val != 4)
1742 if (file->f_mode & FMODE_READ) {
1744 s->dma_adc.subdivision = val;
1745 if ((ret = prog_dmabuf_adc(s)))
1748 if (file->f_mode & FMODE_WRITE) {
1750 s->dma_dac.subdivision = val;
1751 if ((ret = prog_dmabuf_dac(s)))
1756 case SOUND_PCM_READ_RATE:
1757 return put_user((file->f_mode & FMODE_READ) ?
1758 s->dma_adc.sample_rate :
1759 s->dma_dac.sample_rate,
1762 case SOUND_PCM_READ_CHANNELS:
1763 if (file->f_mode & FMODE_READ)
1764 return put_user(s->dma_adc.num_channels, (int *)arg);
1766 return put_user(s->dma_dac.num_channels, (int *)arg);
1768 case SOUND_PCM_READ_BITS:
1769 if (file->f_mode & FMODE_READ)
1770 return put_user(s->dma_adc.sample_size, (int *)arg);
1772 return put_user(s->dma_dac.sample_size, (int *)arg);
1774 case SOUND_PCM_WRITE_FILTER:
1775 case SNDCTL_DSP_SETSYNCRO:
1776 case SOUND_PCM_READ_FILTER:
1780 return mixdev_ioctl(s->codec, cmd, arg);
1785 au1550_open(struct inode *inode, struct file *file)
1787 int minor = MINOR(inode->i_rdev);
1788 DECLARE_WAITQUEUE(wait, current);
1789 struct au1550_state *s = &au1550_state;
1793 if (file->f_flags & O_NONBLOCK)
1794 pr_debug("open: non-blocking\n");
1796 pr_debug("open: blocking\n");
1799 file->private_data = s;
1800 /* wait for device to become free */
1801 mutex_lock(&s->open_mutex);
1802 while (s->open_mode & file->f_mode) {
1803 if (file->f_flags & O_NONBLOCK) {
1804 mutex_unlock(&s->open_mutex);
1807 add_wait_queue(&s->open_wait, &wait);
1808 __set_current_state(TASK_INTERRUPTIBLE);
1809 mutex_unlock(&s->open_mutex);
1811 remove_wait_queue(&s->open_wait, &wait);
1812 set_current_state(TASK_RUNNING);
1813 if (signal_pending(current))
1814 return -ERESTARTSYS;
1815 mutex_lock(&s->open_mutex);
1821 if (file->f_mode & FMODE_READ) {
1822 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
1823 s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
1824 s->dma_adc.num_channels = 1;
1825 s->dma_adc.sample_size = 8;
1826 set_adc_rate(s, 8000);
1827 if ((minor & 0xf) == SND_DEV_DSP16)
1828 s->dma_adc.sample_size = 16;
1831 if (file->f_mode & FMODE_WRITE) {
1832 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
1833 s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
1834 s->dma_dac.num_channels = 1;
1835 s->dma_dac.sample_size = 8;
1836 set_dac_rate(s, 8000);
1837 if ((minor & 0xf) == SND_DEV_DSP16)
1838 s->dma_dac.sample_size = 16;
1841 if (file->f_mode & FMODE_READ) {
1842 if ((ret = prog_dmabuf_adc(s)))
1845 if (file->f_mode & FMODE_WRITE) {
1846 if ((ret = prog_dmabuf_dac(s)))
1850 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1851 mutex_unlock(&s->open_mutex);
1852 mutex_init(&s->sem);
1857 au1550_release(struct inode *inode, struct file *file)
1859 struct au1550_state *s = (struct au1550_state *)file->private_data;
1863 if (file->f_mode & FMODE_WRITE) {
1865 drain_dac(s, file->f_flags & O_NONBLOCK);
1869 mutex_lock(&s->open_mutex);
1870 if (file->f_mode & FMODE_WRITE) {
1872 kfree(s->dma_dac.rawbuf);
1873 s->dma_dac.rawbuf = NULL;
1875 if (file->f_mode & FMODE_READ) {
1877 kfree(s->dma_adc.rawbuf);
1878 s->dma_adc.rawbuf = NULL;
1880 s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
1881 mutex_unlock(&s->open_mutex);
1882 wake_up(&s->open_wait);
1887 static /*const */ struct file_operations au1550_audio_fops = {
1889 llseek: au1550_llseek,
1891 write: au1550_write,
1893 ioctl: au1550_ioctl,
1896 release: au1550_release,
1899 MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
1900 MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
1901 MODULE_LICENSE("GPL");
1904 static int __devinit
1907 struct au1550_state *s = &au1550_state;
1910 memset(s, 0, sizeof(struct au1550_state));
1912 init_waitqueue_head(&s->dma_adc.wait);
1913 init_waitqueue_head(&s->dma_dac.wait);
1914 init_waitqueue_head(&s->open_wait);
1915 mutex_init(&s->open_mutex);
1916 spin_lock_init(&s->lock);
1918 s->codec = ac97_alloc_codec();
1919 if(s->codec == NULL) {
1920 err("Out of memory");
1923 s->codec->private_data = s;
1925 s->codec->codec_read = rdcodec;
1926 s->codec->codec_write = wrcodec;
1927 s->codec->codec_wait = waitcodec;
1929 if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
1930 0x30, "Au1550 AC97")) {
1931 err("AC'97 ports in use");
1934 /* Allocate the DMA Channels
1936 if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
1937 DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
1938 err("Can't get DAC DMA");
1941 au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
1942 if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
1943 NUM_DBDMA_DESCRIPTORS) == 0) {
1944 err("Can't get DAC DMA descriptors");
1948 if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
1949 DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
1950 err("Can't get ADC DMA");
1953 au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
1954 if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
1955 NUM_DBDMA_DESCRIPTORS) == 0) {
1956 err("Can't get ADC DMA descriptors");
1960 pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
1962 /* register devices */
1964 if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
1966 if ((s->codec->dev_mixer =
1967 register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
1970 /* The GPIO for the appropriate PSC was configured by the
1971 * board specific start up.
1973 * configure PSC for AC'97
1975 au_writel(0, AC97_PSC_CTRL); /* Disable PSC */
1977 au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
1980 /* cold reset the AC'97
1982 au_writel(PSC_AC97RST_RST, PSC_AC97RST);
1985 au_writel(0, PSC_AC97RST);
1988 /* need to delay around 500msec(bleech) to give
1989 some CODECs enough time to wakeup */
1992 /* warm reset the AC'97 to start the bitclk
1994 au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
1997 au_writel(0, PSC_AC97RST);
2002 au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
2005 /* Wait for PSC ready.
2008 val = au_readl(PSC_AC97STAT);
2010 } while ((val & PSC_AC97STAT_SR) == 0);
2012 /* Configure AC97 controller.
2013 * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
2015 val = PSC_AC97CFG_SET_LEN(16);
2016 val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
2018 /* Enable device so we can at least
2019 * talk over the AC-link.
2021 au_writel(val, PSC_AC97CFG);
2022 au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
2024 val |= PSC_AC97CFG_DE_ENABLE;
2025 au_writel(val, PSC_AC97CFG);
2028 /* Wait for Device ready.
2031 val = au_readl(PSC_AC97STAT);
2033 } while ((val & PSC_AC97STAT_DR) == 0);
2036 if (!ac97_probe_codec(s->codec))
2039 s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
2040 s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
2041 pr_info("AC'97 Base/Extended ID = %04x/%04x",
2042 s->codec_base_caps, s->codec_ext_caps);
2044 if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
2045 /* codec does not support VRA
2049 /* Boot option says disable VRA
2051 u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
2052 wrcodec(s->codec, AC97_EXTENDED_STATUS,
2053 ac97_extstat & ~AC97_EXTSTAT_VRA);
2057 pr_info("no VRA, interpolating and decimating");
2059 /* set mic to be the recording source */
2060 val = SOUND_MASK_MIC;
2061 mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
2062 (unsigned long) &val);
2067 unregister_sound_mixer(s->codec->dev_mixer);
2069 unregister_sound_dsp(s->dev_audio);
2071 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2073 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2075 release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2077 ac97_release_codec(s->codec);
2081 static void __devinit
2084 struct au1550_state *s = &au1550_state;
2089 au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
2090 au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
2091 release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
2092 unregister_sound_dsp(s->dev_audio);
2093 unregister_sound_mixer(s->codec->dev_mixer);
2094 ac97_release_codec(s->codec);
2100 return au1550_probe();
2104 cleanup_au1550(void)
2109 module_init(init_au1550);
2110 module_exit(cleanup_au1550);
2115 au1550_setup(char *options)
2119 if (!options || !*options)
2122 while ((this_opt = strsep(&options, ","))) {
2125 if (!strncmp(this_opt, "vra", 3)) {
2133 __setup("au1550_audio=", au1550_setup);