1 /******************************************************************************
3 AudioScience HPI driver
4 Copyright (C) 1997-2011 AudioScience Inc. <support@audioscience.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of version 2 of the GNU General Public License as
8 published by the Free Software Foundation;
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 Hardware Programming Interface (HPI) for AudioScience
20 ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters.
21 These PCI and PCIe bus adapters are based on a
22 TMS320C6205 PCI bus mastering DSP,
23 and (except ASI50xx) TI TMS320C6xxx floating point DSP
26 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
28 (C) Copyright AudioScience Inc. 1998-2010
29 *******************************************************************************/
30 #define SOURCEFILE_NAME "hpi6205.c"
32 #include "hpi_internal.h"
33 #include "hpimsginit.h"
39 /*****************************************************************************/
40 /* HPI6205 specific error codes */
41 #define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */
43 /* operational/messaging errors */
44 #define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015
45 #define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016
47 /* initialization/bootload errors */
48 #define HPI6205_ERROR_6205_NO_IRQ 1002
49 #define HPI6205_ERROR_6205_INIT_FAILED 1003
50 #define HPI6205_ERROR_6205_REG 1006
51 #define HPI6205_ERROR_6205_DSPPAGE 1007
52 #define HPI6205_ERROR_C6713_HPIC 1009
53 #define HPI6205_ERROR_C6713_HPIA 1010
54 #define HPI6205_ERROR_C6713_PLL 1011
55 #define HPI6205_ERROR_DSP_INTMEM 1012
56 #define HPI6205_ERROR_DSP_EXTMEM 1013
57 #define HPI6205_ERROR_DSP_PLD 1014
58 #define HPI6205_ERROR_6205_EEPROM 1017
59 #define HPI6205_ERROR_DSP_EMIF 1018
61 /*****************************************************************************/
62 /* for C6205 PCI i/f */
63 /* Host Status Register (HSR) bitfields */
64 #define C6205_HSR_INTSRC 0x01
65 #define C6205_HSR_INTAVAL 0x02
66 #define C6205_HSR_INTAM 0x04
67 #define C6205_HSR_CFGERR 0x08
68 #define C6205_HSR_EEREAD 0x10
69 /* Host-to-DSP Control Register (HDCR) bitfields */
70 #define C6205_HDCR_WARMRESET 0x01
71 #define C6205_HDCR_DSPINT 0x02
72 #define C6205_HDCR_PCIBOOT 0x04
73 /* DSP Page Register (DSPP) bitfields, */
74 /* defines 4 Mbyte page that BAR0 points to */
75 #define C6205_DSPP_MAP1 0x400
77 /* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP.
78 * BAR1 maps to non-prefetchable 8 Mbyte memory block
79 * of DSP memory mapped registers (starting at 0x01800000).
80 * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this
81 * needs to be added to the BAR1 base address set in the PCI config reg
83 #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L)
84 #define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET)
85 #define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4)
86 #define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8)
88 /* used to control LED (revA) and reset C6713 (revB) */
89 #define C6205_BAR0_TIMER1_CTL (0x01980000L)
91 /* For first 6713 in CE1 space, using DA17,16,2 */
92 #define HPICL_ADDR 0x01400000L
93 #define HPICH_ADDR 0x01400004L
94 #define HPIAL_ADDR 0x01410000L
95 #define HPIAH_ADDR 0x01410004L
96 #define HPIDIL_ADDR 0x01420000L
97 #define HPIDIH_ADDR 0x01420004L
98 #define HPIDL_ADDR 0x01430000L
99 #define HPIDH_ADDR 0x01430004L
101 #define C6713_EMIF_GCTL 0x01800000
102 #define C6713_EMIF_CE1 0x01800004
103 #define C6713_EMIF_CE0 0x01800008
104 #define C6713_EMIF_CE2 0x01800010
105 #define C6713_EMIF_CE3 0x01800014
106 #define C6713_EMIF_SDRAMCTL 0x01800018
107 #define C6713_EMIF_SDRAMTIMING 0x0180001C
108 #define C6713_EMIF_SDRAMEXT 0x01800020
118 struct consistent_dma_area h_locked_mem;
119 struct bus_master_interface *p_interface_buffer;
121 u16 flag_outstream_just_reset[HPI_MAX_STREAMS];
122 /* a non-NULL handle means there is an HPI allocated buffer */
123 struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS];
124 struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS];
125 /* non-zero size means a buffer exists, may be external */
126 u32 instream_host_buffer_size[HPI_MAX_STREAMS];
127 u32 outstream_host_buffer_size[HPI_MAX_STREAMS];
129 struct consistent_dma_area h_control_cache;
130 struct hpi_control_cache *p_cache;
133 /*****************************************************************************/
134 /* local prototypes */
136 #define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write)
138 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us);
140 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd);
142 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
143 u32 *pos_error_code);
145 static u16 message_response_sequence(struct hpi_adapter_obj *pao,
146 struct hpi_message *phm, struct hpi_response *phr);
148 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
149 struct hpi_response *phr);
151 #define HPI6205_TIMEOUT 1000000
153 static void subsys_create_adapter(struct hpi_message *phm,
154 struct hpi_response *phr);
155 static void adapter_delete(struct hpi_adapter_obj *pao,
156 struct hpi_message *phm, struct hpi_response *phr);
158 static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
159 u32 *pos_error_code);
161 static void delete_adapter_obj(struct hpi_adapter_obj *pao);
163 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
164 struct hpi_message *phm, struct hpi_response *phr);
166 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
167 struct hpi_message *phm, struct hpi_response *phr);
169 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
170 struct hpi_message *phm, struct hpi_response *phr);
171 static void outstream_write(struct hpi_adapter_obj *pao,
172 struct hpi_message *phm, struct hpi_response *phr);
174 static void outstream_get_info(struct hpi_adapter_obj *pao,
175 struct hpi_message *phm, struct hpi_response *phr);
177 static void outstream_start(struct hpi_adapter_obj *pao,
178 struct hpi_message *phm, struct hpi_response *phr);
180 static void outstream_open(struct hpi_adapter_obj *pao,
181 struct hpi_message *phm, struct hpi_response *phr);
183 static void outstream_reset(struct hpi_adapter_obj *pao,
184 struct hpi_message *phm, struct hpi_response *phr);
186 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
187 struct hpi_message *phm, struct hpi_response *phr);
189 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
190 struct hpi_message *phm, struct hpi_response *phr);
192 static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
193 struct hpi_message *phm, struct hpi_response *phr);
195 static void instream_read(struct hpi_adapter_obj *pao,
196 struct hpi_message *phm, struct hpi_response *phr);
198 static void instream_get_info(struct hpi_adapter_obj *pao,
199 struct hpi_message *phm, struct hpi_response *phr);
201 static void instream_start(struct hpi_adapter_obj *pao,
202 struct hpi_message *phm, struct hpi_response *phr);
204 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
207 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
208 int dsp_index, u32 address, u32 data);
210 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao,
213 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
214 u32 address, u32 length);
216 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
219 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
222 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index);
224 /*****************************************************************************/
226 static void subsys_message(struct hpi_adapter_obj *pao,
227 struct hpi_message *phm, struct hpi_response *phr)
229 switch (phm->function) {
230 case HPI_SUBSYS_CREATE_ADAPTER:
231 subsys_create_adapter(phm, phr);
234 phr->error = HPI_ERROR_INVALID_FUNC;
239 static void control_message(struct hpi_adapter_obj *pao,
240 struct hpi_message *phm, struct hpi_response *phr)
243 struct hpi_hw_obj *phw = pao->priv;
244 u16 pending_cache_error = 0;
246 switch (phm->function) {
247 case HPI_CONTROL_GET_STATE:
248 if (pao->has_control_cache) {
249 rmb(); /* make sure we see updates DMAed from DSP */
250 if (hpi_check_control_cache(phw->p_cache, phm, phr)) {
252 } else if (phm->u.c.attribute == HPI_METER_PEAK) {
253 pending_cache_error =
254 HPI_ERROR_CONTROL_CACHING;
257 hw_message(pao, phm, phr);
258 if (pending_cache_error && !phr->error)
259 phr->error = pending_cache_error;
261 case HPI_CONTROL_GET_INFO:
262 hw_message(pao, phm, phr);
264 case HPI_CONTROL_SET_STATE:
265 hw_message(pao, phm, phr);
266 if (pao->has_control_cache)
267 hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm,
271 phr->error = HPI_ERROR_INVALID_FUNC;
276 static void adapter_message(struct hpi_adapter_obj *pao,
277 struct hpi_message *phm, struct hpi_response *phr)
279 switch (phm->function) {
280 case HPI_ADAPTER_DELETE:
281 adapter_delete(pao, phm, phr);
285 hw_message(pao, phm, phr);
290 static void outstream_message(struct hpi_adapter_obj *pao,
291 struct hpi_message *phm, struct hpi_response *phr)
294 if (phm->obj_index >= HPI_MAX_STREAMS) {
295 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
296 HPI_DEBUG_LOG(WARNING,
297 "Message referencing invalid stream %d "
298 "on adapter index %d\n", phm->obj_index,
303 switch (phm->function) {
304 case HPI_OSTREAM_WRITE:
305 outstream_write(pao, phm, phr);
307 case HPI_OSTREAM_GET_INFO:
308 outstream_get_info(pao, phm, phr);
310 case HPI_OSTREAM_HOSTBUFFER_ALLOC:
311 outstream_host_buffer_allocate(pao, phm, phr);
313 case HPI_OSTREAM_HOSTBUFFER_GET_INFO:
314 outstream_host_buffer_get_info(pao, phm, phr);
316 case HPI_OSTREAM_HOSTBUFFER_FREE:
317 outstream_host_buffer_free(pao, phm, phr);
319 case HPI_OSTREAM_START:
320 outstream_start(pao, phm, phr);
322 case HPI_OSTREAM_OPEN:
323 outstream_open(pao, phm, phr);
325 case HPI_OSTREAM_RESET:
326 outstream_reset(pao, phm, phr);
329 hw_message(pao, phm, phr);
334 static void instream_message(struct hpi_adapter_obj *pao,
335 struct hpi_message *phm, struct hpi_response *phr)
338 if (phm->obj_index >= HPI_MAX_STREAMS) {
339 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
340 HPI_DEBUG_LOG(WARNING,
341 "Message referencing invalid stream %d "
342 "on adapter index %d\n", phm->obj_index,
347 switch (phm->function) {
348 case HPI_ISTREAM_READ:
349 instream_read(pao, phm, phr);
351 case HPI_ISTREAM_GET_INFO:
352 instream_get_info(pao, phm, phr);
354 case HPI_ISTREAM_HOSTBUFFER_ALLOC:
355 instream_host_buffer_allocate(pao, phm, phr);
357 case HPI_ISTREAM_HOSTBUFFER_GET_INFO:
358 instream_host_buffer_get_info(pao, phm, phr);
360 case HPI_ISTREAM_HOSTBUFFER_FREE:
361 instream_host_buffer_free(pao, phm, phr);
363 case HPI_ISTREAM_START:
364 instream_start(pao, phm, phr);
367 hw_message(pao, phm, phr);
372 /*****************************************************************************/
373 /** Entry point to this HPI backend
374 * All calls to the HPI start here
377 void _HPI_6205(struct hpi_adapter_obj *pao, struct hpi_message *phm,
378 struct hpi_response *phr)
380 if (pao && (pao->dsp_crashed >= 10)
381 && (phm->function != HPI_ADAPTER_DEBUG_READ)) {
382 /* allow last resort debug read even after crash */
383 hpi_init_response(phr, phm->object, phm->function,
384 HPI_ERROR_DSP_HARDWARE);
385 HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n", phm->object,
390 /* Init default response */
391 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
392 phr->error = HPI_ERROR_PROCESSING_MESSAGE;
394 HPI_DEBUG_LOG(VERBOSE, "start of switch\n");
396 case HPI_TYPE_REQUEST:
397 switch (phm->object) {
398 case HPI_OBJ_SUBSYSTEM:
399 subsys_message(pao, phm, phr);
402 case HPI_OBJ_ADAPTER:
403 adapter_message(pao, phm, phr);
406 case HPI_OBJ_CONTROL:
407 control_message(pao, phm, phr);
410 case HPI_OBJ_OSTREAM:
411 outstream_message(pao, phm, phr);
414 case HPI_OBJ_ISTREAM:
415 instream_message(pao, phm, phr);
419 hw_message(pao, phm, phr);
425 phr->error = HPI_ERROR_INVALID_TYPE;
430 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
432 struct hpi_adapter_obj *pao = NULL;
434 if (phm->object != HPI_OBJ_SUBSYSTEM) {
435 /* normal messages must have valid adapter index */
436 pao = hpi_find_adapter(phm->adapter_index);
438 /* subsys messages don't address an adapter */
439 _HPI_6205(NULL, phm, phr);
444 _HPI_6205(pao, phm, phr);
446 hpi_init_response(phr, phm->object, phm->function,
447 HPI_ERROR_BAD_ADAPTER_NUMBER);
450 /*****************************************************************************/
453 /** Create an adapter object and initialise it based on resource information
454 * passed in in the message
455 * *** NOTE - you cannot use this function AND the FindAdapters function at the
456 * same time, the application must use only one of them to get the adapters ***
458 static void subsys_create_adapter(struct hpi_message *phm,
459 struct hpi_response *phr)
461 /* create temp adapter obj, because we don't know what index yet */
462 struct hpi_adapter_obj ao;
466 HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n");
468 memset(&ao, 0, sizeof(ao));
470 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
472 HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n");
473 phr->error = HPI_ERROR_MEMORY_ALLOC;
477 ao.pci = *phm->u.s.resource.r.pci;
478 err = create_adapter_obj(&ao, &os_error_code);
480 delete_adapter_obj(&ao);
481 if (err >= HPI_ERROR_BACKEND_BASE) {
482 phr->error = HPI_ERROR_DSP_BOOTLOAD;
483 phr->specific_error = err;
487 phr->u.s.data = os_error_code;
491 phr->u.s.adapter_type = ao.adapter_type;
492 phr->u.s.adapter_index = ao.index;
496 /** delete an adapter - required by WDM driver */
497 static void adapter_delete(struct hpi_adapter_obj *pao,
498 struct hpi_message *phm, struct hpi_response *phr)
500 struct hpi_hw_obj *phw;
503 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
506 phw = (struct hpi_hw_obj *)pao->priv;
507 /* reset adapter h/w */
509 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
511 iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR);
513 delete_adapter_obj(pao);
514 hpi_delete_adapter(pao);
518 /** Create adapter object
519 allocate buffers, bootload DSPs, initialise control cache
521 static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
524 struct hpi_hw_obj *phw = pao->priv;
525 struct bus_master_interface *interface;
530 /* init error reporting */
531 pao->dsp_crashed = 0;
533 for (i = 0; i < HPI_MAX_STREAMS; i++)
534 phw->flag_outstream_just_reset[i] = 1;
536 /* The C6205 memory area 1 is 8Mbyte window into DSP registers */
538 pao->pci.ap_mem_base[1] +
539 C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]);
541 pao->pci.ap_mem_base[1] +
542 C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]);
544 pao->pci.ap_mem_base[1] +
545 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]);
547 pao->has_control_cache = 0;
549 if (hpios_locked_mem_alloc(&phw->h_locked_mem,
550 sizeof(struct bus_master_interface),
552 phw->p_interface_buffer = NULL;
553 else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem,
554 (void *)&phw->p_interface_buffer))
555 phw->p_interface_buffer = NULL;
557 HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n",
558 phw->p_interface_buffer);
560 if (phw->p_interface_buffer) {
561 memset((void *)phw->p_interface_buffer, 0,
562 sizeof(struct bus_master_interface));
563 phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN;
566 err = adapter_boot_load_dsp(pao, pos_error_code);
568 HPI_DEBUG_LOG(ERROR, "DSP code load failed\n");
569 /* no need to clean up as SubSysCreateAdapter */
570 /* calls DeleteAdapter on error. */
573 HPI_DEBUG_LOG(INFO, "load DSP code OK\n");
575 /* allow boot load even if mem alloc wont work */
576 if (!phw->p_interface_buffer)
577 return HPI_ERROR_MEMORY_ALLOC;
579 interface = phw->p_interface_buffer;
581 /* make sure the DSP has started ok */
582 if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) {
583 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n");
584 return HPI6205_ERROR_6205_INIT_FAILED;
586 /* Note that *pao, *phw are zeroed after allocation,
587 * so pointers and flags are NULL by default.
588 * Allocate bus mastering control cache buffer and tell the DSP about it
590 if (interface->control_cache.number_of_controls) {
591 u8 *p_control_cache_virtual;
593 err = hpios_locked_mem_alloc(&phw->h_control_cache,
594 interface->control_cache.size_in_bytes,
597 err = hpios_locked_mem_get_virt_addr(&phw->
599 (void *)&p_control_cache_virtual);
601 memset(p_control_cache_virtual, 0,
602 interface->control_cache.size_in_bytes);
605 hpi_alloc_control_cache(interface->
606 control_cache.number_of_controls,
607 interface->control_cache.size_in_bytes,
608 p_control_cache_virtual);
611 err = HPI_ERROR_MEMORY_ALLOC;
614 err = hpios_locked_mem_get_phys_addr(&phw->
615 h_control_cache, &phys_addr);
616 interface->control_cache.physical_address32 =
621 pao->has_control_cache = 1;
623 if (hpios_locked_mem_valid(&phw->h_control_cache))
624 hpios_locked_mem_free(&phw->h_control_cache);
625 pao->has_control_cache = 0;
628 send_dsp_command(phw, H620_HIF_IDLE);
631 struct hpi_message hm;
632 struct hpi_response hr;
635 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n");
636 memset(&hm, 0, sizeof(hm));
637 /* wAdapterIndex == version == 0 */
638 hm.type = HPI_TYPE_REQUEST;
639 hm.size = sizeof(hm);
640 hm.object = HPI_OBJ_ADAPTER;
641 hm.function = HPI_ADAPTER_GET_INFO;
643 memset(&hr, 0, sizeof(hr));
644 hr.size = sizeof(hr);
646 err = message_response_sequence(pao, &hm, &hr);
648 HPI_DEBUG_LOG(ERROR, "message transport error %d\n",
655 pao->adapter_type = hr.u.ax.info.adapter_type;
656 pao->index = hr.u.ax.info.adapter_index;
659 hr.u.ax.info.num_outstreams +
660 hr.u.ax.info.num_instreams;
662 HPI_DEBUG_LOG(VERBOSE,
663 "got adapter info type %x index %d serial %d\n",
664 hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index,
665 hr.u.ax.info.serial_number);
668 pao->open = 0; /* upon creation the adapter is closed */
671 phw->p_cache->adap_idx = pao->index;
673 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
675 return hpi_add_adapter(pao);
678 /** Free memory areas allocated by adapter
679 * this routine is called from AdapterDelete,
680 * and SubSysCreateAdapter if duplicate index
682 static void delete_adapter_obj(struct hpi_adapter_obj *pao)
684 struct hpi_hw_obj *phw = pao->priv;
687 if (hpios_locked_mem_valid(&phw->h_control_cache)) {
688 hpios_locked_mem_free(&phw->h_control_cache);
689 hpi_free_control_cache(phw->p_cache);
692 if (hpios_locked_mem_valid(&phw->h_locked_mem)) {
693 hpios_locked_mem_free(&phw->h_locked_mem);
694 phw->p_interface_buffer = NULL;
697 for (i = 0; i < HPI_MAX_STREAMS; i++)
698 if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) {
699 hpios_locked_mem_free(&phw->instream_host_buffers[i]);
700 /*?phw->InStreamHostBuffers[i] = NULL; */
701 phw->instream_host_buffer_size[i] = 0;
704 for (i = 0; i < HPI_MAX_STREAMS; i++)
705 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) {
706 hpios_locked_mem_free(&phw->outstream_host_buffers
708 phw->outstream_host_buffer_size[i] = 0;
713 /*****************************************************************************/
714 /* Adapter functions */
716 /*****************************************************************************/
717 /* OutStream Host buffer functions */
719 /** Allocate or attach buffer for busmastering
721 static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
722 struct hpi_message *phm, struct hpi_response *phr)
725 u32 command = phm->u.d.u.buffer.command;
726 struct hpi_hw_obj *phw = pao->priv;
727 struct bus_master_interface *interface = phw->p_interface_buffer;
729 hpi_init_response(phr, phm->object, phm->function, 0);
731 if (command == HPI_BUFFER_CMD_EXTERNAL
732 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
733 /* ALLOC phase, allocate a buffer with power of 2 size,
734 get its bus address for PCI bus mastering
736 phm->u.d.u.buffer.buffer_size =
737 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
738 /* return old size and allocated size,
739 so caller can detect change */
740 phr->u.d.u.stream_info.data_available =
741 phw->outstream_host_buffer_size[phm->obj_index];
742 phr->u.d.u.stream_info.buffer_size =
743 phm->u.d.u.buffer.buffer_size;
745 if (phw->outstream_host_buffer_size[phm->obj_index] ==
746 phm->u.d.u.buffer.buffer_size) {
747 /* Same size, no action required */
751 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
753 hpios_locked_mem_free(&phw->outstream_host_buffers
756 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers
757 [phm->obj_index], phm->u.d.u.buffer.buffer_size,
761 phr->error = HPI_ERROR_INVALID_DATASIZE;
762 phw->outstream_host_buffer_size[phm->obj_index] = 0;
766 err = hpios_locked_mem_get_phys_addr
767 (&phw->outstream_host_buffers[phm->obj_index],
768 &phm->u.d.u.buffer.pci_address);
769 /* get the phys addr into msg for single call alloc caller
770 * needs to do this for split alloc (or use the same message)
771 * return the phy address for split alloc in the respose too
773 phr->u.d.u.stream_info.auxiliary_data_available =
774 phm->u.d.u.buffer.pci_address;
777 hpios_locked_mem_free(&phw->outstream_host_buffers
779 phw->outstream_host_buffer_size[phm->obj_index] = 0;
780 phr->error = HPI_ERROR_MEMORY_ALLOC;
785 if (command == HPI_BUFFER_CMD_EXTERNAL
786 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
787 /* GRANT phase. Set up the BBM status, tell the DSP about
788 the buffer so it can start using BBM.
790 struct hpi_hostbuffer_status *status;
792 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
795 "Buffer size must be 2^N not %d\n",
796 phm->u.d.u.buffer.buffer_size);
797 phr->error = HPI_ERROR_INVALID_DATASIZE;
800 phw->outstream_host_buffer_size[phm->obj_index] =
801 phm->u.d.u.buffer.buffer_size;
802 status = &interface->outstream_host_buffer_status[phm->
804 status->samples_processed = 0;
805 status->stream_state = HPI_STATE_STOPPED;
806 status->dSP_index = 0;
807 status->host_index = status->dSP_index;
808 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
809 status->auxiliary_data_available = 0;
811 hw_message(pao, phm, phr);
814 && hpios_locked_mem_valid(&phw->
815 outstream_host_buffers[phm->obj_index])) {
816 hpios_locked_mem_free(&phw->outstream_host_buffers
818 phw->outstream_host_buffer_size[phm->obj_index] = 0;
823 static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
824 struct hpi_message *phm, struct hpi_response *phr)
826 struct hpi_hw_obj *phw = pao->priv;
827 struct bus_master_interface *interface = phw->p_interface_buffer;
828 struct hpi_hostbuffer_status *status;
831 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
833 if (hpios_locked_mem_get_virt_addr(&phw->
834 outstream_host_buffers[phm->obj_index],
835 (void *)&p_bbm_data)) {
836 phr->error = HPI_ERROR_INVALID_OPERATION;
839 status = &interface->outstream_host_buffer_status[phm->
841 hpi_init_response(phr, HPI_OBJ_OSTREAM,
842 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0);
843 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
844 phr->u.d.u.hostbuffer_info.p_status = status;
846 hpi_init_response(phr, HPI_OBJ_OSTREAM,
847 HPI_OSTREAM_HOSTBUFFER_GET_INFO,
848 HPI_ERROR_INVALID_OPERATION);
852 static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
853 struct hpi_message *phm, struct hpi_response *phr)
855 struct hpi_hw_obj *phw = pao->priv;
856 u32 command = phm->u.d.u.buffer.command;
858 if (phw->outstream_host_buffer_size[phm->obj_index]) {
859 if (command == HPI_BUFFER_CMD_EXTERNAL
860 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
861 phw->outstream_host_buffer_size[phm->obj_index] = 0;
862 hw_message(pao, phm, phr);
863 /* Tell adapter to stop using the host buffer. */
865 if (command == HPI_BUFFER_CMD_EXTERNAL
866 || command == HPI_BUFFER_CMD_INTERNAL_FREE)
867 hpios_locked_mem_free(&phw->outstream_host_buffers
870 /* Should HPI_ERROR_INVALID_OPERATION be returned
871 if no host buffer is allocated? */
873 hpi_init_response(phr, HPI_OBJ_OSTREAM,
874 HPI_OSTREAM_HOSTBUFFER_FREE, 0);
878 static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status)
880 return status->size_in_bytes - (status->host_index -
884 static void outstream_write(struct hpi_adapter_obj *pao,
885 struct hpi_message *phm, struct hpi_response *phr)
887 struct hpi_hw_obj *phw = pao->priv;
888 struct bus_master_interface *interface = phw->p_interface_buffer;
889 struct hpi_hostbuffer_status *status;
892 if (!phw->outstream_host_buffer_size[phm->obj_index]) {
893 /* there is no BBM buffer, write via message */
894 hw_message(pao, phm, phr);
898 hpi_init_response(phr, phm->object, phm->function, 0);
899 status = &interface->outstream_host_buffer_status[phm->obj_index];
901 space_available = outstream_get_space_available(status);
902 if (space_available < phm->u.d.u.data.data_size) {
903 phr->error = HPI_ERROR_INVALID_DATASIZE;
907 /* HostBuffers is used to indicate host buffer is internally allocated.
908 otherwise, assumed external, data written externally */
909 if (phm->u.d.u.data.pb_data
910 && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
914 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
916 if (hpios_locked_mem_get_virt_addr(&phw->
917 outstream_host_buffers[phm->obj_index],
918 (void *)&p_bbm_data)) {
919 phr->error = HPI_ERROR_INVALID_OPERATION;
924 or enough to fit from current to end of BBM buffer */
926 min(phm->u.d.u.data.data_size,
927 status->size_in_bytes -
928 (status->host_index & (status->size_in_bytes - 1)));
931 (status->host_index & (status->size_in_bytes - 1)),
932 p_app_data, l_first_write);
933 /* remaining data if any */
934 memcpy(p_bbm_data, p_app_data + l_first_write,
935 phm->u.d.u.data.data_size - l_first_write);
939 * This version relies on the DSP code triggering an OStream buffer
940 * update immediately following a SET_FORMAT call. The host has
941 * already written data into the BBM buffer, but the DSP won't know
942 * about it until dwHostIndex is adjusted.
944 if (phw->flag_outstream_just_reset[phm->obj_index]) {
945 /* Format can only change after reset. Must tell DSP. */
946 u16 function = phm->function;
947 phw->flag_outstream_just_reset[phm->obj_index] = 0;
948 phm->function = HPI_OSTREAM_SET_FORMAT;
949 hw_message(pao, phm, phr); /* send the format to the DSP */
950 phm->function = function;
955 status->host_index += phm->u.d.u.data.data_size;
958 static void outstream_get_info(struct hpi_adapter_obj *pao,
959 struct hpi_message *phm, struct hpi_response *phr)
961 struct hpi_hw_obj *phw = pao->priv;
962 struct bus_master_interface *interface = phw->p_interface_buffer;
963 struct hpi_hostbuffer_status *status;
965 if (!phw->outstream_host_buffer_size[phm->obj_index]) {
966 hw_message(pao, phm, phr);
970 hpi_init_response(phr, phm->object, phm->function, 0);
972 status = &interface->outstream_host_buffer_status[phm->obj_index];
974 phr->u.d.u.stream_info.state = (u16)status->stream_state;
975 phr->u.d.u.stream_info.samples_transferred =
976 status->samples_processed;
977 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
978 phr->u.d.u.stream_info.data_available =
979 status->size_in_bytes - outstream_get_space_available(status);
980 phr->u.d.u.stream_info.auxiliary_data_available =
981 status->auxiliary_data_available;
984 static void outstream_start(struct hpi_adapter_obj *pao,
985 struct hpi_message *phm, struct hpi_response *phr)
987 hw_message(pao, phm, phr);
990 static void outstream_reset(struct hpi_adapter_obj *pao,
991 struct hpi_message *phm, struct hpi_response *phr)
993 struct hpi_hw_obj *phw = pao->priv;
994 phw->flag_outstream_just_reset[phm->obj_index] = 1;
995 hw_message(pao, phm, phr);
998 static void outstream_open(struct hpi_adapter_obj *pao,
999 struct hpi_message *phm, struct hpi_response *phr)
1001 outstream_reset(pao, phm, phr);
1004 /*****************************************************************************/
1005 /* InStream Host buffer functions */
1007 static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
1008 struct hpi_message *phm, struct hpi_response *phr)
1011 u32 command = phm->u.d.u.buffer.command;
1012 struct hpi_hw_obj *phw = pao->priv;
1013 struct bus_master_interface *interface = phw->p_interface_buffer;
1015 hpi_init_response(phr, phm->object, phm->function, 0);
1017 if (command == HPI_BUFFER_CMD_EXTERNAL
1018 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
1020 phm->u.d.u.buffer.buffer_size =
1021 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
1022 phr->u.d.u.stream_info.data_available =
1023 phw->instream_host_buffer_size[phm->obj_index];
1024 phr->u.d.u.stream_info.buffer_size =
1025 phm->u.d.u.buffer.buffer_size;
1027 if (phw->instream_host_buffer_size[phm->obj_index] ==
1028 phm->u.d.u.buffer.buffer_size) {
1029 /* Same size, no action required */
1033 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1035 hpios_locked_mem_free(&phw->instream_host_buffers
1038 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm->
1039 obj_index], phm->u.d.u.buffer.buffer_size,
1043 phr->error = HPI_ERROR_INVALID_DATASIZE;
1044 phw->instream_host_buffer_size[phm->obj_index] = 0;
1048 err = hpios_locked_mem_get_phys_addr
1049 (&phw->instream_host_buffers[phm->obj_index],
1050 &phm->u.d.u.buffer.pci_address);
1051 /* get the phys addr into msg for single call alloc. Caller
1052 needs to do this for split alloc so return the phy address */
1053 phr->u.d.u.stream_info.auxiliary_data_available =
1054 phm->u.d.u.buffer.pci_address;
1056 hpios_locked_mem_free(&phw->instream_host_buffers
1058 phw->instream_host_buffer_size[phm->obj_index] = 0;
1059 phr->error = HPI_ERROR_MEMORY_ALLOC;
1064 if (command == HPI_BUFFER_CMD_EXTERNAL
1065 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
1066 struct hpi_hostbuffer_status *status;
1068 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
1070 HPI_DEBUG_LOG(ERROR,
1071 "Buffer size must be 2^N not %d\n",
1072 phm->u.d.u.buffer.buffer_size);
1073 phr->error = HPI_ERROR_INVALID_DATASIZE;
1077 phw->instream_host_buffer_size[phm->obj_index] =
1078 phm->u.d.u.buffer.buffer_size;
1079 status = &interface->instream_host_buffer_status[phm->
1081 status->samples_processed = 0;
1082 status->stream_state = HPI_STATE_STOPPED;
1083 status->dSP_index = 0;
1084 status->host_index = status->dSP_index;
1085 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
1086 status->auxiliary_data_available = 0;
1088 hw_message(pao, phm, phr);
1091 && hpios_locked_mem_valid(&phw->
1092 instream_host_buffers[phm->obj_index])) {
1093 hpios_locked_mem_free(&phw->instream_host_buffers
1095 phw->instream_host_buffer_size[phm->obj_index] = 0;
1100 static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
1101 struct hpi_message *phm, struct hpi_response *phr)
1103 struct hpi_hw_obj *phw = pao->priv;
1104 struct bus_master_interface *interface = phw->p_interface_buffer;
1105 struct hpi_hostbuffer_status *status;
1108 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1110 if (hpios_locked_mem_get_virt_addr(&phw->
1111 instream_host_buffers[phm->obj_index],
1112 (void *)&p_bbm_data)) {
1113 phr->error = HPI_ERROR_INVALID_OPERATION;
1116 status = &interface->instream_host_buffer_status[phm->
1118 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1119 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0);
1120 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
1121 phr->u.d.u.hostbuffer_info.p_status = status;
1123 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1124 HPI_ISTREAM_HOSTBUFFER_GET_INFO,
1125 HPI_ERROR_INVALID_OPERATION);
1129 static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
1130 struct hpi_message *phm, struct hpi_response *phr)
1132 struct hpi_hw_obj *phw = pao->priv;
1133 u32 command = phm->u.d.u.buffer.command;
1135 if (phw->instream_host_buffer_size[phm->obj_index]) {
1136 if (command == HPI_BUFFER_CMD_EXTERNAL
1137 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
1138 phw->instream_host_buffer_size[phm->obj_index] = 0;
1139 hw_message(pao, phm, phr);
1142 if (command == HPI_BUFFER_CMD_EXTERNAL
1143 || command == HPI_BUFFER_CMD_INTERNAL_FREE)
1144 hpios_locked_mem_free(&phw->instream_host_buffers
1148 /* Should HPI_ERROR_INVALID_OPERATION be returned
1149 if no host buffer is allocated? */
1150 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1151 HPI_ISTREAM_HOSTBUFFER_FREE, 0);
1157 static void instream_start(struct hpi_adapter_obj *pao,
1158 struct hpi_message *phm, struct hpi_response *phr)
1160 hw_message(pao, phm, phr);
1163 static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status)
1165 return status->dSP_index - status->host_index;
1168 static void instream_read(struct hpi_adapter_obj *pao,
1169 struct hpi_message *phm, struct hpi_response *phr)
1171 struct hpi_hw_obj *phw = pao->priv;
1172 struct bus_master_interface *interface = phw->p_interface_buffer;
1173 struct hpi_hostbuffer_status *status;
1177 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
1179 if (!phw->instream_host_buffer_size[phm->obj_index]) {
1180 hw_message(pao, phm, phr);
1183 hpi_init_response(phr, phm->object, phm->function, 0);
1185 status = &interface->instream_host_buffer_status[phm->obj_index];
1186 data_available = instream_get_bytes_available(status);
1187 if (data_available < phm->u.d.u.data.data_size) {
1188 phr->error = HPI_ERROR_INVALID_DATASIZE;
1192 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1194 if (hpios_locked_mem_get_virt_addr(&phw->
1195 instream_host_buffers[phm->obj_index],
1196 (void *)&p_bbm_data)) {
1197 phr->error = HPI_ERROR_INVALID_OPERATION;
1202 or enough to fit from current to end of BBM buffer */
1204 min(phm->u.d.u.data.data_size,
1205 status->size_in_bytes -
1206 (status->host_index & (status->size_in_bytes - 1)));
1210 (status->host_index & (status->size_in_bytes - 1)),
1212 /* remaining data if any */
1213 memcpy(p_app_data + l_first_read, p_bbm_data,
1214 phm->u.d.u.data.data_size - l_first_read);
1216 status->host_index += phm->u.d.u.data.data_size;
1219 static void instream_get_info(struct hpi_adapter_obj *pao,
1220 struct hpi_message *phm, struct hpi_response *phr)
1222 struct hpi_hw_obj *phw = pao->priv;
1223 struct bus_master_interface *interface = phw->p_interface_buffer;
1224 struct hpi_hostbuffer_status *status;
1225 if (!phw->instream_host_buffer_size[phm->obj_index]) {
1226 hw_message(pao, phm, phr);
1230 status = &interface->instream_host_buffer_status[phm->obj_index];
1232 hpi_init_response(phr, phm->object, phm->function, 0);
1234 phr->u.d.u.stream_info.state = (u16)status->stream_state;
1235 phr->u.d.u.stream_info.samples_transferred =
1236 status->samples_processed;
1237 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
1238 phr->u.d.u.stream_info.data_available =
1239 instream_get_bytes_available(status);
1240 phr->u.d.u.stream_info.auxiliary_data_available =
1241 status->auxiliary_data_available;
1244 /*****************************************************************************/
1246 #define HPI6205_MAX_FILES_TO_LOAD 2
1248 static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
1249 u32 *pos_error_code)
1251 struct hpi_hw_obj *phw = pao->priv;
1252 struct dsp_code dsp_code;
1253 u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD];
1258 boot_code_id[0] = HPI_ADAPTER_ASI(0x6205);
1260 boot_code_id[1] = pao->pci.pci_dev->subsystem_device;
1261 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(boot_code_id[1]);
1263 /* fix up cases where bootcode id[1] != subsys id */
1264 switch (boot_code_id[1]) {
1265 case HPI_ADAPTER_FAMILY_ASI(0x5000):
1266 boot_code_id[0] = boot_code_id[1];
1267 boot_code_id[1] = 0;
1269 case HPI_ADAPTER_FAMILY_ASI(0x5300):
1270 case HPI_ADAPTER_FAMILY_ASI(0x5400):
1271 case HPI_ADAPTER_FAMILY_ASI(0x6300):
1272 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400);
1274 case HPI_ADAPTER_FAMILY_ASI(0x5500):
1275 case HPI_ADAPTER_FAMILY_ASI(0x5600):
1276 case HPI_ADAPTER_FAMILY_ASI(0x6500):
1277 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600);
1279 case HPI_ADAPTER_FAMILY_ASI(0x8800):
1280 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900);
1286 /* reset DSP by writing a 1 to the WARMRESET bit */
1287 temp = C6205_HDCR_WARMRESET;
1288 iowrite32(temp, phw->prHDCR);
1289 hpios_delay_micro_seconds(1000);
1291 /* check that PCI i/f was configured by EEPROM */
1292 temp = ioread32(phw->prHSR);
1293 if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) !=
1295 return HPI6205_ERROR_6205_EEPROM;
1297 /* disable PINTA interrupt */
1298 iowrite32(temp, phw->prHSR);
1300 /* check control register reports PCI boot mode */
1301 temp = ioread32(phw->prHDCR);
1302 if (!(temp & C6205_HDCR_PCIBOOT))
1303 return HPI6205_ERROR_6205_REG;
1305 /* try writing a few numbers to the DSP page register */
1306 /* and reading them back. */
1308 iowrite32(temp, phw->prDSPP);
1309 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1310 return HPI6205_ERROR_6205_DSPPAGE;
1312 iowrite32(temp, phw->prDSPP);
1313 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1314 return HPI6205_ERROR_6205_DSPPAGE;
1316 iowrite32(temp, phw->prDSPP);
1317 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1318 return HPI6205_ERROR_6205_DSPPAGE;
1319 /* reset DSP page to the correct number */
1321 iowrite32(temp, phw->prDSPP);
1322 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1323 return HPI6205_ERROR_6205_DSPPAGE;
1326 /* release 6713 from reset before 6205 is bootloaded.
1327 This ensures that the EMIF is inactive,
1328 and the 6713 HPI gets the correct bootmode etc
1330 if (boot_code_id[1] != 0) {
1331 /* DSP 1 is a C6713 */
1332 /* CLKX0 <- '1' release the C6205 bootmode pulldowns */
1333 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002202);
1334 hpios_delay_micro_seconds(100);
1335 /* Reset the 6713 #1 - revB */
1336 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
1338 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1339 boot_loader_read_mem32(pao, 0, 0);
1341 hpios_delay_micro_seconds(100);
1342 /* Release C6713 from reset - revB */
1343 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4);
1344 hpios_delay_micro_seconds(100);
1347 for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) {
1348 /* is there a DSP to load? */
1349 if (boot_code_id[dsp] == 0)
1352 err = boot_loader_config_emif(pao, dsp);
1356 err = boot_loader_test_internal_memory(pao, dsp);
1360 err = boot_loader_test_external_memory(pao, dsp);
1364 err = boot_loader_test_pld(pao, dsp);
1368 /* write the DSP code down into the DSPs memory */
1369 err = hpi_dsp_code_open(boot_code_id[dsp], pao->pci.pci_dev,
1370 &dsp_code, pos_error_code);
1380 err = hpi_dsp_code_read_word(&dsp_code, &length);
1383 if (length == 0xFFFFFFFF)
1384 break; /* end of code */
1386 err = hpi_dsp_code_read_word(&dsp_code, &address);
1389 err = hpi_dsp_code_read_word(&dsp_code, &type);
1392 err = hpi_dsp_code_read_block(length, &dsp_code,
1396 for (i = 0; i < (int)length; i++) {
1397 boot_loader_write_mem32(pao, dsp, address,
1399 /* dummy read every 4 words */
1400 /* for 6205 advisory 1.4.4 */
1402 boot_loader_read_mem32(pao, dsp,
1410 hpi_dsp_code_close(&dsp_code);
1415 hpi_dsp_code_rewind(&dsp_code);
1423 hpi_dsp_code_read_word(&dsp_code, &length);
1424 if (length == 0xFFFFFFFF)
1425 break; /* end of code */
1427 hpi_dsp_code_read_word(&dsp_code, &address);
1428 hpi_dsp_code_read_word(&dsp_code, &type);
1429 hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1431 for (i = 0; i < (int)length; i++) {
1432 data = boot_loader_read_mem32(pao, dsp,
1434 if (data != *pcode) {
1444 hpi_dsp_code_close(&dsp_code);
1449 /* After bootloading all DSPs, start DSP0 running
1450 * The DSP0 code will handle starting and synchronizing with its slaves
1452 if (phw->p_interface_buffer) {
1453 /* we need to tell the card the physical PCI address */
1454 u32 physicalPC_iaddress;
1455 struct bus_master_interface *interface =
1456 phw->p_interface_buffer;
1457 u32 host_mailbox_address_on_dsp;
1458 u32 physicalPC_iaddress_verify = 0;
1460 /* set ack so we know when DSP is ready to go */
1461 /* (dwDspAck will be changed to HIF_RESET) */
1462 interface->dsp_ack = H620_HIF_UNKNOWN;
1463 wmb(); /* ensure ack is written before dsp writes back */
1465 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem,
1466 &physicalPC_iaddress);
1468 /* locate the host mailbox on the DSP. */
1469 host_mailbox_address_on_dsp = 0x80000000;
1470 while ((physicalPC_iaddress != physicalPC_iaddress_verify)
1472 boot_loader_write_mem32(pao, 0,
1473 host_mailbox_address_on_dsp,
1474 physicalPC_iaddress);
1475 physicalPC_iaddress_verify =
1476 boot_loader_read_mem32(pao, 0,
1477 host_mailbox_address_on_dsp);
1480 HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n");
1481 /* enable interrupts */
1482 temp = ioread32(phw->prHSR);
1483 temp &= ~(u32)C6205_HSR_INTAM;
1484 iowrite32(temp, phw->prHSR);
1486 /* start code running... */
1487 temp = ioread32(phw->prHDCR);
1488 temp |= (u32)C6205_HDCR_DSPINT;
1489 iowrite32(temp, phw->prHDCR);
1491 /* give the DSP 10ms to start up */
1492 hpios_delay_micro_seconds(10000);
1497 /*****************************************************************************/
1498 /* Bootloader utility functions */
1500 static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
1503 struct hpi_hw_obj *phw = pao->priv;
1505 __iomem u32 *p_data;
1507 if (dsp_index == 0) {
1508 /* DSP 0 is always C6205 */
1509 if ((address >= 0x01800000) & (address < 0x02000000)) {
1510 /* BAR1 register access */
1511 p_data = pao->pci.ap_mem_base[1] +
1512 (address & 0x007fffff) /
1513 sizeof(*pao->pci.ap_mem_base[1]);
1514 /* HPI_DEBUG_LOG(WARNING,
1515 "BAR1 access %08x\n", dwAddress); */
1517 u32 dw4M_page = address >> 22L;
1518 if (dw4M_page != phw->dsp_page) {
1519 phw->dsp_page = dw4M_page;
1521 iowrite32(phw->dsp_page, phw->prDSPP);
1524 address &= 0x3fffff; /* address within 4M page */
1525 /* BAR0 memory access */
1526 p_data = pao->pci.ap_mem_base[0] +
1527 address / sizeof(u32);
1529 data = ioread32(p_data);
1530 } else if (dsp_index == 1) {
1531 /* DSP 1 is a C6713 */
1533 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1534 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1535 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR);
1536 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR);
1537 data = (data << 16) | (lsb & 0xFFFF);
1542 static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
1543 int dsp_index, u32 address, u32 data)
1545 struct hpi_hw_obj *phw = pao->priv;
1546 __iomem u32 *p_data;
1547 /* u32 dwVerifyData=0; */
1549 if (dsp_index == 0) {
1550 /* DSP 0 is always C6205 */
1551 if ((address >= 0x01800000) & (address < 0x02000000)) {
1552 /* BAR1 - DSP register access using */
1553 /* Non-prefetchable PCI access */
1554 p_data = pao->pci.ap_mem_base[1] +
1555 (address & 0x007fffff) /
1556 sizeof(*pao->pci.ap_mem_base[1]);
1558 /* BAR0 access - all of DSP memory using */
1559 /* pre-fetchable PCI access */
1560 u32 dw4M_page = address >> 22L;
1561 if (dw4M_page != phw->dsp_page) {
1562 phw->dsp_page = dw4M_page;
1564 iowrite32(phw->dsp_page, phw->prDSPP);
1567 address &= 0x3fffff; /* address within 4M page */
1568 p_data = pao->pci.ap_mem_base[0] +
1569 address / sizeof(u32);
1571 iowrite32(data, p_data);
1572 } else if (dsp_index == 1) {
1573 /* DSP 1 is a C6713 */
1574 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1575 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1577 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1578 boot_loader_read_mem32(pao, 0, 0);
1580 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data);
1581 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16);
1583 /* dummy read every 4 words for 6205 advisory 1.4.4 */
1584 boot_loader_read_mem32(pao, 0, 0);
1588 static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index)
1590 if (dsp_index == 0) {
1593 /* DSP 0 is always C6205 */
1596 /* memory map of C6205 */
1597 /* 00000000-0000FFFF 16Kx32 internal program */
1598 /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */
1602 /* Global EMIF control */
1603 boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779);
1612 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */
1613 setting = 0x00000030;
1614 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting);
1615 if (setting != boot_loader_read_mem32(pao, dsp_index,
1617 return HPI6205_ERROR_DSP_EMIF;
1619 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */
1620 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1621 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */
1622 /* WST should be 71, but 63 is max possible */
1624 (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) |
1625 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1627 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting);
1628 if (setting != boot_loader_read_mem32(pao, dsp_index,
1630 return HPI6205_ERROR_DSP_EMIF;
1632 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */
1633 /* which occupies D15..0. 6713 starts at 27MHz, so need */
1634 /* plenty of wait states */
1636 (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) |
1637 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1639 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting);
1640 if (setting != boot_loader_read_mem32(pao, dsp_index,
1642 return HPI6205_ERROR_DSP_EMIF;
1644 /* EMIF CE3 setup - 32 bit async. */
1645 /* This is the PLD on the ASI5000 cards only */
1647 (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) |
1648 (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) |
1650 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting);
1651 if (setting != boot_loader_read_mem32(pao, dsp_index,
1653 return HPI6205_ERROR_DSP_EMIF;
1655 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */
1656 /* need to use this else DSP code crashes? */
1657 boot_loader_write_mem32(pao, dsp_index, 0x01800018,
1660 /* EMIF SDRAM Refresh Timing */
1661 /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */
1662 boot_loader_write_mem32(pao, dsp_index, 0x0180001C,
1665 } else if (dsp_index == 1) {
1666 /* test access to the C6713s HPI registers */
1667 u32 write_data = 0, read_data = 0, i = 0;
1669 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */
1671 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data);
1672 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data);
1673 /* C67 HPI is on lower 16bits of 32bit EMIF */
1675 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR);
1676 if (write_data != read_data) {
1677 HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data,
1679 return HPI6205_ERROR_C6713_HPIC;
1681 /* HPIA - walking ones test */
1683 for (i = 0; i < 32; i++) {
1684 boot_loader_write_mem32(pao, 0, HPIAL_ADDR,
1686 boot_loader_write_mem32(pao, 0, HPIAH_ADDR,
1687 (write_data >> 16));
1689 0xFFFF & boot_loader_read_mem32(pao, 0,
1692 read_data | ((0xFFFF &
1693 boot_loader_read_mem32(pao, 0,
1696 if (read_data != write_data) {
1697 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n",
1698 write_data, read_data);
1699 return HPI6205_ERROR_C6713_HPIA;
1701 write_data = write_data << 1;
1705 * ** C6713 datasheet says we cannot program PLL from HPI,
1706 * and indeed if we try to set the PLL multiply from the HPI,
1707 * the PLL does not seem to lock, so we enable the PLL and
1708 * use the default multiply of x 7, which for a 27MHz clock
1709 * gives a DSP speed of 189MHz
1712 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000);
1713 hpios_delay_micro_seconds(1000);
1714 /* EMIF = 189/3=63MHz */
1715 boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002);
1717 boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001);
1719 boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000);
1720 hpios_delay_micro_seconds(1000);
1721 /* ** SGT test to take GPO3 high when we start the PLL */
1722 /* and low when the delay is completed */
1723 /* FSX0 <- '1' (GPO3) */
1724 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A);
1725 /* PLL not bypassed */
1726 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001);
1727 hpios_delay_micro_seconds(1000);
1728 /* FSX0 <- '0' (GPO3) */
1729 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02);
1731 /* 6205 EMIF CE1 resetup - 32 bit async. */
1732 /* Now 6713 #1 is running at 189MHz can reduce waitstates */
1733 boot_loader_write_mem32(pao, 0, 0x01800004, /* CE1 */
1734 (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) |
1735 (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) |
1738 hpios_delay_micro_seconds(1000);
1740 /* check that we can read one of the PLL registers */
1741 /* PLL should not be bypassed! */
1742 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF)
1744 return HPI6205_ERROR_C6713_PLL;
1746 /* setup C67x EMIF (note this is the only use of
1747 BAR1 via BootLoader_WriteMem32) */
1748 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL,
1751 /* EMIF CE0 setup - 2Mx32 Sync DRAM
1758 7..4 MTYPE 0011 Sync DRAM 32bits
1762 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0,
1765 /* EMIF SDRAM Extension
1767 31-21 0000b 0000b 000b
1768 20 WR2RD = 2cycles-1 = 1b
1770 19-18 WR2DEAC = 3cycle-1 = 10b
1771 17 WR2WR = 2cycle-1 = 1b
1772 16-15 R2WDQM = 4cycle-1 = 11b
1773 14-12 RD2WR = 6cycles-1 = 101b
1775 11-10 RD2DEAC = 4cycle-1 = 11b
1776 9 RD2RD = 2cycle-1 = 1b
1777 8-7 THZP = 3cycle-1 = 10b
1778 6-5 TWR = 2cycle-1 = 01b (tWR = 17ns)
1779 4 TRRD = 2cycle = 0b (tRRD = 14ns)
1780 3-1 TRAS = 5cycle-1 = 100b (Tras=42ns)
1781 1 CAS latency = 3cyc = 1b
1782 (for Micron 2M32-7 operating at 100MHz)
1784 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT,
1787 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
1790 29..28 SDRSZ 00b 11 row address pins
1792 27..26 SDCSZ 01b 8 column address pins
1793 25 RFEN 1b refersh enabled
1794 24 INIT 1b init SDRAM!
1796 23..20 TRCD 0001b (Trcd/Tcyc)-1 = (20/10)-1 = 1
1798 19..16 TRP 0001b (Trp/Tcyc)-1 = (20/10)-1 = 1
1800 15..12 TRC 0110b (Trc/Tcyc)-1 = (70/10)-1 = 6
1802 11..0 - 0000b 0000b 0000b
1804 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL,
1807 /* SDRAM refresh timing
1808 Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A
1810 boot_loader_write_mem32(pao, dsp_index,
1811 C6713_EMIF_SDRAMTIMING, 0x00000410);
1813 hpios_delay_micro_seconds(1000);
1814 } else if (dsp_index == 2) {
1815 /* DSP 2 is a C6713 */
1821 static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
1822 u32 start_address, u32 length)
1826 u32 test_data = 0, data = 0;
1830 /* for 1st word, test each bit in the 32bit word, */
1831 /* dwLength specifies number of 32bit words to test */
1832 /*for(i=0; i<dwLength; i++) */
1835 test_addr = start_address + i * 4;
1836 test_data = 0x00000001;
1837 for (j = 0; j < 32; j++) {
1838 boot_loader_write_mem32(pao, dsp_index, test_addr,
1840 data = boot_loader_read_mem32(pao, dsp_index,
1842 if (data != test_data) {
1843 HPI_DEBUG_LOG(VERBOSE,
1844 "Memtest error details "
1845 "%08x %08x %08x %i\n", test_addr,
1846 test_data, data, dsp_index);
1847 return 1; /* error */
1849 test_data = test_data << 1;
1853 /* for the next 100 locations test each location, leaving it as zero */
1854 /* write a zero to the next word in memory before we read */
1855 /* the previous write to make sure every memory location is unique */
1856 for (i = 0; i < 100; i++) {
1857 test_addr = start_address + i * 4;
1858 test_data = 0xA5A55A5A;
1859 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data);
1860 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0);
1861 data = boot_loader_read_mem32(pao, dsp_index, test_addr);
1862 if (data != test_data) {
1863 HPI_DEBUG_LOG(VERBOSE,
1864 "Memtest error details "
1865 "%08x %08x %08x %i\n", test_addr, test_data,
1867 return 1; /* error */
1869 /* leave location as zero */
1870 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1873 /* zero out entire memory block */
1874 for (i = 0; i < length; i++) {
1875 test_addr = start_address + i * 4;
1876 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1881 static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
1885 if (dsp_index == 0) {
1886 /* DSP 0 is a C6205 */
1888 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1892 err = boot_loader_test_memory(pao, dsp_index,
1893 0x80000000, 0x10000);
1894 } else if (dsp_index == 1) {
1895 /* DSP 1 is a C6713 */
1896 /* 192K internal mem */
1897 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1900 /* 64K internal mem / L2 cache */
1901 err = boot_loader_test_memory(pao, dsp_index,
1902 0x00030000, 0x10000);
1906 return HPI6205_ERROR_DSP_INTMEM;
1911 static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
1914 u32 dRAM_start_address = 0;
1917 if (dsp_index == 0) {
1918 /* only test for SDRAM if an ASI5000 card */
1919 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
1920 /* DSP 0 is always C6205 */
1921 dRAM_start_address = 0x00400000;
1922 dRAM_size = 0x200000;
1923 /*dwDRAMinc=1024; */
1926 } else if (dsp_index == 1) {
1927 /* DSP 1 is a C6713 */
1928 dRAM_start_address = 0x80000000;
1929 dRAM_size = 0x200000;
1930 /*dwDRAMinc=1024; */
1933 if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address,
1935 return HPI6205_ERROR_DSP_EXTMEM;
1939 static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index)
1942 if (dsp_index == 0) {
1943 /* only test for DSP0 PLD on ASI5000 card */
1944 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
1945 /* PLD is located at CE3=0x03000000 */
1946 data = boot_loader_read_mem32(pao, dsp_index,
1948 if ((data & 0xF) != 0x5)
1949 return HPI6205_ERROR_DSP_PLD;
1950 data = boot_loader_read_mem32(pao, dsp_index,
1952 if ((data & 0xF) != 0xA)
1953 return HPI6205_ERROR_DSP_PLD;
1955 } else if (dsp_index == 1) {
1956 /* DSP 1 is a C6713 */
1957 if (pao->pci.pci_dev->subsystem_device == 0x8700) {
1958 /* PLD is located at CE1=0x90000000 */
1959 data = boot_loader_read_mem32(pao, dsp_index,
1961 if ((data & 0xFF) != 0xAA)
1962 return HPI6205_ERROR_DSP_PLD;
1964 boot_loader_write_mem32(pao, dsp_index, 0x90000000,
1971 /** Transfer data to or from DSP
1972 nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA
1974 static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data,
1975 u32 data_size, int operation)
1977 struct hpi_hw_obj *phw = pao->priv;
1978 u32 data_transferred = 0;
1981 struct bus_master_interface *interface = phw->p_interface_buffer;
1984 return HPI_ERROR_INVALID_DATA_POINTER;
1986 data_size &= ~3L; /* round data_size down to nearest 4 bytes */
1988 /* make sure state is IDLE */
1989 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT))
1990 return HPI_ERROR_DSP_HARDWARE;
1992 while (data_transferred < data_size) {
1993 u32 this_copy = data_size - data_transferred;
1995 if (this_copy > HPI6205_SIZEOF_DATA)
1996 this_copy = HPI6205_SIZEOF_DATA;
1998 if (operation == H620_HIF_SEND_DATA)
1999 memcpy((void *)&interface->u.b_data[0],
2000 &p_data[data_transferred], this_copy);
2002 interface->transfer_size_in_bytes = this_copy;
2004 /* DSP must change this back to nOperation */
2005 interface->dsp_ack = H620_HIF_IDLE;
2006 send_dsp_command(phw, operation);
2008 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT);
2009 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2010 HPI6205_TIMEOUT - temp2, this_copy);
2014 HPI_DEBUG_LOG(ERROR,
2015 "Timed out waiting for " "state %d got %d\n",
2016 operation, interface->dsp_ack);
2020 if (operation == H620_HIF_GET_DATA)
2021 memcpy(&p_data[data_transferred],
2022 (void *)&interface->u.b_data[0], this_copy);
2024 data_transferred += this_copy;
2026 if (interface->dsp_ack != operation)
2027 HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n",
2028 interface->dsp_ack, operation);
2029 /* err=HPI_ERROR_DSP_HARDWARE; */
2031 send_dsp_command(phw, H620_HIF_IDLE);
2036 /* wait for up to timeout_us microseconds for the DSP
2037 to signal state by DMA into dwDspAck
2039 static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us)
2041 struct bus_master_interface *interface = phw->p_interface_buffer;
2042 int t = timeout_us / 4;
2044 rmb(); /* ensure interface->dsp_ack is up to date */
2045 while ((interface->dsp_ack != state) && --t) {
2046 hpios_delay_micro_seconds(4);
2047 rmb(); /* DSP changes dsp_ack by DMA */
2050 /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */
2054 /* set the busmaster interface to cmd, then interrupt the DSP */
2055 static void send_dsp_command(struct hpi_hw_obj *phw, int cmd)
2057 struct bus_master_interface *interface = phw->p_interface_buffer;
2060 interface->host_cmd = cmd;
2061 wmb(); /* DSP gets state by DMA, make sure it is written to memory */
2062 /* before we interrupt the DSP */
2063 r = ioread32(phw->prHDCR);
2064 r |= (u32)C6205_HDCR_DSPINT;
2065 iowrite32(r, phw->prHDCR);
2066 r &= ~(u32)C6205_HDCR_DSPINT;
2067 iowrite32(r, phw->prHDCR);
2070 static unsigned int message_count;
2072 static u16 message_response_sequence(struct hpi_adapter_obj *pao,
2073 struct hpi_message *phm, struct hpi_response *phr)
2075 u32 time_out, time_out2;
2076 struct hpi_hw_obj *phw = pao->priv;
2077 struct bus_master_interface *interface = phw->p_interface_buffer;
2081 if (phm->size > sizeof(interface->u.message_buffer)) {
2082 phr->error = HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL;
2083 phr->specific_error = sizeof(interface->u.message_buffer);
2084 phr->size = sizeof(struct hpi_response_header);
2085 HPI_DEBUG_LOG(ERROR,
2086 "message len %d too big for buffer %zd \n", phm->size,
2087 sizeof(interface->u.message_buffer));
2091 /* Assume buffer of type struct bus_master_interface
2092 is allocated "noncacheable" */
2094 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2095 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n");
2096 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
2099 memcpy(&interface->u.message_buffer, phm, phm->size);
2100 /* signal we want a response */
2101 send_dsp_command(phw, H620_HIF_GET_RESP);
2103 time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT);
2106 HPI_DEBUG_LOG(ERROR,
2107 "(%u) Timed out waiting for " "GET_RESP state [%x]\n",
2108 message_count, interface->dsp_ack);
2110 HPI_DEBUG_LOG(VERBOSE,
2111 "(%u) transition to GET_RESP after %u\n",
2112 message_count, HPI6205_TIMEOUT - time_out2);
2114 /* spin waiting on HIF interrupt flag (end of msg process) */
2115 time_out = HPI6205_TIMEOUT;
2117 /* read the result */
2119 if (interface->u.response_buffer.response.size <= phr->size)
2120 memcpy(phr, &interface->u.response_buffer,
2121 interface->u.response_buffer.response.size);
2123 HPI_DEBUG_LOG(ERROR,
2124 "response len %d too big for buffer %d\n",
2125 interface->u.response_buffer.response.size,
2127 memcpy(phr, &interface->u.response_buffer,
2128 sizeof(struct hpi_response_header));
2129 phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL;
2130 phr->specific_error =
2131 interface->u.response_buffer.response.size;
2132 phr->size = sizeof(struct hpi_response_header);
2135 /* set interface back to idle */
2136 send_dsp_command(phw, H620_HIF_IDLE);
2138 if (!time_out || !time_out2) {
2139 HPI_DEBUG_LOG(DEBUG, "something timed out!\n");
2140 return HPI6205_ERROR_MSG_RESP_TIMEOUT;
2142 /* special case for adapter close - */
2143 /* wait for the DSP to indicate it is idle */
2144 if (phm->function == HPI_ADAPTER_CLOSE) {
2145 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2146 HPI_DEBUG_LOG(DEBUG,
2147 "Timeout waiting for idle "
2148 "(on adapter_close)\n");
2149 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
2152 err = hpi_validate_response(phm, phr);
2156 static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
2157 struct hpi_response *phr)
2162 hpios_dsplock_lock(pao);
2164 err = message_response_sequence(pao, phm, phr);
2166 /* maybe an error response */
2168 /* something failed in the HPI/DSP interface */
2169 if (err >= HPI_ERROR_BACKEND_BASE) {
2170 phr->error = HPI_ERROR_DSP_COMMUNICATION;
2171 phr->specific_error = err;
2178 /* just the header of the response is valid */
2179 phr->size = sizeof(struct hpi_response_header);
2182 pao->dsp_crashed = 0;
2184 if (phr->error != 0) /* something failed in the DSP */
2187 switch (phm->function) {
2188 case HPI_OSTREAM_WRITE:
2189 case HPI_ISTREAM_ANC_WRITE:
2190 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2191 phm->u.d.u.data.data_size, H620_HIF_SEND_DATA);
2194 case HPI_ISTREAM_READ:
2195 case HPI_OSTREAM_ANC_READ:
2196 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2197 phm->u.d.u.data.data_size, H620_HIF_GET_DATA);
2204 hpios_dsplock_unlock(pao);