2 * azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
3 * Copyright (C) 2002, 2005 - 2010 by Andreas Mohr <andi AT lisas.de>
5 * Framework borrowed from Bart Hartgers's als4000.c.
6 * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
7 * found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
9 * PCI168 A(W), sub ID 1800
10 * PCI168 A/AP, sub ID 8000
11 * Please give me feedback in case you try my driver with one of these!!
13 * Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download
14 * (XP/Vista do not support this card at all but every Linux distribution
15 * has very good support out of the box;
16 * just to make sure that the right people hit this and get to know that,
17 * despite the high level of Internet ignorance - as usual :-P -
18 * about very good support for this card - on Linux!)
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation; either version 2 of the License, or
24 * (at your option) any later version.
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
36 * Since Aztech does not provide any chipset documentation,
37 * even on repeated request to various addresses,
38 * and the answer that was finally given was negative
39 * (and I was stupid enough to manage to get hold of a PCI168 soundcard
40 * in the first place >:-P}),
41 * I was forced to base this driver on reverse engineering
42 * (3 weeks' worth of evenings filled with driver work).
43 * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros)
45 * It is quite likely that the AZF3328 chip is the PCI cousin of the
46 * AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs.
48 * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
49 * for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec,
50 * Fincitec acquired by National Semiconductor in 2002, together with the
51 * Fincitec-related company ARSmikro) has the following features:
53 * - compatibility & compliance:
54 * - Microsoft PC 97 ("PC 97 Hardware Design Guide",
55 * http://www.microsoft.com/whdc/archive/pcguides.mspx)
56 * - Microsoft PC 98 Baseline Audio
58 * - Sound Blaster Emulation (DOS Box)
59 * - builtin AC97 conformant codec (SNR over 80dB)
60 * Note that "conformant" != "compliant"!! this chip's mixer register layout
61 * *differs* from the standard AC97 layout:
62 * they chose to not implement the headphone register (which is not a
63 * problem since it's merely optional), yet when doing this, they committed
64 * the grave sin of letting other registers follow immediately instead of
65 * keeping a headphone dummy register, thereby shifting the mixer register
66 * addresses illegally. So far unfortunately it looks like the very flexible
67 * ALSA AC97 support is still not enough to easily compensate for such a
68 * grave layout violation despite all tweaks and quirks mechanisms it offers.
69 * - builtin genuine OPL3 - verified to work fine, 20080506
70 * - full duplex 16bit playback/record at independent sampling rate
71 * - MPU401 (+ legacy address support, claimed by one official spec sheet)
72 * FIXME: how to enable legacy addr??
73 * - game port (legacy address support)
74 * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven
75 * features supported). - See common term "Digital Enhanced Game Port"...
76 * (probably DirectInput 3.0 spec - confirm)
77 * - builtin 3D enhancement (said to be YAMAHA Ymersion)
78 * - built-in General DirectX timer having a 20 bits counter
79 * with 1us resolution (see below!)
80 * - I2S serial output port for external DAC
81 * [FIXME: 3.3V or 5V level? maximum rate is 66.2kHz right?]
82 * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
83 * - supports hardware volume control
84 * - single chip low cost solution (128 pin QFP)
85 * - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip]
86 * required for Microsoft's logo compliance (FIXME: where?)
87 * At least the Trident 4D Wave DX has one bit somewhere
88 * to enable writes to PCI subsystem VID registers, that should be it.
89 * This might easily be in extended PCI reg space, since PCI168 also has
90 * some custom data starting at 0x80. What kind of config settings
91 * are located in our extended PCI space anyway??
92 * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
95 * Note that this driver now is actually *better* than the Windows driver,
96 * since it additionally supports the card's 1MHz DirectX timer - just try
97 * the following snd-seq module parameters etc.:
98 * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
99 * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
100 * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
101 * - "timidity -iAv -B2,8 -Os -EFreverb=0"
102 * - "pmidi -p 128:0 jazz.mid"
104 * OPL3 hardware playback testing, try something like:
105 * cat /proc/asound/hwdep
109 * sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3
110 * where x,y is the xx-yy number as given in hwdep.
112 * pmidi -p a:b jazz.mid
113 * where a:b is the client number plus 0 usually, as given by aconnect above.
114 * Oh, and make sure to unmute the FM mixer control (doh!)
115 * NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!)
116 * despite no CPU activity, possibly due to hindering ACPI idling somehow.
117 * Shouldn't be a problem of the AZF3328 chip itself, I'd hope.
118 * Higher PCM / FM mixer levels seem to conflict (causes crackling),
119 * at least sometimes. Maybe even use with hardware sequencer timer above :)
120 * adplay/adplug-utils might soon offer hardware-based OPL3 playback, too.
122 * Certain PCI versions of this card are susceptible to DMA traffic underruns
123 * in some systems (resulting in sound crackling/clicking/popping),
124 * probably because they don't have a DMA FIFO buffer or so.
125 * Overview (PCI ID/PCI subID/PCI rev.):
126 * - no DMA crackling on SiS735: 0x50DC/0x1801/16
127 * - unknown performance: 0x50DC/0x1801/10
128 * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
130 * Crackling happens with VIA chipsets or, in my case, an SiS735, which is
131 * supposed to be very fast and supposed to get rid of crackling much
132 * better than a VIA, yet ironically I still get crackling, like many other
133 * people with the same chipset.
135 * - use speaker (amplifier) output instead of headphone output
136 * (in case crackling is due to overloaded output clipping)
137 * - plug card into a different PCI slot, preferrably one that isn't shared
138 * too much (this helps a lot, but not completely!)
139 * - get rid of PCI VGA card, use AGP instead
140 * - upgrade or downgrade BIOS
141 * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
143 * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
146 * - full-duplex might *still* be problematic, however a recent test was fine
147 * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated
148 * if you set PCM output switch to "pre 3D" instead of "post 3D".
149 * If this can't be set, then get a mixer application that Isn't Stupid (tm)
150 * (e.g. kmix, gamix) - unfortunately several are!!
151 * - locking is not entirely clean, especially the audio stream activity
152 * ints --> may be racy
153 * - an _unconnected_ secondary joystick at the gameport will be reported
154 * to be "active" (floating values, not precisely -1) due to the way we need
155 * to read the Digital Enhanced Game Port. Not sure whether it is fixable.
159 * - verify driver status on x86_64
160 * - test multi-card driver operation
161 * - (ab)use 1MHz DirectX timer as kernel clocksource
162 * - test MPU401 MIDI playback etc.
163 * - add more power micro-management (disable various units of the card
164 * as long as they're unused, to improve audio quality and save power).
165 * However this requires more I/O ports which I haven't figured out yet
166 * and which thus might not even exist...
167 * The standard suspend/resume functionality could probably make use of
168 * some improvement, too...
169 * - figure out what all unknown port bits are responsible for
170 * - figure out some cleverly evil scheme to possibly make ALSA AC97 code
171 * fully accept our quite incompatible ""AC97"" mixer and thus save some
172 * code (but I'm not too optimistic that doing this is possible at all)
173 * - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport.
177 #include <linux/init.h>
178 #include <linux/pci.h>
179 #include <linux/delay.h>
180 #include <linux/slab.h>
181 #include <linux/gameport.h>
182 #include <linux/moduleparam.h>
183 #include <linux/dma-mapping.h>
184 #include <sound/core.h>
185 #include <sound/control.h>
186 #include <sound/pcm.h>
187 #include <sound/rawmidi.h>
188 #include <sound/mpu401.h>
189 #include <sound/opl3.h>
190 #include <sound/initval.h>
193 MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
194 MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
195 MODULE_LICENSE("GPL");
196 MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
198 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
199 #define SUPPORT_GAMEPORT 1
202 /* === Debug settings ===
203 Further diagnostic functionality than the settings below
204 does not need to be provided, since one can easily write a POSIX shell script
205 to dump the card's I/O ports (those listed in lspci -v -v):
208 local descr=$1; local addr=$2; local count=$3
210 echo "${descr}: ${count} @ ${addr}:"
211 dd if=/dev/port skip=`printf %d ${addr}` count=${count} bs=1 \
212 2>/dev/null| hexdump -C
214 and then use something like
215 "dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8",
216 "dump codec00 0xa800 32", "dump mixer 0xb800 64", "dump synth 0xbc00 8",
217 possibly within a "while true; do ... sleep 1; done" loop.
218 Tweaking ports could be done using
219 VALSTRING="`printf "%02x" $value`"
220 printf "\x""$VALSTRING"|dd of=/dev/port seek=`printf %d ${addr}` bs=1 \
225 #define DEBUG_CALLS 0
226 #define DEBUG_MIXER 0
227 #define DEBUG_CODEC 0
228 #define DEBUG_TIMER 0
231 #define MIXER_TESTING 0
234 #define snd_azf3328_dbgmisc(format, args...) printk(KERN_DEBUG format, ##args)
236 #define snd_azf3328_dbgmisc(format, args...)
240 #define snd_azf3328_dbgcalls(format, args...) printk(format, ##args)
241 #define snd_azf3328_dbgcallenter() printk(KERN_DEBUG "--> %s\n", __func__)
242 #define snd_azf3328_dbgcallleave() printk(KERN_DEBUG "<-- %s\n", __func__)
244 #define snd_azf3328_dbgcalls(format, args...)
245 #define snd_azf3328_dbgcallenter()
246 #define snd_azf3328_dbgcallleave()
250 #define snd_azf3328_dbgmixer(format, args...) printk(KERN_DEBUG format, ##args)
252 #define snd_azf3328_dbgmixer(format, args...)
256 #define snd_azf3328_dbgcodec(format, args...) printk(KERN_DEBUG format, ##args)
258 #define snd_azf3328_dbgcodec(format, args...)
262 #define snd_azf3328_dbgtimer(format, args...) printk(KERN_DEBUG format, ##args)
264 #define snd_azf3328_dbgtimer(format, args...)
268 #define snd_azf3328_dbggame(format, args...) printk(KERN_DEBUG format, ##args)
270 #define snd_azf3328_dbggame(format, args...)
274 #define snd_azf3328_dbgpm(format, args...) printk(KERN_DEBUG format, ##args)
276 #define snd_azf3328_dbgpm(format, args...)
279 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
280 module_param_array(index, int, NULL, 0444);
281 MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
283 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
284 module_param_array(id, charp, NULL, 0444);
285 MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
287 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
288 module_param_array(enable, bool, NULL, 0444);
289 MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
291 static int seqtimer_scaling = 128;
292 module_param(seqtimer_scaling, int, 0444);
293 MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
295 struct snd_azf3328_codec_data {
296 unsigned long io_base;
297 struct snd_pcm_substream *substream;
302 enum snd_azf3328_codec_type {
303 /* warning: fixed indices (also used for bitmask checks!) */
304 AZF_CODEC_PLAYBACK = 0,
305 AZF_CODEC_CAPTURE = 1,
306 AZF_CODEC_I2S_OUT = 2,
310 /* often-used fields towards beginning, then grouped */
312 unsigned long ctrl_io; /* usually 0xb000, size 128 */
313 unsigned long game_io; /* usually 0xb400, size 8 */
314 unsigned long mpu_io; /* usually 0xb800, size 4 */
315 unsigned long opl3_io; /* usually 0xbc00, size 8 */
316 unsigned long mixer_io; /* usually 0xc000, size 64 */
320 struct snd_timer *timer;
322 struct snd_pcm *pcm[3];
324 /* playback, recording and I2S out codecs */
325 struct snd_azf3328_codec_data codecs[3];
327 struct snd_card *card;
328 struct snd_rawmidi *rmidi;
330 #ifdef SUPPORT_GAMEPORT
331 struct gameport *gameport;
338 /* register 0x6a is write-only, thus need to remember setting.
339 * If we need to add more registers here, then we might try to fold this
340 * into some transparent combined shadow register handling with
341 * CONFIG_PM register storage below, but that's slightly difficult. */
342 u16 shadow_reg_ctrl_6AH;
345 /* register value containers for power management
346 * Note: not always full I/O range preserved (similar to Win driver!) */
347 u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4];
348 u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4];
349 u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4];
350 u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4];
351 u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4];
355 static DEFINE_PCI_DEVICE_TABLE(snd_azf3328_ids) = {
356 { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */
357 { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */
361 MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
365 snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set)
367 /* Well, strictly spoken, the inb/outb sequence isn't atomic
368 and would need locking. However we currently don't care
369 since it potentially complicates matters. */
370 u8 prev = inb(reg), new;
372 new = (do_set) ? (prev|mask) : (prev & ~mask);
373 /* we need to always write the new value no matter whether it differs
374 * or not, since some register bits don't indicate their setting */
383 snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec,
388 outb(value, codec->io_base + reg);
392 snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg)
394 return inb(codec->io_base + reg);
398 snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec,
403 outw(value, codec->io_base + reg);
407 snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg)
409 return inw(codec->io_base + reg);
413 snd_azf3328_codec_outl(const struct snd_azf3328_codec_data *codec,
418 outl(value, codec->io_base + reg);
422 snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg)
424 return inl(codec->io_base + reg);
428 snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
430 outb(value, chip->ctrl_io + reg);
434 snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg)
436 return inb(chip->ctrl_io + reg);
440 snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
442 outw(value, chip->ctrl_io + reg);
446 snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value)
448 outl(value, chip->ctrl_io + reg);
452 snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
454 outb(value, chip->game_io + reg);
458 snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
460 outw(value, chip->game_io + reg);
464 snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg)
466 return inb(chip->game_io + reg);
470 snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg)
472 return inw(chip->game_io + reg);
476 snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
478 outw(value, chip->mixer_io + reg);
482 snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg)
484 return inw(chip->mixer_io + reg);
487 #define AZF_MUTE_BIT 0x80
490 snd_azf3328_mixer_set_mute(const struct snd_azf3328 *chip,
491 unsigned reg, bool do_mute
494 unsigned long portbase = chip->mixer_io + reg + 1;
497 /* the mute bit is on the *second* (i.e. right) register of a
498 * left/right channel setting */
499 updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute);
501 /* indicate whether it was muted before */
502 return (do_mute) ? !updated : updated;
506 snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip,
508 unsigned char dst_vol_left,
509 unsigned char dst_vol_right,
510 int chan_sel, int delay
513 unsigned long portbase = chip->mixer_io + reg;
514 unsigned char curr_vol_left = 0, curr_vol_right = 0;
515 int left_change = 0, right_change = 0;
517 snd_azf3328_dbgcallenter();
519 if (chan_sel & SET_CHAN_LEFT) {
520 curr_vol_left = inb(portbase + 1);
522 /* take care of muting flag contained in left channel */
523 if (curr_vol_left & AZF_MUTE_BIT)
524 dst_vol_left |= AZF_MUTE_BIT;
526 dst_vol_left &= ~AZF_MUTE_BIT;
528 left_change = (curr_vol_left > dst_vol_left) ? -1 : 1;
531 if (chan_sel & SET_CHAN_RIGHT) {
532 curr_vol_right = inb(portbase + 0);
534 right_change = (curr_vol_right > dst_vol_right) ? -1 : 1;
539 if (curr_vol_left != dst_vol_left) {
540 curr_vol_left += left_change;
541 outb(curr_vol_left, portbase + 1);
546 if (curr_vol_right != dst_vol_right) {
547 curr_vol_right += right_change;
549 /* during volume change, the right channel is crackling
550 * somewhat more than the left channel, unfortunately.
551 * This seems to be a hardware issue. */
552 outb(curr_vol_right, portbase + 0);
558 } while ((left_change) || (right_change));
559 snd_azf3328_dbgcallleave();
563 * general mixer element
565 struct azf3328_mixer_reg {
567 unsigned int lchan_shift, rchan_shift;
569 unsigned int invert: 1;
570 unsigned int stereo: 1;
571 unsigned int enum_c: 4;
574 #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
575 ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
581 static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
584 r->lchan_shift = (val >> 8) & 0x0f;
585 r->rchan_shift = (val >> 12) & 0x0f;
586 r->mask = (val >> 16) & 0xff;
587 r->invert = (val >> 24) & 1;
588 r->stereo = (val >> 25) & 1;
589 r->enum_c = (val >> 26) & 0x0f;
593 * mixer switches/volumes
596 #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
597 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
598 .info = snd_azf3328_info_mixer, \
599 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
600 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
603 #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
604 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
605 .info = snd_azf3328_info_mixer, \
606 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
607 .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
610 #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
611 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
612 .info = snd_azf3328_info_mixer, \
613 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
614 .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
617 #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
618 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
619 .info = snd_azf3328_info_mixer, \
620 .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
621 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
624 #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
625 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
626 .info = snd_azf3328_info_mixer_enum, \
627 .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
628 .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
632 snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
633 struct snd_ctl_elem_info *uinfo)
635 struct azf3328_mixer_reg reg;
637 snd_azf3328_dbgcallenter();
638 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
639 uinfo->type = reg.mask == 1 ?
640 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
641 uinfo->count = reg.stereo + 1;
642 uinfo->value.integer.min = 0;
643 uinfo->value.integer.max = reg.mask;
644 snd_azf3328_dbgcallleave();
649 snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
650 struct snd_ctl_elem_value *ucontrol)
652 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
653 struct azf3328_mixer_reg reg;
656 snd_azf3328_dbgcallenter();
657 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
659 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
660 val = (oreg >> reg.lchan_shift) & reg.mask;
662 val = reg.mask - val;
663 ucontrol->value.integer.value[0] = val;
665 val = (oreg >> reg.rchan_shift) & reg.mask;
667 val = reg.mask - val;
668 ucontrol->value.integer.value[1] = val;
670 snd_azf3328_dbgmixer("get: %02x is %04x -> vol %02lx|%02lx "
671 "(shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
673 ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
674 reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
675 snd_azf3328_dbgcallleave();
680 snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
681 struct snd_ctl_elem_value *ucontrol)
683 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
684 struct azf3328_mixer_reg reg;
687 snd_azf3328_dbgcallenter();
688 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
689 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
690 val = ucontrol->value.integer.value[0] & reg.mask;
692 val = reg.mask - val;
693 nreg = oreg & ~(reg.mask << reg.lchan_shift);
694 nreg |= (val << reg.lchan_shift);
696 val = ucontrol->value.integer.value[1] & reg.mask;
698 val = reg.mask - val;
699 nreg &= ~(reg.mask << reg.rchan_shift);
700 nreg |= (val << reg.rchan_shift);
702 if (reg.mask >= 0x07) /* it's a volume control, so better take care */
703 snd_azf3328_mixer_write_volume_gradually(
704 chip, reg.reg, nreg >> 8, nreg & 0xff,
705 /* just set both channels, doesn't matter */
706 SET_CHAN_LEFT|SET_CHAN_RIGHT,
709 snd_azf3328_mixer_outw(chip, reg.reg, nreg);
711 snd_azf3328_dbgmixer("put: %02x to %02lx|%02lx, "
712 "oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
713 reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
714 oreg, reg.lchan_shift, reg.rchan_shift,
715 nreg, snd_azf3328_mixer_inw(chip, reg.reg));
716 snd_azf3328_dbgcallleave();
717 return (nreg != oreg);
721 snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
722 struct snd_ctl_elem_info *uinfo)
724 static const char * const texts1[] = {
727 static const char * const texts2[] = {
730 static const char * const texts3[] = {
731 "Mic", "CD", "Video", "Aux",
732 "Line", "Mix", "Mix Mono", "Phone"
734 static const char * const texts4[] = {
737 struct azf3328_mixer_reg reg;
738 const char * const *p = NULL;
740 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
741 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
742 uinfo->count = (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1;
743 uinfo->value.enumerated.items = reg.enum_c;
744 if (uinfo->value.enumerated.item > reg.enum_c - 1U)
745 uinfo->value.enumerated.item = reg.enum_c - 1U;
746 if (reg.reg == IDX_MIXER_ADVCTL2) {
747 switch(reg.lchan_shift) {
748 case 8: /* modem out sel */
751 case 9: /* mono sel source */
754 case 15: /* PCM Out Path */
759 if (reg.reg == IDX_MIXER_REC_SELECT)
762 strcpy(uinfo->value.enumerated.name, p[uinfo->value.enumerated.item]);
767 snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
768 struct snd_ctl_elem_value *ucontrol)
770 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
771 struct azf3328_mixer_reg reg;
774 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
775 val = snd_azf3328_mixer_inw(chip, reg.reg);
776 if (reg.reg == IDX_MIXER_REC_SELECT) {
777 ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
778 ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
780 ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
782 snd_azf3328_dbgmixer("get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
783 reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
784 reg.lchan_shift, reg.enum_c);
789 snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
790 struct snd_ctl_elem_value *ucontrol)
792 struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
793 struct azf3328_mixer_reg reg;
796 snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
797 oreg = snd_azf3328_mixer_inw(chip, reg.reg);
799 if (reg.reg == IDX_MIXER_REC_SELECT) {
800 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
801 ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
803 val = (ucontrol->value.enumerated.item[0] << 8) |
804 (ucontrol->value.enumerated.item[1] << 0);
806 if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
808 val &= ~((reg.enum_c - 1) << reg.lchan_shift);
809 val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
811 snd_azf3328_mixer_outw(chip, reg.reg, val);
814 snd_azf3328_dbgmixer("put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
815 return (nreg != oreg);
818 static struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = {
819 AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
820 AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
821 AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
822 AZF3328_MIXER_VOL_STEREO("PCM Playback Volume",
823 IDX_MIXER_WAVEOUT, 0x1f, 1),
824 AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch",
825 IDX_MIXER_ADVCTL2, 7, 1),
826 AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
827 AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
828 AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
829 AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
830 AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
831 AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
832 AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
833 AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
834 AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
835 AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
836 AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
837 AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
838 AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
839 AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
840 AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
841 AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
842 AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
843 AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
844 AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
845 AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
846 AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
847 AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
848 AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8),
849 AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9),
850 AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */
851 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
852 AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
853 AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
854 AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
855 AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
857 AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
858 AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
859 AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
860 AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
861 AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
862 AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
863 AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
864 AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
865 AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
866 AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
867 AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
868 AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
869 AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
870 AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
871 AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
872 AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
876 static u16 __devinitdata snd_azf3328_init_values[][2] = {
877 { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
878 { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
879 { IDX_MIXER_BASSTREBLE, 0x0000 },
880 { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
881 { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
882 { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
883 { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
884 { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
885 { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
886 { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
887 { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
888 { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
889 { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
893 snd_azf3328_mixer_new(struct snd_azf3328 *chip)
895 struct snd_card *card;
896 const struct snd_kcontrol_new *sw;
900 snd_azf3328_dbgcallenter();
901 if (snd_BUG_ON(!chip || !chip->card))
907 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
909 /* mute and zero volume channels */
910 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) {
911 snd_azf3328_mixer_outw(chip,
912 snd_azf3328_init_values[idx][0],
913 snd_azf3328_init_values[idx][1]);
916 /* add mixer controls */
917 sw = snd_azf3328_mixer_controls;
918 for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls);
920 if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
923 snd_component_add(card, "AZF3328 mixer");
924 strcpy(card->mixername, "AZF3328 mixer");
926 snd_azf3328_dbgcallleave();
931 snd_azf3328_hw_params(struct snd_pcm_substream *substream,
932 struct snd_pcm_hw_params *hw_params)
935 snd_azf3328_dbgcallenter();
936 res = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
937 snd_azf3328_dbgcallleave();
942 snd_azf3328_hw_free(struct snd_pcm_substream *substream)
944 snd_azf3328_dbgcallenter();
945 snd_pcm_lib_free_pages(substream);
946 snd_azf3328_dbgcallleave();
951 snd_azf3328_codec_setfmt(struct snd_azf3328 *chip,
952 enum snd_azf3328_codec_type codec_type,
953 enum azf_freq_t bitrate,
954 unsigned int format_width,
955 unsigned int channels
959 const struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
963 snd_azf3328_dbgcallenter();
965 #define AZF_FMT_XLATE(in_freq, out_bits) \
967 case AZF_FREQ_ ## in_freq: \
968 freq = SOUNDFORMAT_FREQ_ ## out_bits; \
971 AZF_FMT_XLATE(4000, SUSPECTED_4000)
972 AZF_FMT_XLATE(4800, SUSPECTED_4800)
973 /* the AZF3328 names it "5510" for some strange reason: */
974 AZF_FMT_XLATE(5512, 5510)
975 AZF_FMT_XLATE(6620, 6620)
976 AZF_FMT_XLATE(8000, 8000)
977 AZF_FMT_XLATE(9600, 9600)
978 AZF_FMT_XLATE(11025, 11025)
979 AZF_FMT_XLATE(13240, SUSPECTED_13240)
980 AZF_FMT_XLATE(16000, 16000)
981 AZF_FMT_XLATE(22050, 22050)
982 AZF_FMT_XLATE(32000, 32000)
984 snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
986 AZF_FMT_XLATE(44100, 44100)
987 AZF_FMT_XLATE(48000, 48000)
988 AZF_FMT_XLATE(66200, SUSPECTED_66200)
991 /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
992 /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
993 /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
994 /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
995 /* val = 0xff05; 5m11.556s (... -> 44100Hz) */
996 /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
997 /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
998 /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
999 /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
1004 val |= SOUNDFORMAT_FLAG_2CHANNELS;
1006 if (format_width == 16)
1007 val |= SOUNDFORMAT_FLAG_16BIT;
1009 spin_lock_irqsave(&chip->reg_lock, flags);
1011 /* set bitrate/format */
1012 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val);
1014 /* changing the bitrate/format settings switches off the
1015 * audio output with an annoying click in case of 8/16bit format change
1016 * (maybe shutting down DAC/ADC?), thus immediately
1017 * do some tweaking to reenable it and get rid of the clicking
1018 * (FIXME: yes, it works, but what exactly am I doing here?? :)
1019 * FIXME: does this have some side effects for full-duplex
1020 * or other dramatic side effects? */
1021 /* do it for non-capture codecs only */
1022 if (codec_type == AZF_CODEC_PLAYBACK)
1023 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1024 snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) |
1025 DMA_RUN_SOMETHING1 |
1026 DMA_RUN_SOMETHING2 |
1027 SOMETHING_ALMOST_ALWAYS_SET |
1028 DMA_EPILOGUE_SOMETHING |
1032 spin_unlock_irqrestore(&chip->reg_lock, flags);
1033 snd_azf3328_dbgcallleave();
1037 snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328 *chip,
1038 enum snd_azf3328_codec_type codec_type
1041 /* choose lowest frequency for low power consumption.
1042 * While this will cause louder noise due to rather coarse frequency,
1043 * it should never matter since output should always
1044 * get disabled properly when idle anyway. */
1045 snd_azf3328_codec_setfmt(chip, codec_type, AZF_FREQ_4000, 8, 1);
1049 snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip,
1054 bool do_mask = !enable;
1056 chip->shadow_reg_ctrl_6AH |= bitmask;
1058 chip->shadow_reg_ctrl_6AH &= ~bitmask;
1059 snd_azf3328_dbgcodec("6AH_update mask 0x%04x do_mask %d: val 0x%04x\n",
1060 bitmask, do_mask, chip->shadow_reg_ctrl_6AH);
1061 snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH);
1065 snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable)
1067 snd_azf3328_dbgcodec("codec_enable %d\n", enable);
1068 /* no idea what exactly is being done here, but I strongly assume it's
1070 snd_azf3328_ctrl_reg_6AH_update(
1071 chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable
1076 snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip,
1077 enum snd_azf3328_codec_type codec_type,
1081 struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
1082 bool need_change = (codec->running != enable);
1084 snd_azf3328_dbgcodec(
1085 "codec_activity: %s codec, enable %d, need_change %d\n",
1086 codec->name, enable, need_change
1089 static const struct {
1090 enum snd_azf3328_codec_type other1;
1091 enum snd_azf3328_codec_type other2;
1093 { { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT },
1094 { AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT },
1095 { AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } };
1099 /* if enable codec, call enable_codecs func
1100 to enable codec supply... */
1103 /* ...otherwise call enable_codecs func
1104 (which globally shuts down operation of codecs)
1105 only in case the other codecs are currently
1106 not active either! */
1108 ((!chip->codecs[peer_codecs[codec_type].other1]
1110 && (!chip->codecs[peer_codecs[codec_type].other2]
1114 snd_azf3328_ctrl_enable_codecs(chip, enable);
1116 /* ...and adjust clock, too
1117 * (reduce noise and power consumption) */
1119 snd_azf3328_codec_setfmt_lowpower(
1123 codec->running = enable;
1128 snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip,
1129 enum snd_azf3328_codec_type codec_type,
1135 const struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
1136 snd_azf3328_dbgcallenter();
1137 if (!codec->running) {
1138 /* AZF3328 uses a two buffer pointer DMA transfer approach */
1140 unsigned long flags, addr_area2;
1142 /* width 32bit (prevent overflow): */
1143 u32 count_areas, lengths;
1145 count_areas = size/2;
1146 addr_area2 = addr+count_areas;
1147 snd_azf3328_dbgcodec("setdma: buffers %08lx[%u] / %08lx[%u]\n",
1148 addr, count_areas, addr_area2, count_areas);
1150 count_areas--; /* max. index */
1152 /* build combined I/O buffer length word */
1153 lengths = (count_areas << 16) | (count_areas);
1154 spin_lock_irqsave(&chip->reg_lock, flags);
1155 snd_azf3328_codec_outl(codec, IDX_IO_CODEC_DMA_START_1, addr);
1156 snd_azf3328_codec_outl(codec, IDX_IO_CODEC_DMA_START_2,
1158 snd_azf3328_codec_outl(codec, IDX_IO_CODEC_DMA_LENGTHS,
1160 spin_unlock_irqrestore(&chip->reg_lock, flags);
1162 snd_azf3328_dbgcallleave();
1166 snd_azf3328_codec_prepare(struct snd_pcm_substream *substream)
1169 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1170 struct snd_pcm_runtime *runtime = substream->runtime;
1171 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1172 unsigned int count = snd_pcm_lib_period_bytes(substream);
1175 snd_azf3328_dbgcallenter();
1177 snd_azf3328_codec_setfmt(chip, AZF_CODEC_...,
1179 snd_pcm_format_width(runtime->format),
1181 snd_azf3328_codec_setdmaa(chip, AZF_CODEC_...,
1182 runtime->dma_addr, count, size);
1184 snd_azf3328_dbgcallleave();
1189 snd_azf3328_codec_trigger(enum snd_azf3328_codec_type codec_type,
1190 struct snd_pcm_substream *substream, int cmd)
1192 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1193 const struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
1194 struct snd_pcm_runtime *runtime = substream->runtime;
1197 bool previously_muted = 0;
1198 bool is_playback_codec = (AZF_CODEC_PLAYBACK == codec_type);
1200 snd_azf3328_dbgcalls("snd_azf3328_codec_trigger cmd %d\n", cmd);
1203 case SNDRV_PCM_TRIGGER_START:
1204 snd_azf3328_dbgcodec("START %s\n", codec->name);
1206 if (is_playback_codec) {
1207 /* mute WaveOut (avoid clicking during setup) */
1209 snd_azf3328_mixer_set_mute(
1210 chip, IDX_MIXER_WAVEOUT, 1
1214 snd_azf3328_codec_setfmt(chip, codec_type,
1216 snd_pcm_format_width(runtime->format),
1219 spin_lock(&chip->reg_lock);
1220 /* first, remember current value: */
1221 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
1224 flags1 &= ~DMA_RESUME;
1225 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1227 /* FIXME: clear interrupts or what??? */
1228 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, 0xffff);
1229 spin_unlock(&chip->reg_lock);
1231 snd_azf3328_codec_setdmaa(chip, codec_type, runtime->dma_addr,
1232 snd_pcm_lib_period_bytes(substream),
1233 snd_pcm_lib_buffer_bytes(substream)
1236 spin_lock(&chip->reg_lock);
1238 /* FIXME: enable playback/recording??? */
1239 flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2;
1240 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1242 /* start transfer again */
1243 /* FIXME: what is this value (0x0010)??? */
1244 flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
1245 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1247 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1249 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1250 DMA_RUN_SOMETHING1);
1251 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1252 DMA_RUN_SOMETHING1 |
1253 DMA_RUN_SOMETHING2);
1254 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1256 SOMETHING_ALMOST_ALWAYS_SET |
1257 DMA_EPILOGUE_SOMETHING |
1258 DMA_SOMETHING_ELSE);
1260 spin_unlock(&chip->reg_lock);
1261 snd_azf3328_ctrl_codec_activity(chip, codec_type, 1);
1263 if (is_playback_codec) {
1264 /* now unmute WaveOut */
1265 if (!previously_muted)
1266 snd_azf3328_mixer_set_mute(
1267 chip, IDX_MIXER_WAVEOUT, 0
1271 snd_azf3328_dbgcodec("STARTED %s\n", codec->name);
1273 case SNDRV_PCM_TRIGGER_RESUME:
1274 snd_azf3328_dbgcodec("RESUME %s\n", codec->name);
1275 /* resume codec if we were active */
1276 spin_lock(&chip->reg_lock);
1278 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1279 snd_azf3328_codec_inw(
1280 codec, IDX_IO_CODEC_DMA_FLAGS
1283 spin_unlock(&chip->reg_lock);
1285 case SNDRV_PCM_TRIGGER_STOP:
1286 snd_azf3328_dbgcodec("STOP %s\n", codec->name);
1288 if (is_playback_codec) {
1289 /* mute WaveOut (avoid clicking during setup) */
1291 snd_azf3328_mixer_set_mute(
1292 chip, IDX_MIXER_WAVEOUT, 1
1296 spin_lock(&chip->reg_lock);
1297 /* first, remember current value: */
1298 flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
1301 flags1 &= ~DMA_RESUME;
1302 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1304 /* hmm, is this really required? we're resetting the same bit
1305 * immediately thereafter... */
1306 flags1 |= DMA_RUN_SOMETHING1;
1307 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1309 flags1 &= ~DMA_RUN_SOMETHING1;
1310 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
1311 spin_unlock(&chip->reg_lock);
1312 snd_azf3328_ctrl_codec_activity(chip, codec_type, 0);
1314 if (is_playback_codec) {
1315 /* now unmute WaveOut */
1316 if (!previously_muted)
1317 snd_azf3328_mixer_set_mute(
1318 chip, IDX_MIXER_WAVEOUT, 0
1322 snd_azf3328_dbgcodec("STOPPED %s\n", codec->name);
1324 case SNDRV_PCM_TRIGGER_SUSPEND:
1325 snd_azf3328_dbgcodec("SUSPEND %s\n", codec->name);
1326 /* make sure codec is stopped */
1327 snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
1328 snd_azf3328_codec_inw(
1329 codec, IDX_IO_CODEC_DMA_FLAGS
1333 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1334 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
1336 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1337 snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
1340 snd_printk(KERN_ERR "FIXME: unknown trigger mode!\n");
1344 snd_azf3328_dbgcallleave();
1349 snd_azf3328_codec_playback_trigger(struct snd_pcm_substream *substream, int cmd)
1351 return snd_azf3328_codec_trigger(AZF_CODEC_PLAYBACK, substream, cmd);
1355 snd_azf3328_codec_capture_trigger(struct snd_pcm_substream *substream, int cmd)
1357 return snd_azf3328_codec_trigger(AZF_CODEC_CAPTURE, substream, cmd);
1361 snd_azf3328_codec_i2s_out_trigger(struct snd_pcm_substream *substream, int cmd)
1363 return snd_azf3328_codec_trigger(AZF_CODEC_I2S_OUT, substream, cmd);
1366 static snd_pcm_uframes_t
1367 snd_azf3328_codec_pointer(struct snd_pcm_substream *substream,
1368 enum snd_azf3328_codec_type codec_type
1371 const struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1372 const struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
1373 unsigned long bufptr, result;
1374 snd_pcm_uframes_t frmres;
1376 #ifdef QUERY_HARDWARE
1377 bufptr = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1);
1379 bufptr = substream->runtime->dma_addr;
1381 result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS);
1383 /* calculate offset */
1385 frmres = bytes_to_frames( substream->runtime, result);
1386 snd_azf3328_dbgcodec("%08li %s @ 0x%8lx, frames %8ld\n",
1387 jiffies, codec->name, result, frmres);
1391 static snd_pcm_uframes_t
1392 snd_azf3328_codec_playback_pointer(struct snd_pcm_substream *substream)
1394 return snd_azf3328_codec_pointer(substream, AZF_CODEC_PLAYBACK);
1397 static snd_pcm_uframes_t
1398 snd_azf3328_codec_capture_pointer(struct snd_pcm_substream *substream)
1400 return snd_azf3328_codec_pointer(substream, AZF_CODEC_CAPTURE);
1403 static snd_pcm_uframes_t
1404 snd_azf3328_codec_i2s_out_pointer(struct snd_pcm_substream *substream)
1406 return snd_azf3328_codec_pointer(substream, AZF_CODEC_I2S_OUT);
1409 /******************************************************************/
1411 #ifdef SUPPORT_GAMEPORT
1413 snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip,
1417 snd_azf3328_io_reg_setb(
1418 chip->game_io+IDX_GAME_HWCONFIG,
1419 GAME_HWCFG_IRQ_ENABLE,
1425 snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip,
1429 snd_azf3328_io_reg_setb(
1430 chip->game_io+IDX_GAME_HWCONFIG,
1431 GAME_HWCFG_LEGACY_ADDRESS_ENABLE,
1437 snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip,
1438 unsigned int freq_cfg
1441 snd_azf3328_io_reg_setb(
1442 chip->game_io+IDX_GAME_HWCONFIG,
1446 snd_azf3328_io_reg_setb(
1447 chip->game_io+IDX_GAME_HWCONFIG,
1454 snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable)
1456 snd_azf3328_ctrl_reg_6AH_update(
1457 chip, IO_6A_SOMETHING2_GAMEPORT, enable
1462 snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1465 * skeleton handler only
1466 * (we do not want axis reading in interrupt handler - too much load!)
1468 snd_azf3328_dbggame("gameport irq\n");
1470 /* this should ACK the gameport IRQ properly, hopefully. */
1471 snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE);
1475 snd_azf3328_gameport_open(struct gameport *gameport, int mode)
1477 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1480 snd_azf3328_dbggame("gameport_open, mode %d\n", mode);
1482 case GAMEPORT_MODE_COOKED:
1483 case GAMEPORT_MODE_RAW:
1491 snd_azf3328_gameport_set_counter_frequency(chip,
1492 GAME_HWCFG_ADC_COUNTER_FREQ_STD);
1493 snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0));
1499 snd_azf3328_gameport_close(struct gameport *gameport)
1501 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1503 snd_azf3328_dbggame("gameport_close\n");
1504 snd_azf3328_gameport_set_counter_frequency(chip,
1505 GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
1506 snd_azf3328_gameport_axis_circuit_enable(chip, 0);
1510 snd_azf3328_gameport_cooked_read(struct gameport *gameport,
1515 struct snd_azf3328 *chip = gameport_get_port_data(gameport);
1518 unsigned long flags;
1520 if (snd_BUG_ON(!chip))
1523 spin_lock_irqsave(&chip->reg_lock, flags);
1524 val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE);
1525 *buttons = (~(val) >> 4) & 0xf;
1527 /* ok, this one is a bit dirty: cooked_read is being polled by a timer,
1528 * thus we're atomic and cannot actively wait in here
1529 * (which would be useful for us since it probably would be better
1530 * to trigger a measurement in here, then wait a short amount of
1531 * time until it's finished, then read values of _this_ measurement).
1533 * Thus we simply resort to reading values if they're available already
1534 * and trigger the next measurement.
1537 val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG);
1538 if (val & GAME_AXES_SAMPLING_READY) {
1539 for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) {
1540 /* configure the axis to read */
1541 val = (i << 4) | 0x0f;
1542 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
1544 chip->axes[i] = snd_azf3328_game_inw(
1545 chip, IDX_GAME_AXIS_VALUE
1550 /* trigger next sampling of axes, to be evaluated the next time we
1551 * enter this function */
1553 /* for some very, very strange reason we cannot enable
1554 * Measurement Ready monitoring for all axes here,
1555 * at least not when only one joystick connected */
1556 val = 0x03; /* we're able to monitor axes 1 and 2 only */
1557 snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
1559 snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff);
1560 spin_unlock_irqrestore(&chip->reg_lock, flags);
1562 for (i = 0; i < ARRAY_SIZE(chip->axes); i++) {
1563 axes[i] = chip->axes[i];
1564 if (axes[i] == 0xffff)
1568 snd_azf3328_dbggame("cooked_read: axes %d %d %d %d buttons %d\n",
1569 axes[0], axes[1], axes[2], axes[3], *buttons
1575 static int __devinit
1576 snd_azf3328_gameport(struct snd_azf3328 *chip, int dev)
1578 struct gameport *gp;
1580 chip->gameport = gp = gameport_allocate_port();
1582 printk(KERN_ERR "azt3328: cannot alloc memory for gameport\n");
1586 gameport_set_name(gp, "AZF3328 Gameport");
1587 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
1588 gameport_set_dev_parent(gp, &chip->pci->dev);
1589 gp->io = chip->game_io;
1590 gameport_set_port_data(gp, chip);
1592 gp->open = snd_azf3328_gameport_open;
1593 gp->close = snd_azf3328_gameport_close;
1594 gp->fuzz = 16; /* seems ok */
1595 gp->cooked_read = snd_azf3328_gameport_cooked_read;
1597 /* DISABLE legacy address: we don't need it! */
1598 snd_azf3328_gameport_legacy_address_enable(chip, 0);
1600 snd_azf3328_gameport_set_counter_frequency(chip,
1601 GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
1602 snd_azf3328_gameport_axis_circuit_enable(chip, 0);
1604 gameport_register_port(chip->gameport);
1610 snd_azf3328_gameport_free(struct snd_azf3328 *chip)
1612 if (chip->gameport) {
1613 gameport_unregister_port(chip->gameport);
1614 chip->gameport = NULL;
1616 snd_azf3328_gameport_irq_enable(chip, 0);
1620 snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
1622 snd_azf3328_gameport_free(struct snd_azf3328 *chip) { }
1624 snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
1626 printk(KERN_WARNING "huh, game port IRQ occurred!?\n");
1628 #endif /* SUPPORT_GAMEPORT */
1630 /******************************************************************/
1633 snd_azf3328_irq_log_unknown_type(u8 which)
1635 snd_azf3328_dbgcodec(
1636 "azt3328: unknown IRQ type (%x) occurred, please report!\n",
1642 snd_azf3328_codec_interrupt(struct snd_azf3328 *chip, u8 status)
1645 enum snd_azf3328_codec_type codec_type;
1646 const struct snd_azf3328_codec_data *codec;
1648 for (codec_type = AZF_CODEC_PLAYBACK;
1649 codec_type <= AZF_CODEC_I2S_OUT;
1652 /* skip codec if there's no interrupt for it */
1653 if (!(status & (1 << codec_type)))
1656 codec = &chip->codecs[codec_type];
1658 spin_lock(&chip->reg_lock);
1659 which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE);
1660 /* ack all IRQ types immediately */
1661 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which);
1662 spin_unlock(&chip->reg_lock);
1664 if ((chip->pcm[codec_type]) && (codec->substream)) {
1665 snd_pcm_period_elapsed(codec->substream);
1666 snd_azf3328_dbgcodec("%s period done (#%x), @ %x\n",
1669 snd_azf3328_codec_inl(
1670 codec, IDX_IO_CODEC_DMA_CURRPOS
1674 printk(KERN_WARNING "azt3328: irq handler problem!\n");
1675 if (which & IRQ_SOMETHING)
1676 snd_azf3328_irq_log_unknown_type(which);
1681 snd_azf3328_interrupt(int irq, void *dev_id)
1683 struct snd_azf3328 *chip = dev_id;
1686 static unsigned long irq_count;
1689 status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS);
1691 /* fast path out, to ease interrupt sharing */
1693 (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT
1694 |IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER)
1696 return IRQ_NONE; /* must be interrupt for another device */
1698 snd_azf3328_dbgcodec(
1699 "irq_count %ld! IDX_IO_IRQSTATUS %04x\n",
1700 irq_count++ /* debug-only */,
1704 if (status & IRQ_TIMER) {
1705 /* snd_azf3328_dbgcodec("timer %ld\n",
1706 snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE)
1710 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1712 spin_lock(&chip->reg_lock);
1713 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
1714 spin_unlock(&chip->reg_lock);
1715 snd_azf3328_dbgcodec("azt3328: timer IRQ\n");
1718 if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT))
1719 snd_azf3328_codec_interrupt(chip, status);
1721 if (status & IRQ_GAMEPORT)
1722 snd_azf3328_gameport_interrupt(chip);
1724 /* MPU401 has less critical IRQ requirements
1725 * than timer and playback/recording, right? */
1726 if (status & IRQ_MPU401) {
1727 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1729 /* hmm, do we have to ack the IRQ here somehow?
1730 * If so, then I don't know how yet... */
1731 snd_azf3328_dbgcodec("azt3328: MPU401 IRQ\n");
1736 /*****************************************************************/
1738 /* as long as we think we have identical snd_pcm_hardware parameters
1739 for playback, capture and i2s out, we can use the same physical struct
1740 since the struct is simply being copied into a member.
1742 static const struct snd_pcm_hardware snd_azf3328_hardware =
1744 /* FIXME!! Correct? */
1745 .info = SNDRV_PCM_INFO_MMAP |
1746 SNDRV_PCM_INFO_INTERLEAVED |
1747 SNDRV_PCM_INFO_MMAP_VALID,
1748 .formats = SNDRV_PCM_FMTBIT_S8 |
1749 SNDRV_PCM_FMTBIT_U8 |
1750 SNDRV_PCM_FMTBIT_S16_LE |
1751 SNDRV_PCM_FMTBIT_U16_LE,
1752 .rates = SNDRV_PCM_RATE_5512 |
1753 SNDRV_PCM_RATE_8000_48000 |
1754 SNDRV_PCM_RATE_KNOT,
1755 .rate_min = AZF_FREQ_4000,
1756 .rate_max = AZF_FREQ_66200,
1759 .buffer_bytes_max = (64*1024),
1760 .period_bytes_min = 1024,
1761 .period_bytes_max = (32*1024),
1762 /* We simply have two DMA areas (instead of a list of descriptors
1763 such as other cards); I believe that this is a fixed hardware
1764 attribute and there isn't much driver magic to be done to expand it.
1765 Thus indicate that we have at least and at most 2 periods. */
1768 /* FIXME: maybe that card actually has a FIFO?
1769 * Hmm, it seems newer revisions do have one, but we still don't know
1775 static unsigned int snd_azf3328_fixed_rates[] = {
1792 static struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
1793 .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
1794 .list = snd_azf3328_fixed_rates,
1798 /*****************************************************************/
1801 snd_azf3328_pcm_open(struct snd_pcm_substream *substream,
1802 enum snd_azf3328_codec_type codec_type
1805 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1806 struct snd_pcm_runtime *runtime = substream->runtime;
1808 snd_azf3328_dbgcallenter();
1809 chip->codecs[codec_type].substream = substream;
1811 /* same parameters for all our codecs - at least we think so... */
1812 runtime->hw = snd_azf3328_hardware;
1814 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1815 &snd_azf3328_hw_constraints_rates);
1816 snd_azf3328_dbgcallleave();
1821 snd_azf3328_playback_open(struct snd_pcm_substream *substream)
1823 return snd_azf3328_pcm_open(substream, AZF_CODEC_PLAYBACK);
1827 snd_azf3328_capture_open(struct snd_pcm_substream *substream)
1829 return snd_azf3328_pcm_open(substream, AZF_CODEC_CAPTURE);
1833 snd_azf3328_i2s_out_open(struct snd_pcm_substream *substream)
1835 return snd_azf3328_pcm_open(substream, AZF_CODEC_I2S_OUT);
1839 snd_azf3328_pcm_close(struct snd_pcm_substream *substream,
1840 enum snd_azf3328_codec_type codec_type
1843 struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
1845 snd_azf3328_dbgcallenter();
1846 chip->codecs[codec_type].substream = NULL;
1847 snd_azf3328_dbgcallleave();
1852 snd_azf3328_playback_close(struct snd_pcm_substream *substream)
1854 return snd_azf3328_pcm_close(substream, AZF_CODEC_PLAYBACK);
1858 snd_azf3328_capture_close(struct snd_pcm_substream *substream)
1860 return snd_azf3328_pcm_close(substream, AZF_CODEC_CAPTURE);
1864 snd_azf3328_i2s_out_close(struct snd_pcm_substream *substream)
1866 return snd_azf3328_pcm_close(substream, AZF_CODEC_I2S_OUT);
1869 /******************************************************************/
1871 static struct snd_pcm_ops snd_azf3328_playback_ops = {
1872 .open = snd_azf3328_playback_open,
1873 .close = snd_azf3328_playback_close,
1874 .ioctl = snd_pcm_lib_ioctl,
1875 .hw_params = snd_azf3328_hw_params,
1876 .hw_free = snd_azf3328_hw_free,
1877 .prepare = snd_azf3328_codec_prepare,
1878 .trigger = snd_azf3328_codec_playback_trigger,
1879 .pointer = snd_azf3328_codec_playback_pointer
1882 static struct snd_pcm_ops snd_azf3328_capture_ops = {
1883 .open = snd_azf3328_capture_open,
1884 .close = snd_azf3328_capture_close,
1885 .ioctl = snd_pcm_lib_ioctl,
1886 .hw_params = snd_azf3328_hw_params,
1887 .hw_free = snd_azf3328_hw_free,
1888 .prepare = snd_azf3328_codec_prepare,
1889 .trigger = snd_azf3328_codec_capture_trigger,
1890 .pointer = snd_azf3328_codec_capture_pointer
1893 static struct snd_pcm_ops snd_azf3328_i2s_out_ops = {
1894 .open = snd_azf3328_i2s_out_open,
1895 .close = snd_azf3328_i2s_out_close,
1896 .ioctl = snd_pcm_lib_ioctl,
1897 .hw_params = snd_azf3328_hw_params,
1898 .hw_free = snd_azf3328_hw_free,
1899 .prepare = snd_azf3328_codec_prepare,
1900 .trigger = snd_azf3328_codec_i2s_out_trigger,
1901 .pointer = snd_azf3328_codec_i2s_out_pointer
1904 static int __devinit
1905 snd_azf3328_pcm(struct snd_azf3328 *chip)
1907 enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS }; /* pcm devices */
1909 struct snd_pcm *pcm;
1912 snd_azf3328_dbgcallenter();
1914 err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD,
1918 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1919 &snd_azf3328_playback_ops);
1920 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1921 &snd_azf3328_capture_ops);
1923 pcm->private_data = chip;
1924 pcm->info_flags = 0;
1925 strcpy(pcm->name, chip->card->shortname);
1926 /* same pcm object for playback/capture (see snd_pcm_new() above) */
1927 chip->pcm[AZF_CODEC_PLAYBACK] = pcm;
1928 chip->pcm[AZF_CODEC_CAPTURE] = pcm;
1930 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1931 snd_dma_pci_data(chip->pci),
1934 err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT,
1938 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1939 &snd_azf3328_i2s_out_ops);
1941 pcm->private_data = chip;
1942 pcm->info_flags = 0;
1943 strcpy(pcm->name, chip->card->shortname);
1944 chip->pcm[AZF_CODEC_I2S_OUT] = pcm;
1946 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1947 snd_dma_pci_data(chip->pci),
1950 snd_azf3328_dbgcallleave();
1954 /******************************************************************/
1956 /*** NOTE: the physical timer resolution actually is 1024000 ticks per second
1957 *** (probably derived from main crystal via a divider of 24),
1958 *** but announcing those attributes to user-space would make programs
1959 *** configure the timer to a 1 tick value, resulting in an absolutely fatal
1960 *** timer IRQ storm.
1961 *** Thus I chose to announce a down-scaled virtual timer to the outside and
1962 *** calculate real timer countdown values internally.
1963 *** (the scale factor can be set via module parameter "seqtimer_scaling").
1967 snd_azf3328_timer_start(struct snd_timer *timer)
1969 struct snd_azf3328 *chip;
1970 unsigned long flags;
1973 snd_azf3328_dbgcallenter();
1974 chip = snd_timer_chip(timer);
1975 delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
1977 /* uhoh, that's not good, since user-space won't know about
1979 * (we need to do it to avoid a lockup, though) */
1981 snd_azf3328_dbgtimer("delay was too low (%d)!\n", delay);
1982 delay = 49; /* minimum time is 49 ticks */
1984 snd_azf3328_dbgtimer("setting timer countdown value %d\n", delay);
1985 delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE;
1986 spin_lock_irqsave(&chip->reg_lock, flags);
1987 snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay);
1988 spin_unlock_irqrestore(&chip->reg_lock, flags);
1989 snd_azf3328_dbgcallleave();
1994 snd_azf3328_timer_stop(struct snd_timer *timer)
1996 struct snd_azf3328 *chip;
1997 unsigned long flags;
1999 snd_azf3328_dbgcallenter();
2000 chip = snd_timer_chip(timer);
2001 spin_lock_irqsave(&chip->reg_lock, flags);
2002 /* disable timer countdown and interrupt */
2003 /* Hmm, should we write TIMER_IRQ_ACK here?
2004 YES indeed, otherwise a rogue timer operation - which prompts
2005 ALSA(?) to call repeated stop() in vain, but NOT start() -
2006 will never end (value 0x03 is kept shown in control byte).
2007 Simply manually poking 0x04 _once_ immediately successfully stops
2008 the hardware/ALSA interrupt activity. */
2009 snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04);
2010 spin_unlock_irqrestore(&chip->reg_lock, flags);
2011 snd_azf3328_dbgcallleave();
2017 snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
2018 unsigned long *num, unsigned long *den)
2020 snd_azf3328_dbgcallenter();
2022 *den = 1024000 / seqtimer_scaling;
2023 snd_azf3328_dbgcallleave();
2027 static struct snd_timer_hardware snd_azf3328_timer_hw = {
2028 .flags = SNDRV_TIMER_HW_AUTO,
2029 .resolution = 977, /* 1000000/1024000 = 0.9765625us */
2030 .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
2031 .start = snd_azf3328_timer_start,
2032 .stop = snd_azf3328_timer_stop,
2033 .precise_resolution = snd_azf3328_timer_precise_resolution,
2036 static int __devinit
2037 snd_azf3328_timer(struct snd_azf3328 *chip, int device)
2039 struct snd_timer *timer = NULL;
2040 struct snd_timer_id tid;
2043 snd_azf3328_dbgcallenter();
2044 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
2045 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
2046 tid.card = chip->card->number;
2047 tid.device = device;
2050 snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
2051 snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
2053 err = snd_timer_new(chip->card, "AZF3328", &tid, &timer);
2057 strcpy(timer->name, "AZF3328 timer");
2058 timer->private_data = chip;
2059 timer->hw = snd_azf3328_timer_hw;
2061 chip->timer = timer;
2063 snd_azf3328_timer_stop(timer);
2068 snd_azf3328_dbgcallleave();
2072 /******************************************************************/
2075 snd_azf3328_free(struct snd_azf3328 *chip)
2080 /* reset (close) mixer:
2081 * first mute master volume, then reset
2083 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
2084 snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
2086 snd_azf3328_timer_stop(chip->timer);
2087 snd_azf3328_gameport_free(chip);
2090 synchronize_irq(chip->irq);
2093 free_irq(chip->irq, chip);
2094 pci_release_regions(chip->pci);
2095 pci_disable_device(chip->pci);
2102 snd_azf3328_dev_free(struct snd_device *device)
2104 struct snd_azf3328 *chip = device->device_data;
2105 return snd_azf3328_free(chip);
2109 /* check whether a bit can be modified */
2111 snd_azf3328_test_bit(unsigned unsigned reg, int bit)
2113 unsigned char val, valoff, valon;
2117 outb(val & ~(1 << bit), reg);
2120 outb(val|(1 << bit), reg);
2125 printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n",
2126 reg, bit, val, valoff, valon
2132 snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
2137 snd_azf3328_dbgmisc(
2138 "ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, "
2139 "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n",
2140 chip->ctrl_io, chip->game_io, chip->mpu_io,
2141 chip->opl3_io, chip->mixer_io, chip->irq
2144 snd_azf3328_dbgmisc("game %02x %02x %02x %02x %02x %02x\n",
2145 snd_azf3328_game_inb(chip, 0),
2146 snd_azf3328_game_inb(chip, 1),
2147 snd_azf3328_game_inb(chip, 2),
2148 snd_azf3328_game_inb(chip, 3),
2149 snd_azf3328_game_inb(chip, 4),
2150 snd_azf3328_game_inb(chip, 5)
2153 for (tmp = 0; tmp < 0x07; tmp += 1)
2154 snd_azf3328_dbgmisc("mpu_io 0x%04x\n", inb(chip->mpu_io + tmp));
2156 for (tmp = 0; tmp <= 0x07; tmp += 1)
2157 snd_azf3328_dbgmisc("0x%02x: game200 0x%04x, game208 0x%04x\n",
2158 tmp, inb(0x200 + tmp), inb(0x208 + tmp));
2160 for (tmp = 0; tmp <= 0x01; tmp += 1)
2161 snd_azf3328_dbgmisc(
2162 "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, "
2163 "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n",
2173 for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2)
2174 snd_azf3328_dbgmisc("ctrl 0x%02x: 0x%04x\n",
2175 tmp, snd_azf3328_ctrl_inw(chip, tmp)
2178 for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2)
2179 snd_azf3328_dbgmisc("mixer 0x%02x: 0x%04x\n",
2180 tmp, snd_azf3328_mixer_inw(chip, tmp)
2182 #endif /* DEBUG_MISC */
2185 static int __devinit
2186 snd_azf3328_create(struct snd_card *card,
2187 struct pci_dev *pci,
2188 unsigned long device_type,
2189 struct snd_azf3328 **rchip)
2191 struct snd_azf3328 *chip;
2193 static struct snd_device_ops ops = {
2194 .dev_free = snd_azf3328_dev_free,
2197 enum snd_azf3328_codec_type codec_type;
2198 struct snd_azf3328_codec *codec_setup;
2202 err = pci_enable_device(pci);
2206 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2211 spin_lock_init(&chip->reg_lock);
2216 /* check if we can restrict PCI DMA transfers to 24 bits */
2217 if (pci_set_dma_mask(pci, DMA_BIT_MASK(24)) < 0 ||
2218 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(24)) < 0) {
2219 snd_printk(KERN_ERR "architecture does not support "
2220 "24bit PCI busmaster DMA\n"
2226 err = pci_request_regions(pci, "Aztech AZF3328");
2230 chip->ctrl_io = pci_resource_start(pci, 0);
2231 chip->game_io = pci_resource_start(pci, 1);
2232 chip->mpu_io = pci_resource_start(pci, 2);
2233 chip->opl3_io = pci_resource_start(pci, 3);
2234 chip->mixer_io = pci_resource_start(pci, 4);
2236 codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK];
2237 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK;
2238 codec_setup->name = "PLAYBACK";
2240 codec_setup = &chip->codecs[AZF_CODEC_CAPTURE];
2241 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE;
2242 codec_setup->name = "CAPTURE";
2244 codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT];
2245 codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT;
2246 codec_setup->name = "I2S_OUT";
2248 if (request_irq(pci->irq, snd_azf3328_interrupt,
2249 IRQF_SHARED, card->shortname, chip)) {
2250 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2254 chip->irq = pci->irq;
2255 pci_set_master(pci);
2256 synchronize_irq(chip->irq);
2258 snd_azf3328_debug_show_ports(chip);
2260 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2264 /* create mixer interface & switches */
2265 err = snd_azf3328_mixer_new(chip);
2269 /* standard codec init stuff */
2270 /* default DMA init value */
2271 dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
2273 for (codec_type = AZF_CODEC_PLAYBACK;
2274 codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) {
2275 struct snd_azf3328_codec_data *codec =
2276 &chip->codecs[codec_type];
2278 /* shutdown codecs to reduce power / noise */
2279 /* have ...ctrl_codec_activity() act properly */
2281 snd_azf3328_ctrl_codec_activity(chip, codec_type, 0);
2283 spin_lock_irq(&chip->reg_lock);
2284 snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS,
2286 spin_unlock_irq(&chip->reg_lock);
2289 snd_card_set_dev(card, &pci->dev);
2298 snd_azf3328_free(chip);
2299 pci_disable_device(pci);
2305 static int __devinit
2306 snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2309 struct snd_card *card;
2310 struct snd_azf3328 *chip;
2311 struct snd_opl3 *opl3;
2314 snd_azf3328_dbgcallenter();
2315 if (dev >= SNDRV_CARDS)
2322 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2326 strcpy(card->driver, "AZF3328");
2327 strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
2329 err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip);
2333 card->private_data = chip;
2335 /* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401,
2336 since our hardware ought to be similar, thus use same ID. */
2337 err = snd_mpu401_uart_new(
2339 MPU401_HW_AZT2320, chip->mpu_io, MPU401_INFO_INTEGRATED,
2340 pci->irq, 0, &chip->rmidi
2343 snd_printk(KERN_ERR "azf3328: no MPU-401 device at 0x%lx?\n",
2349 err = snd_azf3328_timer(chip, 0);
2353 err = snd_azf3328_pcm(chip);
2357 if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2,
2358 OPL3_HW_AUTO, 1, &opl3) < 0) {
2359 snd_printk(KERN_ERR "azf3328: no OPL3 device at 0x%lx-0x%lx?\n",
2360 chip->opl3_io, chip->opl3_io+2
2363 /* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */
2364 err = snd_opl3_timer_new(opl3, 1, 2);
2367 err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
2372 opl3->private_data = chip;
2374 sprintf(card->longname, "%s at 0x%lx, irq %i",
2375 card->shortname, chip->ctrl_io, chip->irq);
2377 err = snd_card_register(card);
2383 "azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n"
2384 "azt3328: Hardware was completely undocumented, unfortunately.\n"
2385 "azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n"
2386 "azt3328: User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
2387 1024000 / seqtimer_scaling, seqtimer_scaling);
2390 snd_azf3328_gameport(chip, dev);
2392 pci_set_drvdata(pci, card);
2399 snd_printk(KERN_ERR "azf3328: something failed, exiting\n");
2400 snd_card_free(card);
2403 snd_azf3328_dbgcallleave();
2407 static void __devexit
2408 snd_azf3328_remove(struct pci_dev *pci)
2410 snd_azf3328_dbgcallenter();
2411 snd_card_free(pci_get_drvdata(pci));
2412 pci_set_drvdata(pci, NULL);
2413 snd_azf3328_dbgcallleave();
2418 snd_azf3328_suspend_regs(unsigned long io_addr, unsigned count, u32 *saved_regs)
2422 for (reg = 0; reg < count; ++reg) {
2423 *saved_regs = inl(io_addr);
2424 snd_azf3328_dbgpm("suspend: io 0x%04lx: 0x%08x\n",
2425 io_addr, *saved_regs);
2427 io_addr += sizeof(*saved_regs);
2432 snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state)
2434 struct snd_card *card = pci_get_drvdata(pci);
2435 struct snd_azf3328 *chip = card->private_data;
2436 u16 *saved_regs_ctrl_u16;
2438 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2440 /* same pcm object for playback/capture */
2441 snd_pcm_suspend_all(chip->pcm[AZF_CODEC_PLAYBACK]);
2442 snd_pcm_suspend_all(chip->pcm[AZF_CODEC_I2S_OUT]);
2444 snd_azf3328_suspend_regs(chip->mixer_io,
2445 ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer);
2447 /* make sure to disable master volume etc. to prevent looping sound */
2448 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
2449 snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
2451 snd_azf3328_suspend_regs(chip->ctrl_io,
2452 ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl);
2454 /* manually store the one currently relevant write-only reg, too */
2455 saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl;
2456 saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH;
2458 snd_azf3328_suspend_regs(chip->game_io,
2459 ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game);
2460 snd_azf3328_suspend_regs(chip->mpu_io,
2461 ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu);
2462 snd_azf3328_suspend_regs(chip->opl3_io,
2463 ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3);
2465 pci_disable_device(pci);
2466 pci_save_state(pci);
2467 pci_set_power_state(pci, pci_choose_state(pci, state));
2472 snd_azf3328_resume_regs(const u32 *saved_regs,
2473 unsigned long io_addr,
2479 for (reg = 0; reg < count; ++reg) {
2480 outl(*saved_regs, io_addr);
2481 snd_azf3328_dbgpm("resume: io 0x%04lx: 0x%08x --> 0x%08x\n",
2482 io_addr, *saved_regs, inl(io_addr));
2484 io_addr += sizeof(*saved_regs);
2489 snd_azf3328_resume(struct pci_dev *pci)
2491 struct snd_card *card = pci_get_drvdata(pci);
2492 const struct snd_azf3328 *chip = card->private_data;
2494 pci_set_power_state(pci, PCI_D0);
2495 pci_restore_state(pci);
2496 if (pci_enable_device(pci) < 0) {
2497 printk(KERN_ERR "azt3328: pci_enable_device failed, "
2498 "disabling device\n");
2499 snd_card_disconnect(card);
2502 pci_set_master(pci);
2504 snd_azf3328_resume_regs(chip->saved_regs_game, chip->game_io,
2505 ARRAY_SIZE(chip->saved_regs_game));
2506 snd_azf3328_resume_regs(chip->saved_regs_mpu, chip->mpu_io,
2507 ARRAY_SIZE(chip->saved_regs_mpu));
2508 snd_azf3328_resume_regs(chip->saved_regs_opl3, chip->opl3_io,
2509 ARRAY_SIZE(chip->saved_regs_opl3));
2511 snd_azf3328_resume_regs(chip->saved_regs_mixer, chip->mixer_io,
2512 ARRAY_SIZE(chip->saved_regs_mixer));
2514 /* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02)
2515 and IDX_MIXER_RESET (offset 0x00) get touched at the same time,
2516 resulting in a mixer reset condition persisting until _after_
2517 master vol was restored. Thus master vol needs an extra restore. */
2518 outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2);
2520 snd_azf3328_resume_regs(chip->saved_regs_ctrl, chip->ctrl_io,
2521 ARRAY_SIZE(chip->saved_regs_ctrl));
2523 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2526 #endif /* CONFIG_PM */
2529 static struct pci_driver driver = {
2531 .id_table = snd_azf3328_ids,
2532 .probe = snd_azf3328_probe,
2533 .remove = __devexit_p(snd_azf3328_remove),
2535 .suspend = snd_azf3328_suspend,
2536 .resume = snd_azf3328_resume,
2541 alsa_card_azf3328_init(void)
2544 snd_azf3328_dbgcallenter();
2545 err = pci_register_driver(&driver);
2546 snd_azf3328_dbgcallleave();
2551 alsa_card_azf3328_exit(void)
2553 snd_azf3328_dbgcallenter();
2554 pci_unregister_driver(&driver);
2555 snd_azf3328_dbgcallleave();
2558 module_init(alsa_card_azf3328_init)
2559 module_exit(alsa_card_azf3328_exit)