sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #include <linux/pm_runtime.h>
  50 #include <linux/clocksource.h>
  51 #include <linux/time.h>
  52 #include <linux/completion.h>
  53
  54 #ifdef CONFIG_X86
  55 /* for snoop control */
  56 #include <asm/pgtable.h>
  57 #include <asm/cacheflush.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <linux/vgaarb.h>
  62 #include <linux/vga_switcheroo.h>
  63 #include <linux/firmware.h>
  64 #include "hda_codec.h"
  65
  66
  67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  70 static char *model[SNDRV_CARDS];
  71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  74 static int probe_only[SNDRV_CARDS];
  75 static int jackpoll_ms[SNDRV_CARDS];
  76 static bool single_cmd;
  77 static int enable_msi = -1;
  78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  79 static char *patch[SNDRV_CARDS];
  80 #endif
  81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  83                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  84 #endif
  85
  86 module_param_array(index, int, NULL, 0444);
  87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  88 module_param_array(id, charp, NULL, 0444);
  89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  90 module_param_array(enable, bool, NULL, 0444);
  91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  92 module_param_array(model, charp, NULL, 0444);
  93 MODULE_PARM_DESC(model, "Use the given board model.");
  94 module_param_array(position_fix, int, NULL, 0444);
  95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  96                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
  97 module_param_array(bdl_pos_adj, int, NULL, 0644);
  98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  99 module_param_array(probe_mask, int, NULL, 0444);
 100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 101 module_param_array(probe_only, int, NULL, 0444);
 102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 103 module_param_array(jackpoll_ms, int, NULL, 0444);
 104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 105 module_param(single_cmd, bool, 0444);
 106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 107                  "(for debugging only).");
 108 module_param(enable_msi, bint, 0444);
 109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 111 module_param_array(patch, charp, NULL, 0444);
 112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 113 #endif
 114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 115 module_param_array(beep_mode, bool, NULL, 0444);
 116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 117                             "(0=off, 1=on) (default=1).");
 118 #endif
 119
 120 #ifdef CONFIG_PM
 121 static int param_set_xint(const char *val, const struct kernel_param *kp);
 122 static struct kernel_param_ops param_ops_xint = {
 123         .set = param_set_xint,
 124         .get = param_get_int,
 125 };
 126 #define param_check_xint param_check_int
 127
 128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 129 module_param(power_save, xint, 0644);
 130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 131                  "(in second, 0 = disable).");
 132
 133 /* reset the HD-audio controller in power save mode.
 134  * this may give more power-saving, but will take longer time to
 135  * wake up.
 136  */
 137 static int power_save_controller = -1;
 138 module_param(power_save_controller, bint, 0644);
 139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 140 #endif /* CONFIG_PM */
 141
 142 static int align_buffer_size = -1;
 143 module_param(align_buffer_size, bint, 0644);
 144 MODULE_PARM_DESC(align_buffer_size,
 145                 "Force buffer and period sizes to be multiple of 128 bytes.");
 146
 147 #ifdef CONFIG_X86
 148 static bool hda_snoop = true;
 149 module_param_named(snoop, hda_snoop, bool, 0444);
 150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 151 #define azx_snoop(chip)         (chip)->snoop
 152 #else
 153 #define hda_snoop               true
 154 #define azx_snoop(chip)         true
 155 #endif
 156
 157
 158 MODULE_LICENSE("GPL");
 159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 160                          "{Intel, ICH6M},"
 161                          "{Intel, ICH7},"
 162                          "{Intel, ESB2},"
 163                          "{Intel, ICH8},"
 164                          "{Intel, ICH9},"
 165                          "{Intel, ICH10},"
 166                          "{Intel, PCH},"
 167                          "{Intel, CPT},"
 168                          "{Intel, PPT},"
 169                          "{Intel, LPT},"
 170                          "{Intel, LPT_LP},"
 171                          "{Intel, HPT},"
 172                          "{Intel, PBG},"
 173                          "{Intel, SCH},"
 174                          "{ATI, SB450},"
 175                          "{ATI, SB600},"
 176                          "{ATI, RS600},"
 177                          "{ATI, RS690},"
 178                          "{ATI, RS780},"
 179                          "{ATI, R600},"
 180                          "{ATI, RV630},"
 181                          "{ATI, RV610},"
 182                          "{ATI, RV670},"
 183                          "{ATI, RV635},"
 184                          "{ATI, RV620},"
 185                          "{ATI, RV770},"
 186                          "{VIA, VT8251},"
 187                          "{VIA, VT8237A},"
 188                          "{SiS, SIS966},"
 189                          "{ULI, M5461}}");
 190 MODULE_DESCRIPTION("Intel HDA driver");
 191
 192 #ifdef CONFIG_SND_VERBOSE_PRINTK
 193 #define SFX     /* nop */
 194 #else
 195 #define SFX     "hda-intel "
 196 #endif
 197
 198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
 200 #define SUPPORT_VGA_SWITCHEROO
 201 #endif
 202 #endif
 203
 204
 205 /*
 206  * registers
 207  */
 208 #define ICH6_REG_GCAP                   0x00
 209 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 210 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 211 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 212 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 213 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 214 #define ICH6_REG_VMIN                   0x02
 215 #define ICH6_REG_VMAJ                   0x03
 216 #define ICH6_REG_OUTPAY                 0x04
 217 #define ICH6_REG_INPAY                  0x06
 218 #define ICH6_REG_GCTL                   0x08
 219 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 220 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 221 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 222 #define ICH6_REG_WAKEEN                 0x0c
 223 #define ICH6_REG_STATESTS               0x0e
 224 #define ICH6_REG_GSTS                   0x10
 225 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 226 #define ICH6_REG_INTCTL                 0x20
 227 #define ICH6_REG_INTSTS                 0x24
 228 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 229 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 230 #define ICH6_REG_SSYNC                  0x38
 231 #define ICH6_REG_CORBLBASE              0x40
 232 #define ICH6_REG_CORBUBASE              0x44
 233 #define ICH6_REG_CORBWP                 0x48
 234 #define ICH6_REG_CORBRP                 0x4a
 235 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 236 #define ICH6_REG_CORBCTL                0x4c
 237 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 238 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 239 #define ICH6_REG_CORBSTS                0x4d
 240 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 241 #define ICH6_REG_CORBSIZE               0x4e
 242
 243 #define ICH6_REG_RIRBLBASE              0x50
 244 #define ICH6_REG_RIRBUBASE              0x54
 245 #define ICH6_REG_RIRBWP                 0x58
 246 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 247 #define ICH6_REG_RINTCNT                0x5a
 248 #define ICH6_REG_RIRBCTL                0x5c
 249 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 250 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 251 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 252 #define ICH6_REG_RIRBSTS                0x5d
 253 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 254 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 255 #define ICH6_REG_RIRBSIZE               0x5e
 256
 257 #define ICH6_REG_IC                     0x60
 258 #define ICH6_REG_IR                     0x64
 259 #define ICH6_REG_IRS                    0x68
 260 #define   ICH6_IRS_VALID        (1<<1)
 261 #define   ICH6_IRS_BUSY         (1<<0)
 262
 263 #define ICH6_REG_DPLBASE                0x70
 264 #define ICH6_REG_DPUBASE                0x74
 265 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 266
 267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 269
 270 /* stream register offsets from stream base */
 271 #define ICH6_REG_SD_CTL                 0x00
 272 #define ICH6_REG_SD_STS                 0x03
 273 #define ICH6_REG_SD_LPIB                0x04
 274 #define ICH6_REG_SD_CBL                 0x08
 275 #define ICH6_REG_SD_LVI                 0x0c
 276 #define ICH6_REG_SD_FIFOW               0x0e
 277 #define ICH6_REG_SD_FIFOSIZE            0x10
 278 #define ICH6_REG_SD_FORMAT              0x12
 279 #define ICH6_REG_SD_BDLPL               0x18
 280 #define ICH6_REG_SD_BDLPU               0x1c
 281
 282 /* PCI space */
 283 #define ICH6_PCIREG_TCSEL       0x44
 284
 285 /*
 286  * other constants
 287  */
 288
 289 /* max number of SDs */
 290 /* ICH, ATI and VIA have 4 playback and 4 capture */
 291 #define ICH6_NUM_CAPTURE        4
 292 #define ICH6_NUM_PLAYBACK       4
 293
 294 /* ULI has 6 playback and 5 capture */
 295 #define ULI_NUM_CAPTURE         5
 296 #define ULI_NUM_PLAYBACK        6
 297
 298 /* ATI HDMI has 1 playback and 0 capture */
 299 #define ATIHDMI_NUM_CAPTURE     0
 300 #define ATIHDMI_NUM_PLAYBACK    1
 301
 302 /* TERA has 4 playback and 3 capture */
 303 #define TERA_NUM_CAPTURE        3
 304 #define TERA_NUM_PLAYBACK       4
 305
 306 /* this number is statically defined for simplicity */
 307 #define MAX_AZX_DEV             16
 308
 309 /* max number of fragments - we may use more if allocating more pages for BDL */
 310 #define BDL_SIZE                4096
 311 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 312 #define AZX_MAX_FRAG            32
 313 /* max buffer size - no h/w limit, you can increase as you like */
 314 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 315
 316 /* RIRB int mask: overrun[2], response[0] */
 317 #define RIRB_INT_RESPONSE       0x01
 318 #define RIRB_INT_OVERRUN        0x04
 319 #define RIRB_INT_MASK           0x05
 320
 321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 322 #define AZX_MAX_CODECS          8
 323 #define AZX_DEFAULT_CODECS      4
 324 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 325
 326 /* SD_CTL bits */
 327 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 328 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 329 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 330 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 331 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 332 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 333 #define SD_CTL_STREAM_TAG_SHIFT 20
 334
 335 /* SD_CTL and SD_STS */
 336 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 337 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 338 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 339 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 340                                  SD_INT_COMPLETE)
 341
 342 /* SD_STS */
 343 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 344
 345 /* INTCTL and INTSTS */
 346 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 347 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 348 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 349
 350 /* below are so far hardcoded - should read registers in future */
 351 #define ICH6_MAX_CORB_ENTRIES   256
 352 #define ICH6_MAX_RIRB_ENTRIES   256
 353
 354 /* position fix mode */
 355 enum {
 356         POS_FIX_AUTO,
 357         POS_FIX_LPIB,
 358         POS_FIX_POSBUF,
 359         POS_FIX_VIACOMBO,
 360         POS_FIX_COMBO,
 361 };
 362
 363 /* Defines for ATI HD Audio support in SB450 south bridge */
 364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 366
 367 /* Defines for Nvidia HDA support */
 368 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 369 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 370 #define NVIDIA_HDA_ISTRM_COH          0x4d
 371 #define NVIDIA_HDA_OSTRM_COH          0x4c
 372 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 373
 374 /* Defines for Intel SCH HDA snoop control */
 375 #define INTEL_SCH_HDA_DEVC      0x78
 376 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 377
 378 /* Define IN stream 0 FIFO size offset in VIA controller */
 379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 380 /* Define VIA HD Audio Device ID*/
 381 #define VIA_HDAC_DEVICE_ID              0x3288
 382
 383 /* HD Audio class code */
 384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 385
 386 /*
 387  */
 388
 389 struct azx_dev {
 390         struct snd_dma_buffer bdl; /* BDL buffer */
 391         u32 *posbuf;            /* position buffer pointer */
 392
 393         unsigned int bufsize;   /* size of the play buffer in bytes */
 394         unsigned int period_bytes; /* size of the period in bytes */
 395         unsigned int frags;     /* number for period in the play buffer */
 396         unsigned int fifo_size; /* FIFO size */
 397         unsigned long start_wallclk;    /* start + minimum wallclk */
 398         unsigned long period_wallclk;   /* wallclk for period */
 399
 400         void __iomem *sd_addr;  /* stream descriptor pointer */
 401
 402         u32 sd_int_sta_mask;    /* stream int status mask */
 403
 404         /* pcm support */
 405         struct snd_pcm_substream *substream;    /* assigned substream,
 406                                                  * set in PCM open
 407                                                  */
 408         unsigned int format_val;        /* format value to be set in the
 409                                          * controller and the codec
 410                                          */
 411         unsigned char stream_tag;       /* assigned stream */
 412         unsigned char index;            /* stream index */
 413         int assigned_key;               /* last device# key assigned to */
 414
 415         unsigned int opened :1;
 416         unsigned int running :1;
 417         unsigned int irq_pending :1;
 418         /*
 419          * For VIA:
 420          *  A flag to ensure DMA position is 0
 421          *  when link position is not greater than FIFO size
 422          */
 423         unsigned int insufficient :1;
 424         unsigned int wc_marked:1;
 425         unsigned int no_period_wakeup:1;
 426
 427         struct timecounter  azx_tc;
 428         struct cyclecounter azx_cc;
 429 };
 430
 431 /* CORB/RIRB */
 432 struct azx_rb {
 433         u32 *buf;               /* CORB/RIRB buffer
 434                                  * Each CORB entry is 4byte, RIRB is 8byte
 435                                  */
 436         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 437         /* for RIRB */
 438         unsigned short rp, wp;  /* read/write pointers */
 439         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 440         u32 res[AZX_MAX_CODECS];        /* last read value */
 441 };
 442
 443 struct azx_pcm {
 444         struct azx *chip;
 445         struct snd_pcm *pcm;
 446         struct hda_codec *codec;
 447         struct hda_pcm_stream *hinfo[2];
 448         struct list_head list;
 449 };
 450
 451 struct azx {
 452         struct snd_card *card;
 453         struct pci_dev *pci;
 454         int dev_index;
 455
 456         /* chip type specific */
 457         int driver_type;
 458         unsigned int driver_caps;
 459         int playback_streams;
 460         int playback_index_offset;
 461         int capture_streams;
 462         int capture_index_offset;
 463         int num_streams;
 464
 465         /* pci resources */
 466         unsigned long addr;
 467         void __iomem *remap_addr;
 468         int irq;
 469
 470         /* locks */
 471         spinlock_t reg_lock;
 472         struct mutex open_mutex;
 473         struct completion probe_wait;
 474
 475         /* streams (x num_streams) */
 476         struct azx_dev *azx_dev;
 477
 478         /* PCM */
 479         struct list_head pcm_list; /* azx_pcm list */
 480
 481         /* HD codec */
 482         unsigned short codec_mask;
 483         int  codec_probe_mask; /* copied from probe_mask option */
 484         struct hda_bus *bus;
 485         unsigned int beep_mode;
 486
 487         /* CORB/RIRB */
 488         struct azx_rb corb;
 489         struct azx_rb rirb;
 490
 491         /* CORB/RIRB and position buffers */
 492         struct snd_dma_buffer rb;
 493         struct snd_dma_buffer posbuf;
 494
 495 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 496         const struct firmware *fw;
 497 #endif
 498
 499         /* flags */
 500         int position_fix[2]; /* for both playback/capture streams */
 501         int poll_count;
 502         unsigned int running :1;
 503         unsigned int initialized :1;
 504         unsigned int single_cmd :1;
 505         unsigned int polling_mode :1;
 506         unsigned int msi :1;
 507         unsigned int irq_pending_warned :1;
 508         unsigned int probing :1; /* codec probing phase */
 509         unsigned int snoop:1;
 510         unsigned int align_buffer_size:1;
 511         unsigned int region_requested:1;
 512
 513         /* VGA-switcheroo setup */
 514         unsigned int use_vga_switcheroo:1;
 515         unsigned int vga_switcheroo_registered:1;
 516         unsigned int init_failed:1; /* delayed init failed */
 517         unsigned int disabled:1; /* disabled by VGA-switcher */
 518
 519         /* for debugging */
 520         unsigned int last_cmd[AZX_MAX_CODECS];
 521
 522         /* for pending irqs */
 523         struct work_struct irq_pending_work;
 524
 525         /* reboot notifier (for mysterious hangup problem at power-down) */
 526         struct notifier_block reboot_notifier;
 527
 528         /* card list (for power_save trigger) */
 529         struct list_head list;
 530 };
 531
 532 #define CREATE_TRACE_POINTS
 533 #include "hda_intel_trace.h"
 534
 535 /* driver types */
 536 enum {
 537         AZX_DRIVER_ICH,
 538         AZX_DRIVER_PCH,
 539         AZX_DRIVER_SCH,
 540         AZX_DRIVER_ATI,
 541         AZX_DRIVER_ATIHDMI,
 542         AZX_DRIVER_ATIHDMI_NS,
 543         AZX_DRIVER_VIA,
 544         AZX_DRIVER_SIS,
 545         AZX_DRIVER_ULI,
 546         AZX_DRIVER_NVIDIA,
 547         AZX_DRIVER_TERA,
 548         AZX_DRIVER_CTX,
 549         AZX_DRIVER_CTHDA,
 550         AZX_DRIVER_GENERIC,
 551         AZX_NUM_DRIVERS, /* keep this as last entry */
 552 };
 553
 554 /* driver quirks (capabilities) */
 555 /* bits 0-7 are used for indicating driver type */
 556 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 557 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 558 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 559 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 560 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 561 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 562 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 563 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 564 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 565 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 566 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 567 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 568 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 569 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 570 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
 571 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
 572 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
 573 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
 574
 575 /* quirks for Intel PCH */
 576 #define AZX_DCAPS_INTEL_PCH_NOPM \
 577         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
 578          AZX_DCAPS_COUNT_LPIB_DELAY)
 579
 580 #define AZX_DCAPS_INTEL_PCH \
 581         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
 582
 583 /* quirks for ATI SB / AMD Hudson */
 584 #define AZX_DCAPS_PRESET_ATI_SB \
 585         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 586          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 587
 588 /* quirks for ATI/AMD HDMI */
 589 #define AZX_DCAPS_PRESET_ATI_HDMI \
 590         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 591
 592 /* quirks for Nvidia */
 593 #define AZX_DCAPS_PRESET_NVIDIA \
 594         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
 595          AZX_DCAPS_ALIGN_BUFSIZE)
 596
 597 #define AZX_DCAPS_PRESET_CTHDA \
 598         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
 599
 600 /*
 601  * VGA-switcher support
 602  */
 603 #ifdef SUPPORT_VGA_SWITCHEROO
 604 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 605 #else
 606 #define use_vga_switcheroo(chip)        0
 607 #endif
 608
 609 static char *driver_short_names[] = {
 610         [AZX_DRIVER_ICH] = "HDA Intel",
 611         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 612         [AZX_DRIVER_SCH] = "HDA Intel MID",
 613         [AZX_DRIVER_ATI] = "HDA ATI SB",
 614         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 615         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 616         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 617         [AZX_DRIVER_SIS] = "HDA SIS966",
 618         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 619         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 620         [AZX_DRIVER_TERA] = "HDA Teradici",
 621         [AZX_DRIVER_CTX] = "HDA Creative",
 622         [AZX_DRIVER_CTHDA] = "HDA Creative",
 623         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 624 };
 625
 626 /*
 627  * macros for easy use
 628  */
 629 #define azx_writel(chip,reg,value) \
 630         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 631 #define azx_readl(chip,reg) \
 632         readl((chip)->remap_addr + ICH6_REG_##reg)
 633 #define azx_writew(chip,reg,value) \
 634         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 635 #define azx_readw(chip,reg) \
 636         readw((chip)->remap_addr + ICH6_REG_##reg)
 637 #define azx_writeb(chip,reg,value) \
 638         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 639 #define azx_readb(chip,reg) \
 640         readb((chip)->remap_addr + ICH6_REG_##reg)
 641
 642 #define azx_sd_writel(dev,reg,value) \
 643         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 644 #define azx_sd_readl(dev,reg) \
 645         readl((dev)->sd_addr + ICH6_REG_##reg)
 646 #define azx_sd_writew(dev,reg,value) \
 647         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 648 #define azx_sd_readw(dev,reg) \
 649         readw((dev)->sd_addr + ICH6_REG_##reg)
 650 #define azx_sd_writeb(dev,reg,value) \
 651         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 652 #define azx_sd_readb(dev,reg) \
 653         readb((dev)->sd_addr + ICH6_REG_##reg)
 654
 655 /* for pcm support */
 656 #define get_azx_dev(substream) (substream->runtime->private_data)
 657
 658 #ifdef CONFIG_X86
 659 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
 660 {
 661         if (azx_snoop(chip))
 662                 return;
 663         if (addr && size) {
 664                 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 665                 if (on)
 666                         set_memory_wc((unsigned long)addr, pages);
 667                 else
 668                         set_memory_wb((unsigned long)addr, pages);
 669         }
 670 }
 671
 672 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 673                                  bool on)
 674 {
 675         __mark_pages_wc(chip, buf->area, buf->bytes, on);
 676 }
 677 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 678                                    struct snd_pcm_runtime *runtime, bool on)
 679 {
 680         if (azx_dev->wc_marked != on) {
 681                 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
 682                 azx_dev->wc_marked = on;
 683         }
 684 }
 685 #else
 686 /* NOP for other archs */
 687 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 688                                  bool on)
 689 {
 690 }
 691 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 692                                    struct snd_pcm_runtime *runtime, bool on)
 693 {
 694 }
 695 #endif
 696
 697 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 698 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 699 /*
 700  * Interface for HD codec
 701  */
 702
 703 /*
 704  * CORB / RIRB interface
 705  */
 706 static int azx_alloc_cmd_io(struct azx *chip)
 707 {
 708         int err;
 709
 710         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 711         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 712                                   snd_dma_pci_data(chip->pci),
 713                                   PAGE_SIZE, &chip->rb);
 714         if (err < 0) {
 715                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
 716                 return err;
 717         }
 718         mark_pages_wc(chip, &chip->rb, true);
 719         return 0;
 720 }
 721
 722 static void azx_init_cmd_io(struct azx *chip)
 723 {
 724         spin_lock_irq(&chip->reg_lock);
 725         /* CORB set up */
 726         chip->corb.addr = chip->rb.addr;
 727         chip->corb.buf = (u32 *)chip->rb.area;
 728         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 729         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 730
 731         /* set the corb size to 256 entries (ULI requires explicitly) */
 732         azx_writeb(chip, CORBSIZE, 0x02);
 733         /* set the corb write pointer to 0 */
 734         azx_writew(chip, CORBWP, 0);
 735         /* reset the corb hw read pointer */
 736         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 737         /* enable corb dma */
 738         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 739
 740         /* RIRB set up */
 741         chip->rirb.addr = chip->rb.addr + 2048;
 742         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 743         chip->rirb.wp = chip->rirb.rp = 0;
 744         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 745         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 746         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 747
 748         /* set the rirb size to 256 entries (ULI requires explicitly) */
 749         azx_writeb(chip, RIRBSIZE, 0x02);
 750         /* reset the rirb hw write pointer */
 751         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 752         /* set N=1, get RIRB response interrupt for new entry */
 753         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 754                 azx_writew(chip, RINTCNT, 0xc0);
 755         else
 756                 azx_writew(chip, RINTCNT, 1);
 757         /* enable rirb dma and response irq */
 758         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 759         spin_unlock_irq(&chip->reg_lock);
 760 }
 761
 762 static void azx_free_cmd_io(struct azx *chip)
 763 {
 764         spin_lock_irq(&chip->reg_lock);
 765         /* disable ringbuffer DMAs */
 766         azx_writeb(chip, RIRBCTL, 0);
 767         azx_writeb(chip, CORBCTL, 0);
 768         spin_unlock_irq(&chip->reg_lock);
 769 }
 770
 771 static unsigned int azx_command_addr(u32 cmd)
 772 {
 773         unsigned int addr = cmd >> 28;
 774
 775         if (addr >= AZX_MAX_CODECS) {
 776                 snd_BUG();
 777                 addr = 0;
 778         }
 779
 780         return addr;
 781 }
 782
 783 static unsigned int azx_response_addr(u32 res)
 784 {
 785         unsigned int addr = res & 0xf;
 786
 787         if (addr >= AZX_MAX_CODECS) {
 788                 snd_BUG();
 789                 addr = 0;
 790         }
 791
 792         return addr;
 793 }
 794
 795 /* send a command */
 796 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 797 {
 798         struct azx *chip = bus->private_data;
 799         unsigned int addr = azx_command_addr(val);
 800         unsigned int wp, rp;
 801
 802         spin_lock_irq(&chip->reg_lock);
 803
 804         /* add command to corb */
 805         wp = azx_readw(chip, CORBWP);
 806         if (wp == 0xffff) {
 807                 /* something wrong, controller likely turned to D3 */
 808                 spin_unlock_irq(&chip->reg_lock);
 809                 return -EIO;
 810         }
 811         wp++;
 812         wp %= ICH6_MAX_CORB_ENTRIES;
 813
 814         rp = azx_readw(chip, CORBRP);
 815         if (wp == rp) {
 816                 /* oops, it's full */
 817                 spin_unlock_irq(&chip->reg_lock);
 818                 return -EAGAIN;
 819         }
 820
 821         chip->rirb.cmds[addr]++;
 822         chip->corb.buf[wp] = cpu_to_le32(val);
 823         azx_writel(chip, CORBWP, wp);
 824
 825         spin_unlock_irq(&chip->reg_lock);
 826
 827         return 0;
 828 }
 829
 830 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 831
 832 /* retrieve RIRB entry - called from interrupt handler */
 833 static void azx_update_rirb(struct azx *chip)
 834 {
 835         unsigned int rp, wp;
 836         unsigned int addr;
 837         u32 res, res_ex;
 838
 839         wp = azx_readw(chip, RIRBWP);
 840         if (wp == 0xffff) {
 841                 /* something wrong, controller likely turned to D3 */
 842                 return;
 843         }
 844
 845         if (wp == chip->rirb.wp)
 846                 return;
 847         chip->rirb.wp = wp;
 848
 849         while (chip->rirb.rp != wp) {
 850                 chip->rirb.rp++;
 851                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 852
 853                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 854                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 855                 res = le32_to_cpu(chip->rirb.buf[rp]);
 856                 addr = azx_response_addr(res_ex);
 857                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 858                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 859                 else if (chip->rirb.cmds[addr]) {
 860                         chip->rirb.res[addr] = res;
 861                         smp_wmb();
 862                         chip->rirb.cmds[addr]--;
 863                 } else
 864                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
 865                                    "last cmd=%#08x\n",
 866                                    pci_name(chip->pci),
 867                                    res, res_ex,
 868                                    chip->last_cmd[addr]);
 869         }
 870 }
 871
 872 /* receive a response */
 873 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 874                                           unsigned int addr)
 875 {
 876         struct azx *chip = bus->private_data;
 877         unsigned long timeout;
 878         unsigned long loopcounter;
 879         int do_poll = 0;
 880
 881  again:
 882         timeout = jiffies + msecs_to_jiffies(1000);
 883
 884         for (loopcounter = 0;; loopcounter++) {
 885                 if (chip->polling_mode || do_poll) {
 886                         spin_lock_irq(&chip->reg_lock);
 887                         azx_update_rirb(chip);
 888                         spin_unlock_irq(&chip->reg_lock);
 889                 }
 890                 if (!chip->rirb.cmds[addr]) {
 891                         smp_rmb();
 892                         bus->rirb_error = 0;
 893
 894                         if (!do_poll)
 895                                 chip->poll_count = 0;
 896                         return chip->rirb.res[addr]; /* the last value */
 897                 }
 898                 if (time_after(jiffies, timeout))
 899                         break;
 900                 if (bus->needs_damn_long_delay || loopcounter > 3000)
 901                         msleep(2); /* temporary workaround */
 902                 else {
 903                         udelay(10);
 904                         cond_resched();
 905                 }
 906         }
 907
 908         if (!chip->polling_mode && chip->poll_count < 2) {
 909                 snd_printdd(SFX "%s: azx_get_response timeout, "
 910                            "polling the codec once: last cmd=0x%08x\n",
 911                            pci_name(chip->pci), chip->last_cmd[addr]);
 912                 do_poll = 1;
 913                 chip->poll_count++;
 914                 goto again;
 915         }
 916
 917
 918         if (!chip->polling_mode) {
 919                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
 920                            "switching to polling mode: last cmd=0x%08x\n",
 921                            pci_name(chip->pci), chip->last_cmd[addr]);
 922                 chip->polling_mode = 1;
 923                 goto again;
 924         }
 925
 926         if (chip->msi) {
 927                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
 928                            "disabling MSI: last cmd=0x%08x\n",
 929                            pci_name(chip->pci), chip->last_cmd[addr]);
 930                 free_irq(chip->irq, chip);
 931                 chip->irq = -1;
 932                 pci_disable_msi(chip->pci);
 933                 chip->msi = 0;
 934                 if (azx_acquire_irq(chip, 1) < 0) {
 935                         bus->rirb_error = 1;
 936                         return -1;
 937                 }
 938                 goto again;
 939         }
 940
 941         if (chip->probing) {
 942                 /* If this critical timeout happens during the codec probing
 943                  * phase, this is likely an access to a non-existing codec
 944                  * slot.  Better to return an error and reset the system.
 945                  */
 946                 return -1;
 947         }
 948
 949         /* a fatal communication error; need either to reset or to fallback
 950          * to the single_cmd mode
 951          */
 952         bus->rirb_error = 1;
 953         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 954                 bus->response_reset = 1;
 955                 return -1; /* give a chance to retry */
 956         }
 957
 958         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 959                    "switching to single_cmd mode: last cmd=0x%08x\n",
 960                    chip->last_cmd[addr]);
 961         chip->single_cmd = 1;
 962         bus->response_reset = 0;
 963         /* release CORB/RIRB */
 964         azx_free_cmd_io(chip);
 965         /* disable unsolicited responses */
 966         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 967         return -1;
 968 }
 969
 970 /*
 971  * Use the single immediate command instead of CORB/RIRB for simplicity
 972  *
 973  * Note: according to Intel, this is not preferred use.  The command was
 974  *       intended for the BIOS only, and may get confused with unsolicited
 975  *       responses.  So, we shouldn't use it for normal operation from the
 976  *       driver.
 977  *       I left the codes, however, for debugging/testing purposes.
 978  */
 979
 980 /* receive a response */
 981 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 982 {
 983         int timeout = 50;
 984
 985         while (timeout--) {
 986                 /* check IRV busy bit */
 987                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 988                         /* reuse rirb.res as the response return value */
 989                         chip->rirb.res[addr] = azx_readl(chip, IR);
 990                         return 0;
 991                 }
 992                 udelay(1);
 993         }
 994         if (printk_ratelimit())
 995                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
 996                            pci_name(chip->pci), azx_readw(chip, IRS));
 997         chip->rirb.res[addr] = -1;
 998         return -EIO;
 999 }
1000
1001 /* send a command */
1002 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1003 {
1004         struct azx *chip = bus->private_data;
1005         unsigned int addr = azx_command_addr(val);
1006         int timeout = 50;
1007
1008         bus->rirb_error = 0;
1009         while (timeout--) {
1010                 /* check ICB busy bit */
1011                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1012                         /* Clear IRV valid bit */
1013                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1014                                    ICH6_IRS_VALID);
1015                         azx_writel(chip, IC, val);
1016                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1017                                    ICH6_IRS_BUSY);
1018                         return azx_single_wait_for_response(chip, addr);
1019                 }
1020                 udelay(1);
1021         }
1022         if (printk_ratelimit())
1023                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1024                            pci_name(chip->pci), azx_readw(chip, IRS), val);
1025         return -EIO;
1026 }
1027
1028 /* receive a response */
1029 static unsigned int azx_single_get_response(struct hda_bus *bus,
1030                                             unsigned int addr)
1031 {
1032         struct azx *chip = bus->private_data;
1033         return chip->rirb.res[addr];
1034 }
1035
1036 /*
1037  * The below are the main callbacks from hda_codec.
1038  *
1039  * They are just the skeleton to call sub-callbacks according to the
1040  * current setting of chip->single_cmd.
1041  */
1042
1043 /* send a command */
1044 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1045 {
1046         struct azx *chip = bus->private_data;
1047
1048         if (chip->disabled)
1049                 return 0;
1050         chip->last_cmd[azx_command_addr(val)] = val;
1051         if (chip->single_cmd)
1052                 return azx_single_send_cmd(bus, val);
1053         else
1054                 return azx_corb_send_cmd(bus, val);
1055 }
1056
1057 /* get a response */
1058 static unsigned int azx_get_response(struct hda_bus *bus,
1059                                      unsigned int addr)
1060 {
1061         struct azx *chip = bus->private_data;
1062         if (chip->disabled)
1063                 return 0;
1064         if (chip->single_cmd)
1065                 return azx_single_get_response(bus, addr);
1066         else
1067                 return azx_rirb_get_response(bus, addr);
1068 }
1069
1070 #ifdef CONFIG_PM
1071 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1072 #endif
1073
1074 /* reset codec link */
1075 static int azx_reset(struct azx *chip, int full_reset)
1076 {
1077         unsigned long timeout;
1078
1079         if (!full_reset)
1080                 goto __skip;
1081
1082         /* clear STATESTS */
1083         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1084
1085         /* reset controller */
1086         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1087
1088         timeout = jiffies + msecs_to_jiffies(100);
1089         while (azx_readb(chip, GCTL) &&
1090                         time_before(jiffies, timeout))
1091                 usleep_range(500, 1000);
1092
1093         /* delay for >= 100us for codec PLL to settle per spec
1094          * Rev 0.9 section 5.5.1
1095          */
1096         usleep_range(500, 1000);
1097
1098         /* Bring controller out of reset */
1099         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1100
1101         timeout = jiffies + msecs_to_jiffies(100);
1102         while (!azx_readb(chip, GCTL) &&
1103                         time_before(jiffies, timeout))
1104                 usleep_range(500, 1000);
1105
1106         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1107         usleep_range(1000, 1200);
1108
1109       __skip:
1110         /* check to see if controller is ready */
1111         if (!azx_readb(chip, GCTL)) {
1112                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1113                 return -EBUSY;
1114         }
1115
1116         /* Accept unsolicited responses */
1117         if (!chip->single_cmd)
1118                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1119                            ICH6_GCTL_UNSOL);
1120
1121         /* detect codecs */
1122         if (!chip->codec_mask) {
1123                 chip->codec_mask = azx_readw(chip, STATESTS);
1124                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1125         }
1126
1127         return 0;
1128 }
1129
1130
1131 /*
1132  * Lowlevel interface
1133  */
1134
1135 /* enable interrupts */
1136 static void azx_int_enable(struct azx *chip)
1137 {
1138         /* enable controller CIE and GIE */
1139         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1140                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1141 }
1142
1143 /* disable interrupts */
1144 static void azx_int_disable(struct azx *chip)
1145 {
1146         int i;
1147
1148         /* disable interrupts in stream descriptor */
1149         for (i = 0; i < chip->num_streams; i++) {
1150                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1151                 azx_sd_writeb(azx_dev, SD_CTL,
1152                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1153         }
1154
1155         /* disable SIE for all streams */
1156         azx_writeb(chip, INTCTL, 0);
1157
1158         /* disable controller CIE and GIE */
1159         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1160                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1161 }
1162
1163 /* clear interrupts */
1164 static void azx_int_clear(struct azx *chip)
1165 {
1166         int i;
1167
1168         /* clear stream status */
1169         for (i = 0; i < chip->num_streams; i++) {
1170                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1171                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1172         }
1173
1174         /* clear STATESTS */
1175         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1176
1177         /* clear rirb status */
1178         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1179
1180         /* clear int status */
1181         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1182 }
1183
1184 /* start a stream */
1185 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1186 {
1187         /*
1188          * Before stream start, initialize parameter
1189          */
1190         azx_dev->insufficient = 1;
1191
1192         /* enable SIE */
1193         azx_writel(chip, INTCTL,
1194                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1195         /* set DMA start and interrupt mask */
1196         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1197                       SD_CTL_DMA_START | SD_INT_MASK);
1198 }
1199
1200 /* stop DMA */
1201 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1202 {
1203         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1204                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1205         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1206 }
1207
1208 /* stop a stream */
1209 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1210 {
1211         azx_stream_clear(chip, azx_dev);
1212         /* disable SIE */
1213         azx_writel(chip, INTCTL,
1214                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1215 }
1216
1217
1218 /*
1219  * reset and start the controller registers
1220  */
1221 static void azx_init_chip(struct azx *chip, int full_reset)
1222 {
1223         if (chip->initialized)
1224                 return;
1225
1226         /* reset controller */
1227         azx_reset(chip, full_reset);
1228
1229         /* initialize interrupts */
1230         azx_int_clear(chip);
1231         azx_int_enable(chip);
1232
1233         /* initialize the codec command I/O */
1234         if (!chip->single_cmd)
1235                 azx_init_cmd_io(chip);
1236
1237         /* program the position buffer */
1238         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1239         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1240
1241         chip->initialized = 1;
1242 }
1243
1244 /*
1245  * initialize the PCI registers
1246  */
1247 /* update bits in a PCI register byte */
1248 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1249                             unsigned char mask, unsigned char val)
1250 {
1251         unsigned char data;
1252
1253         pci_read_config_byte(pci, reg, &data);
1254         data &= ~mask;
1255         data |= (val & mask);
1256         pci_write_config_byte(pci, reg, data);
1257 }
1258
1259 static void azx_init_pci(struct azx *chip)
1260 {
1261         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1262          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1263          * Ensuring these bits are 0 clears playback static on some HD Audio
1264          * codecs.
1265          * The PCI register TCSEL is defined in the Intel manuals.
1266          */
1267         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1268                 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1269                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1270         }
1271
1272         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1273          * we need to enable snoop.
1274          */
1275         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1276                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1277                 update_pci_byte(chip->pci,
1278                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1279                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1280         }
1281
1282         /* For NVIDIA HDA, enable snoop */
1283         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1284                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1285                 update_pci_byte(chip->pci,
1286                                 NVIDIA_HDA_TRANSREG_ADDR,
1287                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1288                 update_pci_byte(chip->pci,
1289                                 NVIDIA_HDA_ISTRM_COH,
1290                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1291                 update_pci_byte(chip->pci,
1292                                 NVIDIA_HDA_OSTRM_COH,
1293                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1294         }
1295
1296         /* Enable SCH/PCH snoop if needed */
1297         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1298                 unsigned short snoop;
1299                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1300                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1301                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1302                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1303                         if (!azx_snoop(chip))
1304                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1305                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1306                         pci_read_config_word(chip->pci,
1307                                 INTEL_SCH_HDA_DEVC, &snoop);
1308                 }
1309                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1310                                 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1311                                 ? "Disabled" : "Enabled");
1312         }
1313 }
1314
1315
1316 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1317
1318 /*
1319  * interrupt handler
1320  */
1321 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1322 {
1323         struct azx *chip = dev_id;
1324         struct azx_dev *azx_dev;
1325         u32 status;
1326         u8 sd_status;
1327         int i, ok;
1328
1329 #ifdef CONFIG_PM_RUNTIME
1330         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1331                 return IRQ_NONE;
1332 #endif
1333
1334         spin_lock(&chip->reg_lock);
1335
1336         if (chip->disabled) {
1337                 spin_unlock(&chip->reg_lock);
1338                 return IRQ_NONE;
1339         }
1340
1341         status = azx_readl(chip, INTSTS);
1342         if (status == 0) {
1343                 spin_unlock(&chip->reg_lock);
1344                 return IRQ_NONE;
1345         }
1346
1347         for (i = 0; i < chip->num_streams; i++) {
1348                 azx_dev = &chip->azx_dev[i];
1349                 if (status & azx_dev->sd_int_sta_mask) {
1350                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1351                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1352                         if (!azx_dev->substream || !azx_dev->running ||
1353                             !(sd_status & SD_INT_COMPLETE))
1354                                 continue;
1355                         /* check whether this IRQ is really acceptable */
1356                         ok = azx_position_ok(chip, azx_dev);
1357                         if (ok == 1) {
1358                                 azx_dev->irq_pending = 0;
1359                                 spin_unlock(&chip->reg_lock);
1360                                 snd_pcm_period_elapsed(azx_dev->substream);
1361                                 spin_lock(&chip->reg_lock);
1362                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1363                                 /* bogus IRQ, process it later */
1364                                 azx_dev->irq_pending = 1;
1365                                 queue_work(chip->bus->workq,
1366                                            &chip->irq_pending_work);
1367                         }
1368                 }
1369         }
1370
1371         /* clear rirb int */
1372         status = azx_readb(chip, RIRBSTS);
1373         if (status & RIRB_INT_MASK) {
1374                 if (status & RIRB_INT_RESPONSE) {
1375                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1376                                 udelay(80);
1377                         azx_update_rirb(chip);
1378                 }
1379                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1380         }
1381
1382 #if 0
1383         /* clear state status int */
1384         if (azx_readb(chip, STATESTS) & 0x04)
1385                 azx_writeb(chip, STATESTS, 0x04);
1386 #endif
1387         spin_unlock(&chip->reg_lock);
1388
1389         return IRQ_HANDLED;
1390 }
1391
1392
1393 /*
1394  * set up a BDL entry
1395  */
1396 static int setup_bdle(struct azx *chip,
1397                       struct snd_pcm_substream *substream,
1398                       struct azx_dev *azx_dev, u32 **bdlp,
1399                       int ofs, int size, int with_ioc)
1400 {
1401         u32 *bdl = *bdlp;
1402
1403         while (size > 0) {
1404                 dma_addr_t addr;
1405                 int chunk;
1406
1407                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1408                         return -EINVAL;
1409
1410                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1411                 /* program the address field of the BDL entry */
1412                 bdl[0] = cpu_to_le32((u32)addr);
1413                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1414                 /* program the size field of the BDL entry */
1415                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1416                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1417                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1418                         u32 remain = 0x1000 - (ofs & 0xfff);
1419                         if (chunk > remain)
1420                                 chunk = remain;
1421                 }
1422                 bdl[2] = cpu_to_le32(chunk);
1423                 /* program the IOC to enable interrupt
1424                  * only when the whole fragment is processed
1425                  */
1426                 size -= chunk;
1427                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1428                 bdl += 4;
1429                 azx_dev->frags++;
1430                 ofs += chunk;
1431         }
1432         *bdlp = bdl;
1433         return ofs;
1434 }
1435
1436 /*
1437  * set up BDL entries
1438  */
1439 static int azx_setup_periods(struct azx *chip,
1440                              struct snd_pcm_substream *substream,
1441                              struct azx_dev *azx_dev)
1442 {
1443         u32 *bdl;
1444         int i, ofs, periods, period_bytes;
1445         int pos_adj;
1446
1447         /* reset BDL address */
1448         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1449         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1450
1451         period_bytes = azx_dev->period_bytes;
1452         periods = azx_dev->bufsize / period_bytes;
1453
1454         /* program the initial BDL entries */
1455         bdl = (u32 *)azx_dev->bdl.area;
1456         ofs = 0;
1457         azx_dev->frags = 0;
1458         pos_adj = bdl_pos_adj[chip->dev_index];
1459         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1460                 struct snd_pcm_runtime *runtime = substream->runtime;
1461                 int pos_align = pos_adj;
1462                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1463                 if (!pos_adj)
1464                         pos_adj = pos_align;
1465                 else
1466                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1467                                 pos_align;
1468                 pos_adj = frames_to_bytes(runtime, pos_adj);
1469                 if (pos_adj >= period_bytes) {
1470                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1471                                    pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1472                         pos_adj = 0;
1473                 } else {
1474                         ofs = setup_bdle(chip, substream, azx_dev,
1475                                          &bdl, ofs, pos_adj, true);
1476                         if (ofs < 0)
1477                                 goto error;
1478                 }
1479         } else
1480                 pos_adj = 0;
1481         for (i = 0; i < periods; i++) {
1482                 if (i == periods - 1 && pos_adj)
1483                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1484                                          period_bytes - pos_adj, 0);
1485                 else
1486                         ofs = setup_bdle(chip, substream, azx_dev, &bdl, ofs,
1487                                          period_bytes,
1488                                          !azx_dev->no_period_wakeup);
1489                 if (ofs < 0)
1490                         goto error;
1491         }
1492         return 0;
1493
1494  error:
1495         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1496                    pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1497         return -EINVAL;
1498 }
1499
1500 /* reset stream */
1501 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1502 {
1503         unsigned char val;
1504         int timeout;
1505
1506         azx_stream_clear(chip, azx_dev);
1507
1508         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1509                       SD_CTL_STREAM_RESET);
1510         udelay(3);
1511         timeout = 300;
1512         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1513                --timeout)
1514                 ;
1515         val &= ~SD_CTL_STREAM_RESET;
1516         azx_sd_writeb(azx_dev, SD_CTL, val);
1517         udelay(3);
1518
1519         timeout = 300;
1520         /* waiting for hardware to report that the stream is out of reset */
1521         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1522                --timeout)
1523                 ;
1524
1525         /* reset first position - may not be synced with hw at this time */
1526         *azx_dev->posbuf = 0;
1527 }
1528
1529 /*
1530  * set up the SD for streaming
1531  */
1532 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1533 {
1534         unsigned int val;
1535         /* make sure the run bit is zero for SD */
1536         azx_stream_clear(chip, azx_dev);
1537         /* program the stream_tag */
1538         val = azx_sd_readl(azx_dev, SD_CTL);
1539         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1540                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1541         if (!azx_snoop(chip))
1542                 val |= SD_CTL_TRAFFIC_PRIO;
1543         azx_sd_writel(azx_dev, SD_CTL, val);
1544
1545         /* program the length of samples in cyclic buffer */
1546         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1547
1548         /* program the stream format */
1549         /* this value needs to be the same as the one programmed */
1550         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1551
1552         /* program the stream LVI (last valid index) of the BDL */
1553         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1554
1555         /* program the BDL address */
1556         /* lower BDL address */
1557         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1558         /* upper BDL address */
1559         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1560
1561         /* enable the position buffer */
1562         if (chip->position_fix[0] != POS_FIX_LPIB ||
1563             chip->position_fix[1] != POS_FIX_LPIB) {
1564                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1565                         azx_writel(chip, DPLBASE,
1566                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1567         }
1568
1569         /* set the interrupt enable bits in the descriptor control register */
1570         azx_sd_writel(azx_dev, SD_CTL,
1571                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1572
1573         return 0;
1574 }
1575
1576 /*
1577  * Probe the given codec address
1578  */
1579 static int probe_codec(struct azx *chip, int addr)
1580 {
1581         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1582                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1583         unsigned int res;
1584
1585         mutex_lock(&chip->bus->cmd_mutex);
1586         chip->probing = 1;
1587         azx_send_cmd(chip->bus, cmd);
1588         res = azx_get_response(chip->bus, addr);
1589         chip->probing = 0;
1590         mutex_unlock(&chip->bus->cmd_mutex);
1591         if (res == -1)
1592                 return -EIO;
1593         snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1594         return 0;
1595 }
1596
1597 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1598                                  struct hda_pcm *cpcm);
1599 static void azx_stop_chip(struct azx *chip);
1600
1601 static void azx_bus_reset(struct hda_bus *bus)
1602 {
1603         struct azx *chip = bus->private_data;
1604
1605         bus->in_reset = 1;
1606         azx_stop_chip(chip);
1607         azx_init_chip(chip, 1);
1608 #ifdef CONFIG_PM
1609         if (chip->initialized) {
1610                 struct azx_pcm *p;
1611                 list_for_each_entry(p, &chip->pcm_list, list)
1612                         snd_pcm_suspend_all(p->pcm);
1613                 snd_hda_suspend(chip->bus);
1614                 snd_hda_resume(chip->bus);
1615         }
1616 #endif
1617         bus->in_reset = 0;
1618 }
1619
1620 static int get_jackpoll_interval(struct azx *chip)
1621 {
1622         int i = jackpoll_ms[chip->dev_index];
1623         unsigned int j;
1624         if (i == 0)
1625                 return 0;
1626         if (i < 50 || i > 60000)
1627                 j = 0;
1628         else
1629                 j = msecs_to_jiffies(i);
1630         if (j == 0)
1631                 snd_printk(KERN_WARNING SFX
1632                            "jackpoll_ms value out of range: %d\n", i);
1633         return j;
1634 }
1635
1636 /*
1637  * Codec initialization
1638  */
1639
1640 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1641 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1642         [AZX_DRIVER_NVIDIA] = 8,
1643         [AZX_DRIVER_TERA] = 1,
1644 };
1645
1646 static int azx_codec_create(struct azx *chip, const char *model)
1647 {
1648         struct hda_bus_template bus_temp;
1649         int c, codecs, err;
1650         int max_slots;
1651
1652         memset(&bus_temp, 0, sizeof(bus_temp));
1653         bus_temp.private_data = chip;
1654         bus_temp.modelname = model;
1655         bus_temp.pci = chip->pci;
1656         bus_temp.ops.command = azx_send_cmd;
1657         bus_temp.ops.get_response = azx_get_response;
1658         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1659         bus_temp.ops.bus_reset = azx_bus_reset;
1660 #ifdef CONFIG_PM
1661         bus_temp.power_save = &power_save;
1662         bus_temp.ops.pm_notify = azx_power_notify;
1663 #endif
1664
1665         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1666         if (err < 0)
1667                 return err;
1668
1669         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1670                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1671                 chip->bus->needs_damn_long_delay = 1;
1672         }
1673
1674         codecs = 0;
1675         max_slots = azx_max_codecs[chip->driver_type];
1676         if (!max_slots)
1677                 max_slots = AZX_DEFAULT_CODECS;
1678
1679         /* First try to probe all given codec slots */
1680         for (c = 0; c < max_slots; c++) {
1681                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1682                         if (probe_codec(chip, c) < 0) {
1683                                 /* Some BIOSen give you wrong codec addresses
1684                                  * that don't exist
1685                                  */
1686                                 snd_printk(KERN_WARNING SFX
1687                                            "%s: Codec #%d probe error; "
1688                                            "disabling it...\n", pci_name(chip->pci), c);
1689                                 chip->codec_mask &= ~(1 << c);
1690                                 /* More badly, accessing to a non-existing
1691                                  * codec often screws up the controller chip,
1692                                  * and disturbs the further communications.
1693                                  * Thus if an error occurs during probing,
1694                                  * better to reset the controller chip to
1695                                  * get back to the sanity state.
1696                                  */
1697                                 azx_stop_chip(chip);
1698                                 azx_init_chip(chip, 1);
1699                         }
1700                 }
1701         }
1702
1703         /* AMD chipsets often cause the communication stalls upon certain
1704          * sequence like the pin-detection.  It seems that forcing the synced
1705          * access works around the stall.  Grrr...
1706          */
1707         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1708                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1709                         pci_name(chip->pci));
1710                 chip->bus->sync_write = 1;
1711                 chip->bus->allow_bus_reset = 1;
1712         }
1713
1714         /* Then create codec instances */
1715         for (c = 0; c < max_slots; c++) {
1716                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1717                         struct hda_codec *codec;
1718                         err = snd_hda_codec_new(chip->bus, c, &codec);
1719                         if (err < 0)
1720                                 continue;
1721                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1722                         codec->beep_mode = chip->beep_mode;
1723                         codecs++;
1724                 }
1725         }
1726         if (!codecs) {
1727                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1728                 return -ENXIO;
1729         }
1730         return 0;
1731 }
1732
1733 /* configure each codec instance */
1734 static int azx_codec_configure(struct azx *chip)
1735 {
1736         struct hda_codec *codec;
1737         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1738                 snd_hda_codec_configure(codec);
1739         }
1740         return 0;
1741 }
1742
1743
1744 /*
1745  * PCM support
1746  */
1747
1748 /* assign a stream for the PCM */
1749 static inline struct azx_dev *
1750 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1751 {
1752         int dev, i, nums;
1753         struct azx_dev *res = NULL;
1754         /* make a non-zero unique key for the substream */
1755         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1756                 (substream->stream + 1);
1757
1758         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1759                 dev = chip->playback_index_offset;
1760                 nums = chip->playback_streams;
1761         } else {
1762                 dev = chip->capture_index_offset;
1763                 nums = chip->capture_streams;
1764         }
1765         for (i = 0; i < nums; i++, dev++)
1766                 if (!chip->azx_dev[dev].opened) {
1767                         res = &chip->azx_dev[dev];
1768                         if (res->assigned_key == key)
1769                                 break;
1770                 }
1771         if (res) {
1772                 res->opened = 1;
1773                 res->assigned_key = key;
1774         }
1775         return res;
1776 }
1777
1778 /* release the assigned stream */
1779 static inline void azx_release_device(struct azx_dev *azx_dev)
1780 {
1781         azx_dev->opened = 0;
1782 }
1783
1784 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1785 {
1786         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1787         struct snd_pcm_substream *substream = azx_dev->substream;
1788         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1789         struct azx *chip = apcm->chip;
1790
1791         return azx_readl(chip, WALLCLK);
1792 }
1793
1794 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1795                                 bool force, cycle_t last)
1796 {
1797         struct azx_dev *azx_dev = get_azx_dev(substream);
1798         struct timecounter *tc = &azx_dev->azx_tc;
1799         struct cyclecounter *cc = &azx_dev->azx_cc;
1800         u64 nsec;
1801
1802         cc->read = azx_cc_read;
1803         cc->mask = CLOCKSOURCE_MASK(32);
1804
1805         /*
1806          * Converting from 24 MHz to ns means applying a 125/3 factor.
1807          * To avoid any saturation issues in intermediate operations,
1808          * the 125 factor is applied first. The division is applied
1809          * last after reading the timecounter value.
1810          * Applying the 1/3 factor as part of the multiplication
1811          * requires at least 20 bits for a decent precision, however
1812          * overflows occur after about 4 hours or less, not a option.
1813          */
1814
1815         cc->mult = 125; /* saturation after 195 years */
1816         cc->shift = 0;
1817
1818         nsec = 0; /* audio time is elapsed time since trigger */
1819         timecounter_init(tc, cc, nsec);
1820         if (force)
1821                 /*
1822                  * force timecounter to use predefined value,
1823                  * used for synchronized starts
1824                  */
1825                 tc->cycle_last = last;
1826 }
1827
1828 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1829                                 struct timespec *ts)
1830 {
1831         struct azx_dev *azx_dev = get_azx_dev(substream);
1832         u64 nsec;
1833
1834         nsec = timecounter_read(&azx_dev->azx_tc);
1835         nsec = div_u64(nsec, 3); /* can be optimized */
1836
1837         *ts = ns_to_timespec(nsec);
1838
1839         return 0;
1840 }
1841
1842 static struct snd_pcm_hardware azx_pcm_hw = {
1843         .info =                 (SNDRV_PCM_INFO_MMAP |
1844                                  SNDRV_PCM_INFO_INTERLEAVED |
1845                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1846                                  SNDRV_PCM_INFO_MMAP_VALID |
1847                                  /* No full-resume yet implemented */
1848                                  /* SNDRV_PCM_INFO_RESUME |*/
1849                                  SNDRV_PCM_INFO_PAUSE |
1850                                  SNDRV_PCM_INFO_SYNC_START |
1851                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1852                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1853         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1854         .rates =                SNDRV_PCM_RATE_48000,
1855         .rate_min =             48000,
1856         .rate_max =             48000,
1857         .channels_min =         2,
1858         .channels_max =         2,
1859         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1860         .period_bytes_min =     128,
1861         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1862         .periods_min =          2,
1863         .periods_max =          AZX_MAX_FRAG,
1864         .fifo_size =            0,
1865 };
1866
1867 static int azx_pcm_open(struct snd_pcm_substream *substream)
1868 {
1869         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1870         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1871         struct azx *chip = apcm->chip;
1872         struct azx_dev *azx_dev;
1873         struct snd_pcm_runtime *runtime = substream->runtime;
1874         unsigned long flags;
1875         int err;
1876         int buff_step;
1877
1878         mutex_lock(&chip->open_mutex);
1879         azx_dev = azx_assign_device(chip, substream);
1880         if (azx_dev == NULL) {
1881                 mutex_unlock(&chip->open_mutex);
1882                 return -EBUSY;
1883         }
1884         runtime->hw = azx_pcm_hw;
1885         runtime->hw.channels_min = hinfo->channels_min;
1886         runtime->hw.channels_max = hinfo->channels_max;
1887         runtime->hw.formats = hinfo->formats;
1888         runtime->hw.rates = hinfo->rates;
1889         snd_pcm_limit_hw_rates(runtime);
1890         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1891
1892         /* avoid wrap-around with wall-clock */
1893         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1894                                 20,
1895                                 178000000);
1896
1897         if (chip->align_buffer_size)
1898                 /* constrain buffer sizes to be multiple of 128
1899                    bytes. This is more efficient in terms of memory
1900                    access but isn't required by the HDA spec and
1901                    prevents users from specifying exact period/buffer
1902                    sizes. For example for 44.1kHz, a period size set
1903                    to 20ms will be rounded to 19.59ms. */
1904                 buff_step = 128;
1905         else
1906                 /* Don't enforce steps on buffer sizes, still need to
1907                    be multiple of 4 bytes (HDA spec). Tested on Intel
1908                    HDA controllers, may not work on all devices where
1909                    option needs to be disabled */
1910                 buff_step = 4;
1911
1912         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1913                                    buff_step);
1914         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1915                                    buff_step);
1916         snd_hda_power_up_d3wait(apcm->codec);
1917         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1918         if (err < 0) {
1919                 azx_release_device(azx_dev);
1920                 snd_hda_power_down(apcm->codec);
1921                 mutex_unlock(&chip->open_mutex);
1922                 return err;
1923         }
1924         snd_pcm_limit_hw_rates(runtime);
1925         /* sanity check */
1926         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1927             snd_BUG_ON(!runtime->hw.channels_max) ||
1928             snd_BUG_ON(!runtime->hw.formats) ||
1929             snd_BUG_ON(!runtime->hw.rates)) {
1930                 azx_release_device(azx_dev);
1931                 hinfo->ops.close(hinfo, apcm->codec, substream);
1932                 snd_hda_power_down(apcm->codec);
1933                 mutex_unlock(&chip->open_mutex);
1934                 return -EINVAL;
1935         }
1936
1937         /* disable WALLCLOCK timestamps for capture streams
1938            until we figure out how to handle digital inputs */
1939         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1940                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
1941
1942         spin_lock_irqsave(&chip->reg_lock, flags);
1943         azx_dev->substream = substream;
1944         azx_dev->running = 0;
1945         spin_unlock_irqrestore(&chip->reg_lock, flags);
1946
1947         runtime->private_data = azx_dev;
1948         snd_pcm_set_sync(substream);
1949         mutex_unlock(&chip->open_mutex);
1950         return 0;
1951 }
1952
1953 static int azx_pcm_close(struct snd_pcm_substream *substream)
1954 {
1955         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1956         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1957         struct azx *chip = apcm->chip;
1958         struct azx_dev *azx_dev = get_azx_dev(substream);
1959         unsigned long flags;
1960
1961         mutex_lock(&chip->open_mutex);
1962         spin_lock_irqsave(&chip->reg_lock, flags);
1963         azx_dev->substream = NULL;
1964         azx_dev->running = 0;
1965         spin_unlock_irqrestore(&chip->reg_lock, flags);
1966         azx_release_device(azx_dev);
1967         hinfo->ops.close(hinfo, apcm->codec, substream);
1968         snd_hda_power_down(apcm->codec);
1969         mutex_unlock(&chip->open_mutex);
1970         return 0;
1971 }
1972
1973 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1974                              struct snd_pcm_hw_params *hw_params)
1975 {
1976         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1977         struct azx *chip = apcm->chip;
1978         struct snd_pcm_runtime *runtime = substream->runtime;
1979         struct azx_dev *azx_dev = get_azx_dev(substream);
1980         int ret;
1981
1982         mark_runtime_wc(chip, azx_dev, runtime, false);
1983         azx_dev->bufsize = 0;
1984         azx_dev->period_bytes = 0;
1985         azx_dev->format_val = 0;
1986         ret = snd_pcm_lib_malloc_pages(substream,
1987                                         params_buffer_bytes(hw_params));
1988         if (ret < 0)
1989                 return ret;
1990         mark_runtime_wc(chip, azx_dev, runtime, true);
1991         return ret;
1992 }
1993
1994 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1995 {
1996         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1997         struct azx_dev *azx_dev = get_azx_dev(substream);
1998         struct azx *chip = apcm->chip;
1999         struct snd_pcm_runtime *runtime = substream->runtime;
2000         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2001
2002         /* reset BDL address */
2003         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2004         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2005         azx_sd_writel(azx_dev, SD_CTL, 0);
2006         azx_dev->bufsize = 0;
2007         azx_dev->period_bytes = 0;
2008         azx_dev->format_val = 0;
2009
2010         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2011
2012         mark_runtime_wc(chip, azx_dev, runtime, false);
2013         return snd_pcm_lib_free_pages(substream);
2014 }
2015
2016 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2017 {
2018         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2019         struct azx *chip = apcm->chip;
2020         struct azx_dev *azx_dev = get_azx_dev(substream);
2021         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2022         struct snd_pcm_runtime *runtime = substream->runtime;
2023         unsigned int bufsize, period_bytes, format_val, stream_tag;
2024         int err;
2025         struct hda_spdif_out *spdif =
2026                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2027         unsigned short ctls = spdif ? spdif->ctls : 0;
2028
2029         azx_stream_reset(chip, azx_dev);
2030         format_val = snd_hda_calc_stream_format(runtime->rate,
2031                                                 runtime->channels,
2032                                                 runtime->format,
2033                                                 hinfo->maxbps,
2034                                                 ctls);
2035         if (!format_val) {
2036                 snd_printk(KERN_ERR SFX
2037                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2038                            pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2039                 return -EINVAL;
2040         }
2041
2042         bufsize = snd_pcm_lib_buffer_bytes(substream);
2043         period_bytes = snd_pcm_lib_period_bytes(substream);
2044
2045         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2046                     pci_name(chip->pci), bufsize, format_val);
2047
2048         if (bufsize != azx_dev->bufsize ||
2049             period_bytes != azx_dev->period_bytes ||
2050             format_val != azx_dev->format_val ||
2051             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2052                 azx_dev->bufsize = bufsize;
2053                 azx_dev->period_bytes = period_bytes;
2054                 azx_dev->format_val = format_val;
2055                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2056                 err = azx_setup_periods(chip, substream, azx_dev);
2057                 if (err < 0)
2058                         return err;
2059         }
2060
2061         /* wallclk has 24Mhz clock source */
2062         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2063                                                 runtime->rate) * 1000);
2064         azx_setup_controller(chip, azx_dev);
2065         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2066                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2067         else
2068                 azx_dev->fifo_size = 0;
2069
2070         stream_tag = azx_dev->stream_tag;
2071         /* CA-IBG chips need the playback stream starting from 1 */
2072         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2073             stream_tag > chip->capture_streams)
2074                 stream_tag -= chip->capture_streams;
2075         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2076                                      azx_dev->format_val, substream);
2077 }
2078
2079 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2080 {
2081         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2082         struct azx *chip = apcm->chip;
2083         struct azx_dev *azx_dev;
2084         struct snd_pcm_substream *s;
2085         int rstart = 0, start, nsync = 0, sbits = 0;
2086         int nwait, timeout;
2087
2088         azx_dev = get_azx_dev(substream);
2089         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2090
2091         switch (cmd) {
2092         case SNDRV_PCM_TRIGGER_START:
2093                 rstart = 1;
2094         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2095         case SNDRV_PCM_TRIGGER_RESUME:
2096                 start = 1;
2097                 break;
2098         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2099         case SNDRV_PCM_TRIGGER_SUSPEND:
2100         case SNDRV_PCM_TRIGGER_STOP:
2101                 start = 0;
2102                 break;
2103         default:
2104                 return -EINVAL;
2105         }
2106
2107         snd_pcm_group_for_each_entry(s, substream) {
2108                 if (s->pcm->card != substream->pcm->card)
2109                         continue;
2110                 azx_dev = get_azx_dev(s);
2111                 sbits |= 1 << azx_dev->index;
2112                 nsync++;
2113                 snd_pcm_trigger_done(s, substream);
2114         }
2115
2116         spin_lock(&chip->reg_lock);
2117
2118         /* first, set SYNC bits of corresponding streams */
2119         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2120                 azx_writel(chip, OLD_SSYNC,
2121                         azx_readl(chip, OLD_SSYNC) | sbits);
2122         else
2123                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2124
2125         snd_pcm_group_for_each_entry(s, substream) {
2126                 if (s->pcm->card != substream->pcm->card)
2127                         continue;
2128                 azx_dev = get_azx_dev(s);
2129                 if (start) {
2130                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2131                         if (!rstart)
2132                                 azx_dev->start_wallclk -=
2133                                                 azx_dev->period_wallclk;
2134                         azx_stream_start(chip, azx_dev);
2135                 } else {
2136                         azx_stream_stop(chip, azx_dev);
2137                 }
2138                 azx_dev->running = start;
2139         }
2140         spin_unlock(&chip->reg_lock);
2141         if (start) {
2142                 /* wait until all FIFOs get ready */
2143                 for (timeout = 5000; timeout; timeout--) {
2144                         nwait = 0;
2145                         snd_pcm_group_for_each_entry(s, substream) {
2146                                 if (s->pcm->card != substream->pcm->card)
2147                                         continue;
2148                                 azx_dev = get_azx_dev(s);
2149                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2150                                       SD_STS_FIFO_READY))
2151                                         nwait++;
2152                         }
2153                         if (!nwait)
2154                                 break;
2155                         cpu_relax();
2156                 }
2157         } else {
2158                 /* wait until all RUN bits are cleared */
2159                 for (timeout = 5000; timeout; timeout--) {
2160                         nwait = 0;
2161                         snd_pcm_group_for_each_entry(s, substream) {
2162                                 if (s->pcm->card != substream->pcm->card)
2163                                         continue;
2164                                 azx_dev = get_azx_dev(s);
2165                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2166                                     SD_CTL_DMA_START)
2167                                         nwait++;
2168                         }
2169                         if (!nwait)
2170                                 break;
2171                         cpu_relax();
2172                 }
2173         }
2174         spin_lock(&chip->reg_lock);
2175         /* reset SYNC bits */
2176         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2177                 azx_writel(chip, OLD_SSYNC,
2178                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2179         else
2180                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2181         if (start) {
2182                 azx_timecounter_init(substream, 0, 0);
2183                 if (nsync > 1) {
2184                         cycle_t cycle_last;
2185
2186                         /* same start cycle for master and group */
2187                         azx_dev = get_azx_dev(substream);
2188                         cycle_last = azx_dev->azx_tc.cycle_last;
2189
2190                         snd_pcm_group_for_each_entry(s, substream) {
2191                                 if (s->pcm->card != substream->pcm->card)
2192                                         continue;
2193                                 azx_timecounter_init(s, 1, cycle_last);
2194                         }
2195                 }
2196         }
2197         spin_unlock(&chip->reg_lock);
2198         return 0;
2199 }
2200
2201 /* get the current DMA position with correction on VIA chips */
2202 static unsigned int azx_via_get_position(struct azx *chip,
2203                                          struct azx_dev *azx_dev)
2204 {
2205         unsigned int link_pos, mini_pos, bound_pos;
2206         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2207         unsigned int fifo_size;
2208
2209         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2210         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2211                 /* Playback, no problem using link position */
2212                 return link_pos;
2213         }
2214
2215         /* Capture */
2216         /* For new chipset,
2217          * use mod to get the DMA position just like old chipset
2218          */
2219         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2220         mod_dma_pos %= azx_dev->period_bytes;
2221
2222         /* azx_dev->fifo_size can't get FIFO size of in stream.
2223          * Get from base address + offset.
2224          */
2225         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2226
2227         if (azx_dev->insufficient) {
2228                 /* Link position never gather than FIFO size */
2229                 if (link_pos <= fifo_size)
2230                         return 0;
2231
2232                 azx_dev->insufficient = 0;
2233         }
2234
2235         if (link_pos <= fifo_size)
2236                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2237         else
2238                 mini_pos = link_pos - fifo_size;
2239
2240         /* Find nearest previous boudary */
2241         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2242         mod_link_pos = link_pos % azx_dev->period_bytes;
2243         if (mod_link_pos >= fifo_size)
2244                 bound_pos = link_pos - mod_link_pos;
2245         else if (mod_dma_pos >= mod_mini_pos)
2246                 bound_pos = mini_pos - mod_mini_pos;
2247         else {
2248                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2249                 if (bound_pos >= azx_dev->bufsize)
2250                         bound_pos = 0;
2251         }
2252
2253         /* Calculate real DMA position we want */
2254         return bound_pos + mod_dma_pos;
2255 }
2256
2257 static unsigned int azx_get_position(struct azx *chip,
2258                                      struct azx_dev *azx_dev,
2259                                      bool with_check)
2260 {
2261         unsigned int pos;
2262         int stream = azx_dev->substream->stream;
2263         int delay = 0;
2264
2265         switch (chip->position_fix[stream]) {
2266         case POS_FIX_LPIB:
2267                 /* read LPIB */
2268                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2269                 break;
2270         case POS_FIX_VIACOMBO:
2271                 pos = azx_via_get_position(chip, azx_dev);
2272                 break;
2273         default:
2274                 /* use the position buffer */
2275                 pos = le32_to_cpu(*azx_dev->posbuf);
2276                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2277                         if (!pos || pos == (u32)-1) {
2278                                 printk(KERN_WARNING
2279                                        "hda-intel: Invalid position buffer, "
2280                                        "using LPIB read method instead.\n");
2281                                 chip->position_fix[stream] = POS_FIX_LPIB;
2282                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2283                         } else
2284                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2285                 }
2286                 break;
2287         }
2288
2289         if (pos >= azx_dev->bufsize)
2290                 pos = 0;
2291
2292         /* calculate runtime delay from LPIB */
2293         if (azx_dev->substream->runtime &&
2294             chip->position_fix[stream] == POS_FIX_POSBUF &&
2295             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2296                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2297                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2298                         delay = pos - lpib_pos;
2299                 else
2300                         delay = lpib_pos - pos;
2301                 if (delay < 0)
2302                         delay += azx_dev->bufsize;
2303                 if (delay >= azx_dev->period_bytes) {
2304                         snd_printk(KERN_WARNING SFX
2305                                    "%s: Unstable LPIB (%d >= %d); "
2306                                    "disabling LPIB delay counting\n",
2307                                    pci_name(chip->pci), delay, azx_dev->period_bytes);
2308                         delay = 0;
2309                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2310                 }
2311                 azx_dev->substream->runtime->delay =
2312                         bytes_to_frames(azx_dev->substream->runtime, delay);
2313         }
2314         trace_azx_get_position(chip, azx_dev, pos, delay);
2315         return pos;
2316 }
2317
2318 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2319 {
2320         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2321         struct azx *chip = apcm->chip;
2322         struct azx_dev *azx_dev = get_azx_dev(substream);
2323         return bytes_to_frames(substream->runtime,
2324                                azx_get_position(chip, azx_dev, false));
2325 }
2326
2327 /*
2328  * Check whether the current DMA position is acceptable for updating
2329  * periods.  Returns non-zero if it's OK.
2330  *
2331  * Many HD-audio controllers appear pretty inaccurate about
2332  * the update-IRQ timing.  The IRQ is issued before actually the
2333  * data is processed.  So, we need to process it afterwords in a
2334  * workqueue.
2335  */
2336 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2337 {
2338         u32 wallclk;
2339         unsigned int pos;
2340
2341         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2342         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2343                 return -1;      /* bogus (too early) interrupt */
2344
2345         pos = azx_get_position(chip, azx_dev, true);
2346
2347         if (WARN_ONCE(!azx_dev->period_bytes,
2348                       "hda-intel: zero azx_dev->period_bytes"))
2349                 return -1; /* this shouldn't happen! */
2350         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2351             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2352                 /* NG - it's below the first next period boundary */
2353                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2354         azx_dev->start_wallclk += wallclk;
2355         return 1; /* OK, it's fine */
2356 }
2357
2358 /*
2359  * The work for pending PCM period updates.
2360  */
2361 static void azx_irq_pending_work(struct work_struct *work)
2362 {
2363         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2364         int i, pending, ok;
2365
2366         if (!chip->irq_pending_warned) {
2367                 printk(KERN_WARNING
2368                        "hda-intel: IRQ timing workaround is activated "
2369                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2370                        chip->card->number);
2371                 chip->irq_pending_warned = 1;
2372         }
2373
2374         for (;;) {
2375                 pending = 0;
2376                 spin_lock_irq(&chip->reg_lock);
2377                 for (i = 0; i < chip->num_streams; i++) {
2378                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2379                         if (!azx_dev->irq_pending ||
2380                             !azx_dev->substream ||
2381                             !azx_dev->running)
2382                                 continue;
2383                         ok = azx_position_ok(chip, azx_dev);
2384                         if (ok > 0) {
2385                                 azx_dev->irq_pending = 0;
2386                                 spin_unlock(&chip->reg_lock);
2387                                 snd_pcm_period_elapsed(azx_dev->substream);
2388                                 spin_lock(&chip->reg_lock);
2389                         } else if (ok < 0) {
2390                                 pending = 0;    /* too early */
2391                         } else
2392                                 pending++;
2393                 }
2394                 spin_unlock_irq(&chip->reg_lock);
2395                 if (!pending)
2396                         return;
2397                 msleep(1);
2398         }
2399 }
2400
2401 /* clear irq_pending flags and assure no on-going workq */
2402 static void azx_clear_irq_pending(struct azx *chip)
2403 {
2404         int i;
2405
2406         spin_lock_irq(&chip->reg_lock);
2407         for (i = 0; i < chip->num_streams; i++)
2408                 chip->azx_dev[i].irq_pending = 0;
2409         spin_unlock_irq(&chip->reg_lock);
2410 }
2411
2412 #ifdef CONFIG_X86
2413 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2414                         struct vm_area_struct *area)
2415 {
2416         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2417         struct azx *chip = apcm->chip;
2418         if (!azx_snoop(chip))
2419                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2420         return snd_pcm_lib_default_mmap(substream, area);
2421 }
2422 #else
2423 #define azx_pcm_mmap    NULL
2424 #endif
2425
2426 static struct snd_pcm_ops azx_pcm_ops = {
2427         .open = azx_pcm_open,
2428         .close = azx_pcm_close,
2429         .ioctl = snd_pcm_lib_ioctl,
2430         .hw_params = azx_pcm_hw_params,
2431         .hw_free = azx_pcm_hw_free,
2432         .prepare = azx_pcm_prepare,
2433         .trigger = azx_pcm_trigger,
2434         .pointer = azx_pcm_pointer,
2435         .wall_clock =  azx_get_wallclock_tstamp,
2436         .mmap = azx_pcm_mmap,
2437         .page = snd_pcm_sgbuf_ops_page,
2438 };
2439
2440 static void azx_pcm_free(struct snd_pcm *pcm)
2441 {
2442         struct azx_pcm *apcm = pcm->private_data;
2443         if (apcm) {
2444                 list_del(&apcm->list);
2445                 kfree(apcm);
2446         }
2447 }
2448
2449 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2450
2451 static int
2452 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2453                       struct hda_pcm *cpcm)
2454 {
2455         struct azx *chip = bus->private_data;
2456         struct snd_pcm *pcm;
2457         struct azx_pcm *apcm;
2458         int pcm_dev = cpcm->device;
2459         unsigned int size;
2460         int s, err;
2461
2462         list_for_each_entry(apcm, &chip->pcm_list, list) {
2463                 if (apcm->pcm->device == pcm_dev) {
2464                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2465                                    pci_name(chip->pci), pcm_dev);
2466                         return -EBUSY;
2467                 }
2468         }
2469         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2470                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2471                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2472                           &pcm);
2473         if (err < 0)
2474                 return err;
2475         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2476         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2477         if (apcm == NULL)
2478                 return -ENOMEM;
2479         apcm->chip = chip;
2480         apcm->pcm = pcm;
2481         apcm->codec = codec;
2482         pcm->private_data = apcm;
2483         pcm->private_free = azx_pcm_free;
2484         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2485                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2486         list_add_tail(&apcm->list, &chip->pcm_list);
2487         cpcm->pcm = pcm;
2488         for (s = 0; s < 2; s++) {
2489                 apcm->hinfo[s] = &cpcm->stream[s];
2490                 if (cpcm->stream[s].substreams)
2491                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2492         }
2493         /* buffer pre-allocation */
2494         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2495         if (size > MAX_PREALLOC_SIZE)
2496                 size = MAX_PREALLOC_SIZE;
2497         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2498                                               snd_dma_pci_data(chip->pci),
2499                                               size, MAX_PREALLOC_SIZE);
2500         return 0;
2501 }
2502
2503 /*
2504  * mixer creation - all stuff is implemented in hda module
2505  */
2506 static int azx_mixer_create(struct azx *chip)
2507 {
2508         return snd_hda_build_controls(chip->bus);
2509 }
2510
2511
2512 /*
2513  * initialize SD streams
2514  */
2515 static int azx_init_stream(struct azx *chip)
2516 {
2517         int i;
2518
2519         /* initialize each stream (aka device)
2520          * assign the starting bdl address to each stream (device)
2521          * and initialize
2522          */
2523         for (i = 0; i < chip->num_streams; i++) {
2524                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2525                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2526                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2527                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2528                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2529                 azx_dev->sd_int_sta_mask = 1 << i;
2530                 /* stream tag: must be non-zero and unique */
2531                 azx_dev->index = i;
2532                 azx_dev->stream_tag = i + 1;
2533         }
2534
2535         return 0;
2536 }
2537
2538 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2539 {
2540         if (request_irq(chip->pci->irq, azx_interrupt,
2541                         chip->msi ? 0 : IRQF_SHARED,
2542                         KBUILD_MODNAME, chip)) {
2543                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2544                        "disabling device\n", chip->pci->irq);
2545                 if (do_disconnect)
2546                         snd_card_disconnect(chip->card);
2547                 return -1;
2548         }
2549         chip->irq = chip->pci->irq;
2550         pci_intx(chip->pci, !chip->msi);
2551         return 0;
2552 }
2553
2554
2555 static void azx_stop_chip(struct azx *chip)
2556 {
2557         if (!chip->initialized)
2558                 return;
2559
2560         /* disable interrupts */
2561         azx_int_disable(chip);
2562         azx_int_clear(chip);
2563
2564         /* disable CORB/RIRB */
2565         azx_free_cmd_io(chip);
2566
2567         /* disable position buffer */
2568         azx_writel(chip, DPLBASE, 0);
2569         azx_writel(chip, DPUBASE, 0);
2570
2571         chip->initialized = 0;
2572 }
2573
2574 #ifdef CONFIG_PM
2575 /* power-up/down the controller */
2576 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2577 {
2578         struct azx *chip = bus->private_data;
2579
2580         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2581                 return;
2582
2583         if (power_up)
2584                 pm_runtime_get_sync(&chip->pci->dev);
2585         else
2586                 pm_runtime_put_sync(&chip->pci->dev);
2587 }
2588
2589 static DEFINE_MUTEX(card_list_lock);
2590 static LIST_HEAD(card_list);
2591
2592 static void azx_add_card_list(struct azx *chip)
2593 {
2594         mutex_lock(&card_list_lock);
2595         list_add(&chip->list, &card_list);
2596         mutex_unlock(&card_list_lock);
2597 }
2598
2599 static void azx_del_card_list(struct azx *chip)
2600 {
2601         mutex_lock(&card_list_lock);
2602         list_del_init(&chip->list);
2603         mutex_unlock(&card_list_lock);
2604 }
2605
2606 /* trigger power-save check at writing parameter */
2607 static int param_set_xint(const char *val, const struct kernel_param *kp)
2608 {
2609         struct azx *chip;
2610         struct hda_codec *c;
2611         int prev = power_save;
2612         int ret = param_set_int(val, kp);
2613
2614         if (ret || prev == power_save)
2615                 return ret;
2616
2617         mutex_lock(&card_list_lock);
2618         list_for_each_entry(chip, &card_list, list) {
2619                 if (!chip->bus || chip->disabled)
2620                         continue;
2621                 list_for_each_entry(c, &chip->bus->codec_list, list)
2622                         snd_hda_power_sync(c);
2623         }
2624         mutex_unlock(&card_list_lock);
2625         return 0;
2626 }
2627 #else
2628 #define azx_add_card_list(chip) /* NOP */
2629 #define azx_del_card_list(chip) /* NOP */
2630 #endif /* CONFIG_PM */
2631
2632 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2633 /*
2634  * power management
2635  */
2636 static int azx_suspend(struct device *dev)
2637 {
2638         struct pci_dev *pci = to_pci_dev(dev);
2639         struct snd_card *card = dev_get_drvdata(dev);
2640         struct azx *chip = card->private_data;
2641         struct azx_pcm *p;
2642
2643         if (chip->disabled)
2644                 return 0;
2645
2646         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2647         azx_clear_irq_pending(chip);
2648         list_for_each_entry(p, &chip->pcm_list, list)
2649                 snd_pcm_suspend_all(p->pcm);
2650         if (chip->initialized)
2651                 snd_hda_suspend(chip->bus);
2652         azx_stop_chip(chip);
2653         if (chip->irq >= 0) {
2654                 free_irq(chip->irq, chip);
2655                 chip->irq = -1;
2656         }
2657         if (chip->msi)
2658                 pci_disable_msi(chip->pci);
2659         pci_disable_device(pci);
2660         pci_save_state(pci);
2661         pci_set_power_state(pci, PCI_D3hot);
2662         return 0;
2663 }
2664
2665 static int azx_resume(struct device *dev)
2666 {
2667         struct pci_dev *pci = to_pci_dev(dev);
2668         struct snd_card *card = dev_get_drvdata(dev);
2669         struct azx *chip = card->private_data;
2670
2671         if (chip->disabled)
2672                 return 0;
2673
2674         pci_set_power_state(pci, PCI_D0);
2675         pci_restore_state(pci);
2676         if (pci_enable_device(pci) < 0) {
2677                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2678                        "disabling device\n");
2679                 snd_card_disconnect(card);
2680                 return -EIO;
2681         }
2682         pci_set_master(pci);
2683         if (chip->msi)
2684                 if (pci_enable_msi(pci) < 0)
2685                         chip->msi = 0;
2686         if (azx_acquire_irq(chip, 1) < 0)
2687                 return -EIO;
2688         azx_init_pci(chip);
2689
2690         azx_init_chip(chip, 1);
2691
2692         snd_hda_resume(chip->bus);
2693         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2694         return 0;
2695 }
2696 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2697
2698 #ifdef CONFIG_PM_RUNTIME
2699 static int azx_runtime_suspend(struct device *dev)
2700 {
2701         struct snd_card *card = dev_get_drvdata(dev);
2702         struct azx *chip = card->private_data;
2703
2704         azx_stop_chip(chip);
2705         azx_clear_irq_pending(chip);
2706         return 0;
2707 }
2708
2709 static int azx_runtime_resume(struct device *dev)
2710 {
2711         struct snd_card *card = dev_get_drvdata(dev);
2712         struct azx *chip = card->private_data;
2713
2714         azx_init_pci(chip);
2715         azx_init_chip(chip, 1);
2716         return 0;
2717 }
2718
2719 static int azx_runtime_idle(struct device *dev)
2720 {
2721         struct snd_card *card = dev_get_drvdata(dev);
2722         struct azx *chip = card->private_data;
2723
2724         if (power_save_controller > 0)
2725                 return 0;
2726         if (!power_save_controller ||
2727             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2728                 return -EBUSY;
2729
2730         return 0;
2731 }
2732
2733 #endif /* CONFIG_PM_RUNTIME */
2734
2735 #ifdef CONFIG_PM
2736 static const struct dev_pm_ops azx_pm = {
2737         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2738         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
2739 };
2740
2741 #define AZX_PM_OPS      &azx_pm
2742 #else
2743 #define AZX_PM_OPS      NULL
2744 #endif /* CONFIG_PM */
2745
2746
2747 /*
2748  * reboot notifier for hang-up problem at power-down
2749  */
2750 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2751 {
2752         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2753         snd_hda_bus_reboot_notify(chip->bus);
2754         azx_stop_chip(chip);
2755         return NOTIFY_OK;
2756 }
2757
2758 static void azx_notifier_register(struct azx *chip)
2759 {
2760         chip->reboot_notifier.notifier_call = azx_halt;
2761         register_reboot_notifier(&chip->reboot_notifier);
2762 }
2763
2764 static void azx_notifier_unregister(struct azx *chip)
2765 {
2766         if (chip->reboot_notifier.notifier_call)
2767                 unregister_reboot_notifier(&chip->reboot_notifier);
2768 }
2769
2770 static int azx_first_init(struct azx *chip);
2771 static int azx_probe_continue(struct azx *chip);
2772
2773 #ifdef SUPPORT_VGA_SWITCHEROO
2774 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
2775
2776 static void azx_vs_set_state(struct pci_dev *pci,
2777                              enum vga_switcheroo_state state)
2778 {
2779         struct snd_card *card = pci_get_drvdata(pci);
2780         struct azx *chip = card->private_data;
2781         bool disabled;
2782
2783         wait_for_completion(&chip->probe_wait);
2784         if (chip->init_failed)
2785                 return;
2786
2787         disabled = (state == VGA_SWITCHEROO_OFF);
2788         if (chip->disabled == disabled)
2789                 return;
2790
2791         if (!chip->bus) {
2792                 chip->disabled = disabled;
2793                 if (!disabled) {
2794                         snd_printk(KERN_INFO SFX
2795                                    "%s: Start delayed initialization\n",
2796                                    pci_name(chip->pci));
2797                         if (azx_first_init(chip) < 0 ||
2798                             azx_probe_continue(chip) < 0) {
2799                                 snd_printk(KERN_ERR SFX
2800                                            "%s: initialization error\n",
2801                                            pci_name(chip->pci));
2802                                 chip->init_failed = true;
2803                         }
2804                 }
2805         } else {
2806                 snd_printk(KERN_INFO SFX
2807                            "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
2808                            disabled ? "Disabling" : "Enabling");
2809                 if (disabled) {
2810                         azx_suspend(&pci->dev);
2811                         chip->disabled = true;
2812                         if (snd_hda_lock_devices(chip->bus))
2813                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
2814                                            pci_name(chip->pci));
2815                 } else {
2816                         snd_hda_unlock_devices(chip->bus);
2817                         chip->disabled = false;
2818                         azx_resume(&pci->dev);
2819                 }
2820         }
2821 }
2822
2823 static bool azx_vs_can_switch(struct pci_dev *pci)
2824 {
2825         struct snd_card *card = pci_get_drvdata(pci);
2826         struct azx *chip = card->private_data;
2827
2828         wait_for_completion(&chip->probe_wait);
2829         if (chip->init_failed)
2830                 return false;
2831         if (chip->disabled || !chip->bus)
2832                 return true;
2833         if (snd_hda_lock_devices(chip->bus))
2834                 return false;
2835         snd_hda_unlock_devices(chip->bus);
2836         return true;
2837 }
2838
2839 static void init_vga_switcheroo(struct azx *chip)
2840 {
2841         struct pci_dev *p = get_bound_vga(chip->pci);
2842         if (p) {
2843                 snd_printk(KERN_INFO SFX
2844                            "%s: Handle VGA-switcheroo audio client\n",
2845                            pci_name(chip->pci));
2846                 chip->use_vga_switcheroo = 1;
2847                 pci_dev_put(p);
2848         }
2849 }
2850
2851 static const struct vga_switcheroo_client_ops azx_vs_ops = {
2852         .set_gpu_state = azx_vs_set_state,
2853         .can_switch = azx_vs_can_switch,
2854 };
2855
2856 static int register_vga_switcheroo(struct azx *chip)
2857 {
2858         int err;
2859
2860         if (!chip->use_vga_switcheroo)
2861                 return 0;
2862         /* FIXME: currently only handling DIS controller
2863          * is there any machine with two switchable HDMI audio controllers?
2864          */
2865         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
2866                                                     VGA_SWITCHEROO_DIS,
2867                                                     chip->bus != NULL);
2868         if (err < 0)
2869                 return err;
2870         chip->vga_switcheroo_registered = 1;
2871         return 0;
2872 }
2873 #else
2874 #define init_vga_switcheroo(chip)               /* NOP */
2875 #define register_vga_switcheroo(chip)           0
2876 #define check_hdmi_disabled(pci)        false
2877 #endif /* SUPPORT_VGA_SWITCHER */
2878
2879 /*
2880  * destructor
2881  */
2882 static int azx_free(struct azx *chip)
2883 {
2884         int i;
2885
2886         azx_del_card_list(chip);
2887
2888         azx_notifier_unregister(chip);
2889
2890         chip->init_failed = 1; /* to be sure */
2891         complete_all(&chip->probe_wait);
2892
2893         if (use_vga_switcheroo(chip)) {
2894                 if (chip->disabled && chip->bus)
2895                         snd_hda_unlock_devices(chip->bus);
2896                 if (chip->vga_switcheroo_registered)
2897                         vga_switcheroo_unregister_client(chip->pci);
2898         }
2899
2900         if (chip->initialized) {
2901                 azx_clear_irq_pending(chip);
2902                 for (i = 0; i < chip->num_streams; i++)
2903                         azx_stream_stop(chip, &chip->azx_dev[i]);
2904                 azx_stop_chip(chip);
2905         }
2906
2907         if (chip->irq >= 0)
2908                 free_irq(chip->irq, (void*)chip);
2909         if (chip->msi)
2910                 pci_disable_msi(chip->pci);
2911         if (chip->remap_addr)
2912                 iounmap(chip->remap_addr);
2913
2914         if (chip->azx_dev) {
2915                 for (i = 0; i < chip->num_streams; i++)
2916                         if (chip->azx_dev[i].bdl.area) {
2917                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2918                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2919                         }
2920         }
2921         if (chip->rb.area) {
2922                 mark_pages_wc(chip, &chip->rb, false);
2923                 snd_dma_free_pages(&chip->rb);
2924         }
2925         if (chip->posbuf.area) {
2926                 mark_pages_wc(chip, &chip->posbuf, false);
2927                 snd_dma_free_pages(&chip->posbuf);
2928         }
2929         if (chip->region_requested)
2930                 pci_release_regions(chip->pci);
2931         pci_disable_device(chip->pci);
2932         kfree(chip->azx_dev);
2933 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2934         if (chip->fw)
2935                 release_firmware(chip->fw);
2936 #endif
2937         kfree(chip);
2938
2939         return 0;
2940 }
2941
2942 static int azx_dev_free(struct snd_device *device)
2943 {
2944         return azx_free(device->device_data);
2945 }
2946
2947 #ifdef SUPPORT_VGA_SWITCHEROO
2948 /*
2949  * Check of disabled HDMI controller by vga-switcheroo
2950  */
2951 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
2952 {
2953         struct pci_dev *p;
2954
2955         /* check only discrete GPU */
2956         switch (pci->vendor) {
2957         case PCI_VENDOR_ID_ATI:
2958         case PCI_VENDOR_ID_AMD:
2959         case PCI_VENDOR_ID_NVIDIA:
2960                 if (pci->devfn == 1) {
2961                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
2962                                                         pci->bus->number, 0);
2963                         if (p) {
2964                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
2965                                         return p;
2966                                 pci_dev_put(p);
2967                         }
2968                 }
2969                 break;
2970         }
2971         return NULL;
2972 }
2973
2974 static bool check_hdmi_disabled(struct pci_dev *pci)
2975 {
2976         bool vga_inactive = false;
2977         struct pci_dev *p = get_bound_vga(pci);
2978
2979         if (p) {
2980                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
2981                         vga_inactive = true;
2982                 pci_dev_put(p);
2983         }
2984         return vga_inactive;
2985 }
2986 #endif /* SUPPORT_VGA_SWITCHEROO */
2987
2988 /*
2989  * white/black-listing for position_fix
2990  */
2991 static struct snd_pci_quirk position_fix_list[] = {
2992         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2993         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2994         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2995         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2996         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2997         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2998         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2999         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3000         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3001         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3002         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3003         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3004         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3005         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3006         {}
3007 };
3008
3009 static int check_position_fix(struct azx *chip, int fix)
3010 {
3011         const struct snd_pci_quirk *q;
3012
3013         switch (fix) {
3014         case POS_FIX_AUTO:
3015         case POS_FIX_LPIB:
3016         case POS_FIX_POSBUF:
3017         case POS_FIX_VIACOMBO:
3018         case POS_FIX_COMBO:
3019                 return fix;
3020         }
3021
3022         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3023         if (q) {
3024                 printk(KERN_INFO
3025                        "hda_intel: position_fix set to %d "
3026                        "for device %04x:%04x\n",
3027                        q->value, q->subvendor, q->subdevice);
3028                 return q->value;
3029         }
3030
3031         /* Check VIA/ATI HD Audio Controller exist */
3032         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3033                 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3034                 return POS_FIX_VIACOMBO;
3035         }
3036         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3037                 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3038                 return POS_FIX_LPIB;
3039         }
3040         return POS_FIX_AUTO;
3041 }
3042
3043 /*
3044  * black-lists for probe_mask
3045  */
3046 static struct snd_pci_quirk probe_mask_list[] = {
3047         /* Thinkpad often breaks the controller communication when accessing
3048          * to the non-working (or non-existing) modem codec slot.
3049          */
3050         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3051         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3052         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3053         /* broken BIOS */
3054         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3055         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3056         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3057         /* forced codec slots */
3058         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3059         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3060         /* WinFast VP200 H (Teradici) user reported broken communication */
3061         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3062         {}
3063 };
3064
3065 #define AZX_FORCE_CODEC_MASK    0x100
3066
3067 static void check_probe_mask(struct azx *chip, int dev)
3068 {
3069         const struct snd_pci_quirk *q;
3070
3071         chip->codec_probe_mask = probe_mask[dev];
3072         if (chip->codec_probe_mask == -1) {
3073                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3074                 if (q) {
3075                         printk(KERN_INFO
3076                                "hda_intel: probe_mask set to 0x%x "
3077                                "for device %04x:%04x\n",
3078                                q->value, q->subvendor, q->subdevice);
3079                         chip->codec_probe_mask = q->value;
3080                 }
3081         }
3082
3083         /* check forced option */
3084         if (chip->codec_probe_mask != -1 &&
3085             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3086                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3087                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3088                        chip->codec_mask);
3089         }
3090 }
3091
3092 /*
3093  * white/black-list for enable_msi
3094  */
3095 static struct snd_pci_quirk msi_black_list[] = {
3096         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3097         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3098         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3099         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3100         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3101         {}
3102 };
3103
3104 static void check_msi(struct azx *chip)
3105 {
3106         const struct snd_pci_quirk *q;
3107
3108         if (enable_msi >= 0) {
3109                 chip->msi = !!enable_msi;
3110                 return;
3111         }
3112         chip->msi = 1;  /* enable MSI as default */
3113         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3114         if (q) {
3115                 printk(KERN_INFO
3116                        "hda_intel: msi for device %04x:%04x set to %d\n",
3117                        q->subvendor, q->subdevice, q->value);
3118                 chip->msi = q->value;
3119                 return;
3120         }
3121
3122         /* NVidia chipsets seem to cause troubles with MSI */
3123         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3124                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3125                 chip->msi = 0;
3126         }
3127 }
3128
3129 /* check the snoop mode availability */
3130 static void azx_check_snoop_available(struct azx *chip)
3131 {
3132         bool snoop = chip->snoop;
3133
3134         switch (chip->driver_type) {
3135         case AZX_DRIVER_VIA:
3136                 /* force to non-snoop mode for a new VIA controller
3137                  * when BIOS is set
3138                  */
3139                 if (snoop) {
3140                         u8 val;
3141                         pci_read_config_byte(chip->pci, 0x42, &val);
3142                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3143                                 snoop = false;
3144                 }
3145                 break;
3146         case AZX_DRIVER_ATIHDMI_NS:
3147                 /* new ATI HDMI requires non-snoop */
3148                 snoop = false;
3149                 break;
3150         }
3151
3152         if (snoop != chip->snoop) {
3153                 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3154                            pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3155                 chip->snoop = snoop;
3156         }
3157 }
3158
3159 /*
3160  * constructor
3161  */
3162 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3163                       int dev, unsigned int driver_caps,
3164                       struct azx **rchip)
3165 {
3166         static struct snd_device_ops ops = {
3167                 .dev_free = azx_dev_free,
3168         };
3169         struct azx *chip;
3170         int err;
3171
3172         *rchip = NULL;
3173
3174         err = pci_enable_device(pci);
3175         if (err < 0)
3176                 return err;
3177
3178         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3179         if (!chip) {
3180                 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3181                 pci_disable_device(pci);
3182                 return -ENOMEM;
3183         }
3184
3185         spin_lock_init(&chip->reg_lock);
3186         mutex_init(&chip->open_mutex);
3187         chip->card = card;
3188         chip->pci = pci;
3189         chip->irq = -1;
3190         chip->driver_caps = driver_caps;
3191         chip->driver_type = driver_caps & 0xff;
3192         check_msi(chip);
3193         chip->dev_index = dev;
3194         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3195         INIT_LIST_HEAD(&chip->pcm_list);
3196         INIT_LIST_HEAD(&chip->list);
3197         init_vga_switcheroo(chip);
3198         init_completion(&chip->probe_wait);
3199
3200         chip->position_fix[0] = chip->position_fix[1] =
3201                 check_position_fix(chip, position_fix[dev]);
3202         /* combo mode uses LPIB for playback */
3203         if (chip->position_fix[0] == POS_FIX_COMBO) {
3204                 chip->position_fix[0] = POS_FIX_LPIB;
3205                 chip->position_fix[1] = POS_FIX_AUTO;
3206         }
3207
3208         check_probe_mask(chip, dev);
3209
3210         chip->single_cmd = single_cmd;
3211         chip->snoop = hda_snoop;
3212         azx_check_snoop_available(chip);
3213
3214         if (bdl_pos_adj[dev] < 0) {
3215                 switch (chip->driver_type) {
3216                 case AZX_DRIVER_ICH:
3217                 case AZX_DRIVER_PCH:
3218                         bdl_pos_adj[dev] = 1;
3219                         break;
3220                 default:
3221                         bdl_pos_adj[dev] = 32;
3222                         break;
3223                 }
3224         }
3225
3226         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3227         if (err < 0) {
3228                 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3229                    pci_name(chip->pci));
3230                 azx_free(chip);
3231                 return err;
3232         }
3233
3234         *rchip = chip;
3235         return 0;
3236 }
3237
3238 static int azx_first_init(struct azx *chip)
3239 {
3240         int dev = chip->dev_index;
3241         struct pci_dev *pci = chip->pci;
3242         struct snd_card *card = chip->card;
3243         int i, err;
3244         unsigned short gcap;
3245
3246 #if BITS_PER_LONG != 64
3247         /* Fix up base address on ULI M5461 */
3248         if (chip->driver_type == AZX_DRIVER_ULI) {
3249                 u16 tmp3;
3250                 pci_read_config_word(pci, 0x40, &tmp3);
3251                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3252                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3253         }
3254 #endif
3255
3256         err = pci_request_regions(pci, "ICH HD audio");
3257         if (err < 0)
3258                 return err;
3259         chip->region_requested = 1;
3260
3261         chip->addr = pci_resource_start(pci, 0);
3262         chip->remap_addr = pci_ioremap_bar(pci, 0);
3263         if (chip->remap_addr == NULL) {
3264                 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3265                 return -ENXIO;
3266         }
3267
3268         if (chip->msi)
3269                 if (pci_enable_msi(pci) < 0)
3270                         chip->msi = 0;
3271
3272         if (azx_acquire_irq(chip, 0) < 0)
3273                 return -EBUSY;
3274
3275         pci_set_master(pci);
3276         synchronize_irq(chip->irq);
3277
3278         gcap = azx_readw(chip, GCAP);
3279         snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3280
3281         /* disable SB600 64bit support for safety */
3282         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3283                 struct pci_dev *p_smbus;
3284                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3285                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3286                                          NULL);
3287                 if (p_smbus) {
3288                         if (p_smbus->revision < 0x30)
3289                                 gcap &= ~ICH6_GCAP_64OK;
3290                         pci_dev_put(p_smbus);
3291                 }
3292         }
3293
3294         /* disable 64bit DMA address on some devices */
3295         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3296                 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3297                 gcap &= ~ICH6_GCAP_64OK;
3298         }
3299
3300         /* disable buffer size rounding to 128-byte multiples if supported */
3301         if (align_buffer_size >= 0)
3302                 chip->align_buffer_size = !!align_buffer_size;
3303         else {
3304                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3305                         chip->align_buffer_size = 0;
3306                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3307                         chip->align_buffer_size = 1;
3308                 else
3309                         chip->align_buffer_size = 1;
3310         }
3311
3312         /* allow 64bit DMA address if supported by H/W */
3313         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3314                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3315         else {
3316                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3317                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3318         }
3319
3320         /* read number of streams from GCAP register instead of using
3321          * hardcoded value
3322          */
3323         chip->capture_streams = (gcap >> 8) & 0x0f;
3324         chip->playback_streams = (gcap >> 12) & 0x0f;
3325         if (!chip->playback_streams && !chip->capture_streams) {
3326                 /* gcap didn't give any info, switching to old method */
3327
3328                 switch (chip->driver_type) {
3329                 case AZX_DRIVER_ULI:
3330                         chip->playback_streams = ULI_NUM_PLAYBACK;
3331                         chip->capture_streams = ULI_NUM_CAPTURE;
3332                         break;
3333                 case AZX_DRIVER_ATIHDMI:
3334                 case AZX_DRIVER_ATIHDMI_NS:
3335                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3336                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3337                         break;
3338                 case AZX_DRIVER_GENERIC:
3339                 default:
3340                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3341                         chip->capture_streams = ICH6_NUM_CAPTURE;
3342                         break;
3343                 }
3344         }
3345         chip->capture_index_offset = 0;
3346         chip->playback_index_offset = chip->capture_streams;
3347         chip->num_streams = chip->playback_streams + chip->capture_streams;
3348         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3349                                 GFP_KERNEL);
3350         if (!chip->azx_dev) {
3351                 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3352                 return -ENOMEM;
3353         }
3354
3355         for (i = 0; i < chip->num_streams; i++) {
3356                 /* allocate memory for the BDL for each stream */
3357                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3358                                           snd_dma_pci_data(chip->pci),
3359                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3360                 if (err < 0) {
3361                         snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3362                         return -ENOMEM;
3363                 }
3364                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3365         }
3366         /* allocate memory for the position buffer */
3367         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3368                                   snd_dma_pci_data(chip->pci),
3369                                   chip->num_streams * 8, &chip->posbuf);
3370         if (err < 0) {
3371                 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3372                 return -ENOMEM;
3373         }
3374         mark_pages_wc(chip, &chip->posbuf, true);
3375         /* allocate CORB/RIRB */
3376         err = azx_alloc_cmd_io(chip);
3377         if (err < 0)
3378                 return err;
3379
3380         /* initialize streams */
3381         azx_init_stream(chip);
3382
3383         /* initialize chip */
3384         azx_init_pci(chip);
3385         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3386
3387         /* codec detection */
3388         if (!chip->codec_mask) {
3389                 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3390                 return -ENODEV;
3391         }
3392
3393         strcpy(card->driver, "HDA-Intel");
3394         strlcpy(card->shortname, driver_short_names[chip->driver_type],
3395                 sizeof(card->shortname));
3396         snprintf(card->longname, sizeof(card->longname),
3397                  "%s at 0x%lx irq %i",
3398                  card->shortname, chip->addr, chip->irq);
3399
3400         return 0;
3401 }
3402
3403 static void power_down_all_codecs(struct azx *chip)
3404 {
3405 #ifdef CONFIG_PM
3406         /* The codecs were powered up in snd_hda_codec_new().
3407          * Now all initialization done, so turn them down if possible
3408          */
3409         struct hda_codec *codec;
3410         list_for_each_entry(codec, &chip->bus->codec_list, list) {
3411                 snd_hda_power_down(codec);
3412         }
3413 #endif
3414 }
3415
3416 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3417 /* callback from request_firmware_nowait() */
3418 static void azx_firmware_cb(const struct firmware *fw, void *context)
3419 {
3420         struct snd_card *card = context;
3421         struct azx *chip = card->private_data;
3422         struct pci_dev *pci = chip->pci;
3423
3424         if (!fw) {
3425                 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3426                            pci_name(chip->pci));
3427                 goto error;
3428         }
3429
3430         chip->fw = fw;
3431         if (!chip->disabled) {
3432                 /* continue probing */
3433                 if (azx_probe_continue(chip))
3434                         goto error;
3435         }
3436         return; /* OK */
3437
3438  error:
3439         snd_card_free(card);
3440         pci_set_drvdata(pci, NULL);
3441 }
3442 #endif
3443
3444 static int azx_probe(struct pci_dev *pci,
3445                      const struct pci_device_id *pci_id)
3446 {
3447         static int dev;
3448         struct snd_card *card;
3449         struct azx *chip;
3450         bool probe_now;
3451         int err;
3452
3453         if (dev >= SNDRV_CARDS)
3454                 return -ENODEV;
3455         if (!enable[dev]) {
3456                 dev++;
3457                 return -ENOENT;
3458         }
3459
3460         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3461         if (err < 0) {
3462                 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
3463                 return err;
3464         }
3465
3466         snd_card_set_dev(card, &pci->dev);
3467
3468         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3469         if (err < 0)
3470                 goto out_free;
3471         card->private_data = chip;
3472
3473         pci_set_drvdata(pci, card);
3474
3475         err = register_vga_switcheroo(chip);
3476         if (err < 0) {
3477                 snd_printk(KERN_ERR SFX
3478                            "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
3479                 goto out_free;
3480         }
3481
3482         if (check_hdmi_disabled(pci)) {
3483                 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
3484                            pci_name(pci));
3485                 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
3486                 chip->disabled = true;
3487         }
3488
3489         probe_now = !chip->disabled;
3490         if (probe_now) {
3491                 err = azx_first_init(chip);
3492                 if (err < 0)
3493                         goto out_free;
3494         }
3495
3496 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3497         if (patch[dev] && *patch[dev]) {
3498                 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3499                            pci_name(pci), patch[dev]);
3500                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3501                                               &pci->dev, GFP_KERNEL, card,
3502                                               azx_firmware_cb);
3503                 if (err < 0)
3504                         goto out_free;
3505                 probe_now = false; /* continued in azx_firmware_cb() */
3506         }
3507 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3508
3509         if (probe_now) {
3510                 err = azx_probe_continue(chip);
3511                 if (err < 0)
3512                         goto out_free;
3513         }
3514
3515         if (pci_dev_run_wake(pci))
3516                 pm_runtime_put_noidle(&pci->dev);
3517
3518         dev++;
3519         complete_all(&chip->probe_wait);
3520         return 0;
3521
3522 out_free:
3523         snd_card_free(card);
3524         pci_set_drvdata(pci, NULL);
3525         return err;
3526 }
3527
3528 static int azx_probe_continue(struct azx *chip)
3529 {
3530         int dev = chip->dev_index;
3531         int err;
3532
3533 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3534         chip->beep_mode = beep_mode[dev];
3535 #endif
3536
3537         /* create codec instances */
3538         err = azx_codec_create(chip, model[dev]);
3539         if (err < 0)
3540                 goto out_free;
3541 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3542         if (chip->fw) {
3543                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3544                                          chip->fw->data);
3545                 if (err < 0)
3546                         goto out_free;
3547 #ifndef CONFIG_PM
3548                 release_firmware(chip->fw); /* no longer needed */
3549                 chip->fw = NULL;
3550 #endif
3551         }
3552 #endif
3553         if ((probe_only[dev] & 1) == 0) {
3554                 err = azx_codec_configure(chip);
3555                 if (err < 0)
3556                         goto out_free;
3557         }
3558
3559         /* create PCM streams */
3560         err = snd_hda_build_pcms(chip->bus);
3561         if (err < 0)
3562                 goto out_free;
3563
3564         /* create mixer controls */
3565         err = azx_mixer_create(chip);
3566         if (err < 0)
3567                 goto out_free;
3568
3569         err = snd_card_register(chip->card);
3570         if (err < 0)
3571                 goto out_free;
3572
3573         chip->running = 1;
3574         power_down_all_codecs(chip);
3575         azx_notifier_register(chip);
3576         azx_add_card_list(chip);
3577
3578         return 0;
3579
3580 out_free:
3581         chip->init_failed = 1;
3582         return err;
3583 }
3584
3585 static void azx_remove(struct pci_dev *pci)
3586 {
3587         struct snd_card *card = pci_get_drvdata(pci);
3588
3589         if (pci_dev_run_wake(pci))
3590                 pm_runtime_get_noresume(&pci->dev);
3591
3592         if (card)
3593                 snd_card_free(card);
3594         pci_set_drvdata(pci, NULL);
3595 }
3596
3597 /* PCI IDs */
3598 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3599         /* CPT */
3600         { PCI_DEVICE(0x8086, 0x1c20),
3601           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3602         /* PBG */
3603         { PCI_DEVICE(0x8086, 0x1d20),
3604           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3605         /* Panther Point */
3606         { PCI_DEVICE(0x8086, 0x1e20),
3607           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3608         /* Lynx Point */
3609         { PCI_DEVICE(0x8086, 0x8c20),
3610           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3611         /* Lynx Point-LP */
3612         { PCI_DEVICE(0x8086, 0x9c20),
3613           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3614         /* Lynx Point-LP */
3615         { PCI_DEVICE(0x8086, 0x9c21),
3616           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3617         /* Haswell */
3618         { PCI_DEVICE(0x8086, 0x0a0c),
3619           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3620         { PCI_DEVICE(0x8086, 0x0c0c),
3621           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3622         { PCI_DEVICE(0x8086, 0x0d0c),
3623           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3624         /* 5 Series/3400 */
3625         { PCI_DEVICE(0x8086, 0x3b56),
3626           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3627         /* SCH */
3628         { PCI_DEVICE(0x8086, 0x811b),
3629           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3630           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3631         { PCI_DEVICE(0x8086, 0x080a),
3632           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3633           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3634         /* ICH */
3635         { PCI_DEVICE(0x8086, 0x2668),
3636           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3637           AZX_DCAPS_BUFSIZE },  /* ICH6 */
3638         { PCI_DEVICE(0x8086, 0x27d8),
3639           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3640           AZX_DCAPS_BUFSIZE },  /* ICH7 */
3641         { PCI_DEVICE(0x8086, 0x269a),
3642           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3643           AZX_DCAPS_BUFSIZE },  /* ESB2 */
3644         { PCI_DEVICE(0x8086, 0x284b),
3645           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3646           AZX_DCAPS_BUFSIZE },  /* ICH8 */
3647         { PCI_DEVICE(0x8086, 0x293e),
3648           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3649           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3650         { PCI_DEVICE(0x8086, 0x293f),
3651           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3652           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3653         { PCI_DEVICE(0x8086, 0x3a3e),
3654           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3655           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3656         { PCI_DEVICE(0x8086, 0x3a6e),
3657           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3658           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3659         /* Generic Intel */
3660         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3661           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3662           .class_mask = 0xffffff,
3663           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3664         /* ATI SB 450/600/700/800/900 */
3665         { PCI_DEVICE(0x1002, 0x437b),
3666           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3667         { PCI_DEVICE(0x1002, 0x4383),
3668           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3669         /* AMD Hudson */
3670         { PCI_DEVICE(0x1022, 0x780d),
3671           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3672         /* ATI HDMI */
3673         { PCI_DEVICE(0x1002, 0x793b),
3674           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3675         { PCI_DEVICE(0x1002, 0x7919),
3676           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3677         { PCI_DEVICE(0x1002, 0x960f),
3678           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3679         { PCI_DEVICE(0x1002, 0x970f),
3680           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3681         { PCI_DEVICE(0x1002, 0xaa00),
3682           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3683         { PCI_DEVICE(0x1002, 0xaa08),
3684           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3685         { PCI_DEVICE(0x1002, 0xaa10),
3686           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3687         { PCI_DEVICE(0x1002, 0xaa18),
3688           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3689         { PCI_DEVICE(0x1002, 0xaa20),
3690           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3691         { PCI_DEVICE(0x1002, 0xaa28),
3692           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3693         { PCI_DEVICE(0x1002, 0xaa30),
3694           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3695         { PCI_DEVICE(0x1002, 0xaa38),
3696           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3697         { PCI_DEVICE(0x1002, 0xaa40),
3698           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3699         { PCI_DEVICE(0x1002, 0xaa48),
3700           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3701         { PCI_DEVICE(0x1002, 0x9902),
3702           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3703         { PCI_DEVICE(0x1002, 0xaaa0),
3704           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3705         { PCI_DEVICE(0x1002, 0xaaa8),
3706           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3707         { PCI_DEVICE(0x1002, 0xaab0),
3708           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3709         /* VIA VT8251/VT8237A */
3710         { PCI_DEVICE(0x1106, 0x3288),
3711           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3712         /* VIA GFX VT7122/VX900 */
3713         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3714         /* VIA GFX VT6122/VX11 */
3715         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3716         /* SIS966 */
3717         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3718         /* ULI M5461 */
3719         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3720         /* NVIDIA MCP */
3721         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3722           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3723           .class_mask = 0xffffff,
3724           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3725         /* Teradici */
3726         { PCI_DEVICE(0x6549, 0x1200),
3727           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3728         { PCI_DEVICE(0x6549, 0x2200),
3729           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3730         /* Creative X-Fi (CA0110-IBG) */
3731         /* CTHDA chips */
3732         { PCI_DEVICE(0x1102, 0x0010),
3733           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3734         { PCI_DEVICE(0x1102, 0x0012),
3735           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3736 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3737         /* the following entry conflicts with snd-ctxfi driver,
3738          * as ctxfi driver mutates from HD-audio to native mode with
3739          * a special command sequence.
3740          */
3741         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3742           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3743           .class_mask = 0xffffff,
3744           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3745           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3746 #else
3747         /* this entry seems still valid -- i.e. without emu20kx chip */
3748         { PCI_DEVICE(0x1102, 0x0009),
3749           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3750           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3751 #endif
3752         /* Vortex86MX */
3753         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3754         /* VMware HDAudio */
3755         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3756         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3757         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3758           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3759           .class_mask = 0xffffff,
3760           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3761         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3762           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3763           .class_mask = 0xffffff,
3764           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3765         { 0, }
3766 };
3767 MODULE_DEVICE_TABLE(pci, azx_ids);
3768
3769 /* pci_driver definition */
3770 static struct pci_driver azx_driver = {
3771         .name = KBUILD_MODNAME,
3772         .id_table = azx_ids,
3773         .probe = azx_probe,
3774         .remove = azx_remove,
3775         .driver = {
3776                 .pm = AZX_PM_OPS,
3777         },
3778 };
3779
3780 module_pci_driver(azx_driver);