sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #include <linux/pm_runtime.h>
  50 #include <linux/clocksource.h>
  51 #include <linux/time.h>
  52 #include <linux/completion.h>
  53
  54 #ifdef CONFIG_X86
  55 /* for snoop control */
  56 #include <asm/pgtable.h>
  57 #include <asm/cacheflush.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <linux/vgaarb.h>
  62 #include <linux/vga_switcheroo.h>
  63 #include <linux/firmware.h>
  64 #include "hda_codec.h"
  65
  66
  67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  70 static char *model[SNDRV_CARDS];
  71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  74 static int probe_only[SNDRV_CARDS];
  75 static int jackpoll_ms[SNDRV_CARDS];
  76 static bool single_cmd;
  77 static int enable_msi = -1;
  78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  79 static char *patch[SNDRV_CARDS];
  80 #endif
  81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  83                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  84 #endif
  85
  86 module_param_array(index, int, NULL, 0444);
  87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  88 module_param_array(id, charp, NULL, 0444);
  89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  90 module_param_array(enable, bool, NULL, 0444);
  91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  92 module_param_array(model, charp, NULL, 0444);
  93 MODULE_PARM_DESC(model, "Use the given board model.");
  94 module_param_array(position_fix, int, NULL, 0444);
  95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  96                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
  97 module_param_array(bdl_pos_adj, int, NULL, 0644);
  98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  99 module_param_array(probe_mask, int, NULL, 0444);
 100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 101 module_param_array(probe_only, int, NULL, 0444);
 102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 103 module_param_array(jackpoll_ms, int, NULL, 0444);
 104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 105 module_param(single_cmd, bool, 0444);
 106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 107                  "(for debugging only).");
 108 module_param(enable_msi, bint, 0444);
 109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 111 module_param_array(patch, charp, NULL, 0444);
 112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 113 #endif
 114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 115 module_param_array(beep_mode, bool, NULL, 0444);
 116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 117                             "(0=off, 1=on) (default=1).");
 118 #endif
 119
 120 #ifdef CONFIG_PM
 121 static int param_set_xint(const char *val, const struct kernel_param *kp);
 122 static struct kernel_param_ops param_ops_xint = {
 123         .set = param_set_xint,
 124         .get = param_get_int,
 125 };
 126 #define param_check_xint param_check_int
 127
 128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 129 module_param(power_save, xint, 0644);
 130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 131                  "(in second, 0 = disable).");
 132
 133 /* reset the HD-audio controller in power save mode.
 134  * this may give more power-saving, but will take longer time to
 135  * wake up.
 136  */
 137 static int power_save_controller = -1;
 138 module_param(power_save_controller, bint, 0644);
 139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 140 #endif /* CONFIG_PM */
 141
 142 static int align_buffer_size = -1;
 143 module_param(align_buffer_size, bint, 0644);
 144 MODULE_PARM_DESC(align_buffer_size,
 145                 "Force buffer and period sizes to be multiple of 128 bytes.");
 146
 147 #ifdef CONFIG_X86
 148 static bool hda_snoop = true;
 149 module_param_named(snoop, hda_snoop, bool, 0444);
 150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 151 #define azx_snoop(chip)         (chip)->snoop
 152 #else
 153 #define hda_snoop               true
 154 #define azx_snoop(chip)         true
 155 #endif
 156
 157
 158 MODULE_LICENSE("GPL");
 159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 160                          "{Intel, ICH6M},"
 161                          "{Intel, ICH7},"
 162                          "{Intel, ESB2},"
 163                          "{Intel, ICH8},"
 164                          "{Intel, ICH9},"
 165                          "{Intel, ICH10},"
 166                          "{Intel, PCH},"
 167                          "{Intel, CPT},"
 168                          "{Intel, PPT},"
 169                          "{Intel, LPT},"
 170                          "{Intel, LPT_LP},"
 171                          "{Intel, HPT},"
 172                          "{Intel, PBG},"
 173                          "{Intel, SCH},"
 174                          "{ATI, SB450},"
 175                          "{ATI, SB600},"
 176                          "{ATI, RS600},"
 177                          "{ATI, RS690},"
 178                          "{ATI, RS780},"
 179                          "{ATI, R600},"
 180                          "{ATI, RV630},"
 181                          "{ATI, RV610},"
 182                          "{ATI, RV670},"
 183                          "{ATI, RV635},"
 184                          "{ATI, RV620},"
 185                          "{ATI, RV770},"
 186                          "{VIA, VT8251},"
 187                          "{VIA, VT8237A},"
 188                          "{SiS, SIS966},"
 189                          "{ULI, M5461}}");
 190 MODULE_DESCRIPTION("Intel HDA driver");
 191
 192 #ifdef CONFIG_SND_VERBOSE_PRINTK
 193 #define SFX     /* nop */
 194 #else
 195 #define SFX     "hda-intel "
 196 #endif
 197
 198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
 200 #define SUPPORT_VGA_SWITCHEROO
 201 #endif
 202 #endif
 203
 204
 205 /*
 206  * registers
 207  */
 208 #define ICH6_REG_GCAP                   0x00
 209 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 210 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 211 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 212 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 213 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 214 #define ICH6_REG_VMIN                   0x02
 215 #define ICH6_REG_VMAJ                   0x03
 216 #define ICH6_REG_OUTPAY                 0x04
 217 #define ICH6_REG_INPAY                  0x06
 218 #define ICH6_REG_GCTL                   0x08
 219 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 220 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 221 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 222 #define ICH6_REG_WAKEEN                 0x0c
 223 #define ICH6_REG_STATESTS               0x0e
 224 #define ICH6_REG_GSTS                   0x10
 225 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 226 #define ICH6_REG_INTCTL                 0x20
 227 #define ICH6_REG_INTSTS                 0x24
 228 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 229 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 230 #define ICH6_REG_SSYNC                  0x38
 231 #define ICH6_REG_CORBLBASE              0x40
 232 #define ICH6_REG_CORBUBASE              0x44
 233 #define ICH6_REG_CORBWP                 0x48
 234 #define ICH6_REG_CORBRP                 0x4a
 235 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 236 #define ICH6_REG_CORBCTL                0x4c
 237 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 238 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 239 #define ICH6_REG_CORBSTS                0x4d
 240 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 241 #define ICH6_REG_CORBSIZE               0x4e
 242
 243 #define ICH6_REG_RIRBLBASE              0x50
 244 #define ICH6_REG_RIRBUBASE              0x54
 245 #define ICH6_REG_RIRBWP                 0x58
 246 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 247 #define ICH6_REG_RINTCNT                0x5a
 248 #define ICH6_REG_RIRBCTL                0x5c
 249 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 250 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 251 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 252 #define ICH6_REG_RIRBSTS                0x5d
 253 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 254 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 255 #define ICH6_REG_RIRBSIZE               0x5e
 256
 257 #define ICH6_REG_IC                     0x60
 258 #define ICH6_REG_IR                     0x64
 259 #define ICH6_REG_IRS                    0x68
 260 #define   ICH6_IRS_VALID        (1<<1)
 261 #define   ICH6_IRS_BUSY         (1<<0)
 262
 263 #define ICH6_REG_DPLBASE                0x70
 264 #define ICH6_REG_DPUBASE                0x74
 265 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 266
 267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 269
 270 /* stream register offsets from stream base */
 271 #define ICH6_REG_SD_CTL                 0x00
 272 #define ICH6_REG_SD_STS                 0x03
 273 #define ICH6_REG_SD_LPIB                0x04
 274 #define ICH6_REG_SD_CBL                 0x08
 275 #define ICH6_REG_SD_LVI                 0x0c
 276 #define ICH6_REG_SD_FIFOW               0x0e
 277 #define ICH6_REG_SD_FIFOSIZE            0x10
 278 #define ICH6_REG_SD_FORMAT              0x12
 279 #define ICH6_REG_SD_BDLPL               0x18
 280 #define ICH6_REG_SD_BDLPU               0x1c
 281
 282 /* PCI space */
 283 #define ICH6_PCIREG_TCSEL       0x44
 284
 285 /*
 286  * other constants
 287  */
 288
 289 /* max number of SDs */
 290 /* ICH, ATI and VIA have 4 playback and 4 capture */
 291 #define ICH6_NUM_CAPTURE        4
 292 #define ICH6_NUM_PLAYBACK       4
 293
 294 /* ULI has 6 playback and 5 capture */
 295 #define ULI_NUM_CAPTURE         5
 296 #define ULI_NUM_PLAYBACK        6
 297
 298 /* ATI HDMI has 1 playback and 0 capture */
 299 #define ATIHDMI_NUM_CAPTURE     0
 300 #define ATIHDMI_NUM_PLAYBACK    1
 301
 302 /* TERA has 4 playback and 3 capture */
 303 #define TERA_NUM_CAPTURE        3
 304 #define TERA_NUM_PLAYBACK       4
 305
 306 /* this number is statically defined for simplicity */
 307 #define MAX_AZX_DEV             16
 308
 309 /* max number of fragments - we may use more if allocating more pages for BDL */
 310 #define BDL_SIZE                4096
 311 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 312 #define AZX_MAX_FRAG            32
 313 /* max buffer size - no h/w limit, you can increase as you like */
 314 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 315
 316 /* RIRB int mask: overrun[2], response[0] */
 317 #define RIRB_INT_RESPONSE       0x01
 318 #define RIRB_INT_OVERRUN        0x04
 319 #define RIRB_INT_MASK           0x05
 320
 321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 322 #define AZX_MAX_CODECS          8
 323 #define AZX_DEFAULT_CODECS      4
 324 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 325
 326 /* SD_CTL bits */
 327 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 328 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 329 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 330 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 331 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 332 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 333 #define SD_CTL_STREAM_TAG_SHIFT 20
 334
 335 /* SD_CTL and SD_STS */
 336 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 337 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 338 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 339 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 340                                  SD_INT_COMPLETE)
 341
 342 /* SD_STS */
 343 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 344
 345 /* INTCTL and INTSTS */
 346 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 347 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 348 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 349
 350 /* below are so far hardcoded - should read registers in future */
 351 #define ICH6_MAX_CORB_ENTRIES   256
 352 #define ICH6_MAX_RIRB_ENTRIES   256
 353
 354 /* position fix mode */
 355 enum {
 356         POS_FIX_AUTO,
 357         POS_FIX_LPIB,
 358         POS_FIX_POSBUF,
 359         POS_FIX_VIACOMBO,
 360         POS_FIX_COMBO,
 361 };
 362
 363 /* Defines for ATI HD Audio support in SB450 south bridge */
 364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 366
 367 /* Defines for Nvidia HDA support */
 368 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 369 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 370 #define NVIDIA_HDA_ISTRM_COH          0x4d
 371 #define NVIDIA_HDA_OSTRM_COH          0x4c
 372 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 373
 374 /* Defines for Intel SCH HDA snoop control */
 375 #define INTEL_SCH_HDA_DEVC      0x78
 376 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 377
 378 /* Define IN stream 0 FIFO size offset in VIA controller */
 379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 380 /* Define VIA HD Audio Device ID*/
 381 #define VIA_HDAC_DEVICE_ID              0x3288
 382
 383 /* HD Audio class code */
 384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 385
 386 /*
 387  */
 388
 389 struct azx_dev {
 390         struct snd_dma_buffer bdl; /* BDL buffer */
 391         u32 *posbuf;            /* position buffer pointer */
 392
 393         unsigned int bufsize;   /* size of the play buffer in bytes */
 394         unsigned int period_bytes; /* size of the period in bytes */
 395         unsigned int frags;     /* number for period in the play buffer */
 396         unsigned int fifo_size; /* FIFO size */
 397         unsigned long start_wallclk;    /* start + minimum wallclk */
 398         unsigned long period_wallclk;   /* wallclk for period */
 399
 400         void __iomem *sd_addr;  /* stream descriptor pointer */
 401
 402         u32 sd_int_sta_mask;    /* stream int status mask */
 403
 404         /* pcm support */
 405         struct snd_pcm_substream *substream;    /* assigned substream,
 406                                                  * set in PCM open
 407                                                  */
 408         unsigned int format_val;        /* format value to be set in the
 409                                          * controller and the codec
 410                                          */
 411         unsigned char stream_tag;       /* assigned stream */
 412         unsigned char index;            /* stream index */
 413         int assigned_key;               /* last device# key assigned to */
 414
 415         unsigned int opened :1;
 416         unsigned int running :1;
 417         unsigned int irq_pending :1;
 418         unsigned int prepared:1;
 419         unsigned int locked:1;
 420         /*
 421          * For VIA:
 422          *  A flag to ensure DMA position is 0
 423          *  when link position is not greater than FIFO size
 424          */
 425         unsigned int insufficient :1;
 426         unsigned int wc_marked:1;
 427         unsigned int no_period_wakeup:1;
 428
 429         struct timecounter  azx_tc;
 430         struct cyclecounter azx_cc;
 431
 432 #ifdef CONFIG_SND_HDA_DSP_LOADER
 433         struct mutex dsp_mutex;
 434 #endif
 435 };
 436
 437 /* DSP lock helpers */
 438 #ifdef CONFIG_SND_HDA_DSP_LOADER
 439 #define dsp_lock_init(dev)      mutex_init(&(dev)->dsp_mutex)
 440 #define dsp_lock(dev)           mutex_lock(&(dev)->dsp_mutex)
 441 #define dsp_unlock(dev)         mutex_unlock(&(dev)->dsp_mutex)
 442 #define dsp_is_locked(dev)      ((dev)->locked)
 443 #else
 444 #define dsp_lock_init(dev)      do {} while (0)
 445 #define dsp_lock(dev)           do {} while (0)
 446 #define dsp_unlock(dev)         do {} while (0)
 447 #define dsp_is_locked(dev)      0
 448 #endif
 449
 450 /* CORB/RIRB */
 451 struct azx_rb {
 452         u32 *buf;               /* CORB/RIRB buffer
 453                                  * Each CORB entry is 4byte, RIRB is 8byte
 454                                  */
 455         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 456         /* for RIRB */
 457         unsigned short rp, wp;  /* read/write pointers */
 458         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 459         u32 res[AZX_MAX_CODECS];        /* last read value */
 460 };
 461
 462 struct azx_pcm {
 463         struct azx *chip;
 464         struct snd_pcm *pcm;
 465         struct hda_codec *codec;
 466         struct hda_pcm_stream *hinfo[2];
 467         struct list_head list;
 468 };
 469
 470 struct azx {
 471         struct snd_card *card;
 472         struct pci_dev *pci;
 473         int dev_index;
 474
 475         /* chip type specific */
 476         int driver_type;
 477         unsigned int driver_caps;
 478         int playback_streams;
 479         int playback_index_offset;
 480         int capture_streams;
 481         int capture_index_offset;
 482         int num_streams;
 483
 484         /* pci resources */
 485         unsigned long addr;
 486         void __iomem *remap_addr;
 487         int irq;
 488
 489         /* locks */
 490         spinlock_t reg_lock;
 491         struct mutex open_mutex;
 492         struct completion probe_wait;
 493
 494         /* streams (x num_streams) */
 495         struct azx_dev *azx_dev;
 496
 497         /* PCM */
 498         struct list_head pcm_list; /* azx_pcm list */
 499
 500         /* HD codec */
 501         unsigned short codec_mask;
 502         int  codec_probe_mask; /* copied from probe_mask option */
 503         struct hda_bus *bus;
 504         unsigned int beep_mode;
 505
 506         /* CORB/RIRB */
 507         struct azx_rb corb;
 508         struct azx_rb rirb;
 509
 510         /* CORB/RIRB and position buffers */
 511         struct snd_dma_buffer rb;
 512         struct snd_dma_buffer posbuf;
 513
 514 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 515         const struct firmware *fw;
 516 #endif
 517
 518         /* flags */
 519         int position_fix[2]; /* for both playback/capture streams */
 520         int poll_count;
 521         unsigned int running :1;
 522         unsigned int initialized :1;
 523         unsigned int single_cmd :1;
 524         unsigned int polling_mode :1;
 525         unsigned int msi :1;
 526         unsigned int irq_pending_warned :1;
 527         unsigned int probing :1; /* codec probing phase */
 528         unsigned int snoop:1;
 529         unsigned int align_buffer_size:1;
 530         unsigned int region_requested:1;
 531
 532         /* VGA-switcheroo setup */
 533         unsigned int use_vga_switcheroo:1;
 534         unsigned int vga_switcheroo_registered:1;
 535         unsigned int init_failed:1; /* delayed init failed */
 536         unsigned int disabled:1; /* disabled by VGA-switcher */
 537
 538         /* for debugging */
 539         unsigned int last_cmd[AZX_MAX_CODECS];
 540
 541         /* for pending irqs */
 542         struct work_struct irq_pending_work;
 543
 544         /* reboot notifier (for mysterious hangup problem at power-down) */
 545         struct notifier_block reboot_notifier;
 546
 547         /* card list (for power_save trigger) */
 548         struct list_head list;
 549
 550 #ifdef CONFIG_SND_HDA_DSP_LOADER
 551         struct azx_dev saved_azx_dev;
 552 #endif
 553 };
 554
 555 #define CREATE_TRACE_POINTS
 556 #include "hda_intel_trace.h"
 557
 558 /* driver types */
 559 enum {
 560         AZX_DRIVER_ICH,
 561         AZX_DRIVER_PCH,
 562         AZX_DRIVER_SCH,
 563         AZX_DRIVER_ATI,
 564         AZX_DRIVER_ATIHDMI,
 565         AZX_DRIVER_ATIHDMI_NS,
 566         AZX_DRIVER_VIA,
 567         AZX_DRIVER_SIS,
 568         AZX_DRIVER_ULI,
 569         AZX_DRIVER_NVIDIA,
 570         AZX_DRIVER_TERA,
 571         AZX_DRIVER_CTX,
 572         AZX_DRIVER_CTHDA,
 573         AZX_DRIVER_GENERIC,
 574         AZX_NUM_DRIVERS, /* keep this as last entry */
 575 };
 576
 577 /* driver quirks (capabilities) */
 578 /* bits 0-7 are used for indicating driver type */
 579 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 580 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 581 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 582 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 583 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 584 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 585 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 586 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 587 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 588 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 589 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 590 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 591 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 592 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 593 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
 594 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
 595 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
 596 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
 597
 598 /* quirks for Intel PCH */
 599 #define AZX_DCAPS_INTEL_PCH_NOPM \
 600         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
 601          AZX_DCAPS_COUNT_LPIB_DELAY)
 602
 603 #define AZX_DCAPS_INTEL_PCH \
 604         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
 605
 606 /* quirks for ATI SB / AMD Hudson */
 607 #define AZX_DCAPS_PRESET_ATI_SB \
 608         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 609          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 610
 611 /* quirks for ATI/AMD HDMI */
 612 #define AZX_DCAPS_PRESET_ATI_HDMI \
 613         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 614
 615 /* quirks for Nvidia */
 616 #define AZX_DCAPS_PRESET_NVIDIA \
 617         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
 618          AZX_DCAPS_ALIGN_BUFSIZE)
 619
 620 #define AZX_DCAPS_PRESET_CTHDA \
 621         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
 622
 623 /*
 624  * VGA-switcher support
 625  */
 626 #ifdef SUPPORT_VGA_SWITCHEROO
 627 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 628 #else
 629 #define use_vga_switcheroo(chip)        0
 630 #endif
 631
 632 static char *driver_short_names[] = {
 633         [AZX_DRIVER_ICH] = "HDA Intel",
 634         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 635         [AZX_DRIVER_SCH] = "HDA Intel MID",
 636         [AZX_DRIVER_ATI] = "HDA ATI SB",
 637         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 638         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 639         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 640         [AZX_DRIVER_SIS] = "HDA SIS966",
 641         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 642         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 643         [AZX_DRIVER_TERA] = "HDA Teradici",
 644         [AZX_DRIVER_CTX] = "HDA Creative",
 645         [AZX_DRIVER_CTHDA] = "HDA Creative",
 646         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 647 };
 648
 649 /*
 650  * macros for easy use
 651  */
 652 #define azx_writel(chip,reg,value) \
 653         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 654 #define azx_readl(chip,reg) \
 655         readl((chip)->remap_addr + ICH6_REG_##reg)
 656 #define azx_writew(chip,reg,value) \
 657         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 658 #define azx_readw(chip,reg) \
 659         readw((chip)->remap_addr + ICH6_REG_##reg)
 660 #define azx_writeb(chip,reg,value) \
 661         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 662 #define azx_readb(chip,reg) \
 663         readb((chip)->remap_addr + ICH6_REG_##reg)
 664
 665 #define azx_sd_writel(dev,reg,value) \
 666         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 667 #define azx_sd_readl(dev,reg) \
 668         readl((dev)->sd_addr + ICH6_REG_##reg)
 669 #define azx_sd_writew(dev,reg,value) \
 670         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 671 #define azx_sd_readw(dev,reg) \
 672         readw((dev)->sd_addr + ICH6_REG_##reg)
 673 #define azx_sd_writeb(dev,reg,value) \
 674         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 675 #define azx_sd_readb(dev,reg) \
 676         readb((dev)->sd_addr + ICH6_REG_##reg)
 677
 678 /* for pcm support */
 679 #define get_azx_dev(substream) (substream->runtime->private_data)
 680
 681 #ifdef CONFIG_X86
 682 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 683 {
 684         int pages;
 685
 686         if (azx_snoop(chip))
 687                 return;
 688         if (!dmab || !dmab->area || !dmab->bytes)
 689                 return;
 690
 691 #ifdef CONFIG_SND_DMA_SGBUF
 692         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 693                 struct snd_sg_buf *sgbuf = dmab->private_data;
 694                 if (on)
 695                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 696                 else
 697                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 698                 return;
 699         }
 700 #endif
 701
 702         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 703         if (on)
 704                 set_memory_wc((unsigned long)dmab->area, pages);
 705         else
 706                 set_memory_wb((unsigned long)dmab->area, pages);
 707 }
 708
 709 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 710                                  bool on)
 711 {
 712         __mark_pages_wc(chip, buf, on);
 713 }
 714 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 715                                    struct snd_pcm_substream *substream, bool on)
 716 {
 717         if (azx_dev->wc_marked != on) {
 718                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 719                 azx_dev->wc_marked = on;
 720         }
 721 }
 722 #else
 723 /* NOP for other archs */
 724 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 725                                  bool on)
 726 {
 727 }
 728 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 729                                    struct snd_pcm_substream *substream, bool on)
 730 {
 731 }
 732 #endif
 733
 734 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 735 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 736 /*
 737  * Interface for HD codec
 738  */
 739
 740 /*
 741  * CORB / RIRB interface
 742  */
 743 static int azx_alloc_cmd_io(struct azx *chip)
 744 {
 745         int err;
 746
 747         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 748         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 749                                   snd_dma_pci_data(chip->pci),
 750                                   PAGE_SIZE, &chip->rb);
 751         if (err < 0) {
 752                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
 753                 return err;
 754         }
 755         mark_pages_wc(chip, &chip->rb, true);
 756         return 0;
 757 }
 758
 759 static void azx_init_cmd_io(struct azx *chip)
 760 {
 761         spin_lock_irq(&chip->reg_lock);
 762         /* CORB set up */
 763         chip->corb.addr = chip->rb.addr;
 764         chip->corb.buf = (u32 *)chip->rb.area;
 765         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 766         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 767
 768         /* set the corb size to 256 entries (ULI requires explicitly) */
 769         azx_writeb(chip, CORBSIZE, 0x02);
 770         /* set the corb write pointer to 0 */
 771         azx_writew(chip, CORBWP, 0);
 772         /* reset the corb hw read pointer */
 773         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 774         /* enable corb dma */
 775         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 776
 777         /* RIRB set up */
 778         chip->rirb.addr = chip->rb.addr + 2048;
 779         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 780         chip->rirb.wp = chip->rirb.rp = 0;
 781         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 782         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 783         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 784
 785         /* set the rirb size to 256 entries (ULI requires explicitly) */
 786         azx_writeb(chip, RIRBSIZE, 0x02);
 787         /* reset the rirb hw write pointer */
 788         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 789         /* set N=1, get RIRB response interrupt for new entry */
 790         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 791                 azx_writew(chip, RINTCNT, 0xc0);
 792         else
 793                 azx_writew(chip, RINTCNT, 1);
 794         /* enable rirb dma and response irq */
 795         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 796         spin_unlock_irq(&chip->reg_lock);
 797 }
 798
 799 static void azx_free_cmd_io(struct azx *chip)
 800 {
 801         spin_lock_irq(&chip->reg_lock);
 802         /* disable ringbuffer DMAs */
 803         azx_writeb(chip, RIRBCTL, 0);
 804         azx_writeb(chip, CORBCTL, 0);
 805         spin_unlock_irq(&chip->reg_lock);
 806 }
 807
 808 static unsigned int azx_command_addr(u32 cmd)
 809 {
 810         unsigned int addr = cmd >> 28;
 811
 812         if (addr >= AZX_MAX_CODECS) {
 813                 snd_BUG();
 814                 addr = 0;
 815         }
 816
 817         return addr;
 818 }
 819
 820 static unsigned int azx_response_addr(u32 res)
 821 {
 822         unsigned int addr = res & 0xf;
 823
 824         if (addr >= AZX_MAX_CODECS) {
 825                 snd_BUG();
 826                 addr = 0;
 827         }
 828
 829         return addr;
 830 }
 831
 832 /* send a command */
 833 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 834 {
 835         struct azx *chip = bus->private_data;
 836         unsigned int addr = azx_command_addr(val);
 837         unsigned int wp, rp;
 838
 839         spin_lock_irq(&chip->reg_lock);
 840
 841         /* add command to corb */
 842         wp = azx_readw(chip, CORBWP);
 843         if (wp == 0xffff) {
 844                 /* something wrong, controller likely turned to D3 */
 845                 spin_unlock_irq(&chip->reg_lock);
 846                 return -EIO;
 847         }
 848         wp++;
 849         wp %= ICH6_MAX_CORB_ENTRIES;
 850
 851         rp = azx_readw(chip, CORBRP);
 852         if (wp == rp) {
 853                 /* oops, it's full */
 854                 spin_unlock_irq(&chip->reg_lock);
 855                 return -EAGAIN;
 856         }
 857
 858         chip->rirb.cmds[addr]++;
 859         chip->corb.buf[wp] = cpu_to_le32(val);
 860         azx_writel(chip, CORBWP, wp);
 861
 862         spin_unlock_irq(&chip->reg_lock);
 863
 864         return 0;
 865 }
 866
 867 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 868
 869 /* retrieve RIRB entry - called from interrupt handler */
 870 static void azx_update_rirb(struct azx *chip)
 871 {
 872         unsigned int rp, wp;
 873         unsigned int addr;
 874         u32 res, res_ex;
 875
 876         wp = azx_readw(chip, RIRBWP);
 877         if (wp == 0xffff) {
 878                 /* something wrong, controller likely turned to D3 */
 879                 return;
 880         }
 881
 882         if (wp == chip->rirb.wp)
 883                 return;
 884         chip->rirb.wp = wp;
 885
 886         while (chip->rirb.rp != wp) {
 887                 chip->rirb.rp++;
 888                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 889
 890                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 891                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 892                 res = le32_to_cpu(chip->rirb.buf[rp]);
 893                 addr = azx_response_addr(res_ex);
 894                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 895                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 896                 else if (chip->rirb.cmds[addr]) {
 897                         chip->rirb.res[addr] = res;
 898                         smp_wmb();
 899                         chip->rirb.cmds[addr]--;
 900                 } else
 901                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
 902                                    "last cmd=%#08x\n",
 903                                    pci_name(chip->pci),
 904                                    res, res_ex,
 905                                    chip->last_cmd[addr]);
 906         }
 907 }
 908
 909 /* receive a response */
 910 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 911                                           unsigned int addr)
 912 {
 913         struct azx *chip = bus->private_data;
 914         unsigned long timeout;
 915         unsigned long loopcounter;
 916         int do_poll = 0;
 917
 918  again:
 919         timeout = jiffies + msecs_to_jiffies(1000);
 920
 921         for (loopcounter = 0;; loopcounter++) {
 922                 if (chip->polling_mode || do_poll) {
 923                         spin_lock_irq(&chip->reg_lock);
 924                         azx_update_rirb(chip);
 925                         spin_unlock_irq(&chip->reg_lock);
 926                 }
 927                 if (!chip->rirb.cmds[addr]) {
 928                         smp_rmb();
 929                         bus->rirb_error = 0;
 930
 931                         if (!do_poll)
 932                                 chip->poll_count = 0;
 933                         return chip->rirb.res[addr]; /* the last value */
 934                 }
 935                 if (time_after(jiffies, timeout))
 936                         break;
 937                 if (bus->needs_damn_long_delay || loopcounter > 3000)
 938                         msleep(2); /* temporary workaround */
 939                 else {
 940                         udelay(10);
 941                         cond_resched();
 942                 }
 943         }
 944
 945         if (!chip->polling_mode && chip->poll_count < 2) {
 946                 snd_printdd(SFX "%s: azx_get_response timeout, "
 947                            "polling the codec once: last cmd=0x%08x\n",
 948                            pci_name(chip->pci), chip->last_cmd[addr]);
 949                 do_poll = 1;
 950                 chip->poll_count++;
 951                 goto again;
 952         }
 953
 954
 955         if (!chip->polling_mode) {
 956                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
 957                            "switching to polling mode: last cmd=0x%08x\n",
 958                            pci_name(chip->pci), chip->last_cmd[addr]);
 959                 chip->polling_mode = 1;
 960                 goto again;
 961         }
 962
 963         if (chip->msi) {
 964                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
 965                            "disabling MSI: last cmd=0x%08x\n",
 966                            pci_name(chip->pci), chip->last_cmd[addr]);
 967                 free_irq(chip->irq, chip);
 968                 chip->irq = -1;
 969                 pci_disable_msi(chip->pci);
 970                 chip->msi = 0;
 971                 if (azx_acquire_irq(chip, 1) < 0) {
 972                         bus->rirb_error = 1;
 973                         return -1;
 974                 }
 975                 goto again;
 976         }
 977
 978         if (chip->probing) {
 979                 /* If this critical timeout happens during the codec probing
 980                  * phase, this is likely an access to a non-existing codec
 981                  * slot.  Better to return an error and reset the system.
 982                  */
 983                 return -1;
 984         }
 985
 986         /* a fatal communication error; need either to reset or to fallback
 987          * to the single_cmd mode
 988          */
 989         bus->rirb_error = 1;
 990         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 991                 bus->response_reset = 1;
 992                 return -1; /* give a chance to retry */
 993         }
 994
 995         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 996                    "switching to single_cmd mode: last cmd=0x%08x\n",
 997                    chip->last_cmd[addr]);
 998         chip->single_cmd = 1;
 999         bus->response_reset = 0;
1000         /* release CORB/RIRB */
1001         azx_free_cmd_io(chip);
1002         /* disable unsolicited responses */
1003         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1004         return -1;
1005 }
1006
1007 /*
1008  * Use the single immediate command instead of CORB/RIRB for simplicity
1009  *
1010  * Note: according to Intel, this is not preferred use.  The command was
1011  *       intended for the BIOS only, and may get confused with unsolicited
1012  *       responses.  So, we shouldn't use it for normal operation from the
1013  *       driver.
1014  *       I left the codes, however, for debugging/testing purposes.
1015  */
1016
1017 /* receive a response */
1018 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1019 {
1020         int timeout = 50;
1021
1022         while (timeout--) {
1023                 /* check IRV busy bit */
1024                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1025                         /* reuse rirb.res as the response return value */
1026                         chip->rirb.res[addr] = azx_readl(chip, IR);
1027                         return 0;
1028                 }
1029                 udelay(1);
1030         }
1031         if (printk_ratelimit())
1032                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1033                            pci_name(chip->pci), azx_readw(chip, IRS));
1034         chip->rirb.res[addr] = -1;
1035         return -EIO;
1036 }
1037
1038 /* send a command */
1039 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1040 {
1041         struct azx *chip = bus->private_data;
1042         unsigned int addr = azx_command_addr(val);
1043         int timeout = 50;
1044
1045         bus->rirb_error = 0;
1046         while (timeout--) {
1047                 /* check ICB busy bit */
1048                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1049                         /* Clear IRV valid bit */
1050                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1051                                    ICH6_IRS_VALID);
1052                         azx_writel(chip, IC, val);
1053                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1054                                    ICH6_IRS_BUSY);
1055                         return azx_single_wait_for_response(chip, addr);
1056                 }
1057                 udelay(1);
1058         }
1059         if (printk_ratelimit())
1060                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1061                            pci_name(chip->pci), azx_readw(chip, IRS), val);
1062         return -EIO;
1063 }
1064
1065 /* receive a response */
1066 static unsigned int azx_single_get_response(struct hda_bus *bus,
1067                                             unsigned int addr)
1068 {
1069         struct azx *chip = bus->private_data;
1070         return chip->rirb.res[addr];
1071 }
1072
1073 /*
1074  * The below are the main callbacks from hda_codec.
1075  *
1076  * They are just the skeleton to call sub-callbacks according to the
1077  * current setting of chip->single_cmd.
1078  */
1079
1080 /* send a command */
1081 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1082 {
1083         struct azx *chip = bus->private_data;
1084
1085         if (chip->disabled)
1086                 return 0;
1087         chip->last_cmd[azx_command_addr(val)] = val;
1088         if (chip->single_cmd)
1089                 return azx_single_send_cmd(bus, val);
1090         else
1091                 return azx_corb_send_cmd(bus, val);
1092 }
1093
1094 /* get a response */
1095 static unsigned int azx_get_response(struct hda_bus *bus,
1096                                      unsigned int addr)
1097 {
1098         struct azx *chip = bus->private_data;
1099         if (chip->disabled)
1100                 return 0;
1101         if (chip->single_cmd)
1102                 return azx_single_get_response(bus, addr);
1103         else
1104                 return azx_rirb_get_response(bus, addr);
1105 }
1106
1107 #ifdef CONFIG_PM
1108 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1109 #endif
1110
1111 #ifdef CONFIG_SND_HDA_DSP_LOADER
1112 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1113                                 unsigned int byte_size,
1114                                 struct snd_dma_buffer *bufp);
1115 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1116 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1117                                  struct snd_dma_buffer *dmab);
1118 #endif
1119
1120 /* reset codec link */
1121 static int azx_reset(struct azx *chip, int full_reset)
1122 {
1123         unsigned long timeout;
1124
1125         if (!full_reset)
1126                 goto __skip;
1127
1128         /* clear STATESTS */
1129         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1130
1131         /* reset controller */
1132         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1133
1134         timeout = jiffies + msecs_to_jiffies(100);
1135         while (azx_readb(chip, GCTL) &&
1136                         time_before(jiffies, timeout))
1137                 usleep_range(500, 1000);
1138
1139         /* delay for >= 100us for codec PLL to settle per spec
1140          * Rev 0.9 section 5.5.1
1141          */
1142         usleep_range(500, 1000);
1143
1144         /* Bring controller out of reset */
1145         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1146
1147         timeout = jiffies + msecs_to_jiffies(100);
1148         while (!azx_readb(chip, GCTL) &&
1149                         time_before(jiffies, timeout))
1150                 usleep_range(500, 1000);
1151
1152         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1153         usleep_range(1000, 1200);
1154
1155       __skip:
1156         /* check to see if controller is ready */
1157         if (!azx_readb(chip, GCTL)) {
1158                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1159                 return -EBUSY;
1160         }
1161
1162         /* Accept unsolicited responses */
1163         if (!chip->single_cmd)
1164                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1165                            ICH6_GCTL_UNSOL);
1166
1167         /* detect codecs */
1168         if (!chip->codec_mask) {
1169                 chip->codec_mask = azx_readw(chip, STATESTS);
1170                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1171         }
1172
1173         return 0;
1174 }
1175
1176
1177 /*
1178  * Lowlevel interface
1179  */
1180
1181 /* enable interrupts */
1182 static void azx_int_enable(struct azx *chip)
1183 {
1184         /* enable controller CIE and GIE */
1185         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1186                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1187 }
1188
1189 /* disable interrupts */
1190 static void azx_int_disable(struct azx *chip)
1191 {
1192         int i;
1193
1194         /* disable interrupts in stream descriptor */
1195         for (i = 0; i < chip->num_streams; i++) {
1196                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1197                 azx_sd_writeb(azx_dev, SD_CTL,
1198                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1199         }
1200
1201         /* disable SIE for all streams */
1202         azx_writeb(chip, INTCTL, 0);
1203
1204         /* disable controller CIE and GIE */
1205         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1206                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1207 }
1208
1209 /* clear interrupts */
1210 static void azx_int_clear(struct azx *chip)
1211 {
1212         int i;
1213
1214         /* clear stream status */
1215         for (i = 0; i < chip->num_streams; i++) {
1216                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1217                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1218         }
1219
1220         /* clear STATESTS */
1221         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1222
1223         /* clear rirb status */
1224         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1225
1226         /* clear int status */
1227         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1228 }
1229
1230 /* start a stream */
1231 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1232 {
1233         /*
1234          * Before stream start, initialize parameter
1235          */
1236         azx_dev->insufficient = 1;
1237
1238         /* enable SIE */
1239         azx_writel(chip, INTCTL,
1240                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1241         /* set DMA start and interrupt mask */
1242         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1243                       SD_CTL_DMA_START | SD_INT_MASK);
1244 }
1245
1246 /* stop DMA */
1247 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1248 {
1249         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1250                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1251         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1252 }
1253
1254 /* stop a stream */
1255 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1256 {
1257         azx_stream_clear(chip, azx_dev);
1258         /* disable SIE */
1259         azx_writel(chip, INTCTL,
1260                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1261 }
1262
1263
1264 /*
1265  * reset and start the controller registers
1266  */
1267 static void azx_init_chip(struct azx *chip, int full_reset)
1268 {
1269         if (chip->initialized)
1270                 return;
1271
1272         /* reset controller */
1273         azx_reset(chip, full_reset);
1274
1275         /* initialize interrupts */
1276         azx_int_clear(chip);
1277         azx_int_enable(chip);
1278
1279         /* initialize the codec command I/O */
1280         if (!chip->single_cmd)
1281                 azx_init_cmd_io(chip);
1282
1283         /* program the position buffer */
1284         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1285         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1286
1287         chip->initialized = 1;
1288 }
1289
1290 /*
1291  * initialize the PCI registers
1292  */
1293 /* update bits in a PCI register byte */
1294 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1295                             unsigned char mask, unsigned char val)
1296 {
1297         unsigned char data;
1298
1299         pci_read_config_byte(pci, reg, &data);
1300         data &= ~mask;
1301         data |= (val & mask);
1302         pci_write_config_byte(pci, reg, data);
1303 }
1304
1305 static void azx_init_pci(struct azx *chip)
1306 {
1307         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1308          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1309          * Ensuring these bits are 0 clears playback static on some HD Audio
1310          * codecs.
1311          * The PCI register TCSEL is defined in the Intel manuals.
1312          */
1313         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1314                 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1315                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1316         }
1317
1318         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1319          * we need to enable snoop.
1320          */
1321         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1322                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1323                 update_pci_byte(chip->pci,
1324                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1325                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1326         }
1327
1328         /* For NVIDIA HDA, enable snoop */
1329         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1330                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1331                 update_pci_byte(chip->pci,
1332                                 NVIDIA_HDA_TRANSREG_ADDR,
1333                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1334                 update_pci_byte(chip->pci,
1335                                 NVIDIA_HDA_ISTRM_COH,
1336                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1337                 update_pci_byte(chip->pci,
1338                                 NVIDIA_HDA_OSTRM_COH,
1339                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1340         }
1341
1342         /* Enable SCH/PCH snoop if needed */
1343         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1344                 unsigned short snoop;
1345                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1346                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1347                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1348                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1349                         if (!azx_snoop(chip))
1350                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1351                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1352                         pci_read_config_word(chip->pci,
1353                                 INTEL_SCH_HDA_DEVC, &snoop);
1354                 }
1355                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1356                                 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1357                                 ? "Disabled" : "Enabled");
1358         }
1359 }
1360
1361
1362 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1363
1364 /*
1365  * interrupt handler
1366  */
1367 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1368 {
1369         struct azx *chip = dev_id;
1370         struct azx_dev *azx_dev;
1371         u32 status;
1372         u8 sd_status;
1373         int i, ok;
1374
1375 #ifdef CONFIG_PM_RUNTIME
1376         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1377                 return IRQ_NONE;
1378 #endif
1379
1380         spin_lock(&chip->reg_lock);
1381
1382         if (chip->disabled) {
1383                 spin_unlock(&chip->reg_lock);
1384                 return IRQ_NONE;
1385         }
1386
1387         status = azx_readl(chip, INTSTS);
1388         if (status == 0) {
1389                 spin_unlock(&chip->reg_lock);
1390                 return IRQ_NONE;
1391         }
1392
1393         for (i = 0; i < chip->num_streams; i++) {
1394                 azx_dev = &chip->azx_dev[i];
1395                 if (status & azx_dev->sd_int_sta_mask) {
1396                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1397                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1398                         if (!azx_dev->substream || !azx_dev->running ||
1399                             !(sd_status & SD_INT_COMPLETE))
1400                                 continue;
1401                         /* check whether this IRQ is really acceptable */
1402                         ok = azx_position_ok(chip, azx_dev);
1403                         if (ok == 1) {
1404                                 azx_dev->irq_pending = 0;
1405                                 spin_unlock(&chip->reg_lock);
1406                                 snd_pcm_period_elapsed(azx_dev->substream);
1407                                 spin_lock(&chip->reg_lock);
1408                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1409                                 /* bogus IRQ, process it later */
1410                                 azx_dev->irq_pending = 1;
1411                                 queue_work(chip->bus->workq,
1412                                            &chip->irq_pending_work);
1413                         }
1414                 }
1415         }
1416
1417         /* clear rirb int */
1418         status = azx_readb(chip, RIRBSTS);
1419         if (status & RIRB_INT_MASK) {
1420                 if (status & RIRB_INT_RESPONSE) {
1421                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1422                                 udelay(80);
1423                         azx_update_rirb(chip);
1424                 }
1425                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1426         }
1427
1428 #if 0
1429         /* clear state status int */
1430         if (azx_readb(chip, STATESTS) & 0x04)
1431                 azx_writeb(chip, STATESTS, 0x04);
1432 #endif
1433         spin_unlock(&chip->reg_lock);
1434
1435         return IRQ_HANDLED;
1436 }
1437
1438
1439 /*
1440  * set up a BDL entry
1441  */
1442 static int setup_bdle(struct azx *chip,
1443                       struct snd_dma_buffer *dmab,
1444                       struct azx_dev *azx_dev, u32 **bdlp,
1445                       int ofs, int size, int with_ioc)
1446 {
1447         u32 *bdl = *bdlp;
1448
1449         while (size > 0) {
1450                 dma_addr_t addr;
1451                 int chunk;
1452
1453                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1454                         return -EINVAL;
1455
1456                 addr = snd_sgbuf_get_addr(dmab, ofs);
1457                 /* program the address field of the BDL entry */
1458                 bdl[0] = cpu_to_le32((u32)addr);
1459                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1460                 /* program the size field of the BDL entry */
1461                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1462                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1463                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1464                         u32 remain = 0x1000 - (ofs & 0xfff);
1465                         if (chunk > remain)
1466                                 chunk = remain;
1467                 }
1468                 bdl[2] = cpu_to_le32(chunk);
1469                 /* program the IOC to enable interrupt
1470                  * only when the whole fragment is processed
1471                  */
1472                 size -= chunk;
1473                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1474                 bdl += 4;
1475                 azx_dev->frags++;
1476                 ofs += chunk;
1477         }
1478         *bdlp = bdl;
1479         return ofs;
1480 }
1481
1482 /*
1483  * set up BDL entries
1484  */
1485 static int azx_setup_periods(struct azx *chip,
1486                              struct snd_pcm_substream *substream,
1487                              struct azx_dev *azx_dev)
1488 {
1489         u32 *bdl;
1490         int i, ofs, periods, period_bytes;
1491         int pos_adj;
1492
1493         /* reset BDL address */
1494         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1495         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1496
1497         period_bytes = azx_dev->period_bytes;
1498         periods = azx_dev->bufsize / period_bytes;
1499
1500         /* program the initial BDL entries */
1501         bdl = (u32 *)azx_dev->bdl.area;
1502         ofs = 0;
1503         azx_dev->frags = 0;
1504         pos_adj = bdl_pos_adj[chip->dev_index];
1505         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1506                 struct snd_pcm_runtime *runtime = substream->runtime;
1507                 int pos_align = pos_adj;
1508                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1509                 if (!pos_adj)
1510                         pos_adj = pos_align;
1511                 else
1512                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1513                                 pos_align;
1514                 pos_adj = frames_to_bytes(runtime, pos_adj);
1515                 if (pos_adj >= period_bytes) {
1516                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1517                                    pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1518                         pos_adj = 0;
1519                 } else {
1520                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1521                                          azx_dev,
1522                                          &bdl, ofs, pos_adj, true);
1523                         if (ofs < 0)
1524                                 goto error;
1525                 }
1526         } else
1527                 pos_adj = 0;
1528         for (i = 0; i < periods; i++) {
1529                 if (i == periods - 1 && pos_adj)
1530                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1531                                          azx_dev, &bdl, ofs,
1532                                          period_bytes - pos_adj, 0);
1533                 else
1534                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1535                                          azx_dev, &bdl, ofs,
1536                                          period_bytes,
1537                                          !azx_dev->no_period_wakeup);
1538                 if (ofs < 0)
1539                         goto error;
1540         }
1541         return 0;
1542
1543  error:
1544         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1545                    pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1546         return -EINVAL;
1547 }
1548
1549 /* reset stream */
1550 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1551 {
1552         unsigned char val;
1553         int timeout;
1554
1555         azx_stream_clear(chip, azx_dev);
1556
1557         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1558                       SD_CTL_STREAM_RESET);
1559         udelay(3);
1560         timeout = 300;
1561         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1562                --timeout)
1563                 ;
1564         val &= ~SD_CTL_STREAM_RESET;
1565         azx_sd_writeb(azx_dev, SD_CTL, val);
1566         udelay(3);
1567
1568         timeout = 300;
1569         /* waiting for hardware to report that the stream is out of reset */
1570         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1571                --timeout)
1572                 ;
1573
1574         /* reset first position - may not be synced with hw at this time */
1575         *azx_dev->posbuf = 0;
1576 }
1577
1578 /*
1579  * set up the SD for streaming
1580  */
1581 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1582 {
1583         unsigned int val;
1584         /* make sure the run bit is zero for SD */
1585         azx_stream_clear(chip, azx_dev);
1586         /* program the stream_tag */
1587         val = azx_sd_readl(azx_dev, SD_CTL);
1588         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1589                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1590         if (!azx_snoop(chip))
1591                 val |= SD_CTL_TRAFFIC_PRIO;
1592         azx_sd_writel(azx_dev, SD_CTL, val);
1593
1594         /* program the length of samples in cyclic buffer */
1595         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1596
1597         /* program the stream format */
1598         /* this value needs to be the same as the one programmed */
1599         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1600
1601         /* program the stream LVI (last valid index) of the BDL */
1602         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1603
1604         /* program the BDL address */
1605         /* lower BDL address */
1606         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1607         /* upper BDL address */
1608         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1609
1610         /* enable the position buffer */
1611         if (chip->position_fix[0] != POS_FIX_LPIB ||
1612             chip->position_fix[1] != POS_FIX_LPIB) {
1613                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1614                         azx_writel(chip, DPLBASE,
1615                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1616         }
1617
1618         /* set the interrupt enable bits in the descriptor control register */
1619         azx_sd_writel(azx_dev, SD_CTL,
1620                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1621
1622         return 0;
1623 }
1624
1625 /*
1626  * Probe the given codec address
1627  */
1628 static int probe_codec(struct azx *chip, int addr)
1629 {
1630         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1631                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1632         unsigned int res;
1633
1634         mutex_lock(&chip->bus->cmd_mutex);
1635         chip->probing = 1;
1636         azx_send_cmd(chip->bus, cmd);
1637         res = azx_get_response(chip->bus, addr);
1638         chip->probing = 0;
1639         mutex_unlock(&chip->bus->cmd_mutex);
1640         if (res == -1)
1641                 return -EIO;
1642         snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1643         return 0;
1644 }
1645
1646 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1647                                  struct hda_pcm *cpcm);
1648 static void azx_stop_chip(struct azx *chip);
1649
1650 static void azx_bus_reset(struct hda_bus *bus)
1651 {
1652         struct azx *chip = bus->private_data;
1653
1654         bus->in_reset = 1;
1655         azx_stop_chip(chip);
1656         azx_init_chip(chip, 1);
1657 #ifdef CONFIG_PM
1658         if (chip->initialized) {
1659                 struct azx_pcm *p;
1660                 list_for_each_entry(p, &chip->pcm_list, list)
1661                         snd_pcm_suspend_all(p->pcm);
1662                 snd_hda_suspend(chip->bus);
1663                 snd_hda_resume(chip->bus);
1664         }
1665 #endif
1666         bus->in_reset = 0;
1667 }
1668
1669 static int get_jackpoll_interval(struct azx *chip)
1670 {
1671         int i = jackpoll_ms[chip->dev_index];
1672         unsigned int j;
1673         if (i == 0)
1674                 return 0;
1675         if (i < 50 || i > 60000)
1676                 j = 0;
1677         else
1678                 j = msecs_to_jiffies(i);
1679         if (j == 0)
1680                 snd_printk(KERN_WARNING SFX
1681                            "jackpoll_ms value out of range: %d\n", i);
1682         return j;
1683 }
1684
1685 /*
1686  * Codec initialization
1687  */
1688
1689 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1690 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1691         [AZX_DRIVER_NVIDIA] = 8,
1692         [AZX_DRIVER_TERA] = 1,
1693 };
1694
1695 static int azx_codec_create(struct azx *chip, const char *model)
1696 {
1697         struct hda_bus_template bus_temp;
1698         int c, codecs, err;
1699         int max_slots;
1700
1701         memset(&bus_temp, 0, sizeof(bus_temp));
1702         bus_temp.private_data = chip;
1703         bus_temp.modelname = model;
1704         bus_temp.pci = chip->pci;
1705         bus_temp.ops.command = azx_send_cmd;
1706         bus_temp.ops.get_response = azx_get_response;
1707         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1708         bus_temp.ops.bus_reset = azx_bus_reset;
1709 #ifdef CONFIG_PM
1710         bus_temp.power_save = &power_save;
1711         bus_temp.ops.pm_notify = azx_power_notify;
1712 #endif
1713 #ifdef CONFIG_SND_HDA_DSP_LOADER
1714         bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1715         bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1716         bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1717 #endif
1718
1719         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1720         if (err < 0)
1721                 return err;
1722
1723         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1724                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1725                 chip->bus->needs_damn_long_delay = 1;
1726         }
1727
1728         codecs = 0;
1729         max_slots = azx_max_codecs[chip->driver_type];
1730         if (!max_slots)
1731                 max_slots = AZX_DEFAULT_CODECS;
1732
1733         /* First try to probe all given codec slots */
1734         for (c = 0; c < max_slots; c++) {
1735                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1736                         if (probe_codec(chip, c) < 0) {
1737                                 /* Some BIOSen give you wrong codec addresses
1738                                  * that don't exist
1739                                  */
1740                                 snd_printk(KERN_WARNING SFX
1741                                            "%s: Codec #%d probe error; "
1742                                            "disabling it...\n", pci_name(chip->pci), c);
1743                                 chip->codec_mask &= ~(1 << c);
1744                                 /* More badly, accessing to a non-existing
1745                                  * codec often screws up the controller chip,
1746                                  * and disturbs the further communications.
1747                                  * Thus if an error occurs during probing,
1748                                  * better to reset the controller chip to
1749                                  * get back to the sanity state.
1750                                  */
1751                                 azx_stop_chip(chip);
1752                                 azx_init_chip(chip, 1);
1753                         }
1754                 }
1755         }
1756
1757         /* AMD chipsets often cause the communication stalls upon certain
1758          * sequence like the pin-detection.  It seems that forcing the synced
1759          * access works around the stall.  Grrr...
1760          */
1761         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1762                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1763                         pci_name(chip->pci));
1764                 chip->bus->sync_write = 1;
1765                 chip->bus->allow_bus_reset = 1;
1766         }
1767
1768         /* Then create codec instances */
1769         for (c = 0; c < max_slots; c++) {
1770                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1771                         struct hda_codec *codec;
1772                         err = snd_hda_codec_new(chip->bus, c, &codec);
1773                         if (err < 0)
1774                                 continue;
1775                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1776                         codec->beep_mode = chip->beep_mode;
1777                         codecs++;
1778                 }
1779         }
1780         if (!codecs) {
1781                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1782                 return -ENXIO;
1783         }
1784         return 0;
1785 }
1786
1787 /* configure each codec instance */
1788 static int azx_codec_configure(struct azx *chip)
1789 {
1790         struct hda_codec *codec;
1791         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1792                 snd_hda_codec_configure(codec);
1793         }
1794         return 0;
1795 }
1796
1797
1798 /*
1799  * PCM support
1800  */
1801
1802 /* assign a stream for the PCM */
1803 static inline struct azx_dev *
1804 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1805 {
1806         int dev, i, nums;
1807         struct azx_dev *res = NULL;
1808         /* make a non-zero unique key for the substream */
1809         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1810                 (substream->stream + 1);
1811
1812         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1813                 dev = chip->playback_index_offset;
1814                 nums = chip->playback_streams;
1815         } else {
1816                 dev = chip->capture_index_offset;
1817                 nums = chip->capture_streams;
1818         }
1819         for (i = 0; i < nums; i++, dev++) {
1820                 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1821                 dsp_lock(azx_dev);
1822                 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1823                         res = azx_dev;
1824                         if (res->assigned_key == key) {
1825                                 res->opened = 1;
1826                                 res->assigned_key = key;
1827                                 dsp_unlock(azx_dev);
1828                                 return azx_dev;
1829                         }
1830                 }
1831                 dsp_unlock(azx_dev);
1832         }
1833         if (res) {
1834                 dsp_lock(res);
1835                 res->opened = 1;
1836                 res->assigned_key = key;
1837                 dsp_unlock(res);
1838         }
1839         return res;
1840 }
1841
1842 /* release the assigned stream */
1843 static inline void azx_release_device(struct azx_dev *azx_dev)
1844 {
1845         azx_dev->opened = 0;
1846 }
1847
1848 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1849 {
1850         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1851         struct snd_pcm_substream *substream = azx_dev->substream;
1852         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1853         struct azx *chip = apcm->chip;
1854
1855         return azx_readl(chip, WALLCLK);
1856 }
1857
1858 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1859                                 bool force, cycle_t last)
1860 {
1861         struct azx_dev *azx_dev = get_azx_dev(substream);
1862         struct timecounter *tc = &azx_dev->azx_tc;
1863         struct cyclecounter *cc = &azx_dev->azx_cc;
1864         u64 nsec;
1865
1866         cc->read = azx_cc_read;
1867         cc->mask = CLOCKSOURCE_MASK(32);
1868
1869         /*
1870          * Converting from 24 MHz to ns means applying a 125/3 factor.
1871          * To avoid any saturation issues in intermediate operations,
1872          * the 125 factor is applied first. The division is applied
1873          * last after reading the timecounter value.
1874          * Applying the 1/3 factor as part of the multiplication
1875          * requires at least 20 bits for a decent precision, however
1876          * overflows occur after about 4 hours or less, not a option.
1877          */
1878
1879         cc->mult = 125; /* saturation after 195 years */
1880         cc->shift = 0;
1881
1882         nsec = 0; /* audio time is elapsed time since trigger */
1883         timecounter_init(tc, cc, nsec);
1884         if (force)
1885                 /*
1886                  * force timecounter to use predefined value,
1887                  * used for synchronized starts
1888                  */
1889                 tc->cycle_last = last;
1890 }
1891
1892 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1893                                 struct timespec *ts)
1894 {
1895         struct azx_dev *azx_dev = get_azx_dev(substream);
1896         u64 nsec;
1897
1898         nsec = timecounter_read(&azx_dev->azx_tc);
1899         nsec = div_u64(nsec, 3); /* can be optimized */
1900
1901         *ts = ns_to_timespec(nsec);
1902
1903         return 0;
1904 }
1905
1906 static struct snd_pcm_hardware azx_pcm_hw = {
1907         .info =                 (SNDRV_PCM_INFO_MMAP |
1908                                  SNDRV_PCM_INFO_INTERLEAVED |
1909                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1910                                  SNDRV_PCM_INFO_MMAP_VALID |
1911                                  /* No full-resume yet implemented */
1912                                  /* SNDRV_PCM_INFO_RESUME |*/
1913                                  SNDRV_PCM_INFO_PAUSE |
1914                                  SNDRV_PCM_INFO_SYNC_START |
1915                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1916                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1917         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1918         .rates =                SNDRV_PCM_RATE_48000,
1919         .rate_min =             48000,
1920         .rate_max =             48000,
1921         .channels_min =         2,
1922         .channels_max =         2,
1923         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1924         .period_bytes_min =     128,
1925         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1926         .periods_min =          2,
1927         .periods_max =          AZX_MAX_FRAG,
1928         .fifo_size =            0,
1929 };
1930
1931 static int azx_pcm_open(struct snd_pcm_substream *substream)
1932 {
1933         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1934         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1935         struct azx *chip = apcm->chip;
1936         struct azx_dev *azx_dev;
1937         struct snd_pcm_runtime *runtime = substream->runtime;
1938         unsigned long flags;
1939         int err;
1940         int buff_step;
1941
1942         mutex_lock(&chip->open_mutex);
1943         azx_dev = azx_assign_device(chip, substream);
1944         if (azx_dev == NULL) {
1945                 mutex_unlock(&chip->open_mutex);
1946                 return -EBUSY;
1947         }
1948         runtime->hw = azx_pcm_hw;
1949         runtime->hw.channels_min = hinfo->channels_min;
1950         runtime->hw.channels_max = hinfo->channels_max;
1951         runtime->hw.formats = hinfo->formats;
1952         runtime->hw.rates = hinfo->rates;
1953         snd_pcm_limit_hw_rates(runtime);
1954         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1955
1956         /* avoid wrap-around with wall-clock */
1957         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
1958                                 20,
1959                                 178000000);
1960
1961         if (chip->align_buffer_size)
1962                 /* constrain buffer sizes to be multiple of 128
1963                    bytes. This is more efficient in terms of memory
1964                    access but isn't required by the HDA spec and
1965                    prevents users from specifying exact period/buffer
1966                    sizes. For example for 44.1kHz, a period size set
1967                    to 20ms will be rounded to 19.59ms. */
1968                 buff_step = 128;
1969         else
1970                 /* Don't enforce steps on buffer sizes, still need to
1971                    be multiple of 4 bytes (HDA spec). Tested on Intel
1972                    HDA controllers, may not work on all devices where
1973                    option needs to be disabled */
1974                 buff_step = 4;
1975
1976         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1977                                    buff_step);
1978         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1979                                    buff_step);
1980         snd_hda_power_up_d3wait(apcm->codec);
1981         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1982         if (err < 0) {
1983                 azx_release_device(azx_dev);
1984                 snd_hda_power_down(apcm->codec);
1985                 mutex_unlock(&chip->open_mutex);
1986                 return err;
1987         }
1988         snd_pcm_limit_hw_rates(runtime);
1989         /* sanity check */
1990         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1991             snd_BUG_ON(!runtime->hw.channels_max) ||
1992             snd_BUG_ON(!runtime->hw.formats) ||
1993             snd_BUG_ON(!runtime->hw.rates)) {
1994                 azx_release_device(azx_dev);
1995                 hinfo->ops.close(hinfo, apcm->codec, substream);
1996                 snd_hda_power_down(apcm->codec);
1997                 mutex_unlock(&chip->open_mutex);
1998                 return -EINVAL;
1999         }
2000
2001         /* disable WALLCLOCK timestamps for capture streams
2002            until we figure out how to handle digital inputs */
2003         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2004                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2005
2006         spin_lock_irqsave(&chip->reg_lock, flags);
2007         azx_dev->substream = substream;
2008         azx_dev->running = 0;
2009         spin_unlock_irqrestore(&chip->reg_lock, flags);
2010
2011         runtime->private_data = azx_dev;
2012         snd_pcm_set_sync(substream);
2013         mutex_unlock(&chip->open_mutex);
2014         return 0;
2015 }
2016
2017 static int azx_pcm_close(struct snd_pcm_substream *substream)
2018 {
2019         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2020         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2021         struct azx *chip = apcm->chip;
2022         struct azx_dev *azx_dev = get_azx_dev(substream);
2023         unsigned long flags;
2024
2025         mutex_lock(&chip->open_mutex);
2026         spin_lock_irqsave(&chip->reg_lock, flags);
2027         azx_dev->substream = NULL;
2028         azx_dev->running = 0;
2029         spin_unlock_irqrestore(&chip->reg_lock, flags);
2030         azx_release_device(azx_dev);
2031         hinfo->ops.close(hinfo, apcm->codec, substream);
2032         snd_hda_power_down(apcm->codec);
2033         mutex_unlock(&chip->open_mutex);
2034         return 0;
2035 }
2036
2037 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2038                              struct snd_pcm_hw_params *hw_params)
2039 {
2040         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2041         struct azx *chip = apcm->chip;
2042         struct azx_dev *azx_dev = get_azx_dev(substream);
2043         int ret;
2044
2045         dsp_lock(azx_dev);
2046         if (dsp_is_locked(azx_dev)) {
2047                 ret = -EBUSY;
2048                 goto unlock;
2049         }
2050
2051         mark_runtime_wc(chip, azx_dev, substream, false);
2052         azx_dev->bufsize = 0;
2053         azx_dev->period_bytes = 0;
2054         azx_dev->format_val = 0;
2055         ret = snd_pcm_lib_malloc_pages(substream,
2056                                         params_buffer_bytes(hw_params));
2057         if (ret < 0)
2058                 goto unlock;
2059         mark_runtime_wc(chip, azx_dev, substream, true);
2060  unlock:
2061         dsp_unlock(azx_dev);
2062         return ret;
2063 }
2064
2065 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2066 {
2067         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2068         struct azx_dev *azx_dev = get_azx_dev(substream);
2069         struct azx *chip = apcm->chip;
2070         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2071
2072         /* reset BDL address */
2073         dsp_lock(azx_dev);
2074         if (!dsp_is_locked(azx_dev)) {
2075                 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2076                 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2077                 azx_sd_writel(azx_dev, SD_CTL, 0);
2078                 azx_dev->bufsize = 0;
2079                 azx_dev->period_bytes = 0;
2080                 azx_dev->format_val = 0;
2081         }
2082
2083         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2084
2085         mark_runtime_wc(chip, azx_dev, substream, false);
2086         azx_dev->prepared = 0;
2087         dsp_unlock(azx_dev);
2088         return snd_pcm_lib_free_pages(substream);
2089 }
2090
2091 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2092 {
2093         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2094         struct azx *chip = apcm->chip;
2095         struct azx_dev *azx_dev = get_azx_dev(substream);
2096         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2097         struct snd_pcm_runtime *runtime = substream->runtime;
2098         unsigned int bufsize, period_bytes, format_val, stream_tag;
2099         int err;
2100         struct hda_spdif_out *spdif =
2101                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2102         unsigned short ctls = spdif ? spdif->ctls : 0;
2103
2104         dsp_lock(azx_dev);
2105         if (dsp_is_locked(azx_dev)) {
2106                 err = -EBUSY;
2107                 goto unlock;
2108         }
2109
2110         azx_stream_reset(chip, azx_dev);
2111         format_val = snd_hda_calc_stream_format(runtime->rate,
2112                                                 runtime->channels,
2113                                                 runtime->format,
2114                                                 hinfo->maxbps,
2115                                                 ctls);
2116         if (!format_val) {
2117                 snd_printk(KERN_ERR SFX
2118                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2119                            pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2120                 err = -EINVAL;
2121                 goto unlock;
2122         }
2123
2124         bufsize = snd_pcm_lib_buffer_bytes(substream);
2125         period_bytes = snd_pcm_lib_period_bytes(substream);
2126
2127         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2128                     pci_name(chip->pci), bufsize, format_val);
2129
2130         if (bufsize != azx_dev->bufsize ||
2131             period_bytes != azx_dev->period_bytes ||
2132             format_val != azx_dev->format_val ||
2133             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2134                 azx_dev->bufsize = bufsize;
2135                 azx_dev->period_bytes = period_bytes;
2136                 azx_dev->format_val = format_val;
2137                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2138                 err = azx_setup_periods(chip, substream, azx_dev);
2139                 if (err < 0)
2140                         goto unlock;
2141         }
2142
2143         /* wallclk has 24Mhz clock source */
2144         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2145                                                 runtime->rate) * 1000);
2146         azx_setup_controller(chip, azx_dev);
2147         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2148                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2149         else
2150                 azx_dev->fifo_size = 0;
2151
2152         stream_tag = azx_dev->stream_tag;
2153         /* CA-IBG chips need the playback stream starting from 1 */
2154         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2155             stream_tag > chip->capture_streams)
2156                 stream_tag -= chip->capture_streams;
2157         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2158                                      azx_dev->format_val, substream);
2159
2160  unlock:
2161         if (!err)
2162                 azx_dev->prepared = 1;
2163         dsp_unlock(azx_dev);
2164         return err;
2165 }
2166
2167 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2168 {
2169         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2170         struct azx *chip = apcm->chip;
2171         struct azx_dev *azx_dev;
2172         struct snd_pcm_substream *s;
2173         int rstart = 0, start, nsync = 0, sbits = 0;
2174         int nwait, timeout;
2175
2176         azx_dev = get_azx_dev(substream);
2177         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2178
2179         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2180                 return -EPIPE;
2181
2182         switch (cmd) {
2183         case SNDRV_PCM_TRIGGER_START:
2184                 rstart = 1;
2185         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2186         case SNDRV_PCM_TRIGGER_RESUME:
2187                 start = 1;
2188                 break;
2189         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2190         case SNDRV_PCM_TRIGGER_SUSPEND:
2191         case SNDRV_PCM_TRIGGER_STOP:
2192                 start = 0;
2193                 break;
2194         default:
2195                 return -EINVAL;
2196         }
2197
2198         snd_pcm_group_for_each_entry(s, substream) {
2199                 if (s->pcm->card != substream->pcm->card)
2200                         continue;
2201                 azx_dev = get_azx_dev(s);
2202                 sbits |= 1 << azx_dev->index;
2203                 nsync++;
2204                 snd_pcm_trigger_done(s, substream);
2205         }
2206
2207         spin_lock(&chip->reg_lock);
2208
2209         /* first, set SYNC bits of corresponding streams */
2210         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2211                 azx_writel(chip, OLD_SSYNC,
2212                         azx_readl(chip, OLD_SSYNC) | sbits);
2213         else
2214                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2215
2216         snd_pcm_group_for_each_entry(s, substream) {
2217                 if (s->pcm->card != substream->pcm->card)
2218                         continue;
2219                 azx_dev = get_azx_dev(s);
2220                 if (start) {
2221                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2222                         if (!rstart)
2223                                 azx_dev->start_wallclk -=
2224                                                 azx_dev->period_wallclk;
2225                         azx_stream_start(chip, azx_dev);
2226                 } else {
2227                         azx_stream_stop(chip, azx_dev);
2228                 }
2229                 azx_dev->running = start;
2230         }
2231         spin_unlock(&chip->reg_lock);
2232         if (start) {
2233                 /* wait until all FIFOs get ready */
2234                 for (timeout = 5000; timeout; timeout--) {
2235                         nwait = 0;
2236                         snd_pcm_group_for_each_entry(s, substream) {
2237                                 if (s->pcm->card != substream->pcm->card)
2238                                         continue;
2239                                 azx_dev = get_azx_dev(s);
2240                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2241                                       SD_STS_FIFO_READY))
2242                                         nwait++;
2243                         }
2244                         if (!nwait)
2245                                 break;
2246                         cpu_relax();
2247                 }
2248         } else {
2249                 /* wait until all RUN bits are cleared */
2250                 for (timeout = 5000; timeout; timeout--) {
2251                         nwait = 0;
2252                         snd_pcm_group_for_each_entry(s, substream) {
2253                                 if (s->pcm->card != substream->pcm->card)
2254                                         continue;
2255                                 azx_dev = get_azx_dev(s);
2256                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2257                                     SD_CTL_DMA_START)
2258                                         nwait++;
2259                         }
2260                         if (!nwait)
2261                                 break;
2262                         cpu_relax();
2263                 }
2264         }
2265         spin_lock(&chip->reg_lock);
2266         /* reset SYNC bits */
2267         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2268                 azx_writel(chip, OLD_SSYNC,
2269                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2270         else
2271                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2272         if (start) {
2273                 azx_timecounter_init(substream, 0, 0);
2274                 if (nsync > 1) {
2275                         cycle_t cycle_last;
2276
2277                         /* same start cycle for master and group */
2278                         azx_dev = get_azx_dev(substream);
2279                         cycle_last = azx_dev->azx_tc.cycle_last;
2280
2281                         snd_pcm_group_for_each_entry(s, substream) {
2282                                 if (s->pcm->card != substream->pcm->card)
2283                                         continue;
2284                                 azx_timecounter_init(s, 1, cycle_last);
2285                         }
2286                 }
2287         }
2288         spin_unlock(&chip->reg_lock);
2289         return 0;
2290 }
2291
2292 /* get the current DMA position with correction on VIA chips */
2293 static unsigned int azx_via_get_position(struct azx *chip,
2294                                          struct azx_dev *azx_dev)
2295 {
2296         unsigned int link_pos, mini_pos, bound_pos;
2297         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2298         unsigned int fifo_size;
2299
2300         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2301         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2302                 /* Playback, no problem using link position */
2303                 return link_pos;
2304         }
2305
2306         /* Capture */
2307         /* For new chipset,
2308          * use mod to get the DMA position just like old chipset
2309          */
2310         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2311         mod_dma_pos %= azx_dev->period_bytes;
2312
2313         /* azx_dev->fifo_size can't get FIFO size of in stream.
2314          * Get from base address + offset.
2315          */
2316         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2317
2318         if (azx_dev->insufficient) {
2319                 /* Link position never gather than FIFO size */
2320                 if (link_pos <= fifo_size)
2321                         return 0;
2322
2323                 azx_dev->insufficient = 0;
2324         }
2325
2326         if (link_pos <= fifo_size)
2327                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2328         else
2329                 mini_pos = link_pos - fifo_size;
2330
2331         /* Find nearest previous boudary */
2332         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2333         mod_link_pos = link_pos % azx_dev->period_bytes;
2334         if (mod_link_pos >= fifo_size)
2335                 bound_pos = link_pos - mod_link_pos;
2336         else if (mod_dma_pos >= mod_mini_pos)
2337                 bound_pos = mini_pos - mod_mini_pos;
2338         else {
2339                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2340                 if (bound_pos >= azx_dev->bufsize)
2341                         bound_pos = 0;
2342         }
2343
2344         /* Calculate real DMA position we want */
2345         return bound_pos + mod_dma_pos;
2346 }
2347
2348 static unsigned int azx_get_position(struct azx *chip,
2349                                      struct azx_dev *azx_dev,
2350                                      bool with_check)
2351 {
2352         unsigned int pos;
2353         int stream = azx_dev->substream->stream;
2354         int delay = 0;
2355
2356         switch (chip->position_fix[stream]) {
2357         case POS_FIX_LPIB:
2358                 /* read LPIB */
2359                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2360                 break;
2361         case POS_FIX_VIACOMBO:
2362                 pos = azx_via_get_position(chip, azx_dev);
2363                 break;
2364         default:
2365                 /* use the position buffer */
2366                 pos = le32_to_cpu(*azx_dev->posbuf);
2367                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2368                         if (!pos || pos == (u32)-1) {
2369                                 printk(KERN_WARNING
2370                                        "hda-intel: Invalid position buffer, "
2371                                        "using LPIB read method instead.\n");
2372                                 chip->position_fix[stream] = POS_FIX_LPIB;
2373                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2374                         } else
2375                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2376                 }
2377                 break;
2378         }
2379
2380         if (pos >= azx_dev->bufsize)
2381                 pos = 0;
2382
2383         /* calculate runtime delay from LPIB */
2384         if (azx_dev->substream->runtime &&
2385             chip->position_fix[stream] == POS_FIX_POSBUF &&
2386             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2387                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2388                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2389                         delay = pos - lpib_pos;
2390                 else
2391                         delay = lpib_pos - pos;
2392                 if (delay < 0)
2393                         delay += azx_dev->bufsize;
2394                 if (delay >= azx_dev->period_bytes) {
2395                         snd_printk(KERN_WARNING SFX
2396                                    "%s: Unstable LPIB (%d >= %d); "
2397                                    "disabling LPIB delay counting\n",
2398                                    pci_name(chip->pci), delay, azx_dev->period_bytes);
2399                         delay = 0;
2400                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2401                 }
2402                 azx_dev->substream->runtime->delay =
2403                         bytes_to_frames(azx_dev->substream->runtime, delay);
2404         }
2405         trace_azx_get_position(chip, azx_dev, pos, delay);
2406         return pos;
2407 }
2408
2409 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2410 {
2411         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2412         struct azx *chip = apcm->chip;
2413         struct azx_dev *azx_dev = get_azx_dev(substream);
2414         return bytes_to_frames(substream->runtime,
2415                                azx_get_position(chip, azx_dev, false));
2416 }
2417
2418 /*
2419  * Check whether the current DMA position is acceptable for updating
2420  * periods.  Returns non-zero if it's OK.
2421  *
2422  * Many HD-audio controllers appear pretty inaccurate about
2423  * the update-IRQ timing.  The IRQ is issued before actually the
2424  * data is processed.  So, we need to process it afterwords in a
2425  * workqueue.
2426  */
2427 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2428 {
2429         u32 wallclk;
2430         unsigned int pos;
2431
2432         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2433         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2434                 return -1;      /* bogus (too early) interrupt */
2435
2436         pos = azx_get_position(chip, azx_dev, true);
2437
2438         if (WARN_ONCE(!azx_dev->period_bytes,
2439                       "hda-intel: zero azx_dev->period_bytes"))
2440                 return -1; /* this shouldn't happen! */
2441         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2442             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2443                 /* NG - it's below the first next period boundary */
2444                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2445         azx_dev->start_wallclk += wallclk;
2446         return 1; /* OK, it's fine */
2447 }
2448
2449 /*
2450  * The work for pending PCM period updates.
2451  */
2452 static void azx_irq_pending_work(struct work_struct *work)
2453 {
2454         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2455         int i, pending, ok;
2456
2457         if (!chip->irq_pending_warned) {
2458                 printk(KERN_WARNING
2459                        "hda-intel: IRQ timing workaround is activated "
2460                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2461                        chip->card->number);
2462                 chip->irq_pending_warned = 1;
2463         }
2464
2465         for (;;) {
2466                 pending = 0;
2467                 spin_lock_irq(&chip->reg_lock);
2468                 for (i = 0; i < chip->num_streams; i++) {
2469                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2470                         if (!azx_dev->irq_pending ||
2471                             !azx_dev->substream ||
2472                             !azx_dev->running)
2473                                 continue;
2474                         ok = azx_position_ok(chip, azx_dev);
2475                         if (ok > 0) {
2476                                 azx_dev->irq_pending = 0;
2477                                 spin_unlock(&chip->reg_lock);
2478                                 snd_pcm_period_elapsed(azx_dev->substream);
2479                                 spin_lock(&chip->reg_lock);
2480                         } else if (ok < 0) {
2481                                 pending = 0;    /* too early */
2482                         } else
2483                                 pending++;
2484                 }
2485                 spin_unlock_irq(&chip->reg_lock);
2486                 if (!pending)
2487                         return;
2488                 msleep(1);
2489         }
2490 }
2491
2492 /* clear irq_pending flags and assure no on-going workq */
2493 static void azx_clear_irq_pending(struct azx *chip)
2494 {
2495         int i;
2496
2497         spin_lock_irq(&chip->reg_lock);
2498         for (i = 0; i < chip->num_streams; i++)
2499                 chip->azx_dev[i].irq_pending = 0;
2500         spin_unlock_irq(&chip->reg_lock);
2501 }
2502
2503 #ifdef CONFIG_X86
2504 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2505                         struct vm_area_struct *area)
2506 {
2507         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2508         struct azx *chip = apcm->chip;
2509         if (!azx_snoop(chip))
2510                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2511         return snd_pcm_lib_default_mmap(substream, area);
2512 }
2513 #else
2514 #define azx_pcm_mmap    NULL
2515 #endif
2516
2517 static struct snd_pcm_ops azx_pcm_ops = {
2518         .open = azx_pcm_open,
2519         .close = azx_pcm_close,
2520         .ioctl = snd_pcm_lib_ioctl,
2521         .hw_params = azx_pcm_hw_params,
2522         .hw_free = azx_pcm_hw_free,
2523         .prepare = azx_pcm_prepare,
2524         .trigger = azx_pcm_trigger,
2525         .pointer = azx_pcm_pointer,
2526         .wall_clock =  azx_get_wallclock_tstamp,
2527         .mmap = azx_pcm_mmap,
2528         .page = snd_pcm_sgbuf_ops_page,
2529 };
2530
2531 static void azx_pcm_free(struct snd_pcm *pcm)
2532 {
2533         struct azx_pcm *apcm = pcm->private_data;
2534         if (apcm) {
2535                 list_del(&apcm->list);
2536                 kfree(apcm);
2537         }
2538 }
2539
2540 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2541
2542 static int
2543 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2544                       struct hda_pcm *cpcm)
2545 {
2546         struct azx *chip = bus->private_data;
2547         struct snd_pcm *pcm;
2548         struct azx_pcm *apcm;
2549         int pcm_dev = cpcm->device;
2550         unsigned int size;
2551         int s, err;
2552
2553         list_for_each_entry(apcm, &chip->pcm_list, list) {
2554                 if (apcm->pcm->device == pcm_dev) {
2555                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2556                                    pci_name(chip->pci), pcm_dev);
2557                         return -EBUSY;
2558                 }
2559         }
2560         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2561                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2562                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2563                           &pcm);
2564         if (err < 0)
2565                 return err;
2566         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2567         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2568         if (apcm == NULL)
2569                 return -ENOMEM;
2570         apcm->chip = chip;
2571         apcm->pcm = pcm;
2572         apcm->codec = codec;
2573         pcm->private_data = apcm;
2574         pcm->private_free = azx_pcm_free;
2575         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2576                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2577         list_add_tail(&apcm->list, &chip->pcm_list);
2578         cpcm->pcm = pcm;
2579         for (s = 0; s < 2; s++) {
2580                 apcm->hinfo[s] = &cpcm->stream[s];
2581                 if (cpcm->stream[s].substreams)
2582                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2583         }
2584         /* buffer pre-allocation */
2585         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2586         if (size > MAX_PREALLOC_SIZE)
2587                 size = MAX_PREALLOC_SIZE;
2588         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2589                                               snd_dma_pci_data(chip->pci),
2590                                               size, MAX_PREALLOC_SIZE);
2591         return 0;
2592 }
2593
2594 /*
2595  * mixer creation - all stuff is implemented in hda module
2596  */
2597 static int azx_mixer_create(struct azx *chip)
2598 {
2599         return snd_hda_build_controls(chip->bus);
2600 }
2601
2602
2603 /*
2604  * initialize SD streams
2605  */
2606 static int azx_init_stream(struct azx *chip)
2607 {
2608         int i;
2609
2610         /* initialize each stream (aka device)
2611          * assign the starting bdl address to each stream (device)
2612          * and initialize
2613          */
2614         for (i = 0; i < chip->num_streams; i++) {
2615                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2616                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2617                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2618                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2619                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2620                 azx_dev->sd_int_sta_mask = 1 << i;
2621                 /* stream tag: must be non-zero and unique */
2622                 azx_dev->index = i;
2623                 azx_dev->stream_tag = i + 1;
2624         }
2625
2626         return 0;
2627 }
2628
2629 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2630 {
2631         if (request_irq(chip->pci->irq, azx_interrupt,
2632                         chip->msi ? 0 : IRQF_SHARED,
2633                         KBUILD_MODNAME, chip)) {
2634                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2635                        "disabling device\n", chip->pci->irq);
2636                 if (do_disconnect)
2637                         snd_card_disconnect(chip->card);
2638                 return -1;
2639         }
2640         chip->irq = chip->pci->irq;
2641         pci_intx(chip->pci, !chip->msi);
2642         return 0;
2643 }
2644
2645
2646 static void azx_stop_chip(struct azx *chip)
2647 {
2648         if (!chip->initialized)
2649                 return;
2650
2651         /* disable interrupts */
2652         azx_int_disable(chip);
2653         azx_int_clear(chip);
2654
2655         /* disable CORB/RIRB */
2656         azx_free_cmd_io(chip);
2657
2658         /* disable position buffer */
2659         azx_writel(chip, DPLBASE, 0);
2660         azx_writel(chip, DPUBASE, 0);
2661
2662         chip->initialized = 0;
2663 }
2664
2665 #ifdef CONFIG_SND_HDA_DSP_LOADER
2666 /*
2667  * DSP loading code (e.g. for CA0132)
2668  */
2669
2670 /* use the first stream for loading DSP */
2671 static struct azx_dev *
2672 azx_get_dsp_loader_dev(struct azx *chip)
2673 {
2674         return &chip->azx_dev[chip->playback_index_offset];
2675 }
2676
2677 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2678                                 unsigned int byte_size,
2679                                 struct snd_dma_buffer *bufp)
2680 {
2681         u32 *bdl;
2682         struct azx *chip = bus->private_data;
2683         struct azx_dev *azx_dev;
2684         int err;
2685
2686         azx_dev = azx_get_dsp_loader_dev(chip);
2687
2688         dsp_lock(azx_dev);
2689         spin_lock_irq(&chip->reg_lock);
2690         if (azx_dev->running || azx_dev->locked) {
2691                 spin_unlock_irq(&chip->reg_lock);
2692                 err = -EBUSY;
2693                 goto unlock;
2694         }
2695         azx_dev->prepared = 0;
2696         chip->saved_azx_dev = *azx_dev;
2697         azx_dev->locked = 1;
2698         spin_unlock_irq(&chip->reg_lock);
2699
2700         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2701                                   snd_dma_pci_data(chip->pci),
2702                                   byte_size, bufp);
2703         if (err < 0)
2704                 goto err_alloc;
2705
2706         mark_pages_wc(chip, bufp, true);
2707         azx_dev->bufsize = byte_size;
2708         azx_dev->period_bytes = byte_size;
2709         azx_dev->format_val = format;
2710
2711         azx_stream_reset(chip, azx_dev);
2712
2713         /* reset BDL address */
2714         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2715         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2716
2717         azx_dev->frags = 0;
2718         bdl = (u32 *)azx_dev->bdl.area;
2719         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2720         if (err < 0)
2721                 goto error;
2722
2723         azx_setup_controller(chip, azx_dev);
2724         dsp_unlock(azx_dev);
2725         return azx_dev->stream_tag;
2726
2727  error:
2728         mark_pages_wc(chip, bufp, false);
2729         snd_dma_free_pages(bufp);
2730  err_alloc:
2731         spin_lock_irq(&chip->reg_lock);
2732         if (azx_dev->opened)
2733                 *azx_dev = chip->saved_azx_dev;
2734         azx_dev->locked = 0;
2735         spin_unlock_irq(&chip->reg_lock);
2736  unlock:
2737         dsp_unlock(azx_dev);
2738         return err;
2739 }
2740
2741 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2742 {
2743         struct azx *chip = bus->private_data;
2744         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2745
2746         if (start)
2747                 azx_stream_start(chip, azx_dev);
2748         else
2749                 azx_stream_stop(chip, azx_dev);
2750         azx_dev->running = start;
2751 }
2752
2753 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2754                                  struct snd_dma_buffer *dmab)
2755 {
2756         struct azx *chip = bus->private_data;
2757         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2758
2759         if (!dmab->area || !azx_dev->locked)
2760                 return;
2761
2762         dsp_lock(azx_dev);
2763         /* reset BDL address */
2764         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2765         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2766         azx_sd_writel(azx_dev, SD_CTL, 0);
2767         azx_dev->bufsize = 0;
2768         azx_dev->period_bytes = 0;
2769         azx_dev->format_val = 0;
2770
2771         mark_pages_wc(chip, dmab, false);
2772         snd_dma_free_pages(dmab);
2773         dmab->area = NULL;
2774
2775         spin_lock_irq(&chip->reg_lock);
2776         if (azx_dev->opened)
2777                 *azx_dev = chip->saved_azx_dev;
2778         azx_dev->locked = 0;
2779         spin_unlock_irq(&chip->reg_lock);
2780         dsp_unlock(azx_dev);
2781 }
2782 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2783
2784 #ifdef CONFIG_PM
2785 /* power-up/down the controller */
2786 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2787 {
2788         struct azx *chip = bus->private_data;
2789
2790         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2791                 return;
2792
2793         if (power_up)
2794                 pm_runtime_get_sync(&chip->pci->dev);
2795         else
2796                 pm_runtime_put_sync(&chip->pci->dev);
2797 }
2798
2799 static DEFINE_MUTEX(card_list_lock);
2800 static LIST_HEAD(card_list);
2801
2802 static void azx_add_card_list(struct azx *chip)
2803 {
2804         mutex_lock(&card_list_lock);
2805         list_add(&chip->list, &card_list);
2806         mutex_unlock(&card_list_lock);
2807 }
2808
2809 static void azx_del_card_list(struct azx *chip)
2810 {
2811         mutex_lock(&card_list_lock);
2812         list_del_init(&chip->list);
2813         mutex_unlock(&card_list_lock);
2814 }
2815
2816 /* trigger power-save check at writing parameter */
2817 static int param_set_xint(const char *val, const struct kernel_param *kp)
2818 {
2819         struct azx *chip;
2820         struct hda_codec *c;
2821         int prev = power_save;
2822         int ret = param_set_int(val, kp);
2823
2824         if (ret || prev == power_save)
2825                 return ret;
2826
2827         mutex_lock(&card_list_lock);
2828         list_for_each_entry(chip, &card_list, list) {
2829                 if (!chip->bus || chip->disabled)
2830                         continue;
2831                 list_for_each_entry(c, &chip->bus->codec_list, list)
2832                         snd_hda_power_sync(c);
2833         }
2834         mutex_unlock(&card_list_lock);
2835         return 0;
2836 }
2837 #else
2838 #define azx_add_card_list(chip) /* NOP */
2839 #define azx_del_card_list(chip) /* NOP */
2840 #endif /* CONFIG_PM */
2841
2842 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2843 /*
2844  * power management
2845  */
2846 static int azx_suspend(struct device *dev)
2847 {
2848         struct pci_dev *pci = to_pci_dev(dev);
2849         struct snd_card *card = dev_get_drvdata(dev);
2850         struct azx *chip = card->private_data;
2851         struct azx_pcm *p;
2852
2853         if (chip->disabled)
2854                 return 0;
2855
2856         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2857         azx_clear_irq_pending(chip);
2858         list_for_each_entry(p, &chip->pcm_list, list)
2859                 snd_pcm_suspend_all(p->pcm);
2860         if (chip->initialized)
2861                 snd_hda_suspend(chip->bus);
2862         azx_stop_chip(chip);
2863         if (chip->irq >= 0) {
2864                 free_irq(chip->irq, chip);
2865                 chip->irq = -1;
2866         }
2867         if (chip->msi)
2868                 pci_disable_msi(chip->pci);
2869         pci_disable_device(pci);
2870         pci_save_state(pci);
2871         pci_set_power_state(pci, PCI_D3hot);
2872         return 0;
2873 }
2874
2875 static int azx_resume(struct device *dev)
2876 {
2877         struct pci_dev *pci = to_pci_dev(dev);
2878         struct snd_card *card = dev_get_drvdata(dev);
2879         struct azx *chip = card->private_data;
2880
2881         if (chip->disabled)
2882                 return 0;
2883
2884         pci_set_power_state(pci, PCI_D0);
2885         pci_restore_state(pci);
2886         if (pci_enable_device(pci) < 0) {
2887                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2888                        "disabling device\n");
2889                 snd_card_disconnect(card);
2890                 return -EIO;
2891         }
2892         pci_set_master(pci);
2893         if (chip->msi)
2894                 if (pci_enable_msi(pci) < 0)
2895                         chip->msi = 0;
2896         if (azx_acquire_irq(chip, 1) < 0)
2897                 return -EIO;
2898         azx_init_pci(chip);
2899
2900         azx_init_chip(chip, 1);
2901
2902         snd_hda_resume(chip->bus);
2903         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2904         return 0;
2905 }
2906 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2907
2908 #ifdef CONFIG_PM_RUNTIME
2909 static int azx_runtime_suspend(struct device *dev)
2910 {
2911         struct snd_card *card = dev_get_drvdata(dev);
2912         struct azx *chip = card->private_data;
2913
2914         azx_stop_chip(chip);
2915         azx_clear_irq_pending(chip);
2916         return 0;
2917 }
2918
2919 static int azx_runtime_resume(struct device *dev)
2920 {
2921         struct snd_card *card = dev_get_drvdata(dev);
2922         struct azx *chip = card->private_data;
2923
2924         azx_init_pci(chip);
2925         azx_init_chip(chip, 1);
2926         return 0;
2927 }
2928
2929 static int azx_runtime_idle(struct device *dev)
2930 {
2931         struct snd_card *card = dev_get_drvdata(dev);
2932         struct azx *chip = card->private_data;
2933
2934         if (power_save_controller > 0)
2935                 return 0;
2936         if (!power_save_controller ||
2937             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2938                 return -EBUSY;
2939
2940         return 0;
2941 }
2942
2943 #endif /* CONFIG_PM_RUNTIME */
2944
2945 #ifdef CONFIG_PM
2946 static const struct dev_pm_ops azx_pm = {
2947         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2948         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
2949 };
2950
2951 #define AZX_PM_OPS      &azx_pm
2952 #else
2953 #define AZX_PM_OPS      NULL
2954 #endif /* CONFIG_PM */
2955
2956
2957 /*
2958  * reboot notifier for hang-up problem at power-down
2959  */
2960 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2961 {
2962         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2963         snd_hda_bus_reboot_notify(chip->bus);
2964         azx_stop_chip(chip);
2965         return NOTIFY_OK;
2966 }
2967
2968 static void azx_notifier_register(struct azx *chip)
2969 {
2970         chip->reboot_notifier.notifier_call = azx_halt;
2971         register_reboot_notifier(&chip->reboot_notifier);
2972 }
2973
2974 static void azx_notifier_unregister(struct azx *chip)
2975 {
2976         if (chip->reboot_notifier.notifier_call)
2977                 unregister_reboot_notifier(&chip->reboot_notifier);
2978 }
2979
2980 static int azx_first_init(struct azx *chip);
2981 static int azx_probe_continue(struct azx *chip);
2982
2983 #ifdef SUPPORT_VGA_SWITCHEROO
2984 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
2985
2986 static void azx_vs_set_state(struct pci_dev *pci,
2987                              enum vga_switcheroo_state state)
2988 {
2989         struct snd_card *card = pci_get_drvdata(pci);
2990         struct azx *chip = card->private_data;
2991         bool disabled;
2992
2993         wait_for_completion(&chip->probe_wait);
2994         if (chip->init_failed)
2995                 return;
2996
2997         disabled = (state == VGA_SWITCHEROO_OFF);
2998         if (chip->disabled == disabled)
2999                 return;
3000
3001         if (!chip->bus) {
3002                 chip->disabled = disabled;
3003                 if (!disabled) {
3004                         snd_printk(KERN_INFO SFX
3005                                    "%s: Start delayed initialization\n",
3006                                    pci_name(chip->pci));
3007                         if (azx_first_init(chip) < 0 ||
3008                             azx_probe_continue(chip) < 0) {
3009                                 snd_printk(KERN_ERR SFX
3010                                            "%s: initialization error\n",
3011                                            pci_name(chip->pci));
3012                                 chip->init_failed = true;
3013                         }
3014                 }
3015         } else {
3016                 snd_printk(KERN_INFO SFX
3017                            "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3018                            disabled ? "Disabling" : "Enabling");
3019                 if (disabled) {
3020                         azx_suspend(&pci->dev);
3021                         chip->disabled = true;
3022                         if (snd_hda_lock_devices(chip->bus))
3023                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3024                                            pci_name(chip->pci));
3025                 } else {
3026                         snd_hda_unlock_devices(chip->bus);
3027                         chip->disabled = false;
3028                         azx_resume(&pci->dev);
3029                 }
3030         }
3031 }
3032
3033 static bool azx_vs_can_switch(struct pci_dev *pci)
3034 {
3035         struct snd_card *card = pci_get_drvdata(pci);
3036         struct azx *chip = card->private_data;
3037
3038         wait_for_completion(&chip->probe_wait);
3039         if (chip->init_failed)
3040                 return false;
3041         if (chip->disabled || !chip->bus)
3042                 return true;
3043         if (snd_hda_lock_devices(chip->bus))
3044                 return false;
3045         snd_hda_unlock_devices(chip->bus);
3046         return true;
3047 }
3048
3049 static void init_vga_switcheroo(struct azx *chip)
3050 {
3051         struct pci_dev *p = get_bound_vga(chip->pci);
3052         if (p) {
3053                 snd_printk(KERN_INFO SFX
3054                            "%s: Handle VGA-switcheroo audio client\n",
3055                            pci_name(chip->pci));
3056                 chip->use_vga_switcheroo = 1;
3057                 pci_dev_put(p);
3058         }
3059 }
3060
3061 static const struct vga_switcheroo_client_ops azx_vs_ops = {
3062         .set_gpu_state = azx_vs_set_state,
3063         .can_switch = azx_vs_can_switch,
3064 };
3065
3066 static int register_vga_switcheroo(struct azx *chip)
3067 {
3068         int err;
3069
3070         if (!chip->use_vga_switcheroo)
3071                 return 0;
3072         /* FIXME: currently only handling DIS controller
3073          * is there any machine with two switchable HDMI audio controllers?
3074          */
3075         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3076                                                     VGA_SWITCHEROO_DIS,
3077                                                     chip->bus != NULL);
3078         if (err < 0)
3079                 return err;
3080         chip->vga_switcheroo_registered = 1;
3081         return 0;
3082 }
3083 #else
3084 #define init_vga_switcheroo(chip)               /* NOP */
3085 #define register_vga_switcheroo(chip)           0
3086 #define check_hdmi_disabled(pci)        false
3087 #endif /* SUPPORT_VGA_SWITCHER */
3088
3089 /*
3090  * destructor
3091  */
3092 static int azx_free(struct azx *chip)
3093 {
3094         int i;
3095
3096         azx_del_card_list(chip);
3097
3098         azx_notifier_unregister(chip);
3099
3100         chip->init_failed = 1; /* to be sure */
3101         complete_all(&chip->probe_wait);
3102
3103         if (use_vga_switcheroo(chip)) {
3104                 if (chip->disabled && chip->bus)
3105                         snd_hda_unlock_devices(chip->bus);
3106                 if (chip->vga_switcheroo_registered)
3107                         vga_switcheroo_unregister_client(chip->pci);
3108         }
3109
3110         if (chip->initialized) {
3111                 azx_clear_irq_pending(chip);
3112                 for (i = 0; i < chip->num_streams; i++)
3113                         azx_stream_stop(chip, &chip->azx_dev[i]);
3114                 azx_stop_chip(chip);
3115         }
3116
3117         if (chip->irq >= 0)
3118                 free_irq(chip->irq, (void*)chip);
3119         if (chip->msi)
3120                 pci_disable_msi(chip->pci);
3121         if (chip->remap_addr)
3122                 iounmap(chip->remap_addr);
3123
3124         if (chip->azx_dev) {
3125                 for (i = 0; i < chip->num_streams; i++)
3126                         if (chip->azx_dev[i].bdl.area) {
3127                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
3128                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
3129                         }
3130         }
3131         if (chip->rb.area) {
3132                 mark_pages_wc(chip, &chip->rb, false);
3133                 snd_dma_free_pages(&chip->rb);
3134         }
3135         if (chip->posbuf.area) {
3136                 mark_pages_wc(chip, &chip->posbuf, false);
3137                 snd_dma_free_pages(&chip->posbuf);
3138         }
3139         if (chip->region_requested)
3140                 pci_release_regions(chip->pci);
3141         pci_disable_device(chip->pci);
3142         kfree(chip->azx_dev);
3143 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3144         if (chip->fw)
3145                 release_firmware(chip->fw);
3146 #endif
3147         kfree(chip);
3148
3149         return 0;
3150 }
3151
3152 static int azx_dev_free(struct snd_device *device)
3153 {
3154         return azx_free(device->device_data);
3155 }
3156
3157 #ifdef SUPPORT_VGA_SWITCHEROO
3158 /*
3159  * Check of disabled HDMI controller by vga-switcheroo
3160  */
3161 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3162 {
3163         struct pci_dev *p;
3164
3165         /* check only discrete GPU */
3166         switch (pci->vendor) {
3167         case PCI_VENDOR_ID_ATI:
3168         case PCI_VENDOR_ID_AMD:
3169         case PCI_VENDOR_ID_NVIDIA:
3170                 if (pci->devfn == 1) {
3171                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3172                                                         pci->bus->number, 0);
3173                         if (p) {
3174                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3175                                         return p;
3176                                 pci_dev_put(p);
3177                         }
3178                 }
3179                 break;
3180         }
3181         return NULL;
3182 }
3183
3184 static bool check_hdmi_disabled(struct pci_dev *pci)
3185 {
3186         bool vga_inactive = false;
3187         struct pci_dev *p = get_bound_vga(pci);
3188
3189         if (p) {
3190                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3191                         vga_inactive = true;
3192                 pci_dev_put(p);
3193         }
3194         return vga_inactive;
3195 }
3196 #endif /* SUPPORT_VGA_SWITCHEROO */
3197
3198 /*
3199  * white/black-listing for position_fix
3200  */
3201 static struct snd_pci_quirk position_fix_list[] = {
3202         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3203         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3204         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3205         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3206         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3207         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3208         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3209         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3210         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3211         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3212         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3213         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3214         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3215         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3216         {}
3217 };
3218
3219 static int check_position_fix(struct azx *chip, int fix)
3220 {
3221         const struct snd_pci_quirk *q;
3222
3223         switch (fix) {
3224         case POS_FIX_AUTO:
3225         case POS_FIX_LPIB:
3226         case POS_FIX_POSBUF:
3227         case POS_FIX_VIACOMBO:
3228         case POS_FIX_COMBO:
3229                 return fix;
3230         }
3231
3232         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3233         if (q) {
3234                 printk(KERN_INFO
3235                        "hda_intel: position_fix set to %d "
3236                        "for device %04x:%04x\n",
3237                        q->value, q->subvendor, q->subdevice);
3238                 return q->value;
3239         }
3240
3241         /* Check VIA/ATI HD Audio Controller exist */
3242         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3243                 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3244                 return POS_FIX_VIACOMBO;
3245         }
3246         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3247                 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3248                 return POS_FIX_LPIB;
3249         }
3250         return POS_FIX_AUTO;
3251 }
3252
3253 /*
3254  * black-lists for probe_mask
3255  */
3256 static struct snd_pci_quirk probe_mask_list[] = {
3257         /* Thinkpad often breaks the controller communication when accessing
3258          * to the non-working (or non-existing) modem codec slot.
3259          */
3260         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3261         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3262         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3263         /* broken BIOS */
3264         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3265         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3266         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3267         /* forced codec slots */
3268         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3269         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3270         /* WinFast VP200 H (Teradici) user reported broken communication */
3271         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3272         {}
3273 };
3274
3275 #define AZX_FORCE_CODEC_MASK    0x100
3276
3277 static void check_probe_mask(struct azx *chip, int dev)
3278 {
3279         const struct snd_pci_quirk *q;
3280
3281         chip->codec_probe_mask = probe_mask[dev];
3282         if (chip->codec_probe_mask == -1) {
3283                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3284                 if (q) {
3285                         printk(KERN_INFO
3286                                "hda_intel: probe_mask set to 0x%x "
3287                                "for device %04x:%04x\n",
3288                                q->value, q->subvendor, q->subdevice);
3289                         chip->codec_probe_mask = q->value;
3290                 }
3291         }
3292
3293         /* check forced option */
3294         if (chip->codec_probe_mask != -1 &&
3295             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3296                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3297                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3298                        chip->codec_mask);
3299         }
3300 }
3301
3302 /*
3303  * white/black-list for enable_msi
3304  */
3305 static struct snd_pci_quirk msi_black_list[] = {
3306         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3307         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3308         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3309         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3310         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3311         {}
3312 };
3313
3314 static void check_msi(struct azx *chip)
3315 {
3316         const struct snd_pci_quirk *q;
3317
3318         if (enable_msi >= 0) {
3319                 chip->msi = !!enable_msi;
3320                 return;
3321         }
3322         chip->msi = 1;  /* enable MSI as default */
3323         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3324         if (q) {
3325                 printk(KERN_INFO
3326                        "hda_intel: msi for device %04x:%04x set to %d\n",
3327                        q->subvendor, q->subdevice, q->value);
3328                 chip->msi = q->value;
3329                 return;
3330         }
3331
3332         /* NVidia chipsets seem to cause troubles with MSI */
3333         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3334                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3335                 chip->msi = 0;
3336         }
3337 }
3338
3339 /* check the snoop mode availability */
3340 static void azx_check_snoop_available(struct azx *chip)
3341 {
3342         bool snoop = chip->snoop;
3343
3344         switch (chip->driver_type) {
3345         case AZX_DRIVER_VIA:
3346                 /* force to non-snoop mode for a new VIA controller
3347                  * when BIOS is set
3348                  */
3349                 if (snoop) {
3350                         u8 val;
3351                         pci_read_config_byte(chip->pci, 0x42, &val);
3352                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3353                                 snoop = false;
3354                 }
3355                 break;
3356         case AZX_DRIVER_ATIHDMI_NS:
3357                 /* new ATI HDMI requires non-snoop */
3358                 snoop = false;
3359                 break;
3360         case AZX_DRIVER_CTHDA:
3361                 snoop = false;
3362                 break;
3363         }
3364
3365         if (snoop != chip->snoop) {
3366                 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3367                            pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3368                 chip->snoop = snoop;
3369         }
3370 }
3371
3372 /*
3373  * constructor
3374  */
3375 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3376                       int dev, unsigned int driver_caps,
3377                       struct azx **rchip)
3378 {
3379         static struct snd_device_ops ops = {
3380                 .dev_free = azx_dev_free,
3381         };
3382         struct azx *chip;
3383         int err;
3384
3385         *rchip = NULL;
3386
3387         err = pci_enable_device(pci);
3388         if (err < 0)
3389                 return err;
3390
3391         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3392         if (!chip) {
3393                 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3394                 pci_disable_device(pci);
3395                 return -ENOMEM;
3396         }
3397
3398         spin_lock_init(&chip->reg_lock);
3399         mutex_init(&chip->open_mutex);
3400         chip->card = card;
3401         chip->pci = pci;
3402         chip->irq = -1;
3403         chip->driver_caps = driver_caps;
3404         chip->driver_type = driver_caps & 0xff;
3405         check_msi(chip);
3406         chip->dev_index = dev;
3407         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3408         INIT_LIST_HEAD(&chip->pcm_list);
3409         INIT_LIST_HEAD(&chip->list);
3410         init_vga_switcheroo(chip);
3411         init_completion(&chip->probe_wait);
3412
3413         chip->position_fix[0] = chip->position_fix[1] =
3414                 check_position_fix(chip, position_fix[dev]);
3415         /* combo mode uses LPIB for playback */
3416         if (chip->position_fix[0] == POS_FIX_COMBO) {
3417                 chip->position_fix[0] = POS_FIX_LPIB;
3418                 chip->position_fix[1] = POS_FIX_AUTO;
3419         }
3420
3421         check_probe_mask(chip, dev);
3422
3423         chip->single_cmd = single_cmd;
3424         chip->snoop = hda_snoop;
3425         azx_check_snoop_available(chip);
3426
3427         if (bdl_pos_adj[dev] < 0) {
3428                 switch (chip->driver_type) {
3429                 case AZX_DRIVER_ICH:
3430                 case AZX_DRIVER_PCH:
3431                         bdl_pos_adj[dev] = 1;
3432                         break;
3433                 default:
3434                         bdl_pos_adj[dev] = 32;
3435                         break;
3436                 }
3437         }
3438
3439         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3440         if (err < 0) {
3441                 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3442                    pci_name(chip->pci));
3443                 azx_free(chip);
3444                 return err;
3445         }
3446
3447         *rchip = chip;
3448         return 0;
3449 }
3450
3451 static int azx_first_init(struct azx *chip)
3452 {
3453         int dev = chip->dev_index;
3454         struct pci_dev *pci = chip->pci;
3455         struct snd_card *card = chip->card;
3456         int i, err;
3457         unsigned short gcap;
3458
3459 #if BITS_PER_LONG != 64
3460         /* Fix up base address on ULI M5461 */
3461         if (chip->driver_type == AZX_DRIVER_ULI) {
3462                 u16 tmp3;
3463                 pci_read_config_word(pci, 0x40, &tmp3);
3464                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3465                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3466         }
3467 #endif
3468
3469         err = pci_request_regions(pci, "ICH HD audio");
3470         if (err < 0)
3471                 return err;
3472         chip->region_requested = 1;
3473
3474         chip->addr = pci_resource_start(pci, 0);
3475         chip->remap_addr = pci_ioremap_bar(pci, 0);
3476         if (chip->remap_addr == NULL) {
3477                 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3478                 return -ENXIO;
3479         }
3480
3481         if (chip->msi)
3482                 if (pci_enable_msi(pci) < 0)
3483                         chip->msi = 0;
3484
3485         if (azx_acquire_irq(chip, 0) < 0)
3486                 return -EBUSY;
3487
3488         pci_set_master(pci);
3489         synchronize_irq(chip->irq);
3490
3491         gcap = azx_readw(chip, GCAP);
3492         snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3493
3494         /* disable SB600 64bit support for safety */
3495         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3496                 struct pci_dev *p_smbus;
3497                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3498                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3499                                          NULL);
3500                 if (p_smbus) {
3501                         if (p_smbus->revision < 0x30)
3502                                 gcap &= ~ICH6_GCAP_64OK;
3503                         pci_dev_put(p_smbus);
3504                 }
3505         }
3506
3507         /* disable 64bit DMA address on some devices */
3508         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3509                 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3510                 gcap &= ~ICH6_GCAP_64OK;
3511         }
3512
3513         /* disable buffer size rounding to 128-byte multiples if supported */
3514         if (align_buffer_size >= 0)
3515                 chip->align_buffer_size = !!align_buffer_size;
3516         else {
3517                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3518                         chip->align_buffer_size = 0;
3519                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3520                         chip->align_buffer_size = 1;
3521                 else
3522                         chip->align_buffer_size = 1;
3523         }
3524
3525         /* allow 64bit DMA address if supported by H/W */
3526         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3527                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3528         else {
3529                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3530                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3531         }
3532
3533         /* read number of streams from GCAP register instead of using
3534          * hardcoded value
3535          */
3536         chip->capture_streams = (gcap >> 8) & 0x0f;
3537         chip->playback_streams = (gcap >> 12) & 0x0f;
3538         if (!chip->playback_streams && !chip->capture_streams) {
3539                 /* gcap didn't give any info, switching to old method */
3540
3541                 switch (chip->driver_type) {
3542                 case AZX_DRIVER_ULI:
3543                         chip->playback_streams = ULI_NUM_PLAYBACK;
3544                         chip->capture_streams = ULI_NUM_CAPTURE;
3545                         break;
3546                 case AZX_DRIVER_ATIHDMI:
3547                 case AZX_DRIVER_ATIHDMI_NS:
3548                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3549                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3550                         break;
3551                 case AZX_DRIVER_GENERIC:
3552                 default:
3553                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3554                         chip->capture_streams = ICH6_NUM_CAPTURE;
3555                         break;
3556                 }
3557         }
3558         chip->capture_index_offset = 0;
3559         chip->playback_index_offset = chip->capture_streams;
3560         chip->num_streams = chip->playback_streams + chip->capture_streams;
3561         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3562                                 GFP_KERNEL);
3563         if (!chip->azx_dev) {
3564                 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3565                 return -ENOMEM;
3566         }
3567
3568         for (i = 0; i < chip->num_streams; i++) {
3569                 dsp_lock_init(&chip->azx_dev[i]);
3570                 /* allocate memory for the BDL for each stream */
3571                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3572                                           snd_dma_pci_data(chip->pci),
3573                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3574                 if (err < 0) {
3575                         snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3576                         return -ENOMEM;
3577                 }
3578                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3579         }
3580         /* allocate memory for the position buffer */
3581         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3582                                   snd_dma_pci_data(chip->pci),
3583                                   chip->num_streams * 8, &chip->posbuf);
3584         if (err < 0) {
3585                 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3586                 return -ENOMEM;
3587         }
3588         mark_pages_wc(chip, &chip->posbuf, true);
3589         /* allocate CORB/RIRB */
3590         err = azx_alloc_cmd_io(chip);
3591         if (err < 0)
3592                 return err;
3593
3594         /* initialize streams */
3595         azx_init_stream(chip);
3596
3597         /* initialize chip */
3598         azx_init_pci(chip);
3599         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3600
3601         /* codec detection */
3602         if (!chip->codec_mask) {
3603                 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3604                 return -ENODEV;
3605         }
3606
3607         strcpy(card->driver, "HDA-Intel");
3608         strlcpy(card->shortname, driver_short_names[chip->driver_type],
3609                 sizeof(card->shortname));
3610         snprintf(card->longname, sizeof(card->longname),
3611                  "%s at 0x%lx irq %i",
3612                  card->shortname, chip->addr, chip->irq);
3613
3614         return 0;
3615 }
3616
3617 static void power_down_all_codecs(struct azx *chip)
3618 {
3619 #ifdef CONFIG_PM
3620         /* The codecs were powered up in snd_hda_codec_new().
3621          * Now all initialization done, so turn them down if possible
3622          */
3623         struct hda_codec *codec;
3624         list_for_each_entry(codec, &chip->bus->codec_list, list) {
3625                 snd_hda_power_down(codec);
3626         }
3627 #endif
3628 }
3629
3630 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3631 /* callback from request_firmware_nowait() */
3632 static void azx_firmware_cb(const struct firmware *fw, void *context)
3633 {
3634         struct snd_card *card = context;
3635         struct azx *chip = card->private_data;
3636         struct pci_dev *pci = chip->pci;
3637
3638         if (!fw) {
3639                 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3640                            pci_name(chip->pci));
3641                 goto error;
3642         }
3643
3644         chip->fw = fw;
3645         if (!chip->disabled) {
3646                 /* continue probing */
3647                 if (azx_probe_continue(chip))
3648                         goto error;
3649         }
3650         return; /* OK */
3651
3652  error:
3653         snd_card_free(card);
3654         pci_set_drvdata(pci, NULL);
3655 }
3656 #endif
3657
3658 static int azx_probe(struct pci_dev *pci,
3659                      const struct pci_device_id *pci_id)
3660 {
3661         static int dev;
3662         struct snd_card *card;
3663         struct azx *chip;
3664         bool probe_now;
3665         int err;
3666
3667         if (dev >= SNDRV_CARDS)
3668                 return -ENODEV;
3669         if (!enable[dev]) {
3670                 dev++;
3671                 return -ENOENT;
3672         }
3673
3674         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3675         if (err < 0) {
3676                 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
3677                 return err;
3678         }
3679
3680         snd_card_set_dev(card, &pci->dev);
3681
3682         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3683         if (err < 0)
3684                 goto out_free;
3685         card->private_data = chip;
3686
3687         pci_set_drvdata(pci, card);
3688
3689         err = register_vga_switcheroo(chip);
3690         if (err < 0) {
3691                 snd_printk(KERN_ERR SFX
3692                            "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
3693                 goto out_free;
3694         }
3695
3696         if (check_hdmi_disabled(pci)) {
3697                 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
3698                            pci_name(pci));
3699                 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
3700                 chip->disabled = true;
3701         }
3702
3703         probe_now = !chip->disabled;
3704         if (probe_now) {
3705                 err = azx_first_init(chip);
3706                 if (err < 0)
3707                         goto out_free;
3708         }
3709
3710 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3711         if (patch[dev] && *patch[dev]) {
3712                 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3713                            pci_name(pci), patch[dev]);
3714                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3715                                               &pci->dev, GFP_KERNEL, card,
3716                                               azx_firmware_cb);
3717                 if (err < 0)
3718                         goto out_free;
3719                 probe_now = false; /* continued in azx_firmware_cb() */
3720         }
3721 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3722
3723         if (probe_now) {
3724                 err = azx_probe_continue(chip);
3725                 if (err < 0)
3726                         goto out_free;
3727         }
3728
3729         if (pci_dev_run_wake(pci))
3730                 pm_runtime_put_noidle(&pci->dev);
3731
3732         dev++;
3733         complete_all(&chip->probe_wait);
3734         return 0;
3735
3736 out_free:
3737         snd_card_free(card);
3738         pci_set_drvdata(pci, NULL);
3739         return err;
3740 }
3741
3742 static int azx_probe_continue(struct azx *chip)
3743 {
3744         int dev = chip->dev_index;
3745         int err;
3746
3747 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3748         chip->beep_mode = beep_mode[dev];
3749 #endif
3750
3751         /* create codec instances */
3752         err = azx_codec_create(chip, model[dev]);
3753         if (err < 0)
3754                 goto out_free;
3755 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3756         if (chip->fw) {
3757                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3758                                          chip->fw->data);
3759                 if (err < 0)
3760                         goto out_free;
3761 #ifndef CONFIG_PM
3762                 release_firmware(chip->fw); /* no longer needed */
3763                 chip->fw = NULL;
3764 #endif
3765         }
3766 #endif
3767         if ((probe_only[dev] & 1) == 0) {
3768                 err = azx_codec_configure(chip);
3769                 if (err < 0)
3770                         goto out_free;
3771         }
3772
3773         /* create PCM streams */
3774         err = snd_hda_build_pcms(chip->bus);
3775         if (err < 0)
3776                 goto out_free;
3777
3778         /* create mixer controls */
3779         err = azx_mixer_create(chip);
3780         if (err < 0)
3781                 goto out_free;
3782
3783         err = snd_card_register(chip->card);
3784         if (err < 0)
3785                 goto out_free;
3786
3787         chip->running = 1;
3788         power_down_all_codecs(chip);
3789         azx_notifier_register(chip);
3790         azx_add_card_list(chip);
3791
3792         return 0;
3793
3794 out_free:
3795         chip->init_failed = 1;
3796         return err;
3797 }
3798
3799 static void azx_remove(struct pci_dev *pci)
3800 {
3801         struct snd_card *card = pci_get_drvdata(pci);
3802
3803         if (pci_dev_run_wake(pci))
3804                 pm_runtime_get_noresume(&pci->dev);
3805
3806         if (card)
3807                 snd_card_free(card);
3808         pci_set_drvdata(pci, NULL);
3809 }
3810
3811 /* PCI IDs */
3812 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3813         /* CPT */
3814         { PCI_DEVICE(0x8086, 0x1c20),
3815           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3816         /* PBG */
3817         { PCI_DEVICE(0x8086, 0x1d20),
3818           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3819         /* Panther Point */
3820         { PCI_DEVICE(0x8086, 0x1e20),
3821           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3822         /* Lynx Point */
3823         { PCI_DEVICE(0x8086, 0x8c20),
3824           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3825         /* Wellsburg */
3826         { PCI_DEVICE(0x8086, 0x8d20),
3827           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3828         { PCI_DEVICE(0x8086, 0x8d21),
3829           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3830         /* Lynx Point-LP */
3831         { PCI_DEVICE(0x8086, 0x9c20),
3832           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3833         /* Lynx Point-LP */
3834         { PCI_DEVICE(0x8086, 0x9c21),
3835           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3836         /* Haswell */
3837         { PCI_DEVICE(0x8086, 0x0a0c),
3838           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3839         { PCI_DEVICE(0x8086, 0x0c0c),
3840           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3841         { PCI_DEVICE(0x8086, 0x0d0c),
3842           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3843         /* 5 Series/3400 */
3844         { PCI_DEVICE(0x8086, 0x3b56),
3845           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3846         /* Poulsbo */
3847         { PCI_DEVICE(0x8086, 0x811b),
3848           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3849         /* Oaktrail */
3850         { PCI_DEVICE(0x8086, 0x080a),
3851           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3852         /* ICH */
3853         { PCI_DEVICE(0x8086, 0x2668),
3854           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3855           AZX_DCAPS_BUFSIZE },  /* ICH6 */
3856         { PCI_DEVICE(0x8086, 0x27d8),
3857           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3858           AZX_DCAPS_BUFSIZE },  /* ICH7 */
3859         { PCI_DEVICE(0x8086, 0x269a),
3860           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3861           AZX_DCAPS_BUFSIZE },  /* ESB2 */
3862         { PCI_DEVICE(0x8086, 0x284b),
3863           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3864           AZX_DCAPS_BUFSIZE },  /* ICH8 */
3865         { PCI_DEVICE(0x8086, 0x293e),
3866           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3867           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3868         { PCI_DEVICE(0x8086, 0x293f),
3869           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3870           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3871         { PCI_DEVICE(0x8086, 0x3a3e),
3872           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3873           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3874         { PCI_DEVICE(0x8086, 0x3a6e),
3875           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3876           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3877         /* Generic Intel */
3878         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3879           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3880           .class_mask = 0xffffff,
3881           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3882         /* ATI SB 450/600/700/800/900 */
3883         { PCI_DEVICE(0x1002, 0x437b),
3884           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3885         { PCI_DEVICE(0x1002, 0x4383),
3886           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3887         /* AMD Hudson */
3888         { PCI_DEVICE(0x1022, 0x780d),
3889           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3890         /* ATI HDMI */
3891         { PCI_DEVICE(0x1002, 0x793b),
3892           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3893         { PCI_DEVICE(0x1002, 0x7919),
3894           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3895         { PCI_DEVICE(0x1002, 0x960f),
3896           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3897         { PCI_DEVICE(0x1002, 0x970f),
3898           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3899         { PCI_DEVICE(0x1002, 0xaa00),
3900           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3901         { PCI_DEVICE(0x1002, 0xaa08),
3902           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3903         { PCI_DEVICE(0x1002, 0xaa10),
3904           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3905         { PCI_DEVICE(0x1002, 0xaa18),
3906           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3907         { PCI_DEVICE(0x1002, 0xaa20),
3908           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3909         { PCI_DEVICE(0x1002, 0xaa28),
3910           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3911         { PCI_DEVICE(0x1002, 0xaa30),
3912           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3913         { PCI_DEVICE(0x1002, 0xaa38),
3914           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3915         { PCI_DEVICE(0x1002, 0xaa40),
3916           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3917         { PCI_DEVICE(0x1002, 0xaa48),
3918           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3919         { PCI_DEVICE(0x1002, 0x9902),
3920           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3921         { PCI_DEVICE(0x1002, 0xaaa0),
3922           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3923         { PCI_DEVICE(0x1002, 0xaaa8),
3924           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3925         { PCI_DEVICE(0x1002, 0xaab0),
3926           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3927         /* VIA VT8251/VT8237A */
3928         { PCI_DEVICE(0x1106, 0x3288),
3929           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3930         /* VIA GFX VT7122/VX900 */
3931         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3932         /* VIA GFX VT6122/VX11 */
3933         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3934         /* SIS966 */
3935         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3936         /* ULI M5461 */
3937         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3938         /* NVIDIA MCP */
3939         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3940           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3941           .class_mask = 0xffffff,
3942           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3943         /* Teradici */
3944         { PCI_DEVICE(0x6549, 0x1200),
3945           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3946         { PCI_DEVICE(0x6549, 0x2200),
3947           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3948         /* Creative X-Fi (CA0110-IBG) */
3949         /* CTHDA chips */
3950         { PCI_DEVICE(0x1102, 0x0010),
3951           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3952         { PCI_DEVICE(0x1102, 0x0012),
3953           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
3954 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3955         /* the following entry conflicts with snd-ctxfi driver,
3956          * as ctxfi driver mutates from HD-audio to native mode with
3957          * a special command sequence.
3958          */
3959         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3960           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3961           .class_mask = 0xffffff,
3962           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3963           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3964 #else
3965         /* this entry seems still valid -- i.e. without emu20kx chip */
3966         { PCI_DEVICE(0x1102, 0x0009),
3967           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3968           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3969 #endif
3970         /* Vortex86MX */
3971         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3972         /* VMware HDAudio */
3973         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3974         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3975         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3976           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3977           .class_mask = 0xffffff,
3978           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3979         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3980           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3981           .class_mask = 0xffffff,
3982           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3983         { 0, }
3984 };
3985 MODULE_DEVICE_TABLE(pci, azx_ids);
3986
3987 /* pci_driver definition */
3988 static struct pci_driver azx_driver = {
3989         .name = KBUILD_MODNAME,
3990         .id_table = azx_ids,
3991         .probe = azx_probe,
3992         .remove = azx_remove,
3993         .driver = {
3994                 .pm = AZX_PM_OPS,
3995         },
3996 };
3997
3998 module_pci_driver(azx_driver);