sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/io.h>
  48 #include <linux/pm_runtime.h>
  49 #include <linux/clocksource.h>
  50 #include <linux/time.h>
  51 #include <linux/completion.h>
  52
  53 #ifdef CONFIG_X86
  54 /* for snoop control */
  55 #include <asm/pgtable.h>
  56 #include <asm/cacheflush.h>
  57 #include <asm/cpufeature.h>
  58 #endif
  59 #include <sound/core.h>
  60 #include <sound/initval.h>
  61 #include <sound/hdaudio.h>
  62 #include <sound/hda_i915.h>
  63 #include <linux/vgaarb.h>
  64 #include <linux/vga_switcheroo.h>
  65 #include <linux/firmware.h>
  66 #include "hda_codec.h"
  67 #include "hda_controller.h"
  68 #include "hda_intel.h"
  69
  70 #define CREATE_TRACE_POINTS
  71 #include "hda_intel_trace.h"
  72
  73 /* position fix mode */
  74 enum {
  75         POS_FIX_AUTO,
  76         POS_FIX_LPIB,
  77         POS_FIX_POSBUF,
  78         POS_FIX_VIACOMBO,
  79         POS_FIX_COMBO,
  80         POS_FIX_SKL,
  81 };
  82
  83 /* Defines for ATI HD Audio support in SB450 south bridge */
  84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
  85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
  86
  87 /* Defines for Nvidia HDA support */
  88 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
  89 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
  90 #define NVIDIA_HDA_ISTRM_COH          0x4d
  91 #define NVIDIA_HDA_OSTRM_COH          0x4c
  92 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
  93
  94 /* Defines for Intel SCH HDA snoop control */
  95 #define INTEL_HDA_CGCTL  0x48
  96 #define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
  97 #define INTEL_SCH_HDA_DEVC      0x78
  98 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
  99
 100 /* Define IN stream 0 FIFO size offset in VIA controller */
 101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 102 /* Define VIA HD Audio Device ID*/
 103 #define VIA_HDAC_DEVICE_ID              0x3288
 104
 105 /* max number of SDs */
 106 /* ICH, ATI and VIA have 4 playback and 4 capture */
 107 #define ICH6_NUM_CAPTURE        4
 108 #define ICH6_NUM_PLAYBACK       4
 109
 110 /* ULI has 6 playback and 5 capture */
 111 #define ULI_NUM_CAPTURE         5
 112 #define ULI_NUM_PLAYBACK        6
 113
 114 /* ATI HDMI may have up to 8 playbacks and 0 capture */
 115 #define ATIHDMI_NUM_CAPTURE     0
 116 #define ATIHDMI_NUM_PLAYBACK    8
 117
 118 /* TERA has 4 playback and 3 capture */
 119 #define TERA_NUM_CAPTURE        3
 120 #define TERA_NUM_PLAYBACK       4
 121
 122
 123 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
 124 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
 125 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
 126 static char *model[SNDRV_CARDS];
 127 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 128 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 129 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
 130 static int probe_only[SNDRV_CARDS];
 131 static int jackpoll_ms[SNDRV_CARDS];
 132 static int single_cmd = -1;
 133 static int enable_msi = -1;
 134 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 135 static char *patch[SNDRV_CARDS];
 136 #endif
 137 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 138 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
 139                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
 140 #endif
 141
 142 module_param_array(index, int, NULL, 0444);
 143 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
 144 module_param_array(id, charp, NULL, 0444);
 145 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
 146 module_param_array(enable, bool, NULL, 0444);
 147 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
 148 module_param_array(model, charp, NULL, 0444);
 149 MODULE_PARM_DESC(model, "Use the given board model.");
 150 module_param_array(position_fix, int, NULL, 0444);
 151 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
 152                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
 153 module_param_array(bdl_pos_adj, int, NULL, 0644);
 154 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
 155 module_param_array(probe_mask, int, NULL, 0444);
 156 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
 157 module_param_array(probe_only, int, NULL, 0444);
 158 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
 159 module_param_array(jackpoll_ms, int, NULL, 0444);
 160 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
 161 module_param(single_cmd, bint, 0444);
 162 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
 163                  "(for debugging only).");
 164 module_param(enable_msi, bint, 0444);
 165 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
 166 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 167 module_param_array(patch, charp, NULL, 0444);
 168 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 169 #endif
 170 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 171 module_param_array(beep_mode, bool, NULL, 0444);
 172 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 173                             "(0=off, 1=on) (default=1).");
 174 #endif
 175
 176 #ifdef CONFIG_PM
 177 static int param_set_xint(const char *val, const struct kernel_param *kp);
 178 static const struct kernel_param_ops param_ops_xint = {
 179         .set = param_set_xint,
 180         .get = param_get_int,
 181 };
 182 #define param_check_xint param_check_int
 183
 184 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 185 module_param(power_save, xint, 0644);
 186 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 187                  "(in second, 0 = disable).");
 188
 189 /* reset the HD-audio controller in power save mode.
 190  * this may give more power-saving, but will take longer time to
 191  * wake up.
 192  */
 193 static bool power_save_controller = 1;
 194 module_param(power_save_controller, bool, 0644);
 195 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 196 #else
 197 #define power_save      0
 198 #endif /* CONFIG_PM */
 199
 200 static int align_buffer_size = -1;
 201 module_param(align_buffer_size, bint, 0644);
 202 MODULE_PARM_DESC(align_buffer_size,
 203                 "Force buffer and period sizes to be multiple of 128 bytes.");
 204
 205 #ifdef CONFIG_X86
 206 static int hda_snoop = -1;
 207 module_param_named(snoop, hda_snoop, bint, 0444);
 208 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 209 #else
 210 #define hda_snoop               true
 211 #endif
 212
 213
 214 MODULE_LICENSE("GPL");
 215 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 216                          "{Intel, ICH6M},"
 217                          "{Intel, ICH7},"
 218                          "{Intel, ESB2},"
 219                          "{Intel, ICH8},"
 220                          "{Intel, ICH9},"
 221                          "{Intel, ICH10},"
 222                          "{Intel, PCH},"
 223                          "{Intel, CPT},"
 224                          "{Intel, PPT},"
 225                          "{Intel, LPT},"
 226                          "{Intel, LPT_LP},"
 227                          "{Intel, WPT_LP},"
 228                          "{Intel, SPT},"
 229                          "{Intel, SPT_LP},"
 230                          "{Intel, HPT},"
 231                          "{Intel, PBG},"
 232                          "{Intel, SCH},"
 233                          "{ATI, SB450},"
 234                          "{ATI, SB600},"
 235                          "{ATI, RS600},"
 236                          "{ATI, RS690},"
 237                          "{ATI, RS780},"
 238                          "{ATI, R600},"
 239                          "{ATI, RV630},"
 240                          "{ATI, RV610},"
 241                          "{ATI, RV670},"
 242                          "{ATI, RV635},"
 243                          "{ATI, RV620},"
 244                          "{ATI, RV770},"
 245                          "{VIA, VT8251},"
 246                          "{VIA, VT8237A},"
 247                          "{SiS, SIS966},"
 248                          "{ULI, M5461}}");
 249 MODULE_DESCRIPTION("Intel HDA driver");
 250
 251 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
 252 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
 253 #define SUPPORT_VGA_SWITCHEROO
 254 #endif
 255 #endif
 256
 257
 258 /*
 259  */
 260
 261 /* driver types */
 262 enum {
 263         AZX_DRIVER_ICH,
 264         AZX_DRIVER_PCH,
 265         AZX_DRIVER_SCH,
 266         AZX_DRIVER_HDMI,
 267         AZX_DRIVER_ATI,
 268         AZX_DRIVER_ATIHDMI,
 269         AZX_DRIVER_ATIHDMI_NS,
 270         AZX_DRIVER_VIA,
 271         AZX_DRIVER_SIS,
 272         AZX_DRIVER_ULI,
 273         AZX_DRIVER_NVIDIA,
 274         AZX_DRIVER_TERA,
 275         AZX_DRIVER_CTX,
 276         AZX_DRIVER_CTHDA,
 277         AZX_DRIVER_CMEDIA,
 278         AZX_DRIVER_GENERIC,
 279         AZX_NUM_DRIVERS, /* keep this as last entry */
 280 };
 281
 282 #define azx_get_snoop_type(chip) \
 283         (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
 284 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
 285
 286 /* quirks for old Intel chipsets */
 287 #define AZX_DCAPS_INTEL_ICH \
 288         (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
 289
 290 /* quirks for Intel PCH */
 291 #define AZX_DCAPS_INTEL_PCH_BASE \
 292         (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
 293          AZX_DCAPS_SNOOP_TYPE(SCH))
 294
 295 /* PCH up to IVB; no runtime PM */
 296 #define AZX_DCAPS_INTEL_PCH_NOPM \
 297         (AZX_DCAPS_INTEL_PCH_BASE)
 298
 299 /* PCH for HSW/BDW; with runtime PM */
 300 #define AZX_DCAPS_INTEL_PCH \
 301         (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
 302
 303 /* HSW HDMI */
 304 #define AZX_DCAPS_INTEL_HASWELL \
 305         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
 306          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 307          AZX_DCAPS_SNOOP_TYPE(SCH))
 308
 309 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
 310 #define AZX_DCAPS_INTEL_BROADWELL \
 311         (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
 312          AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
 313          AZX_DCAPS_SNOOP_TYPE(SCH))
 314
 315 #define AZX_DCAPS_INTEL_BAYTRAIL \
 316         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
 317
 318 #define AZX_DCAPS_INTEL_BRASWELL \
 319         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
 320
 321 #define AZX_DCAPS_INTEL_SKYLAKE \
 322         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 323          AZX_DCAPS_I915_POWERWELL)
 324
 325 #define AZX_DCAPS_INTEL_BROXTON \
 326         (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
 327          AZX_DCAPS_I915_POWERWELL)
 328
 329 /* quirks for ATI SB / AMD Hudson */
 330 #define AZX_DCAPS_PRESET_ATI_SB \
 331         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
 332          AZX_DCAPS_SNOOP_TYPE(ATI))
 333
 334 /* quirks for ATI/AMD HDMI */
 335 #define AZX_DCAPS_PRESET_ATI_HDMI \
 336         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
 337          AZX_DCAPS_NO_MSI64)
 338
 339 /* quirks for ATI HDMI with snoop off */
 340 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
 341         (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
 342
 343 /* quirks for Nvidia */
 344 #define AZX_DCAPS_PRESET_NVIDIA \
 345         (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
 346          AZX_DCAPS_SNOOP_TYPE(NVIDIA))
 347
 348 #define AZX_DCAPS_PRESET_CTHDA \
 349         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
 350          AZX_DCAPS_NO_64BIT |\
 351          AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
 352
 353 /*
 354  * vga_switcheroo support
 355  */
 356 #ifdef SUPPORT_VGA_SWITCHEROO
 357 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
 358 #else
 359 #define use_vga_switcheroo(chip)        0
 360 #endif
 361
 362 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
 363                                         ((pci)->device == 0x0c0c) || \
 364                                         ((pci)->device == 0x0d0c) || \
 365                                         ((pci)->device == 0x160c))
 366
 367 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
 368 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
 369 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
 370 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
 371 #define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
 372 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
 373 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
 374                         IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci)
 375
 376 static char *driver_short_names[] = {
 377         [AZX_DRIVER_ICH] = "HDA Intel",
 378         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 379         [AZX_DRIVER_SCH] = "HDA Intel MID",
 380         [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
 381         [AZX_DRIVER_ATI] = "HDA ATI SB",
 382         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 383         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
 384         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 385         [AZX_DRIVER_SIS] = "HDA SIS966",
 386         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 387         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 388         [AZX_DRIVER_TERA] = "HDA Teradici",
 389         [AZX_DRIVER_CTX] = "HDA Creative",
 390         [AZX_DRIVER_CTHDA] = "HDA Creative",
 391         [AZX_DRIVER_CMEDIA] = "HDA C-Media",
 392         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 393 };
 394
 395 #ifdef CONFIG_X86
 396 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
 397 {
 398         int pages;
 399
 400         if (azx_snoop(chip))
 401                 return;
 402         if (!dmab || !dmab->area || !dmab->bytes)
 403                 return;
 404
 405 #ifdef CONFIG_SND_DMA_SGBUF
 406         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
 407                 struct snd_sg_buf *sgbuf = dmab->private_data;
 408                 if (chip->driver_type == AZX_DRIVER_CMEDIA)
 409                         return; /* deal with only CORB/RIRB buffers */
 410                 if (on)
 411                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
 412                 else
 413                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
 414                 return;
 415         }
 416 #endif
 417
 418         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
 419         if (on)
 420                 set_memory_wc((unsigned long)dmab->area, pages);
 421         else
 422                 set_memory_wb((unsigned long)dmab->area, pages);
 423 }
 424
 425 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 426                                  bool on)
 427 {
 428         __mark_pages_wc(chip, buf, on);
 429 }
 430 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 431                                    struct snd_pcm_substream *substream, bool on)
 432 {
 433         if (azx_dev->wc_marked != on) {
 434                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
 435                 azx_dev->wc_marked = on;
 436         }
 437 }
 438 #else
 439 /* NOP for other archs */
 440 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 441                                  bool on)
 442 {
 443 }
 444 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 445                                    struct snd_pcm_substream *substream, bool on)
 446 {
 447 }
 448 #endif
 449
 450 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 451
 452 /*
 453  * initialize the PCI registers
 454  */
 455 /* update bits in a PCI register byte */
 456 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 457                             unsigned char mask, unsigned char val)
 458 {
 459         unsigned char data;
 460
 461         pci_read_config_byte(pci, reg, &data);
 462         data &= ~mask;
 463         data |= (val & mask);
 464         pci_write_config_byte(pci, reg, data);
 465 }
 466
 467 static void azx_init_pci(struct azx *chip)
 468 {
 469         int snoop_type = azx_get_snoop_type(chip);
 470
 471         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 472          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 473          * Ensuring these bits are 0 clears playback static on some HD Audio
 474          * codecs.
 475          * The PCI register TCSEL is defined in the Intel manuals.
 476          */
 477         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
 478                 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
 479                 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
 480         }
 481
 482         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
 483          * we need to enable snoop.
 484          */
 485         if (snoop_type == AZX_SNOOP_TYPE_ATI) {
 486                 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
 487                         azx_snoop(chip));
 488                 update_pci_byte(chip->pci,
 489                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
 490                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
 491         }
 492
 493         /* For NVIDIA HDA, enable snoop */
 494         if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
 495                 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
 496                         azx_snoop(chip));
 497                 update_pci_byte(chip->pci,
 498                                 NVIDIA_HDA_TRANSREG_ADDR,
 499                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 500                 update_pci_byte(chip->pci,
 501                                 NVIDIA_HDA_ISTRM_COH,
 502                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 503                 update_pci_byte(chip->pci,
 504                                 NVIDIA_HDA_OSTRM_COH,
 505                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 506         }
 507
 508         /* Enable SCH/PCH snoop if needed */
 509         if (snoop_type == AZX_SNOOP_TYPE_SCH) {
 510                 unsigned short snoop;
 511                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 512                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
 513                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
 514                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
 515                         if (!azx_snoop(chip))
 516                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
 517                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
 518                         pci_read_config_word(chip->pci,
 519                                 INTEL_SCH_HDA_DEVC, &snoop);
 520                 }
 521                 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
 522                         (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
 523                         "Disabled" : "Enabled");
 524         }
 525 }
 526
 527 /*
 528  * In BXT-P A0, HD-Audio DMA requests is later than expected,
 529  * and makes an audio stream sensitive to system latencies when
 530  * 24/32 bits are playing.
 531  * Adjusting threshold of DMA fifo to force the DMA request
 532  * sooner to improve latency tolerance at the expense of power.
 533  */
 534 static void bxt_reduce_dma_latency(struct azx *chip)
 535 {
 536         u32 val;
 537
 538         val = azx_readl(chip, VS_EM4L);
 539         val &= (0x3 << 20);
 540         azx_writel(chip, VS_EM4L, val);
 541 }
 542
 543 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
 544 {
 545         struct hdac_bus *bus = azx_bus(chip);
 546         struct pci_dev *pci = chip->pci;
 547         u32 val;
 548
 549         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 550                 snd_hdac_set_codec_wakeup(bus, true);
 551         if (IS_SKL_PLUS(pci)) {
 552                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 553                 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
 554                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 555         }
 556         azx_init_chip(chip, full_reset);
 557         if (IS_SKL_PLUS(pci)) {
 558                 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
 559                 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
 560                 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
 561         }
 562         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
 563                 snd_hdac_set_codec_wakeup(bus, false);
 564
 565         /* reduce dma latency to avoid noise */
 566         if (IS_BXT(pci))
 567                 bxt_reduce_dma_latency(chip);
 568 }
 569
 570 /* calculate runtime delay from LPIB */
 571 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 572                                    unsigned int pos)
 573 {
 574         struct snd_pcm_substream *substream = azx_dev->core.substream;
 575         int stream = substream->stream;
 576         unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
 577         int delay;
 578
 579         if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 580                 delay = pos - lpib_pos;
 581         else
 582                 delay = lpib_pos - pos;
 583         if (delay < 0) {
 584                 if (delay >= azx_dev->core.delay_negative_threshold)
 585                         delay = 0;
 586                 else
 587                         delay += azx_dev->core.bufsize;
 588         }
 589
 590         if (delay >= azx_dev->core.period_bytes) {
 591                 dev_info(chip->card->dev,
 592                          "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
 593                          delay, azx_dev->core.period_bytes);
 594                 delay = 0;
 595                 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
 596                 chip->get_delay[stream] = NULL;
 597         }
 598
 599         return bytes_to_frames(substream->runtime, delay);
 600 }
 601
 602 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 603
 604 /* called from IRQ */
 605 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
 606 {
 607         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 608         int ok;
 609
 610         ok = azx_position_ok(chip, azx_dev);
 611         if (ok == 1) {
 612                 azx_dev->irq_pending = 0;
 613                 return ok;
 614         } else if (ok == 0) {
 615                 /* bogus IRQ, process it later */
 616                 azx_dev->irq_pending = 1;
 617                 schedule_work(&hda->irq_pending_work);
 618         }
 619         return 0;
 620 }
 621
 622 /* Enable/disable i915 display power for the link */
 623 static int azx_intel_link_power(struct azx *chip, bool enable)
 624 {
 625         struct hdac_bus *bus = azx_bus(chip);
 626
 627         return snd_hdac_display_power(bus, enable);
 628 }
 629
 630 /*
 631  * Check whether the current DMA position is acceptable for updating
 632  * periods.  Returns non-zero if it's OK.
 633  *
 634  * Many HD-audio controllers appear pretty inaccurate about
 635  * the update-IRQ timing.  The IRQ is issued before actually the
 636  * data is processed.  So, we need to process it afterwords in a
 637  * workqueue.
 638  */
 639 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 640 {
 641         struct snd_pcm_substream *substream = azx_dev->core.substream;
 642         int stream = substream->stream;
 643         u32 wallclk;
 644         unsigned int pos;
 645
 646         wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 647         if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 648                 return -1;      /* bogus (too early) interrupt */
 649
 650         if (chip->get_position[stream])
 651                 pos = chip->get_position[stream](chip, azx_dev);
 652         else { /* use the position buffer as default */
 653                 pos = azx_get_pos_posbuf(chip, azx_dev);
 654                 if (!pos || pos == (u32)-1) {
 655                         dev_info(chip->card->dev,
 656                                  "Invalid position buffer, using LPIB read method instead.\n");
 657                         chip->get_position[stream] = azx_get_pos_lpib;
 658                         if (chip->get_position[0] == azx_get_pos_lpib &&
 659                             chip->get_position[1] == azx_get_pos_lpib)
 660                                 azx_bus(chip)->use_posbuf = false;
 661                         pos = azx_get_pos_lpib(chip, azx_dev);
 662                         chip->get_delay[stream] = NULL;
 663                 } else {
 664                         chip->get_position[stream] = azx_get_pos_posbuf;
 665                         if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
 666                                 chip->get_delay[stream] = azx_get_delay_from_lpib;
 667                 }
 668         }
 669
 670         if (pos >= azx_dev->core.bufsize)
 671                 pos = 0;
 672
 673         if (WARN_ONCE(!azx_dev->core.period_bytes,
 674                       "hda-intel: zero azx_dev->period_bytes"))
 675                 return -1; /* this shouldn't happen! */
 676         if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
 677             pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
 678                 /* NG - it's below the first next period boundary */
 679                 return chip->bdl_pos_adj ? 0 : -1;
 680         azx_dev->core.start_wallclk += wallclk;
 681         return 1; /* OK, it's fine */
 682 }
 683
 684 /*
 685  * The work for pending PCM period updates.
 686  */
 687 static void azx_irq_pending_work(struct work_struct *work)
 688 {
 689         struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
 690         struct azx *chip = &hda->chip;
 691         struct hdac_bus *bus = azx_bus(chip);
 692         struct hdac_stream *s;
 693         int pending, ok;
 694
 695         if (!hda->irq_pending_warned) {
 696                 dev_info(chip->card->dev,
 697                          "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
 698                          chip->card->number);
 699                 hda->irq_pending_warned = 1;
 700         }
 701
 702         for (;;) {
 703                 pending = 0;
 704                 spin_lock_irq(&bus->reg_lock);
 705                 list_for_each_entry(s, &bus->stream_list, list) {
 706                         struct azx_dev *azx_dev = stream_to_azx_dev(s);
 707                         if (!azx_dev->irq_pending ||
 708                             !s->substream ||
 709                             !s->running)
 710                                 continue;
 711                         ok = azx_position_ok(chip, azx_dev);
 712                         if (ok > 0) {
 713                                 azx_dev->irq_pending = 0;
 714                                 spin_unlock(&bus->reg_lock);
 715                                 snd_pcm_period_elapsed(s->substream);
 716                                 spin_lock(&bus->reg_lock);
 717                         } else if (ok < 0) {
 718                                 pending = 0;    /* too early */
 719                         } else
 720                                 pending++;
 721                 }
 722                 spin_unlock_irq(&bus->reg_lock);
 723                 if (!pending)
 724                         return;
 725                 msleep(1);
 726         }
 727 }
 728
 729 /* clear irq_pending flags and assure no on-going workq */
 730 static void azx_clear_irq_pending(struct azx *chip)
 731 {
 732         struct hdac_bus *bus = azx_bus(chip);
 733         struct hdac_stream *s;
 734
 735         spin_lock_irq(&bus->reg_lock);
 736         list_for_each_entry(s, &bus->stream_list, list) {
 737                 struct azx_dev *azx_dev = stream_to_azx_dev(s);
 738                 azx_dev->irq_pending = 0;
 739         }
 740         spin_unlock_irq(&bus->reg_lock);
 741 }
 742
 743 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
 744 {
 745         struct hdac_bus *bus = azx_bus(chip);
 746
 747         if (request_irq(chip->pci->irq, azx_interrupt,
 748                         chip->msi ? 0 : IRQF_SHARED,
 749                         chip->card->irq_descr, chip)) {
 750                 dev_err(chip->card->dev,
 751                         "unable to grab IRQ %d, disabling device\n",
 752                         chip->pci->irq);
 753                 if (do_disconnect)
 754                         snd_card_disconnect(chip->card);
 755                 return -1;
 756         }
 757         bus->irq = chip->pci->irq;
 758         pci_intx(chip->pci, !chip->msi);
 759         return 0;
 760 }
 761
 762 /* get the current DMA position with correction on VIA chips */
 763 static unsigned int azx_via_get_position(struct azx *chip,
 764                                          struct azx_dev *azx_dev)
 765 {
 766         unsigned int link_pos, mini_pos, bound_pos;
 767         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
 768         unsigned int fifo_size;
 769
 770         link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
 771         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 772                 /* Playback, no problem using link position */
 773                 return link_pos;
 774         }
 775
 776         /* Capture */
 777         /* For new chipset,
 778          * use mod to get the DMA position just like old chipset
 779          */
 780         mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
 781         mod_dma_pos %= azx_dev->core.period_bytes;
 782
 783         /* azx_dev->fifo_size can't get FIFO size of in stream.
 784          * Get from base address + offset.
 785          */
 786         fifo_size = readw(azx_bus(chip)->remap_addr +
 787                           VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
 788
 789         if (azx_dev->insufficient) {
 790                 /* Link position never gather than FIFO size */
 791                 if (link_pos <= fifo_size)
 792                         return 0;
 793
 794                 azx_dev->insufficient = 0;
 795         }
 796
 797         if (link_pos <= fifo_size)
 798                 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
 799         else
 800                 mini_pos = link_pos - fifo_size;
 801
 802         /* Find nearest previous boudary */
 803         mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
 804         mod_link_pos = link_pos % azx_dev->core.period_bytes;
 805         if (mod_link_pos >= fifo_size)
 806                 bound_pos = link_pos - mod_link_pos;
 807         else if (mod_dma_pos >= mod_mini_pos)
 808                 bound_pos = mini_pos - mod_mini_pos;
 809         else {
 810                 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
 811                 if (bound_pos >= azx_dev->core.bufsize)
 812                         bound_pos = 0;
 813         }
 814
 815         /* Calculate real DMA position we want */
 816         return bound_pos + mod_dma_pos;
 817 }
 818
 819 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
 820                                          struct azx_dev *azx_dev)
 821 {
 822         return _snd_hdac_chip_readl(azx_bus(chip),
 823                                     AZX_REG_VS_SDXDPIB_XBASE +
 824                                     (AZX_REG_VS_SDXDPIB_XINTERVAL *
 825                                      azx_dev->core.index));
 826 }
 827
 828 /* get the current DMA position with correction on SKL+ chips */
 829 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
 830 {
 831         /* DPIB register gives a more accurate position for playback */
 832         if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 833                 return azx_skl_get_dpib_pos(chip, azx_dev);
 834
 835         /* For capture, we need to read posbuf, but it requires a delay
 836          * for the possible boundary overlap; the read of DPIB fetches the
 837          * actual posbuf
 838          */
 839         udelay(20);
 840         azx_skl_get_dpib_pos(chip, azx_dev);
 841         return azx_get_pos_posbuf(chip, azx_dev);
 842 }
 843
 844 #ifdef CONFIG_PM
 845 static DEFINE_MUTEX(card_list_lock);
 846 static LIST_HEAD(card_list);
 847
 848 static void azx_add_card_list(struct azx *chip)
 849 {
 850         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 851         mutex_lock(&card_list_lock);
 852         list_add(&hda->list, &card_list);
 853         mutex_unlock(&card_list_lock);
 854 }
 855
 856 static void azx_del_card_list(struct azx *chip)
 857 {
 858         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
 859         mutex_lock(&card_list_lock);
 860         list_del_init(&hda->list);
 861         mutex_unlock(&card_list_lock);
 862 }
 863
 864 /* trigger power-save check at writing parameter */
 865 static int param_set_xint(const char *val, const struct kernel_param *kp)
 866 {
 867         struct hda_intel *hda;
 868         struct azx *chip;
 869         int prev = power_save;
 870         int ret = param_set_int(val, kp);
 871
 872         if (ret || prev == power_save)
 873                 return ret;
 874
 875         mutex_lock(&card_list_lock);
 876         list_for_each_entry(hda, &card_list, list) {
 877                 chip = &hda->chip;
 878                 if (!hda->probe_continued || chip->disabled)
 879                         continue;
 880                 snd_hda_set_power_save(&chip->bus, power_save * 1000);
 881         }
 882         mutex_unlock(&card_list_lock);
 883         return 0;
 884 }
 885 #else
 886 #define azx_add_card_list(chip) /* NOP */
 887 #define azx_del_card_list(chip) /* NOP */
 888 #endif /* CONFIG_PM */
 889
 890 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
 891 /*
 892  * power management
 893  */
 894 static int azx_suspend(struct device *dev)
 895 {
 896         struct snd_card *card = dev_get_drvdata(dev);
 897         struct azx *chip;
 898         struct hda_intel *hda;
 899         struct hdac_bus *bus;
 900
 901         if (!card)
 902                 return 0;
 903
 904         chip = card->private_data;
 905         hda = container_of(chip, struct hda_intel, chip);
 906         if (chip->disabled || hda->init_failed || !chip->running)
 907                 return 0;
 908
 909         bus = azx_bus(chip);
 910         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
 911         azx_clear_irq_pending(chip);
 912         azx_stop_chip(chip);
 913         azx_enter_link_reset(chip);
 914         if (bus->irq >= 0) {
 915                 free_irq(bus->irq, chip);
 916                 bus->irq = -1;
 917         }
 918
 919         if (chip->msi)
 920                 pci_disable_msi(chip->pci);
 921         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
 922                 && hda->need_i915_power)
 923                 snd_hdac_display_power(bus, false);
 924
 925         trace_azx_suspend(chip);
 926         return 0;
 927 }
 928
 929 static int azx_resume(struct device *dev)
 930 {
 931         struct pci_dev *pci = to_pci_dev(dev);
 932         struct snd_card *card = dev_get_drvdata(dev);
 933         struct azx *chip;
 934         struct hda_intel *hda;
 935         struct hdac_bus *bus;
 936
 937         if (!card)
 938                 return 0;
 939
 940         chip = card->private_data;
 941         hda = container_of(chip, struct hda_intel, chip);
 942         bus = azx_bus(chip);
 943         if (chip->disabled || hda->init_failed || !chip->running)
 944                 return 0;
 945
 946         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 947                 snd_hdac_display_power(bus, true);
 948                 if (hda->need_i915_power)
 949                         snd_hdac_i915_set_bclk(bus);
 950         }
 951
 952         if (chip->msi)
 953                 if (pci_enable_msi(pci) < 0)
 954                         chip->msi = 0;
 955         if (azx_acquire_irq(chip, 1) < 0)
 956                 return -EIO;
 957         azx_init_pci(chip);
 958
 959         hda_intel_init_chip(chip, true);
 960
 961         /* power down again for link-controlled chips */
 962         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
 963             !hda->need_i915_power)
 964                 snd_hdac_display_power(bus, false);
 965
 966         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 967
 968         trace_azx_resume(chip);
 969         return 0;
 970 }
 971 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
 972
 973 #ifdef CONFIG_PM_SLEEP
 974 /* put codec down to D3 at hibernation for Intel SKL+;
 975  * otherwise BIOS may still access the codec and screw up the driver
 976  */
 977 static int azx_freeze_noirq(struct device *dev)
 978 {
 979         struct pci_dev *pci = to_pci_dev(dev);
 980
 981         if (IS_SKL_PLUS(pci))
 982                 pci_set_power_state(pci, PCI_D3hot);
 983
 984         return 0;
 985 }
 986
 987 static int azx_thaw_noirq(struct device *dev)
 988 {
 989         struct pci_dev *pci = to_pci_dev(dev);
 990
 991         if (IS_SKL_PLUS(pci))
 992                 pci_set_power_state(pci, PCI_D0);
 993
 994         return 0;
 995 }
 996 #endif /* CONFIG_PM_SLEEP */
 997
 998 #ifdef CONFIG_PM
 999 static int azx_runtime_suspend(struct device *dev)
1000 {
1001         struct snd_card *card = dev_get_drvdata(dev);
1002         struct azx *chip;
1003         struct hda_intel *hda;
1004
1005         if (!card)
1006                 return 0;
1007
1008         chip = card->private_data;
1009         hda = container_of(chip, struct hda_intel, chip);
1010         if (chip->disabled || hda->init_failed)
1011                 return 0;
1012
1013         if (!azx_has_pm_runtime(chip))
1014                 return 0;
1015
1016         /* enable controller wake up event */
1017         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1018                   STATESTS_INT_MASK);
1019
1020         azx_stop_chip(chip);
1021         azx_enter_link_reset(chip);
1022         azx_clear_irq_pending(chip);
1023         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1024                 && hda->need_i915_power)
1025                 snd_hdac_display_power(azx_bus(chip), false);
1026
1027         trace_azx_runtime_suspend(chip);
1028         return 0;
1029 }
1030
1031 static int azx_runtime_resume(struct device *dev)
1032 {
1033         struct snd_card *card = dev_get_drvdata(dev);
1034         struct azx *chip;
1035         struct hda_intel *hda;
1036         struct hdac_bus *bus;
1037         struct hda_codec *codec;
1038         int status;
1039
1040         if (!card)
1041                 return 0;
1042
1043         chip = card->private_data;
1044         hda = container_of(chip, struct hda_intel, chip);
1045         bus = azx_bus(chip);
1046         if (chip->disabled || hda->init_failed)
1047                 return 0;
1048
1049         if (!azx_has_pm_runtime(chip))
1050                 return 0;
1051
1052         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1053                 snd_hdac_display_power(bus, true);
1054                 if (hda->need_i915_power)
1055                         snd_hdac_i915_set_bclk(bus);
1056         }
1057
1058         /* Read STATESTS before controller reset */
1059         status = azx_readw(chip, STATESTS);
1060
1061         azx_init_pci(chip);
1062         hda_intel_init_chip(chip, true);
1063
1064         if (status) {
1065                 list_for_each_codec(codec, &chip->bus)
1066                         if (status & (1 << codec->addr))
1067                                 schedule_delayed_work(&codec->jackpoll_work,
1068                                                       codec->jackpoll_interval);
1069         }
1070
1071         /* disable controller Wake Up event*/
1072         azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1073                         ~STATESTS_INT_MASK);
1074
1075         /* power down again for link-controlled chips */
1076         if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1077             !hda->need_i915_power)
1078                 snd_hdac_display_power(bus, false);
1079
1080         trace_azx_runtime_resume(chip);
1081         return 0;
1082 }
1083
1084 static int azx_runtime_idle(struct device *dev)
1085 {
1086         struct snd_card *card = dev_get_drvdata(dev);
1087         struct azx *chip;
1088         struct hda_intel *hda;
1089
1090         if (!card)
1091                 return 0;
1092
1093         chip = card->private_data;
1094         hda = container_of(chip, struct hda_intel, chip);
1095         if (chip->disabled || hda->init_failed)
1096                 return 0;
1097
1098         if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1099             azx_bus(chip)->codec_powered || !chip->running)
1100                 return -EBUSY;
1101
1102         return 0;
1103 }
1104
1105 static const struct dev_pm_ops azx_pm = {
1106         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1107 #ifdef CONFIG_PM_SLEEP
1108         .freeze_noirq = azx_freeze_noirq,
1109         .thaw_noirq = azx_thaw_noirq,
1110 #endif
1111         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1112 };
1113
1114 #define AZX_PM_OPS      &azx_pm
1115 #else
1116 #define AZX_PM_OPS      NULL
1117 #endif /* CONFIG_PM */
1118
1119
1120 static int azx_probe_continue(struct azx *chip);
1121
1122 #ifdef SUPPORT_VGA_SWITCHEROO
1123 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1124
1125 static void azx_vs_set_state(struct pci_dev *pci,
1126                              enum vga_switcheroo_state state)
1127 {
1128         struct snd_card *card = pci_get_drvdata(pci);
1129         struct azx *chip = card->private_data;
1130         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1131         bool disabled;
1132
1133         wait_for_completion(&hda->probe_wait);
1134         if (hda->init_failed)
1135                 return;
1136
1137         disabled = (state == VGA_SWITCHEROO_OFF);
1138         if (chip->disabled == disabled)
1139                 return;
1140
1141         if (!hda->probe_continued) {
1142                 chip->disabled = disabled;
1143                 if (!disabled) {
1144                         dev_info(chip->card->dev,
1145                                  "Start delayed initialization\n");
1146                         if (azx_probe_continue(chip) < 0) {
1147                                 dev_err(chip->card->dev, "initialization error\n");
1148                                 hda->init_failed = true;
1149                         }
1150                 }
1151         } else {
1152                 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1153                          disabled ? "Disabling" : "Enabling");
1154                 if (disabled) {
1155                         pm_runtime_put_sync_suspend(card->dev);
1156                         azx_suspend(card->dev);
1157                         /* when we get suspended by vga_switcheroo we end up in D3cold,
1158                          * however we have no ACPI handle, so pci/acpi can't put us there,
1159                          * put ourselves there */
1160                         pci->current_state = PCI_D3cold;
1161                         chip->disabled = true;
1162                         if (snd_hda_lock_devices(&chip->bus))
1163                                 dev_warn(chip->card->dev,
1164                                          "Cannot lock devices!\n");
1165                 } else {
1166                         snd_hda_unlock_devices(&chip->bus);
1167                         pm_runtime_get_noresume(card->dev);
1168                         chip->disabled = false;
1169                         azx_resume(card->dev);
1170                 }
1171         }
1172 }
1173
1174 static bool azx_vs_can_switch(struct pci_dev *pci)
1175 {
1176         struct snd_card *card = pci_get_drvdata(pci);
1177         struct azx *chip = card->private_data;
1178         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1179
1180         wait_for_completion(&hda->probe_wait);
1181         if (hda->init_failed)
1182                 return false;
1183         if (chip->disabled || !hda->probe_continued)
1184                 return true;
1185         if (snd_hda_lock_devices(&chip->bus))
1186                 return false;
1187         snd_hda_unlock_devices(&chip->bus);
1188         return true;
1189 }
1190
1191 static void init_vga_switcheroo(struct azx *chip)
1192 {
1193         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1194         struct pci_dev *p = get_bound_vga(chip->pci);
1195         if (p) {
1196                 dev_info(chip->card->dev,
1197                          "Handle vga_switcheroo audio client\n");
1198                 hda->use_vga_switcheroo = 1;
1199                 pci_dev_put(p);
1200         }
1201 }
1202
1203 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1204         .set_gpu_state = azx_vs_set_state,
1205         .can_switch = azx_vs_can_switch,
1206 };
1207
1208 static int register_vga_switcheroo(struct azx *chip)
1209 {
1210         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1211         int err;
1212
1213         if (!hda->use_vga_switcheroo)
1214                 return 0;
1215         /* FIXME: currently only handling DIS controller
1216          * is there any machine with two switchable HDMI audio controllers?
1217          */
1218         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1219                                                    VGA_SWITCHEROO_DIS);
1220         if (err < 0)
1221                 return err;
1222         hda->vga_switcheroo_registered = 1;
1223
1224         /* register as an optimus hdmi audio power domain */
1225         vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1226                                                          &hda->hdmi_pm_domain);
1227         return 0;
1228 }
1229 #else
1230 #define init_vga_switcheroo(chip)               /* NOP */
1231 #define register_vga_switcheroo(chip)           0
1232 #define check_hdmi_disabled(pci)        false
1233 #endif /* SUPPORT_VGA_SWITCHER */
1234
1235 /*
1236  * destructor
1237  */
1238 static int azx_free(struct azx *chip)
1239 {
1240         struct pci_dev *pci = chip->pci;
1241         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1242         struct hdac_bus *bus = azx_bus(chip);
1243
1244         if (azx_has_pm_runtime(chip) && chip->running)
1245                 pm_runtime_get_noresume(&pci->dev);
1246
1247         azx_del_card_list(chip);
1248
1249         hda->init_failed = 1; /* to be sure */
1250         complete_all(&hda->probe_wait);
1251
1252         if (use_vga_switcheroo(hda)) {
1253                 if (chip->disabled && hda->probe_continued)
1254                         snd_hda_unlock_devices(&chip->bus);
1255                 if (hda->vga_switcheroo_registered) {
1256                         vga_switcheroo_unregister_client(chip->pci);
1257                         vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1258                 }
1259         }
1260
1261         if (bus->chip_init) {
1262                 azx_clear_irq_pending(chip);
1263                 azx_stop_all_streams(chip);
1264                 azx_stop_chip(chip);
1265         }
1266
1267         if (bus->irq >= 0)
1268                 free_irq(bus->irq, (void*)chip);
1269         if (chip->msi)
1270                 pci_disable_msi(chip->pci);
1271         iounmap(bus->remap_addr);
1272
1273         azx_free_stream_pages(chip);
1274         azx_free_streams(chip);
1275         snd_hdac_bus_exit(bus);
1276
1277         if (chip->region_requested)
1278                 pci_release_regions(chip->pci);
1279
1280         pci_disable_device(chip->pci);
1281 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1282         release_firmware(chip->fw);
1283 #endif
1284
1285         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1286                 if (hda->need_i915_power)
1287                         snd_hdac_display_power(bus, false);
1288                 snd_hdac_i915_exit(bus);
1289         }
1290         kfree(hda);
1291
1292         return 0;
1293 }
1294
1295 static int azx_dev_disconnect(struct snd_device *device)
1296 {
1297         struct azx *chip = device->device_data;
1298
1299         chip->bus.shutdown = 1;
1300         return 0;
1301 }
1302
1303 static int azx_dev_free(struct snd_device *device)
1304 {
1305         return azx_free(device->device_data);
1306 }
1307
1308 #ifdef SUPPORT_VGA_SWITCHEROO
1309 /*
1310  * Check of disabled HDMI controller by vga_switcheroo
1311  */
1312 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1313 {
1314         struct pci_dev *p;
1315
1316         /* check only discrete GPU */
1317         switch (pci->vendor) {
1318         case PCI_VENDOR_ID_ATI:
1319         case PCI_VENDOR_ID_AMD:
1320         case PCI_VENDOR_ID_NVIDIA:
1321                 if (pci->devfn == 1) {
1322                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1323                                                         pci->bus->number, 0);
1324                         if (p) {
1325                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1326                                         return p;
1327                                 pci_dev_put(p);
1328                         }
1329                 }
1330                 break;
1331         }
1332         return NULL;
1333 }
1334
1335 static bool check_hdmi_disabled(struct pci_dev *pci)
1336 {
1337         bool vga_inactive = false;
1338         struct pci_dev *p = get_bound_vga(pci);
1339
1340         if (p) {
1341                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1342                         vga_inactive = true;
1343                 pci_dev_put(p);
1344         }
1345         return vga_inactive;
1346 }
1347 #endif /* SUPPORT_VGA_SWITCHEROO */
1348
1349 /*
1350  * white/black-listing for position_fix
1351  */
1352 static struct snd_pci_quirk position_fix_list[] = {
1353         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1354         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1355         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1356         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1357         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1358         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1359         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1360         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1361         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1362         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1363         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1364         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1365         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1366         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1367         {}
1368 };
1369
1370 static int check_position_fix(struct azx *chip, int fix)
1371 {
1372         const struct snd_pci_quirk *q;
1373
1374         switch (fix) {
1375         case POS_FIX_AUTO:
1376         case POS_FIX_LPIB:
1377         case POS_FIX_POSBUF:
1378         case POS_FIX_VIACOMBO:
1379         case POS_FIX_COMBO:
1380         case POS_FIX_SKL:
1381                 return fix;
1382         }
1383
1384         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1385         if (q) {
1386                 dev_info(chip->card->dev,
1387                          "position_fix set to %d for device %04x:%04x\n",
1388                          q->value, q->subvendor, q->subdevice);
1389                 return q->value;
1390         }
1391
1392         /* Check VIA/ATI HD Audio Controller exist */
1393         if (chip->driver_type == AZX_DRIVER_VIA) {
1394                 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1395                 return POS_FIX_VIACOMBO;
1396         }
1397         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1398                 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1399                 return POS_FIX_LPIB;
1400         }
1401         if (IS_SKL_PLUS(chip->pci)) {
1402                 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1403                 return POS_FIX_SKL;
1404         }
1405         return POS_FIX_AUTO;
1406 }
1407
1408 static void assign_position_fix(struct azx *chip, int fix)
1409 {
1410         static azx_get_pos_callback_t callbacks[] = {
1411                 [POS_FIX_AUTO] = NULL,
1412                 [POS_FIX_LPIB] = azx_get_pos_lpib,
1413                 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1414                 [POS_FIX_VIACOMBO] = azx_via_get_position,
1415                 [POS_FIX_COMBO] = azx_get_pos_lpib,
1416                 [POS_FIX_SKL] = azx_get_pos_skl,
1417         };
1418
1419         chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1420
1421         /* combo mode uses LPIB only for playback */
1422         if (fix == POS_FIX_COMBO)
1423                 chip->get_position[1] = NULL;
1424
1425         if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1426             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1427                 chip->get_delay[0] = chip->get_delay[1] =
1428                         azx_get_delay_from_lpib;
1429         }
1430
1431 }
1432
1433 /*
1434  * black-lists for probe_mask
1435  */
1436 static struct snd_pci_quirk probe_mask_list[] = {
1437         /* Thinkpad often breaks the controller communication when accessing
1438          * to the non-working (or non-existing) modem codec slot.
1439          */
1440         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1441         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1442         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1443         /* broken BIOS */
1444         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1445         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1446         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1447         /* forced codec slots */
1448         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1449         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1450         /* WinFast VP200 H (Teradici) user reported broken communication */
1451         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1452         {}
1453 };
1454
1455 #define AZX_FORCE_CODEC_MASK    0x100
1456
1457 static void check_probe_mask(struct azx *chip, int dev)
1458 {
1459         const struct snd_pci_quirk *q;
1460
1461         chip->codec_probe_mask = probe_mask[dev];
1462         if (chip->codec_probe_mask == -1) {
1463                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1464                 if (q) {
1465                         dev_info(chip->card->dev,
1466                                  "probe_mask set to 0x%x for device %04x:%04x\n",
1467                                  q->value, q->subvendor, q->subdevice);
1468                         chip->codec_probe_mask = q->value;
1469                 }
1470         }
1471
1472         /* check forced option */
1473         if (chip->codec_probe_mask != -1 &&
1474             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1475                 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1476                 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1477                          (int)azx_bus(chip)->codec_mask);
1478         }
1479 }
1480
1481 /*
1482  * white/black-list for enable_msi
1483  */
1484 static struct snd_pci_quirk msi_black_list[] = {
1485         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1486         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1487         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1488         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1489         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1490         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1491         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1492         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1493         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1494         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1495         {}
1496 };
1497
1498 static void check_msi(struct azx *chip)
1499 {
1500         const struct snd_pci_quirk *q;
1501
1502         if (enable_msi >= 0) {
1503                 chip->msi = !!enable_msi;
1504                 return;
1505         }
1506         chip->msi = 1;  /* enable MSI as default */
1507         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1508         if (q) {
1509                 dev_info(chip->card->dev,
1510                          "msi for device %04x:%04x set to %d\n",
1511                          q->subvendor, q->subdevice, q->value);
1512                 chip->msi = q->value;
1513                 return;
1514         }
1515
1516         /* NVidia chipsets seem to cause troubles with MSI */
1517         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1518                 dev_info(chip->card->dev, "Disabling MSI\n");
1519                 chip->msi = 0;
1520         }
1521 }
1522
1523 /* check the snoop mode availability */
1524 static void azx_check_snoop_available(struct azx *chip)
1525 {
1526         int snoop = hda_snoop;
1527
1528         if (snoop >= 0) {
1529                 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1530                          snoop ? "snoop" : "non-snoop");
1531                 chip->snoop = snoop;
1532                 return;
1533         }
1534
1535         snoop = true;
1536         if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1537             chip->driver_type == AZX_DRIVER_VIA) {
1538                 /* force to non-snoop mode for a new VIA controller
1539                  * when BIOS is set
1540                  */
1541                 u8 val;
1542                 pci_read_config_byte(chip->pci, 0x42, &val);
1543                 if (!(val & 0x80) && chip->pci->revision == 0x30)
1544                         snoop = false;
1545         }
1546
1547         if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1548                 snoop = false;
1549
1550         chip->snoop = snoop;
1551         if (!snoop)
1552                 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1553 }
1554
1555 static void azx_probe_work(struct work_struct *work)
1556 {
1557         struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1558         azx_probe_continue(&hda->chip);
1559 }
1560
1561 static int default_bdl_pos_adj(struct azx *chip)
1562 {
1563         /* some exceptions: Atoms seem problematic with value 1 */
1564         if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1565                 switch (chip->pci->device) {
1566                 case 0x0f04: /* Baytrail */
1567                 case 0x2284: /* Braswell */
1568                         return 32;
1569                 }
1570         }
1571
1572         switch (chip->driver_type) {
1573         case AZX_DRIVER_ICH:
1574         case AZX_DRIVER_PCH:
1575                 return 1;
1576         default:
1577                 return 32;
1578         }
1579 }
1580
1581 /*
1582  * constructor
1583  */
1584 static const struct hdac_io_ops pci_hda_io_ops;
1585 static const struct hda_controller_ops pci_hda_ops;
1586
1587 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1588                       int dev, unsigned int driver_caps,
1589                       struct azx **rchip)
1590 {
1591         static struct snd_device_ops ops = {
1592                 .dev_disconnect = azx_dev_disconnect,
1593                 .dev_free = azx_dev_free,
1594         };
1595         struct hda_intel *hda;
1596         struct azx *chip;
1597         int err;
1598
1599         *rchip = NULL;
1600
1601         err = pci_enable_device(pci);
1602         if (err < 0)
1603                 return err;
1604
1605         hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1606         if (!hda) {
1607                 pci_disable_device(pci);
1608                 return -ENOMEM;
1609         }
1610
1611         chip = &hda->chip;
1612         mutex_init(&chip->open_mutex);
1613         chip->card = card;
1614         chip->pci = pci;
1615         chip->ops = &pci_hda_ops;
1616         chip->driver_caps = driver_caps;
1617         chip->driver_type = driver_caps & 0xff;
1618         check_msi(chip);
1619         chip->dev_index = dev;
1620         chip->jackpoll_ms = jackpoll_ms;
1621         INIT_LIST_HEAD(&chip->pcm_list);
1622         INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1623         INIT_LIST_HEAD(&hda->list);
1624         init_vga_switcheroo(chip);
1625         init_completion(&hda->probe_wait);
1626
1627         assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1628
1629         check_probe_mask(chip, dev);
1630
1631         if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1632                 chip->fallback_to_single_cmd = 1;
1633         else /* explicitly set to single_cmd or not */
1634                 chip->single_cmd = single_cmd;
1635
1636         azx_check_snoop_available(chip);
1637
1638         if (bdl_pos_adj[dev] < 0)
1639                 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1640         else
1641                 chip->bdl_pos_adj = bdl_pos_adj[dev];
1642
1643         err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1644         if (err < 0) {
1645                 kfree(hda);
1646                 pci_disable_device(pci);
1647                 return err;
1648         }
1649
1650         if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1651                 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1652                 chip->bus.needs_damn_long_delay = 1;
1653         }
1654
1655         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1656         if (err < 0) {
1657                 dev_err(card->dev, "Error creating device [card]!\n");
1658                 azx_free(chip);
1659                 return err;
1660         }
1661
1662         /* continue probing in work context as may trigger request module */
1663         INIT_WORK(&hda->probe_work, azx_probe_work);
1664
1665         *rchip = chip;
1666
1667         return 0;
1668 }
1669
1670 static int azx_first_init(struct azx *chip)
1671 {
1672         int dev = chip->dev_index;
1673         struct pci_dev *pci = chip->pci;
1674         struct snd_card *card = chip->card;
1675         struct hdac_bus *bus = azx_bus(chip);
1676         int err;
1677         unsigned short gcap;
1678         unsigned int dma_bits = 64;
1679
1680 #if BITS_PER_LONG != 64
1681         /* Fix up base address on ULI M5461 */
1682         if (chip->driver_type == AZX_DRIVER_ULI) {
1683                 u16 tmp3;
1684                 pci_read_config_word(pci, 0x40, &tmp3);
1685                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1686                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1687         }
1688 #endif
1689
1690         err = pci_request_regions(pci, "ICH HD audio");
1691         if (err < 0)
1692                 return err;
1693         chip->region_requested = 1;
1694
1695         bus->addr = pci_resource_start(pci, 0);
1696         bus->remap_addr = pci_ioremap_bar(pci, 0);
1697         if (bus->remap_addr == NULL) {
1698                 dev_err(card->dev, "ioremap error\n");
1699                 return -ENXIO;
1700         }
1701
1702         if (IS_SKL_PLUS(pci))
1703                 snd_hdac_bus_parse_capabilities(bus);
1704
1705         /*
1706          * Some Intel CPUs has always running timer (ART) feature and
1707          * controller may have Global time sync reporting capability, so
1708          * check both of these before declaring synchronized time reporting
1709          * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1710          */
1711         chip->gts_present = false;
1712
1713 #ifdef CONFIG_X86
1714         if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1715                 chip->gts_present = true;
1716 #endif
1717
1718         if (chip->msi) {
1719                 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1720                         dev_dbg(card->dev, "Disabling 64bit MSI\n");
1721                         pci->no_64bit_msi = true;
1722                 }
1723                 if (pci_enable_msi(pci) < 0)
1724                         chip->msi = 0;
1725         }
1726
1727         if (azx_acquire_irq(chip, 0) < 0)
1728                 return -EBUSY;
1729
1730         pci_set_master(pci);
1731         synchronize_irq(bus->irq);
1732
1733         gcap = azx_readw(chip, GCAP);
1734         dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1735
1736         /* AMD devices support 40 or 48bit DMA, take the safe one */
1737         if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1738                 dma_bits = 40;
1739
1740         /* disable SB600 64bit support for safety */
1741         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1742                 struct pci_dev *p_smbus;
1743                 dma_bits = 40;
1744                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1745                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1746                                          NULL);
1747                 if (p_smbus) {
1748                         if (p_smbus->revision < 0x30)
1749                                 gcap &= ~AZX_GCAP_64OK;
1750                         pci_dev_put(p_smbus);
1751                 }
1752         }
1753
1754         /* NVidia hardware normally only supports up to 40 bits of DMA */
1755         if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1756                 dma_bits = 40;
1757
1758         /* disable 64bit DMA address on some devices */
1759         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1760                 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1761                 gcap &= ~AZX_GCAP_64OK;
1762         }
1763
1764         /* disable buffer size rounding to 128-byte multiples if supported */
1765         if (align_buffer_size >= 0)
1766                 chip->align_buffer_size = !!align_buffer_size;
1767         else {
1768                 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1769                         chip->align_buffer_size = 0;
1770                 else
1771                         chip->align_buffer_size = 1;
1772         }
1773
1774         /* allow 64bit DMA address if supported by H/W */
1775         if (!(gcap & AZX_GCAP_64OK))
1776                 dma_bits = 32;
1777         if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1778                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1779         } else {
1780                 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1781                 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1782         }
1783
1784         /* read number of streams from GCAP register instead of using
1785          * hardcoded value
1786          */
1787         chip->capture_streams = (gcap >> 8) & 0x0f;
1788         chip->playback_streams = (gcap >> 12) & 0x0f;
1789         if (!chip->playback_streams && !chip->capture_streams) {
1790                 /* gcap didn't give any info, switching to old method */
1791
1792                 switch (chip->driver_type) {
1793                 case AZX_DRIVER_ULI:
1794                         chip->playback_streams = ULI_NUM_PLAYBACK;
1795                         chip->capture_streams = ULI_NUM_CAPTURE;
1796                         break;
1797                 case AZX_DRIVER_ATIHDMI:
1798                 case AZX_DRIVER_ATIHDMI_NS:
1799                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1800                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1801                         break;
1802                 case AZX_DRIVER_GENERIC:
1803                 default:
1804                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1805                         chip->capture_streams = ICH6_NUM_CAPTURE;
1806                         break;
1807                 }
1808         }
1809         chip->capture_index_offset = 0;
1810         chip->playback_index_offset = chip->capture_streams;
1811         chip->num_streams = chip->playback_streams + chip->capture_streams;
1812
1813         /* sanity check for the SDxCTL.STRM field overflow */
1814         if (chip->num_streams > 15 &&
1815             (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1816                 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1817                          "forcing separate stream tags", chip->num_streams);
1818                 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1819         }
1820
1821         /* initialize streams */
1822         err = azx_init_streams(chip);
1823         if (err < 0)
1824                 return err;
1825
1826         err = azx_alloc_stream_pages(chip);
1827         if (err < 0)
1828                 return err;
1829
1830         /* initialize chip */
1831         azx_init_pci(chip);
1832
1833         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1834                 snd_hdac_i915_set_bclk(bus);
1835
1836         hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1837
1838         /* codec detection */
1839         if (!azx_bus(chip)->codec_mask) {
1840                 dev_err(card->dev, "no codecs found!\n");
1841                 return -ENODEV;
1842         }
1843
1844         strcpy(card->driver, "HDA-Intel");
1845         strlcpy(card->shortname, driver_short_names[chip->driver_type],
1846                 sizeof(card->shortname));
1847         snprintf(card->longname, sizeof(card->longname),
1848                  "%s at 0x%lx irq %i",
1849                  card->shortname, bus->addr, bus->irq);
1850
1851         return 0;
1852 }
1853
1854 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1855 /* callback from request_firmware_nowait() */
1856 static void azx_firmware_cb(const struct firmware *fw, void *context)
1857 {
1858         struct snd_card *card = context;
1859         struct azx *chip = card->private_data;
1860         struct pci_dev *pci = chip->pci;
1861
1862         if (!fw) {
1863                 dev_err(card->dev, "Cannot load firmware, aborting\n");
1864                 goto error;
1865         }
1866
1867         chip->fw = fw;
1868         if (!chip->disabled) {
1869                 /* continue probing */
1870                 if (azx_probe_continue(chip))
1871                         goto error;
1872         }
1873         return; /* OK */
1874
1875  error:
1876         snd_card_free(card);
1877         pci_set_drvdata(pci, NULL);
1878 }
1879 #endif
1880
1881 /*
1882  * HDA controller ops.
1883  */
1884
1885 /* PCI register access. */
1886 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1887 {
1888         writel(value, addr);
1889 }
1890
1891 static u32 pci_azx_readl(u32 __iomem *addr)
1892 {
1893         return readl(addr);
1894 }
1895
1896 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1897 {
1898         writew(value, addr);
1899 }
1900
1901 static u16 pci_azx_readw(u16 __iomem *addr)
1902 {
1903         return readw(addr);
1904 }
1905
1906 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
1907 {
1908         writeb(value, addr);
1909 }
1910
1911 static u8 pci_azx_readb(u8 __iomem *addr)
1912 {
1913         return readb(addr);
1914 }
1915
1916 static int disable_msi_reset_irq(struct azx *chip)
1917 {
1918         struct hdac_bus *bus = azx_bus(chip);
1919         int err;
1920
1921         free_irq(bus->irq, chip);
1922         bus->irq = -1;
1923         pci_disable_msi(chip->pci);
1924         chip->msi = 0;
1925         err = azx_acquire_irq(chip, 1);
1926         if (err < 0)
1927                 return err;
1928
1929         return 0;
1930 }
1931
1932 /* DMA page allocation helpers.  */
1933 static int dma_alloc_pages(struct hdac_bus *bus,
1934                            int type,
1935                            size_t size,
1936                            struct snd_dma_buffer *buf)
1937 {
1938         struct azx *chip = bus_to_azx(bus);
1939         int err;
1940
1941         err = snd_dma_alloc_pages(type,
1942                                   bus->dev,
1943                                   size, buf);
1944         if (err < 0)
1945                 return err;
1946         mark_pages_wc(chip, buf, true);
1947         return 0;
1948 }
1949
1950 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
1951 {
1952         struct azx *chip = bus_to_azx(bus);
1953
1954         mark_pages_wc(chip, buf, false);
1955         snd_dma_free_pages(buf);
1956 }
1957
1958 static int substream_alloc_pages(struct azx *chip,
1959                                  struct snd_pcm_substream *substream,
1960                                  size_t size)
1961 {
1962         struct azx_dev *azx_dev = get_azx_dev(substream);
1963         int ret;
1964
1965         mark_runtime_wc(chip, azx_dev, substream, false);
1966         ret = snd_pcm_lib_malloc_pages(substream, size);
1967         if (ret < 0)
1968                 return ret;
1969         mark_runtime_wc(chip, azx_dev, substream, true);
1970         return 0;
1971 }
1972
1973 static int substream_free_pages(struct azx *chip,
1974                                 struct snd_pcm_substream *substream)
1975 {
1976         struct azx_dev *azx_dev = get_azx_dev(substream);
1977         mark_runtime_wc(chip, azx_dev, substream, false);
1978         return snd_pcm_lib_free_pages(substream);
1979 }
1980
1981 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
1982                              struct vm_area_struct *area)
1983 {
1984 #ifdef CONFIG_X86
1985         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1986         struct azx *chip = apcm->chip;
1987         if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
1988                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
1989 #endif
1990 }
1991
1992 static const struct hdac_io_ops pci_hda_io_ops = {
1993         .reg_writel = pci_azx_writel,
1994         .reg_readl = pci_azx_readl,
1995         .reg_writew = pci_azx_writew,
1996         .reg_readw = pci_azx_readw,
1997         .reg_writeb = pci_azx_writeb,
1998         .reg_readb = pci_azx_readb,
1999         .dma_alloc_pages = dma_alloc_pages,
2000         .dma_free_pages = dma_free_pages,
2001 };
2002
2003 static const struct hda_controller_ops pci_hda_ops = {
2004         .disable_msi_reset_irq = disable_msi_reset_irq,
2005         .substream_alloc_pages = substream_alloc_pages,
2006         .substream_free_pages = substream_free_pages,
2007         .pcm_mmap_prepare = pcm_mmap_prepare,
2008         .position_check = azx_position_check,
2009         .link_power = azx_intel_link_power,
2010 };
2011
2012 static int azx_probe(struct pci_dev *pci,
2013                      const struct pci_device_id *pci_id)
2014 {
2015         static int dev;
2016         struct snd_card *card;
2017         struct hda_intel *hda;
2018         struct azx *chip;
2019         bool schedule_probe;
2020         int err;
2021
2022         if (dev >= SNDRV_CARDS)
2023                 return -ENODEV;
2024         if (!enable[dev]) {
2025                 dev++;
2026                 return -ENOENT;
2027         }
2028
2029         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2030                            0, &card);
2031         if (err < 0) {
2032                 dev_err(&pci->dev, "Error creating card!\n");
2033                 return err;
2034         }
2035
2036         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2037         if (err < 0)
2038                 goto out_free;
2039         card->private_data = chip;
2040         hda = container_of(chip, struct hda_intel, chip);
2041
2042         pci_set_drvdata(pci, card);
2043
2044         err = register_vga_switcheroo(chip);
2045         if (err < 0) {
2046                 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2047                 goto out_free;
2048         }
2049
2050         if (check_hdmi_disabled(pci)) {
2051                 dev_info(card->dev, "VGA controller is disabled\n");
2052                 dev_info(card->dev, "Delaying initialization\n");
2053                 chip->disabled = true;
2054         }
2055
2056         schedule_probe = !chip->disabled;
2057
2058 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2059         if (patch[dev] && *patch[dev]) {
2060                 dev_info(card->dev, "Applying patch firmware '%s'\n",
2061                          patch[dev]);
2062                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2063                                               &pci->dev, GFP_KERNEL, card,
2064                                               azx_firmware_cb);
2065                 if (err < 0)
2066                         goto out_free;
2067                 schedule_probe = false; /* continued in azx_firmware_cb() */
2068         }
2069 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2070
2071 #ifndef CONFIG_SND_HDA_I915
2072         if (CONTROLLER_IN_GPU(pci))
2073                 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2074 #endif
2075
2076         if (schedule_probe)
2077                 schedule_work(&hda->probe_work);
2078
2079         dev++;
2080         if (chip->disabled)
2081                 complete_all(&hda->probe_wait);
2082         return 0;
2083
2084 out_free:
2085         snd_card_free(card);
2086         return err;
2087 }
2088
2089 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2090 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2091         [AZX_DRIVER_NVIDIA] = 8,
2092         [AZX_DRIVER_TERA] = 1,
2093 };
2094
2095 static int azx_probe_continue(struct azx *chip)
2096 {
2097         struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2098         struct hdac_bus *bus = azx_bus(chip);
2099         struct pci_dev *pci = chip->pci;
2100         int dev = chip->dev_index;
2101         int err;
2102
2103         hda->probe_continued = 1;
2104
2105         /* Request display power well for the HDA controller or codec. For
2106          * Haswell/Broadwell, both the display HDA controller and codec need
2107          * this power. For other platforms, like Baytrail/Braswell, only the
2108          * display codec needs the power and it can be released after probe.
2109          */
2110         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2111                 /* HSW/BDW controllers need this power */
2112                 if (CONTROLLER_IN_GPU(pci))
2113                         hda->need_i915_power = 1;
2114
2115                 err = snd_hdac_i915_init(bus);
2116                 if (err < 0) {
2117                         /* if the controller is bound only with HDMI/DP
2118                          * (for HSW and BDW), we need to abort the probe;
2119                          * for other chips, still continue probing as other
2120                          * codecs can be on the same link.
2121                          */
2122                         if (CONTROLLER_IN_GPU(pci)) {
2123                                 dev_err(chip->card->dev,
2124                                         "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2125                                 goto out_free;
2126                         } else
2127                                 goto skip_i915;
2128                 }
2129
2130                 err = snd_hdac_display_power(bus, true);
2131                 if (err < 0) {
2132                         dev_err(chip->card->dev,
2133                                 "Cannot turn on display power on i915\n");
2134                         goto i915_power_fail;
2135                 }
2136         }
2137
2138  skip_i915:
2139         err = azx_first_init(chip);
2140         if (err < 0)
2141                 goto out_free;
2142
2143 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2144         chip->beep_mode = beep_mode[dev];
2145 #endif
2146
2147         /* create codec instances */
2148         err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2149         if (err < 0)
2150                 goto out_free;
2151
2152 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2153         if (chip->fw) {
2154                 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2155                                          chip->fw->data);
2156                 if (err < 0)
2157                         goto out_free;
2158 #ifndef CONFIG_PM
2159                 release_firmware(chip->fw); /* no longer needed */
2160                 chip->fw = NULL;
2161 #endif
2162         }
2163 #endif
2164         if ((probe_only[dev] & 1) == 0) {
2165                 err = azx_codec_configure(chip);
2166                 if (err < 0)
2167                         goto out_free;
2168         }
2169
2170         err = snd_card_register(chip->card);
2171         if (err < 0)
2172                 goto out_free;
2173
2174         chip->running = 1;
2175         azx_add_card_list(chip);
2176         snd_hda_set_power_save(&chip->bus, power_save * 1000);
2177         if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2178                 pm_runtime_put_autosuspend(&pci->dev);
2179
2180 out_free:
2181         if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2182                 && !hda->need_i915_power)
2183                 snd_hdac_display_power(bus, false);
2184
2185 i915_power_fail:
2186         if (err < 0)
2187                 hda->init_failed = 1;
2188         complete_all(&hda->probe_wait);
2189         return err;
2190 }
2191
2192 static void azx_remove(struct pci_dev *pci)
2193 {
2194         struct snd_card *card = pci_get_drvdata(pci);
2195         struct azx *chip;
2196         struct hda_intel *hda;
2197
2198         if (card) {
2199                 /* cancel the pending probing work */
2200                 chip = card->private_data;
2201                 hda = container_of(chip, struct hda_intel, chip);
2202                 /* FIXME: below is an ugly workaround.
2203                  * Both device_release_driver() and driver_probe_device()
2204                  * take *both* the device's and its parent's lock before
2205                  * calling the remove() and probe() callbacks.  The codec
2206                  * probe takes the locks of both the codec itself and its
2207                  * parent, i.e. the PCI controller dev.  Meanwhile, when
2208                  * the PCI controller is unbound, it takes its lock, too
2209                  * ==> ouch, a deadlock!
2210                  * As a workaround, we unlock temporarily here the controller
2211                  * device during cancel_work_sync() call.
2212                  */
2213                 device_unlock(&pci->dev);
2214                 cancel_work_sync(&hda->probe_work);
2215                 device_lock(&pci->dev);
2216
2217                 snd_card_free(card);
2218         }
2219 }
2220
2221 static void azx_shutdown(struct pci_dev *pci)
2222 {
2223         struct snd_card *card = pci_get_drvdata(pci);
2224         struct azx *chip;
2225
2226         if (!card)
2227                 return;
2228         chip = card->private_data;
2229         if (chip && chip->running)
2230                 azx_stop_chip(chip);
2231 }
2232
2233 /* PCI IDs */
2234 static const struct pci_device_id azx_ids[] = {
2235         /* CPT */
2236         { PCI_DEVICE(0x8086, 0x1c20),
2237           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2238         /* PBG */
2239         { PCI_DEVICE(0x8086, 0x1d20),
2240           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2241         /* Panther Point */
2242         { PCI_DEVICE(0x8086, 0x1e20),
2243           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2244         /* Lynx Point */
2245         { PCI_DEVICE(0x8086, 0x8c20),
2246           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2247         /* 9 Series */
2248         { PCI_DEVICE(0x8086, 0x8ca0),
2249           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2250         /* Wellsburg */
2251         { PCI_DEVICE(0x8086, 0x8d20),
2252           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2253         { PCI_DEVICE(0x8086, 0x8d21),
2254           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2255         /* Lewisburg */
2256         { PCI_DEVICE(0x8086, 0xa1f0),
2257           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2258         { PCI_DEVICE(0x8086, 0xa270),
2259           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2260         /* Lynx Point-LP */
2261         { PCI_DEVICE(0x8086, 0x9c20),
2262           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2263         /* Lynx Point-LP */
2264         { PCI_DEVICE(0x8086, 0x9c21),
2265           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2266         /* Wildcat Point-LP */
2267         { PCI_DEVICE(0x8086, 0x9ca0),
2268           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2269         /* Sunrise Point */
2270         { PCI_DEVICE(0x8086, 0xa170),
2271           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2272         /* Sunrise Point-LP */
2273         { PCI_DEVICE(0x8086, 0x9d70),
2274           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2275         /* Kabylake */
2276         { PCI_DEVICE(0x8086, 0xa171),
2277           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2278         /* Kabylake-LP */
2279         { PCI_DEVICE(0x8086, 0x9d71),
2280           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2281         /* Kabylake-H */
2282         { PCI_DEVICE(0x8086, 0xa2f0),
2283           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2284         /* Broxton-P(Apollolake) */
2285         { PCI_DEVICE(0x8086, 0x5a98),
2286           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2287         /* Broxton-T */
2288         { PCI_DEVICE(0x8086, 0x1a98),
2289           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2290         /* Gemini-Lake */
2291         { PCI_DEVICE(0x8086, 0x3198),
2292           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2293         /* Haswell */
2294         { PCI_DEVICE(0x8086, 0x0a0c),
2295           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2296         { PCI_DEVICE(0x8086, 0x0c0c),
2297           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2298         { PCI_DEVICE(0x8086, 0x0d0c),
2299           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2300         /* Broadwell */
2301         { PCI_DEVICE(0x8086, 0x160c),
2302           .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2303         /* 5 Series/3400 */
2304         { PCI_DEVICE(0x8086, 0x3b56),
2305           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2306         /* Poulsbo */
2307         { PCI_DEVICE(0x8086, 0x811b),
2308           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2309         /* Oaktrail */
2310         { PCI_DEVICE(0x8086, 0x080a),
2311           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2312         /* BayTrail */
2313         { PCI_DEVICE(0x8086, 0x0f04),
2314           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2315         /* Braswell */
2316         { PCI_DEVICE(0x8086, 0x2284),
2317           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2318         /* ICH6 */
2319         { PCI_DEVICE(0x8086, 0x2668),
2320           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2321         /* ICH7 */
2322         { PCI_DEVICE(0x8086, 0x27d8),
2323           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2324         /* ESB2 */
2325         { PCI_DEVICE(0x8086, 0x269a),
2326           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2327         /* ICH8 */
2328         { PCI_DEVICE(0x8086, 0x284b),
2329           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2330         /* ICH9 */
2331         { PCI_DEVICE(0x8086, 0x293e),
2332           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2333         /* ICH9 */
2334         { PCI_DEVICE(0x8086, 0x293f),
2335           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2336         /* ICH10 */
2337         { PCI_DEVICE(0x8086, 0x3a3e),
2338           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2339         /* ICH10 */
2340         { PCI_DEVICE(0x8086, 0x3a6e),
2341           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2342         /* Generic Intel */
2343         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2344           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2345           .class_mask = 0xffffff,
2346           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2347         /* ATI SB 450/600/700/800/900 */
2348         { PCI_DEVICE(0x1002, 0x437b),
2349           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2350         { PCI_DEVICE(0x1002, 0x4383),
2351           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2352         /* AMD Hudson */
2353         { PCI_DEVICE(0x1022, 0x780d),
2354           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2355         /* ATI HDMI */
2356         { PCI_DEVICE(0x1002, 0x0002),
2357           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2358         { PCI_DEVICE(0x1002, 0x1308),
2359           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2360         { PCI_DEVICE(0x1002, 0x157a),
2361           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2362         { PCI_DEVICE(0x1002, 0x15b3),
2363           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2364         { PCI_DEVICE(0x1002, 0x793b),
2365           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2366         { PCI_DEVICE(0x1002, 0x7919),
2367           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2368         { PCI_DEVICE(0x1002, 0x960f),
2369           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2370         { PCI_DEVICE(0x1002, 0x970f),
2371           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2372         { PCI_DEVICE(0x1002, 0x9840),
2373           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2374         { PCI_DEVICE(0x1002, 0xaa00),
2375           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2376         { PCI_DEVICE(0x1002, 0xaa08),
2377           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2378         { PCI_DEVICE(0x1002, 0xaa10),
2379           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2380         { PCI_DEVICE(0x1002, 0xaa18),
2381           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2382         { PCI_DEVICE(0x1002, 0xaa20),
2383           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2384         { PCI_DEVICE(0x1002, 0xaa28),
2385           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2386         { PCI_DEVICE(0x1002, 0xaa30),
2387           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2388         { PCI_DEVICE(0x1002, 0xaa38),
2389           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2390         { PCI_DEVICE(0x1002, 0xaa40),
2391           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2392         { PCI_DEVICE(0x1002, 0xaa48),
2393           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2394         { PCI_DEVICE(0x1002, 0xaa50),
2395           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2396         { PCI_DEVICE(0x1002, 0xaa58),
2397           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2398         { PCI_DEVICE(0x1002, 0xaa60),
2399           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2400         { PCI_DEVICE(0x1002, 0xaa68),
2401           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2402         { PCI_DEVICE(0x1002, 0xaa80),
2403           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2404         { PCI_DEVICE(0x1002, 0xaa88),
2405           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2406         { PCI_DEVICE(0x1002, 0xaa90),
2407           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2408         { PCI_DEVICE(0x1002, 0xaa98),
2409           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2410         { PCI_DEVICE(0x1002, 0x9902),
2411           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2412         { PCI_DEVICE(0x1002, 0xaaa0),
2413           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2414         { PCI_DEVICE(0x1002, 0xaaa8),
2415           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2416         { PCI_DEVICE(0x1002, 0xaab0),
2417           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2418         { PCI_DEVICE(0x1002, 0xaac0),
2419           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2420         { PCI_DEVICE(0x1002, 0xaac8),
2421           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2422         { PCI_DEVICE(0x1002, 0xaad8),
2423           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2424         { PCI_DEVICE(0x1002, 0xaae8),
2425           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2426         { PCI_DEVICE(0x1002, 0xaae0),
2427           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2428         { PCI_DEVICE(0x1002, 0xaaf0),
2429           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2430         /* VIA VT8251/VT8237A */
2431         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2432         /* VIA GFX VT7122/VX900 */
2433         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2434         /* VIA GFX VT6122/VX11 */
2435         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2436         /* SIS966 */
2437         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2438         /* ULI M5461 */
2439         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2440         /* NVIDIA MCP */
2441         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2442           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2443           .class_mask = 0xffffff,
2444           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2445         /* Teradici */
2446         { PCI_DEVICE(0x6549, 0x1200),
2447           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2448         { PCI_DEVICE(0x6549, 0x2200),
2449           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2450         /* Creative X-Fi (CA0110-IBG) */
2451         /* CTHDA chips */
2452         { PCI_DEVICE(0x1102, 0x0010),
2453           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2454         { PCI_DEVICE(0x1102, 0x0012),
2455           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2456 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2457         /* the following entry conflicts with snd-ctxfi driver,
2458          * as ctxfi driver mutates from HD-audio to native mode with
2459          * a special command sequence.
2460          */
2461         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2462           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2463           .class_mask = 0xffffff,
2464           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2465           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2466 #else
2467         /* this entry seems still valid -- i.e. without emu20kx chip */
2468         { PCI_DEVICE(0x1102, 0x0009),
2469           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2470           AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2471 #endif
2472         /* CM8888 */
2473         { PCI_DEVICE(0x13f6, 0x5011),
2474           .driver_data = AZX_DRIVER_CMEDIA |
2475           AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2476         /* Vortex86MX */
2477         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2478         /* VMware HDAudio */
2479         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2480         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2481         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2482           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2483           .class_mask = 0xffffff,
2484           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2485         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2486           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2487           .class_mask = 0xffffff,
2488           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2489         { 0, }
2490 };
2491 MODULE_DEVICE_TABLE(pci, azx_ids);
2492
2493 /* pci_driver definition */
2494 static struct pci_driver azx_driver = {
2495         .name = KBUILD_MODNAME,
2496         .id_table = azx_ids,
2497         .probe = azx_probe,
2498         .remove = azx_remove,
2499         .shutdown = azx_shutdown,
2500         .driver = {
2501                 .pm = AZX_PM_OPS,
2502         },
2503 };
2504
2505 module_pci_driver(azx_driver);