3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <sound/driver.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <sound/core.h>
49 #include <sound/initval.h>
50 #include "hda_codec.h"
53 static int index = SNDRV_DEFAULT_IDX1;
54 static char *id = SNDRV_DEFAULT_STR1;
56 static int position_fix;
57 static int probe_mask = -1;
58 static int single_cmd;
59 static int enable_msi;
61 module_param(index, int, 0444);
62 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
63 module_param(id, charp, 0444);
64 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
65 module_param(model, charp, 0444);
66 MODULE_PARM_DESC(model, "Use the given board model.");
67 module_param(position_fix, int, 0444);
68 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
69 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
70 module_param(probe_mask, int, 0444);
71 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
72 module_param(single_cmd, bool, 0444);
73 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
74 "(for debugging only).");
75 module_param(enable_msi, int, 0);
76 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
78 #ifdef CONFIG_SND_HDA_POWER_SAVE
79 /* power_save option is defined in hda_codec.c */
81 /* reset the HD-audio controller in power save mode.
82 * this may give more power-saving, but will take longer time to
85 static int power_save_controller = 1;
86 module_param(power_save_controller, bool, 0644);
87 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
90 /* just for backward compatibility */
92 module_param(enable, bool, 0444);
94 MODULE_LICENSE("GPL");
95 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
111 MODULE_DESCRIPTION("Intel HDA driver");
113 #define SFX "hda-intel: "
119 #define ICH6_REG_GCAP 0x00
120 #define ICH6_REG_VMIN 0x02
121 #define ICH6_REG_VMAJ 0x03
122 #define ICH6_REG_OUTPAY 0x04
123 #define ICH6_REG_INPAY 0x06
124 #define ICH6_REG_GCTL 0x08
125 #define ICH6_REG_WAKEEN 0x0c
126 #define ICH6_REG_STATESTS 0x0e
127 #define ICH6_REG_GSTS 0x10
128 #define ICH6_REG_INTCTL 0x20
129 #define ICH6_REG_INTSTS 0x24
130 #define ICH6_REG_WALCLK 0x30
131 #define ICH6_REG_SYNC 0x34
132 #define ICH6_REG_CORBLBASE 0x40
133 #define ICH6_REG_CORBUBASE 0x44
134 #define ICH6_REG_CORBWP 0x48
135 #define ICH6_REG_CORBRP 0x4A
136 #define ICH6_REG_CORBCTL 0x4c
137 #define ICH6_REG_CORBSTS 0x4d
138 #define ICH6_REG_CORBSIZE 0x4e
140 #define ICH6_REG_RIRBLBASE 0x50
141 #define ICH6_REG_RIRBUBASE 0x54
142 #define ICH6_REG_RIRBWP 0x58
143 #define ICH6_REG_RINTCNT 0x5a
144 #define ICH6_REG_RIRBCTL 0x5c
145 #define ICH6_REG_RIRBSTS 0x5d
146 #define ICH6_REG_RIRBSIZE 0x5e
148 #define ICH6_REG_IC 0x60
149 #define ICH6_REG_IR 0x64
150 #define ICH6_REG_IRS 0x68
151 #define ICH6_IRS_VALID (1<<1)
152 #define ICH6_IRS_BUSY (1<<0)
154 #define ICH6_REG_DPLBASE 0x70
155 #define ICH6_REG_DPUBASE 0x74
156 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
158 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
159 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
161 /* stream register offsets from stream base */
162 #define ICH6_REG_SD_CTL 0x00
163 #define ICH6_REG_SD_STS 0x03
164 #define ICH6_REG_SD_LPIB 0x04
165 #define ICH6_REG_SD_CBL 0x08
166 #define ICH6_REG_SD_LVI 0x0c
167 #define ICH6_REG_SD_FIFOW 0x0e
168 #define ICH6_REG_SD_FIFOSIZE 0x10
169 #define ICH6_REG_SD_FORMAT 0x12
170 #define ICH6_REG_SD_BDLPL 0x18
171 #define ICH6_REG_SD_BDLPU 0x1c
174 #define ICH6_PCIREG_TCSEL 0x44
180 /* max number of SDs */
181 /* ICH, ATI and VIA have 4 playback and 4 capture */
182 #define ICH6_CAPTURE_INDEX 0
183 #define ICH6_NUM_CAPTURE 4
184 #define ICH6_PLAYBACK_INDEX 4
185 #define ICH6_NUM_PLAYBACK 4
187 /* ULI has 6 playback and 5 capture */
188 #define ULI_CAPTURE_INDEX 0
189 #define ULI_NUM_CAPTURE 5
190 #define ULI_PLAYBACK_INDEX 5
191 #define ULI_NUM_PLAYBACK 6
193 /* ATI HDMI has 1 playback and 0 capture */
194 #define ATIHDMI_CAPTURE_INDEX 0
195 #define ATIHDMI_NUM_CAPTURE 0
196 #define ATIHDMI_PLAYBACK_INDEX 0
197 #define ATIHDMI_NUM_PLAYBACK 1
199 /* this number is statically defined for simplicity */
200 #define MAX_AZX_DEV 16
202 /* max number of fragments - we may use more if allocating more pages for BDL */
203 #define BDL_SIZE PAGE_ALIGN(8192)
204 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
205 /* max buffer size - no h/w limit, you can increase as you like */
206 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
207 /* max number of PCM devics per card */
208 #define AZX_MAX_AUDIO_PCMS 6
209 #define AZX_MAX_MODEM_PCMS 2
210 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
212 /* RIRB int mask: overrun[2], response[0] */
213 #define RIRB_INT_RESPONSE 0x01
214 #define RIRB_INT_OVERRUN 0x04
215 #define RIRB_INT_MASK 0x05
217 /* STATESTS int mask: SD2,SD1,SD0 */
218 #define AZX_MAX_CODECS 3
219 #define STATESTS_INT_MASK 0x07
222 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
223 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
224 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
225 #define SD_CTL_STREAM_TAG_SHIFT 20
227 /* SD_CTL and SD_STS */
228 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
229 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
230 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
231 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
235 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
237 /* INTCTL and INTSTS */
238 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
239 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
240 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
242 /* GCTL unsolicited response enable bit */
243 #define ICH6_GCTL_UREN (1<<8)
246 #define ICH6_GCTL_RESET (1<<0)
248 /* CORB/RIRB control, read/write pointer */
249 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
250 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
251 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
252 /* below are so far hardcoded - should read registers in future */
253 #define ICH6_MAX_CORB_ENTRIES 256
254 #define ICH6_MAX_RIRB_ENTRIES 256
256 /* position fix mode */
264 /* Defines for ATI HD Audio support in SB450 south bridge */
265 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
266 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
268 /* Defines for Nvidia HDA support */
269 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
270 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
276 u32 *bdl; /* virtual address of the BDL */
277 dma_addr_t bdl_addr; /* physical address of the BDL */
278 u32 *posbuf; /* position buffer pointer */
280 unsigned int bufsize; /* size of the play buffer in bytes */
281 unsigned int fragsize; /* size of each period in bytes */
282 unsigned int frags; /* number for period in the play buffer */
283 unsigned int fifo_size; /* FIFO size */
285 void __iomem *sd_addr; /* stream descriptor pointer */
287 u32 sd_int_sta_mask; /* stream int status mask */
290 struct snd_pcm_substream *substream; /* assigned substream,
293 unsigned int format_val; /* format value to be set in the
294 * controller and the codec
296 unsigned char stream_tag; /* assigned stream */
297 unsigned char index; /* stream index */
298 /* for sanity check of position buffer */
299 unsigned int period_intr;
301 unsigned int opened :1;
302 unsigned int running :1;
307 u32 *buf; /* CORB/RIRB buffer
308 * Each CORB entry is 4byte, RIRB is 8byte
310 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
312 unsigned short rp, wp; /* read/write pointers */
313 int cmds; /* number of pending requests */
314 u32 res; /* last read value */
318 struct snd_card *card;
321 /* chip type specific */
323 int playback_streams;
324 int playback_index_offset;
326 int capture_index_offset;
331 void __iomem *remap_addr;
336 struct mutex open_mutex;
338 /* streams (x num_streams) */
339 struct azx_dev *azx_dev;
342 unsigned int pcm_devs;
343 struct snd_pcm *pcm[AZX_MAX_PCMS];
346 unsigned short codec_mask;
353 /* BDL, CORB/RIRB and position buffers */
354 struct snd_dma_buffer bdl;
355 struct snd_dma_buffer rb;
356 struct snd_dma_buffer posbuf;
360 unsigned int running :1;
361 unsigned int initialized :1;
362 unsigned int single_cmd :1;
363 unsigned int polling_mode :1;
367 unsigned int last_cmd; /* last issued command (to sync) */
381 static char *driver_short_names[] __devinitdata = {
382 [AZX_DRIVER_ICH] = "HDA Intel",
383 [AZX_DRIVER_ATI] = "HDA ATI SB",
384 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
385 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
386 [AZX_DRIVER_SIS] = "HDA SIS966",
387 [AZX_DRIVER_ULI] = "HDA ULI M5461",
388 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
392 * macros for easy use
394 #define azx_writel(chip,reg,value) \
395 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
396 #define azx_readl(chip,reg) \
397 readl((chip)->remap_addr + ICH6_REG_##reg)
398 #define azx_writew(chip,reg,value) \
399 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
400 #define azx_readw(chip,reg) \
401 readw((chip)->remap_addr + ICH6_REG_##reg)
402 #define azx_writeb(chip,reg,value) \
403 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
404 #define azx_readb(chip,reg) \
405 readb((chip)->remap_addr + ICH6_REG_##reg)
407 #define azx_sd_writel(dev,reg,value) \
408 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
409 #define azx_sd_readl(dev,reg) \
410 readl((dev)->sd_addr + ICH6_REG_##reg)
411 #define azx_sd_writew(dev,reg,value) \
412 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
413 #define azx_sd_readw(dev,reg) \
414 readw((dev)->sd_addr + ICH6_REG_##reg)
415 #define azx_sd_writeb(dev,reg,value) \
416 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
417 #define azx_sd_readb(dev,reg) \
418 readb((dev)->sd_addr + ICH6_REG_##reg)
420 /* for pcm support */
421 #define get_azx_dev(substream) (substream->runtime->private_data)
423 /* Get the upper 32bit of the given dma_addr_t
424 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
426 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
428 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
431 * Interface for HD codec
435 * CORB / RIRB interface
437 static int azx_alloc_cmd_io(struct azx *chip)
441 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
442 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
443 snd_dma_pci_data(chip->pci),
444 PAGE_SIZE, &chip->rb);
446 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
452 static void azx_init_cmd_io(struct azx *chip)
455 chip->corb.addr = chip->rb.addr;
456 chip->corb.buf = (u32 *)chip->rb.area;
457 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
458 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
460 /* set the corb size to 256 entries (ULI requires explicitly) */
461 azx_writeb(chip, CORBSIZE, 0x02);
462 /* set the corb write pointer to 0 */
463 azx_writew(chip, CORBWP, 0);
464 /* reset the corb hw read pointer */
465 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
466 /* enable corb dma */
467 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
470 chip->rirb.addr = chip->rb.addr + 2048;
471 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
472 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
473 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
475 /* set the rirb size to 256 entries (ULI requires explicitly) */
476 azx_writeb(chip, RIRBSIZE, 0x02);
477 /* reset the rirb hw write pointer */
478 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
479 /* set N=1, get RIRB response interrupt for new entry */
480 azx_writew(chip, RINTCNT, 1);
481 /* enable rirb dma and response irq */
482 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
483 chip->rirb.rp = chip->rirb.cmds = 0;
486 static void azx_free_cmd_io(struct azx *chip)
488 /* disable ringbuffer DMAs */
489 azx_writeb(chip, RIRBCTL, 0);
490 azx_writeb(chip, CORBCTL, 0);
494 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
496 struct azx *chip = codec->bus->private_data;
499 /* add command to corb */
500 wp = azx_readb(chip, CORBWP);
502 wp %= ICH6_MAX_CORB_ENTRIES;
504 spin_lock_irq(&chip->reg_lock);
506 chip->corb.buf[wp] = cpu_to_le32(val);
507 azx_writel(chip, CORBWP, wp);
508 spin_unlock_irq(&chip->reg_lock);
513 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
515 /* retrieve RIRB entry - called from interrupt handler */
516 static void azx_update_rirb(struct azx *chip)
521 wp = azx_readb(chip, RIRBWP);
522 if (wp == chip->rirb.wp)
526 while (chip->rirb.rp != wp) {
528 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
530 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
531 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
532 res = le32_to_cpu(chip->rirb.buf[rp]);
533 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
534 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
535 else if (chip->rirb.cmds) {
537 chip->rirb.res = res;
542 /* receive a response */
543 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
545 struct azx *chip = codec->bus->private_data;
546 unsigned long timeout;
549 timeout = jiffies + msecs_to_jiffies(1000);
551 if (chip->polling_mode) {
552 spin_lock_irq(&chip->reg_lock);
553 azx_update_rirb(chip);
554 spin_unlock_irq(&chip->reg_lock);
556 if (!chip->rirb.cmds)
557 return chip->rirb.res; /* the last value */
559 } while (time_after_eq(timeout, jiffies));
562 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
563 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
564 free_irq(chip->irq, chip);
566 pci_disable_msi(chip->pci);
568 if (azx_acquire_irq(chip, 1) < 0)
573 if (!chip->polling_mode) {
574 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
575 "switching to polling mode: last cmd=0x%08x\n",
577 chip->polling_mode = 1;
581 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
582 "switching to single_cmd mode: last cmd=0x%08x\n",
584 chip->rirb.rp = azx_readb(chip, RIRBWP);
586 /* switch to single_cmd mode */
587 chip->single_cmd = 1;
588 azx_free_cmd_io(chip);
593 * Use the single immediate command instead of CORB/RIRB for simplicity
595 * Note: according to Intel, this is not preferred use. The command was
596 * intended for the BIOS only, and may get confused with unsolicited
597 * responses. So, we shouldn't use it for normal operation from the
599 * I left the codes, however, for debugging/testing purposes.
603 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
605 struct azx *chip = codec->bus->private_data;
609 /* check ICB busy bit */
610 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
611 /* Clear IRV valid bit */
612 azx_writew(chip, IRS, azx_readw(chip, IRS) |
614 azx_writel(chip, IC, val);
615 azx_writew(chip, IRS, azx_readw(chip, IRS) |
621 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
622 azx_readw(chip, IRS), val);
626 /* receive a response */
627 static unsigned int azx_single_get_response(struct hda_codec *codec)
629 struct azx *chip = codec->bus->private_data;
633 /* check IRV busy bit */
634 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
635 return azx_readl(chip, IR);
638 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
639 azx_readw(chip, IRS));
640 return (unsigned int)-1;
644 * The below are the main callbacks from hda_codec.
646 * They are just the skeleton to call sub-callbacks according to the
647 * current setting of chip->single_cmd.
651 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
652 int direct, unsigned int verb,
655 struct azx *chip = codec->bus->private_data;
658 val = (u32)(codec->addr & 0x0f) << 28;
659 val |= (u32)direct << 27;
660 val |= (u32)nid << 20;
663 chip->last_cmd = val;
665 if (chip->single_cmd)
666 return azx_single_send_cmd(codec, val);
668 return azx_corb_send_cmd(codec, val);
672 static unsigned int azx_get_response(struct hda_codec *codec)
674 struct azx *chip = codec->bus->private_data;
675 if (chip->single_cmd)
676 return azx_single_get_response(codec);
678 return azx_rirb_get_response(codec);
681 #ifdef CONFIG_SND_HDA_POWER_SAVE
682 static void azx_power_notify(struct hda_codec *codec);
685 /* reset codec link */
686 static int azx_reset(struct azx *chip)
691 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
693 /* reset controller */
694 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
697 while (azx_readb(chip, GCTL) && --count)
700 /* delay for >= 100us for codec PLL to settle per spec
701 * Rev 0.9 section 5.5.1
705 /* Bring controller out of reset */
706 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
709 while (!azx_readb(chip, GCTL) && --count)
712 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
715 /* check to see if controller is ready */
716 if (!azx_readb(chip, GCTL)) {
717 snd_printd("azx_reset: controller not ready!\n");
721 /* Accept unsolicited responses */
722 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
725 if (!chip->codec_mask) {
726 chip->codec_mask = azx_readw(chip, STATESTS);
727 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
738 /* enable interrupts */
739 static void azx_int_enable(struct azx *chip)
741 /* enable controller CIE and GIE */
742 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
743 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
746 /* disable interrupts */
747 static void azx_int_disable(struct azx *chip)
751 /* disable interrupts in stream descriptor */
752 for (i = 0; i < chip->num_streams; i++) {
753 struct azx_dev *azx_dev = &chip->azx_dev[i];
754 azx_sd_writeb(azx_dev, SD_CTL,
755 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
758 /* disable SIE for all streams */
759 azx_writeb(chip, INTCTL, 0);
761 /* disable controller CIE and GIE */
762 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
763 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
766 /* clear interrupts */
767 static void azx_int_clear(struct azx *chip)
771 /* clear stream status */
772 for (i = 0; i < chip->num_streams; i++) {
773 struct azx_dev *azx_dev = &chip->azx_dev[i];
774 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
778 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
780 /* clear rirb status */
781 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
783 /* clear int status */
784 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
788 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
791 azx_writeb(chip, INTCTL,
792 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
793 /* set DMA start and interrupt mask */
794 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
795 SD_CTL_DMA_START | SD_INT_MASK);
799 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
802 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
803 ~(SD_CTL_DMA_START | SD_INT_MASK));
804 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
806 azx_writeb(chip, INTCTL,
807 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
812 * reset and start the controller registers
814 static void azx_init_chip(struct azx *chip)
816 if (chip->initialized)
819 /* reset controller */
822 /* initialize interrupts */
824 azx_int_enable(chip);
826 /* initialize the codec command I/O */
827 if (!chip->single_cmd)
828 azx_init_cmd_io(chip);
830 /* program the position buffer */
831 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
832 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
834 chip->initialized = 1;
838 * initialize the PCI registers
840 /* update bits in a PCI register byte */
841 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
842 unsigned char mask, unsigned char val)
846 pci_read_config_byte(pci, reg, &data);
848 data |= (val & mask);
849 pci_write_config_byte(pci, reg, data);
852 static void azx_init_pci(struct azx *chip)
854 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
855 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
856 * Ensuring these bits are 0 clears playback static on some HD Audio
859 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
861 switch (chip->driver_type) {
863 /* For ATI SB450 azalia HD audio, we need to enable snoop */
864 update_pci_byte(chip->pci,
865 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
866 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
868 case AZX_DRIVER_NVIDIA:
869 /* For NVIDIA HDA, enable snoop */
870 update_pci_byte(chip->pci,
871 NVIDIA_HDA_TRANSREG_ADDR,
872 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
881 static irqreturn_t azx_interrupt(int irq, void *dev_id)
883 struct azx *chip = dev_id;
884 struct azx_dev *azx_dev;
888 spin_lock(&chip->reg_lock);
890 status = azx_readl(chip, INTSTS);
892 spin_unlock(&chip->reg_lock);
896 for (i = 0; i < chip->num_streams; i++) {
897 azx_dev = &chip->azx_dev[i];
898 if (status & azx_dev->sd_int_sta_mask) {
899 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
900 if (azx_dev->substream && azx_dev->running) {
901 azx_dev->period_intr++;
902 spin_unlock(&chip->reg_lock);
903 snd_pcm_period_elapsed(azx_dev->substream);
904 spin_lock(&chip->reg_lock);
910 status = azx_readb(chip, RIRBSTS);
911 if (status & RIRB_INT_MASK) {
912 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
913 azx_update_rirb(chip);
914 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
918 /* clear state status int */
919 if (azx_readb(chip, STATESTS) & 0x04)
920 azx_writeb(chip, STATESTS, 0x04);
922 spin_unlock(&chip->reg_lock);
931 static void azx_setup_periods(struct azx_dev *azx_dev)
933 u32 *bdl = azx_dev->bdl;
934 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
937 /* reset BDL address */
938 azx_sd_writel(azx_dev, SD_BDLPL, 0);
939 azx_sd_writel(azx_dev, SD_BDLPU, 0);
941 /* program the initial BDL entries */
942 for (idx = 0; idx < azx_dev->frags; idx++) {
943 unsigned int off = idx << 2; /* 4 dword step */
944 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
945 /* program the address field of the BDL entry */
946 bdl[off] = cpu_to_le32((u32)addr);
947 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
949 /* program the size field of the BDL entry */
950 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
952 /* program the IOC to enable interrupt when buffer completes */
953 bdl[off+3] = cpu_to_le32(0x01);
958 * set up the SD for streaming
960 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
965 /* make sure the run bit is zero for SD */
966 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
969 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
970 SD_CTL_STREAM_RESET);
973 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
976 val &= ~SD_CTL_STREAM_RESET;
977 azx_sd_writeb(azx_dev, SD_CTL, val);
981 /* waiting for hardware to report that the stream is out of reset */
982 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
986 /* program the stream_tag */
987 azx_sd_writel(azx_dev, SD_CTL,
988 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
989 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
991 /* program the length of samples in cyclic buffer */
992 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
994 /* program the stream format */
995 /* this value needs to be the same as the one programmed */
996 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
998 /* program the stream LVI (last valid index) of the BDL */
999 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1001 /* program the BDL address */
1002 /* lower BDL address */
1003 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
1004 /* upper BDL address */
1005 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
1007 /* enable the position buffer */
1008 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1009 azx_writel(chip, DPLBASE,
1010 (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
1012 /* set the interrupt enable bits in the descriptor control register */
1013 azx_sd_writel(azx_dev, SD_CTL,
1014 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1021 * Codec initialization
1024 static unsigned int azx_max_codecs[] __devinitdata = {
1025 [AZX_DRIVER_ICH] = 3,
1026 [AZX_DRIVER_ATI] = 4,
1027 [AZX_DRIVER_ATIHDMI] = 4,
1028 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1029 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1030 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1031 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1034 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1036 struct hda_bus_template bus_temp;
1037 int c, codecs, audio_codecs, err;
1039 memset(&bus_temp, 0, sizeof(bus_temp));
1040 bus_temp.private_data = chip;
1041 bus_temp.modelname = model;
1042 bus_temp.pci = chip->pci;
1043 bus_temp.ops.command = azx_send_cmd;
1044 bus_temp.ops.get_response = azx_get_response;
1045 #ifdef CONFIG_SND_HDA_POWER_SAVE
1046 bus_temp.ops.pm_notify = azx_power_notify;
1049 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1053 codecs = audio_codecs = 0;
1054 for (c = 0; c < AZX_MAX_CODECS; c++) {
1055 if ((chip->codec_mask & (1 << c)) & probe_mask) {
1056 struct hda_codec *codec;
1057 err = snd_hda_codec_new(chip->bus, c, &codec);
1065 if (!audio_codecs) {
1066 /* probe additional slots if no codec is found */
1067 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1068 if ((chip->codec_mask & (1 << c)) & probe_mask) {
1069 err = snd_hda_codec_new(chip->bus, c, NULL);
1077 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1089 /* assign a stream for the PCM */
1090 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1093 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1094 dev = chip->playback_index_offset;
1095 nums = chip->playback_streams;
1097 dev = chip->capture_index_offset;
1098 nums = chip->capture_streams;
1100 for (i = 0; i < nums; i++, dev++)
1101 if (!chip->azx_dev[dev].opened) {
1102 chip->azx_dev[dev].opened = 1;
1103 return &chip->azx_dev[dev];
1108 /* release the assigned stream */
1109 static inline void azx_release_device(struct azx_dev *azx_dev)
1111 azx_dev->opened = 0;
1114 static struct snd_pcm_hardware azx_pcm_hw = {
1115 .info = (SNDRV_PCM_INFO_MMAP |
1116 SNDRV_PCM_INFO_INTERLEAVED |
1117 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1118 SNDRV_PCM_INFO_MMAP_VALID |
1119 /* No full-resume yet implemented */
1120 /* SNDRV_PCM_INFO_RESUME |*/
1121 SNDRV_PCM_INFO_PAUSE),
1122 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1123 .rates = SNDRV_PCM_RATE_48000,
1128 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1129 .period_bytes_min = 128,
1130 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1132 .periods_max = AZX_MAX_FRAG,
1138 struct hda_codec *codec;
1139 struct hda_pcm_stream *hinfo[2];
1142 static int azx_pcm_open(struct snd_pcm_substream *substream)
1144 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1145 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1146 struct azx *chip = apcm->chip;
1147 struct azx_dev *azx_dev;
1148 struct snd_pcm_runtime *runtime = substream->runtime;
1149 unsigned long flags;
1152 mutex_lock(&chip->open_mutex);
1153 azx_dev = azx_assign_device(chip, substream->stream);
1154 if (azx_dev == NULL) {
1155 mutex_unlock(&chip->open_mutex);
1158 runtime->hw = azx_pcm_hw;
1159 runtime->hw.channels_min = hinfo->channels_min;
1160 runtime->hw.channels_max = hinfo->channels_max;
1161 runtime->hw.formats = hinfo->formats;
1162 runtime->hw.rates = hinfo->rates;
1163 snd_pcm_limit_hw_rates(runtime);
1164 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1165 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1167 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1169 snd_hda_power_up(apcm->codec);
1170 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1172 azx_release_device(azx_dev);
1173 snd_hda_power_down(apcm->codec);
1174 mutex_unlock(&chip->open_mutex);
1177 spin_lock_irqsave(&chip->reg_lock, flags);
1178 azx_dev->substream = substream;
1179 azx_dev->running = 0;
1180 spin_unlock_irqrestore(&chip->reg_lock, flags);
1182 runtime->private_data = azx_dev;
1183 mutex_unlock(&chip->open_mutex);
1187 static int azx_pcm_close(struct snd_pcm_substream *substream)
1189 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1190 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1191 struct azx *chip = apcm->chip;
1192 struct azx_dev *azx_dev = get_azx_dev(substream);
1193 unsigned long flags;
1195 mutex_lock(&chip->open_mutex);
1196 spin_lock_irqsave(&chip->reg_lock, flags);
1197 azx_dev->substream = NULL;
1198 azx_dev->running = 0;
1199 spin_unlock_irqrestore(&chip->reg_lock, flags);
1200 azx_release_device(azx_dev);
1201 hinfo->ops.close(hinfo, apcm->codec, substream);
1202 snd_hda_power_down(apcm->codec);
1203 mutex_unlock(&chip->open_mutex);
1207 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1208 struct snd_pcm_hw_params *hw_params)
1210 return snd_pcm_lib_malloc_pages(substream,
1211 params_buffer_bytes(hw_params));
1214 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1216 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1217 struct azx_dev *azx_dev = get_azx_dev(substream);
1218 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1220 /* reset BDL address */
1221 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1222 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1223 azx_sd_writel(azx_dev, SD_CTL, 0);
1225 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1227 return snd_pcm_lib_free_pages(substream);
1230 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1232 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1233 struct azx *chip = apcm->chip;
1234 struct azx_dev *azx_dev = get_azx_dev(substream);
1235 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1236 struct snd_pcm_runtime *runtime = substream->runtime;
1238 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1239 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1240 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1241 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1245 if (!azx_dev->format_val) {
1246 snd_printk(KERN_ERR SFX
1247 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1248 runtime->rate, runtime->channels, runtime->format);
1252 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, "
1254 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1255 azx_setup_periods(azx_dev);
1256 azx_setup_controller(chip, azx_dev);
1257 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1258 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1260 azx_dev->fifo_size = 0;
1262 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1263 azx_dev->format_val, substream);
1266 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1268 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1269 struct azx_dev *azx_dev = get_azx_dev(substream);
1270 struct azx *chip = apcm->chip;
1273 spin_lock(&chip->reg_lock);
1275 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1276 case SNDRV_PCM_TRIGGER_RESUME:
1277 case SNDRV_PCM_TRIGGER_START:
1278 azx_stream_start(chip, azx_dev);
1279 azx_dev->running = 1;
1281 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1282 case SNDRV_PCM_TRIGGER_SUSPEND:
1283 case SNDRV_PCM_TRIGGER_STOP:
1284 azx_stream_stop(chip, azx_dev);
1285 azx_dev->running = 0;
1290 spin_unlock(&chip->reg_lock);
1291 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1292 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1293 cmd == SNDRV_PCM_TRIGGER_STOP) {
1295 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1302 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1304 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1305 struct azx *chip = apcm->chip;
1306 struct azx_dev *azx_dev = get_azx_dev(substream);
1309 if (chip->position_fix == POS_FIX_POSBUF ||
1310 chip->position_fix == POS_FIX_AUTO) {
1311 /* use the position buffer */
1312 pos = le32_to_cpu(*azx_dev->posbuf);
1313 if (chip->position_fix == POS_FIX_AUTO &&
1314 azx_dev->period_intr == 1 && !pos) {
1316 "hda-intel: Invalid position buffer, "
1317 "using LPIB read method instead.\n");
1318 chip->position_fix = POS_FIX_NONE;
1324 pos = azx_sd_readl(azx_dev, SD_LPIB);
1325 if (chip->position_fix == POS_FIX_FIFO)
1326 pos += azx_dev->fifo_size;
1328 if (pos >= azx_dev->bufsize)
1330 return bytes_to_frames(substream->runtime, pos);
1333 static struct snd_pcm_ops azx_pcm_ops = {
1334 .open = azx_pcm_open,
1335 .close = azx_pcm_close,
1336 .ioctl = snd_pcm_lib_ioctl,
1337 .hw_params = azx_pcm_hw_params,
1338 .hw_free = azx_pcm_hw_free,
1339 .prepare = azx_pcm_prepare,
1340 .trigger = azx_pcm_trigger,
1341 .pointer = azx_pcm_pointer,
1344 static void azx_pcm_free(struct snd_pcm *pcm)
1346 kfree(pcm->private_data);
1349 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1350 struct hda_pcm *cpcm, int pcm_dev)
1353 struct snd_pcm *pcm;
1354 struct azx_pcm *apcm;
1356 /* if no substreams are defined for both playback and capture,
1357 * it's just a placeholder. ignore it.
1359 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1362 snd_assert(cpcm->name, return -EINVAL);
1364 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1365 cpcm->stream[0].substreams,
1366 cpcm->stream[1].substreams,
1370 strcpy(pcm->name, cpcm->name);
1371 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1375 apcm->codec = codec;
1376 apcm->hinfo[0] = &cpcm->stream[0];
1377 apcm->hinfo[1] = &cpcm->stream[1];
1378 pcm->private_data = apcm;
1379 pcm->private_free = azx_pcm_free;
1380 if (cpcm->stream[0].substreams)
1381 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1382 if (cpcm->stream[1].substreams)
1383 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1384 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1385 snd_dma_pci_data(chip->pci),
1386 1024 * 64, 1024 * 1024);
1387 chip->pcm[pcm_dev] = pcm;
1388 if (chip->pcm_devs < pcm_dev + 1)
1389 chip->pcm_devs = pcm_dev + 1;
1394 static int __devinit azx_pcm_create(struct azx *chip)
1396 struct list_head *p;
1397 struct hda_codec *codec;
1401 err = snd_hda_build_pcms(chip->bus);
1405 /* create audio PCMs */
1407 list_for_each(p, &chip->bus->codec_list) {
1408 codec = list_entry(p, struct hda_codec, list);
1409 for (c = 0; c < codec->num_pcms; c++) {
1410 if (codec->pcm_info[c].is_modem)
1411 continue; /* create later */
1412 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1413 snd_printk(KERN_ERR SFX
1414 "Too many audio PCMs\n");
1417 err = create_codec_pcm(chip, codec,
1418 &codec->pcm_info[c], pcm_dev);
1425 /* create modem PCMs */
1426 pcm_dev = AZX_MAX_AUDIO_PCMS;
1427 list_for_each(p, &chip->bus->codec_list) {
1428 codec = list_entry(p, struct hda_codec, list);
1429 for (c = 0; c < codec->num_pcms; c++) {
1430 if (!codec->pcm_info[c].is_modem)
1431 continue; /* already created */
1432 if (pcm_dev >= AZX_MAX_PCMS) {
1433 snd_printk(KERN_ERR SFX
1434 "Too many modem PCMs\n");
1437 err = create_codec_pcm(chip, codec,
1438 &codec->pcm_info[c], pcm_dev);
1441 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1449 * mixer creation - all stuff is implemented in hda module
1451 static int __devinit azx_mixer_create(struct azx *chip)
1453 return snd_hda_build_controls(chip->bus);
1458 * initialize SD streams
1460 static int __devinit azx_init_stream(struct azx *chip)
1464 /* initialize each stream (aka device)
1465 * assign the starting bdl address to each stream (device)
1468 for (i = 0; i < chip->num_streams; i++) {
1469 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1470 struct azx_dev *azx_dev = &chip->azx_dev[i];
1471 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1472 azx_dev->bdl_addr = chip->bdl.addr + off;
1473 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1474 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1475 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1476 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1477 azx_dev->sd_int_sta_mask = 1 << i;
1478 /* stream tag: must be non-zero and unique */
1480 azx_dev->stream_tag = i + 1;
1486 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1488 if (request_irq(chip->pci->irq, azx_interrupt,
1489 chip->msi ? 0 : IRQF_SHARED,
1490 "HDA Intel", chip)) {
1491 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1492 "disabling device\n", chip->pci->irq);
1494 snd_card_disconnect(chip->card);
1497 chip->irq = chip->pci->irq;
1498 pci_intx(chip->pci, !chip->msi);
1503 static void azx_stop_chip(struct azx *chip)
1505 if (!chip->initialized)
1508 /* disable interrupts */
1509 azx_int_disable(chip);
1510 azx_int_clear(chip);
1512 /* disable CORB/RIRB */
1513 azx_free_cmd_io(chip);
1515 /* disable position buffer */
1516 azx_writel(chip, DPLBASE, 0);
1517 azx_writel(chip, DPUBASE, 0);
1519 chip->initialized = 0;
1522 #ifdef CONFIG_SND_HDA_POWER_SAVE
1523 /* power-up/down the controller */
1524 static void azx_power_notify(struct hda_codec *codec)
1526 struct azx *chip = codec->bus->private_data;
1527 struct hda_codec *c;
1530 list_for_each_entry(c, &codec->bus->codec_list, list) {
1537 azx_init_chip(chip);
1538 else if (chip->running && power_save_controller)
1539 azx_stop_chip(chip);
1541 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1547 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1549 struct snd_card *card = pci_get_drvdata(pci);
1550 struct azx *chip = card->private_data;
1553 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1554 for (i = 0; i < chip->pcm_devs; i++)
1555 snd_pcm_suspend_all(chip->pcm[i]);
1556 if (chip->initialized)
1557 snd_hda_suspend(chip->bus, state);
1558 azx_stop_chip(chip);
1559 if (chip->irq >= 0) {
1560 synchronize_irq(chip->irq);
1561 free_irq(chip->irq, chip);
1565 pci_disable_msi(chip->pci);
1566 pci_disable_device(pci);
1567 pci_save_state(pci);
1568 pci_set_power_state(pci, pci_choose_state(pci, state));
1572 static int azx_resume(struct pci_dev *pci)
1574 struct snd_card *card = pci_get_drvdata(pci);
1575 struct azx *chip = card->private_data;
1577 pci_set_power_state(pci, PCI_D0);
1578 pci_restore_state(pci);
1579 if (pci_enable_device(pci) < 0) {
1580 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1581 "disabling device\n");
1582 snd_card_disconnect(card);
1585 pci_set_master(pci);
1587 if (pci_enable_msi(pci) < 0)
1589 if (azx_acquire_irq(chip, 1) < 0)
1593 if (snd_hda_codecs_inuse(chip->bus))
1594 azx_init_chip(chip);
1596 snd_hda_resume(chip->bus);
1597 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1600 #endif /* CONFIG_PM */
1606 static int azx_free(struct azx *chip)
1608 if (chip->initialized) {
1610 for (i = 0; i < chip->num_streams; i++)
1611 azx_stream_stop(chip, &chip->azx_dev[i]);
1612 azx_stop_chip(chip);
1615 if (chip->irq >= 0) {
1616 synchronize_irq(chip->irq);
1617 free_irq(chip->irq, (void*)chip);
1620 pci_disable_msi(chip->pci);
1621 if (chip->remap_addr)
1622 iounmap(chip->remap_addr);
1625 snd_dma_free_pages(&chip->bdl);
1627 snd_dma_free_pages(&chip->rb);
1628 if (chip->posbuf.area)
1629 snd_dma_free_pages(&chip->posbuf);
1630 pci_release_regions(chip->pci);
1631 pci_disable_device(chip->pci);
1632 kfree(chip->azx_dev);
1638 static int azx_dev_free(struct snd_device *device)
1640 return azx_free(device->device_data);
1644 * white/black-listing for position_fix
1646 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1647 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1648 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1652 static int __devinit check_position_fix(struct azx *chip, int fix)
1654 const struct snd_pci_quirk *q;
1656 if (fix == POS_FIX_AUTO) {
1657 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1660 "hda_intel: position_fix set to %d "
1661 "for device %04x:%04x\n",
1662 q->value, q->subvendor, q->subdevice);
1670 * black-lists for probe_mask
1672 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1673 /* Thinkpad often breaks the controller communication when accessing
1674 * to the non-working (or non-existing) modem codec slot.
1676 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1677 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1678 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1682 static void __devinit check_probe_mask(struct azx *chip)
1684 const struct snd_pci_quirk *q;
1686 if (probe_mask == -1) {
1687 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1690 "hda_intel: probe_mask set to 0x%x "
1691 "for device %04x:%04x\n",
1692 q->value, q->subvendor, q->subdevice);
1693 probe_mask = q->value;
1702 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1708 static struct snd_device_ops ops = {
1709 .dev_free = azx_dev_free,
1714 err = pci_enable_device(pci);
1718 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1720 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1721 pci_disable_device(pci);
1725 spin_lock_init(&chip->reg_lock);
1726 mutex_init(&chip->open_mutex);
1730 chip->driver_type = driver_type;
1731 chip->msi = enable_msi;
1733 chip->position_fix = check_position_fix(chip, position_fix);
1734 check_probe_mask(chip);
1736 chip->single_cmd = single_cmd;
1738 #if BITS_PER_LONG != 64
1739 /* Fix up base address on ULI M5461 */
1740 if (chip->driver_type == AZX_DRIVER_ULI) {
1742 pci_read_config_word(pci, 0x40, &tmp3);
1743 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1744 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1748 err = pci_request_regions(pci, "ICH HD audio");
1751 pci_disable_device(pci);
1755 chip->addr = pci_resource_start(pci, 0);
1756 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1757 if (chip->remap_addr == NULL) {
1758 snd_printk(KERN_ERR SFX "ioremap error\n");
1764 if (pci_enable_msi(pci) < 0)
1767 if (azx_acquire_irq(chip, 0) < 0) {
1772 pci_set_master(pci);
1773 synchronize_irq(chip->irq);
1775 switch (chip->driver_type) {
1776 case AZX_DRIVER_ULI:
1777 chip->playback_streams = ULI_NUM_PLAYBACK;
1778 chip->capture_streams = ULI_NUM_CAPTURE;
1779 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1780 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1782 case AZX_DRIVER_ATIHDMI:
1783 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1784 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1785 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1786 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1789 chip->playback_streams = ICH6_NUM_PLAYBACK;
1790 chip->capture_streams = ICH6_NUM_CAPTURE;
1791 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1792 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1795 chip->num_streams = chip->playback_streams + chip->capture_streams;
1796 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1798 if (!chip->azx_dev) {
1799 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1803 /* allocate memory for the BDL for each stream */
1804 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1805 snd_dma_pci_data(chip->pci),
1806 BDL_SIZE, &chip->bdl);
1808 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1811 /* allocate memory for the position buffer */
1812 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1813 snd_dma_pci_data(chip->pci),
1814 chip->num_streams * 8, &chip->posbuf);
1816 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1819 /* allocate CORB/RIRB */
1820 if (!chip->single_cmd) {
1821 err = azx_alloc_cmd_io(chip);
1826 /* initialize streams */
1827 azx_init_stream(chip);
1829 /* initialize chip */
1831 azx_init_chip(chip);
1833 /* codec detection */
1834 if (!chip->codec_mask) {
1835 snd_printk(KERN_ERR SFX "no codecs found!\n");
1840 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1842 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1846 strcpy(card->driver, "HDA-Intel");
1847 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1848 sprintf(card->longname, "%s at 0x%lx irq %i",
1849 card->shortname, chip->addr, chip->irq);
1859 static void power_down_all_codecs(struct azx *chip)
1861 #ifdef CONFIG_SND_HDA_POWER_SAVE
1862 /* The codecs were powered up in snd_hda_codec_new().
1863 * Now all initialization done, so turn them down if possible
1865 struct hda_codec *codec;
1866 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1867 snd_hda_power_down(codec);
1872 static int __devinit azx_probe(struct pci_dev *pci,
1873 const struct pci_device_id *pci_id)
1875 struct snd_card *card;
1879 card = snd_card_new(index, id, THIS_MODULE, 0);
1881 snd_printk(KERN_ERR SFX "Error creating card!\n");
1885 err = azx_create(card, pci, pci_id->driver_data, &chip);
1887 snd_card_free(card);
1890 card->private_data = chip;
1892 /* create codec instances */
1893 err = azx_codec_create(chip, model);
1895 snd_card_free(card);
1899 /* create PCM streams */
1900 err = azx_pcm_create(chip);
1902 snd_card_free(card);
1906 /* create mixer controls */
1907 err = azx_mixer_create(chip);
1909 snd_card_free(card);
1913 snd_card_set_dev(card, &pci->dev);
1915 err = snd_card_register(card);
1917 snd_card_free(card);
1921 pci_set_drvdata(pci, card);
1923 power_down_all_codecs(chip);
1928 static void __devexit azx_remove(struct pci_dev *pci)
1930 snd_card_free(pci_get_drvdata(pci));
1931 pci_set_drvdata(pci, NULL);
1935 static struct pci_device_id azx_ids[] = {
1936 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1937 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1938 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
1939 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
1940 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1941 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1942 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1943 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
1944 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
1945 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
1946 { 0x1002, 0x960c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
1947 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
1948 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1949 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1950 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
1951 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
1952 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
1953 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1954 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1955 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1956 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1957 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1958 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1959 { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
1960 { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
1961 { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1962 { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1963 { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1964 { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1967 MODULE_DEVICE_TABLE(pci, azx_ids);
1969 /* pci_driver definition */
1970 static struct pci_driver driver = {
1971 .name = "HDA Intel",
1972 .id_table = azx_ids,
1974 .remove = __devexit_p(azx_remove),
1976 .suspend = azx_suspend,
1977 .resume = azx_resume,
1981 static int __init alsa_card_azx_init(void)
1983 return pci_register_driver(&driver);
1986 static void __exit alsa_card_azx_exit(void)
1988 pci_unregister_driver(&driver);
1991 module_init(alsa_card_azx_init)
1992 module_exit(alsa_card_azx_exit)