3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi = -1;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
72 module_param_array(index, int, NULL, 0444);
73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
74 module_param_array(id, charp, NULL, 0444);
75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
76 module_param_array(enable, bool, NULL, 0444);
77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78 module_param_array(model, charp, NULL, 0444);
79 MODULE_PARM_DESC(model, "Use the given board model.");
80 module_param_array(position_fix, int, NULL, 0444);
81 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
82 "(0 = auto, 1 = none, 2 = POSBUF).");
83 module_param_array(bdl_pos_adj, int, NULL, 0644);
84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
85 module_param_array(probe_mask, int, NULL, 0444);
86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
87 module_param_array(probe_only, bool, NULL, 0444);
88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
89 module_param(single_cmd, bool, 0444);
90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
92 module_param(enable_msi, int, 0444);
93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
95 module_param_array(patch, charp, NULL, 0444);
96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
99 module_param_array(beep_mode, int, NULL, 0444);
100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
104 #ifdef CONFIG_SND_HDA_POWER_SAVE
105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106 module_param(power_save, int, 0644);
107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
110 /* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
114 static int power_save_controller = 1;
115 module_param(power_save_controller, bool, 0644);
116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
146 MODULE_DESCRIPTION("Intel HDA driver");
148 #ifdef CONFIG_SND_VERBOSE_PRINTK
149 #define SFX /* nop */
151 #define SFX "hda-intel: "
157 #define ICH6_REG_GCAP 0x00
158 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
159 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
160 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
161 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
162 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
163 #define ICH6_REG_VMIN 0x02
164 #define ICH6_REG_VMAJ 0x03
165 #define ICH6_REG_OUTPAY 0x04
166 #define ICH6_REG_INPAY 0x06
167 #define ICH6_REG_GCTL 0x08
168 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
169 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
170 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
171 #define ICH6_REG_WAKEEN 0x0c
172 #define ICH6_REG_STATESTS 0x0e
173 #define ICH6_REG_GSTS 0x10
174 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
175 #define ICH6_REG_INTCTL 0x20
176 #define ICH6_REG_INTSTS 0x24
177 #define ICH6_REG_WALCLK 0x30
178 #define ICH6_REG_SYNC 0x34
179 #define ICH6_REG_CORBLBASE 0x40
180 #define ICH6_REG_CORBUBASE 0x44
181 #define ICH6_REG_CORBWP 0x48
182 #define ICH6_REG_CORBRP 0x4a
183 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
184 #define ICH6_REG_CORBCTL 0x4c
185 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
186 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
187 #define ICH6_REG_CORBSTS 0x4d
188 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
189 #define ICH6_REG_CORBSIZE 0x4e
191 #define ICH6_REG_RIRBLBASE 0x50
192 #define ICH6_REG_RIRBUBASE 0x54
193 #define ICH6_REG_RIRBWP 0x58
194 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
195 #define ICH6_REG_RINTCNT 0x5a
196 #define ICH6_REG_RIRBCTL 0x5c
197 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
198 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
199 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
200 #define ICH6_REG_RIRBSTS 0x5d
201 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
202 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
203 #define ICH6_REG_RIRBSIZE 0x5e
205 #define ICH6_REG_IC 0x60
206 #define ICH6_REG_IR 0x64
207 #define ICH6_REG_IRS 0x68
208 #define ICH6_IRS_VALID (1<<1)
209 #define ICH6_IRS_BUSY (1<<0)
211 #define ICH6_REG_DPLBASE 0x70
212 #define ICH6_REG_DPUBASE 0x74
213 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
215 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
216 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
218 /* stream register offsets from stream base */
219 #define ICH6_REG_SD_CTL 0x00
220 #define ICH6_REG_SD_STS 0x03
221 #define ICH6_REG_SD_LPIB 0x04
222 #define ICH6_REG_SD_CBL 0x08
223 #define ICH6_REG_SD_LVI 0x0c
224 #define ICH6_REG_SD_FIFOW 0x0e
225 #define ICH6_REG_SD_FIFOSIZE 0x10
226 #define ICH6_REG_SD_FORMAT 0x12
227 #define ICH6_REG_SD_BDLPL 0x18
228 #define ICH6_REG_SD_BDLPU 0x1c
231 #define ICH6_PCIREG_TCSEL 0x44
237 /* max number of SDs */
238 /* ICH, ATI and VIA have 4 playback and 4 capture */
239 #define ICH6_NUM_CAPTURE 4
240 #define ICH6_NUM_PLAYBACK 4
242 /* ULI has 6 playback and 5 capture */
243 #define ULI_NUM_CAPTURE 5
244 #define ULI_NUM_PLAYBACK 6
246 /* ATI HDMI has 1 playback and 0 capture */
247 #define ATIHDMI_NUM_CAPTURE 0
248 #define ATIHDMI_NUM_PLAYBACK 1
250 /* TERA has 4 playback and 3 capture */
251 #define TERA_NUM_CAPTURE 3
252 #define TERA_NUM_PLAYBACK 4
254 /* this number is statically defined for simplicity */
255 #define MAX_AZX_DEV 16
257 /* max number of fragments - we may use more if allocating more pages for BDL */
258 #define BDL_SIZE 4096
259 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
260 #define AZX_MAX_FRAG 32
261 /* max buffer size - no h/w limit, you can increase as you like */
262 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
263 /* max number of PCM devics per card */
264 #define AZX_MAX_PCMS 8
266 /* RIRB int mask: overrun[2], response[0] */
267 #define RIRB_INT_RESPONSE 0x01
268 #define RIRB_INT_OVERRUN 0x04
269 #define RIRB_INT_MASK 0x05
271 /* STATESTS int mask: S3,SD2,SD1,SD0 */
272 #define AZX_MAX_CODECS 4
273 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
276 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
277 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
278 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
279 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
280 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
281 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
282 #define SD_CTL_STREAM_TAG_SHIFT 20
284 /* SD_CTL and SD_STS */
285 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
286 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
287 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
288 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
292 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
294 /* INTCTL and INTSTS */
295 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
296 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
297 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
299 /* below are so far hardcoded - should read registers in future */
300 #define ICH6_MAX_CORB_ENTRIES 256
301 #define ICH6_MAX_RIRB_ENTRIES 256
303 /* position fix mode */
310 /* Defines for ATI HD Audio support in SB450 south bridge */
311 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
312 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
314 /* Defines for Nvidia HDA support */
315 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
316 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
317 #define NVIDIA_HDA_ISTRM_COH 0x4d
318 #define NVIDIA_HDA_OSTRM_COH 0x4c
319 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
321 /* Defines for Intel SCH HDA snoop control */
322 #define INTEL_SCH_HDA_DEVC 0x78
323 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
325 /* Define IN stream 0 FIFO size offset in VIA controller */
326 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
327 /* Define VIA HD Audio Device ID*/
328 #define VIA_HDAC_DEVICE_ID 0x3288
330 /* HD Audio class code */
331 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
337 struct snd_dma_buffer bdl; /* BDL buffer */
338 u32 *posbuf; /* position buffer pointer */
340 unsigned int bufsize; /* size of the play buffer in bytes */
341 unsigned int period_bytes; /* size of the period in bytes */
342 unsigned int frags; /* number for period in the play buffer */
343 unsigned int fifo_size; /* FIFO size */
344 unsigned long start_jiffies; /* start + minimum jiffies */
345 unsigned long min_jiffies; /* minimum jiffies before position is valid */
347 void __iomem *sd_addr; /* stream descriptor pointer */
349 u32 sd_int_sta_mask; /* stream int status mask */
352 struct snd_pcm_substream *substream; /* assigned substream,
355 unsigned int format_val; /* format value to be set in the
356 * controller and the codec
358 unsigned char stream_tag; /* assigned stream */
359 unsigned char index; /* stream index */
360 int device; /* last device number assigned to */
362 unsigned int opened :1;
363 unsigned int running :1;
364 unsigned int irq_pending :1;
365 unsigned int start_flag: 1; /* stream full start flag */
368 * A flag to ensure DMA position is 0
369 * when link position is not greater than FIFO size
371 unsigned int insufficient :1;
376 u32 *buf; /* CORB/RIRB buffer
377 * Each CORB entry is 4byte, RIRB is 8byte
379 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
381 unsigned short rp, wp; /* read/write pointers */
382 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
383 u32 res[AZX_MAX_CODECS]; /* last read value */
387 struct snd_card *card;
391 /* chip type specific */
393 int playback_streams;
394 int playback_index_offset;
396 int capture_index_offset;
401 void __iomem *remap_addr;
406 struct mutex open_mutex;
408 /* streams (x num_streams) */
409 struct azx_dev *azx_dev;
412 struct snd_pcm *pcm[AZX_MAX_PCMS];
415 unsigned short codec_mask;
416 int codec_probe_mask; /* copied from probe_mask option */
418 unsigned int beep_mode;
424 /* CORB/RIRB and position buffers */
425 struct snd_dma_buffer rb;
426 struct snd_dma_buffer posbuf;
431 unsigned int running :1;
432 unsigned int initialized :1;
433 unsigned int single_cmd :1;
434 unsigned int polling_mode :1;
436 unsigned int irq_pending_warned :1;
437 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
438 unsigned int probing :1; /* codec probing phase */
441 unsigned int last_cmd[AZX_MAX_CODECS];
443 /* for pending irqs */
444 struct work_struct irq_pending_work;
446 /* reboot notifier (for mysterious hangup problem at power-down) */
447 struct notifier_block reboot_notifier;
463 AZX_NUM_DRIVERS, /* keep this as last entry */
466 static char *driver_short_names[] __devinitdata = {
467 [AZX_DRIVER_ICH] = "HDA Intel",
468 [AZX_DRIVER_PCH] = "HDA Intel PCH",
469 [AZX_DRIVER_SCH] = "HDA Intel MID",
470 [AZX_DRIVER_ATI] = "HDA ATI SB",
471 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
472 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
473 [AZX_DRIVER_SIS] = "HDA SIS966",
474 [AZX_DRIVER_ULI] = "HDA ULI M5461",
475 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
476 [AZX_DRIVER_TERA] = "HDA Teradici",
477 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
481 * macros for easy use
483 #define azx_writel(chip,reg,value) \
484 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
485 #define azx_readl(chip,reg) \
486 readl((chip)->remap_addr + ICH6_REG_##reg)
487 #define azx_writew(chip,reg,value) \
488 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
489 #define azx_readw(chip,reg) \
490 readw((chip)->remap_addr + ICH6_REG_##reg)
491 #define azx_writeb(chip,reg,value) \
492 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
493 #define azx_readb(chip,reg) \
494 readb((chip)->remap_addr + ICH6_REG_##reg)
496 #define azx_sd_writel(dev,reg,value) \
497 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
498 #define azx_sd_readl(dev,reg) \
499 readl((dev)->sd_addr + ICH6_REG_##reg)
500 #define azx_sd_writew(dev,reg,value) \
501 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
502 #define azx_sd_readw(dev,reg) \
503 readw((dev)->sd_addr + ICH6_REG_##reg)
504 #define azx_sd_writeb(dev,reg,value) \
505 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
506 #define azx_sd_readb(dev,reg) \
507 readb((dev)->sd_addr + ICH6_REG_##reg)
509 /* for pcm support */
510 #define get_azx_dev(substream) (substream->runtime->private_data)
512 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
513 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
515 * Interface for HD codec
519 * CORB / RIRB interface
521 static int azx_alloc_cmd_io(struct azx *chip)
525 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
526 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
527 snd_dma_pci_data(chip->pci),
528 PAGE_SIZE, &chip->rb);
530 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
536 static void azx_init_cmd_io(struct azx *chip)
538 spin_lock_irq(&chip->reg_lock);
540 chip->corb.addr = chip->rb.addr;
541 chip->corb.buf = (u32 *)chip->rb.area;
542 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
543 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
545 /* set the corb size to 256 entries (ULI requires explicitly) */
546 azx_writeb(chip, CORBSIZE, 0x02);
547 /* set the corb write pointer to 0 */
548 azx_writew(chip, CORBWP, 0);
549 /* reset the corb hw read pointer */
550 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
551 /* enable corb dma */
552 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
555 chip->rirb.addr = chip->rb.addr + 2048;
556 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
557 chip->rirb.wp = chip->rirb.rp = 0;
558 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
559 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
560 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
562 /* set the rirb size to 256 entries (ULI requires explicitly) */
563 azx_writeb(chip, RIRBSIZE, 0x02);
564 /* reset the rirb hw write pointer */
565 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
566 /* set N=1, get RIRB response interrupt for new entry */
567 azx_writew(chip, RINTCNT, 1);
568 /* enable rirb dma and response irq */
569 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
570 spin_unlock_irq(&chip->reg_lock);
573 static void azx_free_cmd_io(struct azx *chip)
575 spin_lock_irq(&chip->reg_lock);
576 /* disable ringbuffer DMAs */
577 azx_writeb(chip, RIRBCTL, 0);
578 azx_writeb(chip, CORBCTL, 0);
579 spin_unlock_irq(&chip->reg_lock);
582 static unsigned int azx_command_addr(u32 cmd)
584 unsigned int addr = cmd >> 28;
586 if (addr >= AZX_MAX_CODECS) {
594 static unsigned int azx_response_addr(u32 res)
596 unsigned int addr = res & 0xf;
598 if (addr >= AZX_MAX_CODECS) {
607 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
609 struct azx *chip = bus->private_data;
610 unsigned int addr = azx_command_addr(val);
613 spin_lock_irq(&chip->reg_lock);
615 /* add command to corb */
616 wp = azx_readb(chip, CORBWP);
618 wp %= ICH6_MAX_CORB_ENTRIES;
620 chip->rirb.cmds[addr]++;
621 chip->corb.buf[wp] = cpu_to_le32(val);
622 azx_writel(chip, CORBWP, wp);
624 spin_unlock_irq(&chip->reg_lock);
629 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
631 /* retrieve RIRB entry - called from interrupt handler */
632 static void azx_update_rirb(struct azx *chip)
638 wp = azx_readb(chip, RIRBWP);
639 if (wp == chip->rirb.wp)
643 while (chip->rirb.rp != wp) {
645 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
647 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
648 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
649 res = le32_to_cpu(chip->rirb.buf[rp]);
650 addr = azx_response_addr(res_ex);
651 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
652 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
653 else if (chip->rirb.cmds[addr]) {
654 chip->rirb.res[addr] = res;
656 chip->rirb.cmds[addr]--;
658 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
661 chip->last_cmd[addr]);
665 /* receive a response */
666 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
669 struct azx *chip = bus->private_data;
670 unsigned long timeout;
674 timeout = jiffies + msecs_to_jiffies(1000);
676 if (chip->polling_mode || do_poll) {
677 spin_lock_irq(&chip->reg_lock);
678 azx_update_rirb(chip);
679 spin_unlock_irq(&chip->reg_lock);
681 if (!chip->rirb.cmds[addr]) {
686 chip->poll_count = 0;
687 return chip->rirb.res[addr]; /* the last value */
689 if (time_after(jiffies, timeout))
691 if (bus->needs_damn_long_delay)
692 msleep(2); /* temporary workaround */
699 if (!chip->polling_mode && chip->poll_count < 2) {
700 snd_printdd(SFX "azx_get_response timeout, "
701 "polling the codec once: last cmd=0x%08x\n",
702 chip->last_cmd[addr]);
709 if (!chip->polling_mode) {
710 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
711 "switching to polling mode: last cmd=0x%08x\n",
712 chip->last_cmd[addr]);
713 chip->polling_mode = 1;
718 snd_printk(KERN_WARNING SFX "No response from codec, "
719 "disabling MSI: last cmd=0x%08x\n",
720 chip->last_cmd[addr]);
721 free_irq(chip->irq, chip);
723 pci_disable_msi(chip->pci);
725 if (azx_acquire_irq(chip, 1) < 0) {
733 /* If this critical timeout happens during the codec probing
734 * phase, this is likely an access to a non-existing codec
735 * slot. Better to return an error and reset the system.
740 /* a fatal communication error; need either to reset or to fallback
741 * to the single_cmd mode
744 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
745 bus->response_reset = 1;
746 return -1; /* give a chance to retry */
749 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
750 "switching to single_cmd mode: last cmd=0x%08x\n",
751 chip->last_cmd[addr]);
752 chip->single_cmd = 1;
753 bus->response_reset = 0;
754 /* release CORB/RIRB */
755 azx_free_cmd_io(chip);
756 /* disable unsolicited responses */
757 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
762 * Use the single immediate command instead of CORB/RIRB for simplicity
764 * Note: according to Intel, this is not preferred use. The command was
765 * intended for the BIOS only, and may get confused with unsolicited
766 * responses. So, we shouldn't use it for normal operation from the
768 * I left the codes, however, for debugging/testing purposes.
771 /* receive a response */
772 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
777 /* check IRV busy bit */
778 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
779 /* reuse rirb.res as the response return value */
780 chip->rirb.res[addr] = azx_readl(chip, IR);
785 if (printk_ratelimit())
786 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
787 azx_readw(chip, IRS));
788 chip->rirb.res[addr] = -1;
793 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
795 struct azx *chip = bus->private_data;
796 unsigned int addr = azx_command_addr(val);
801 /* check ICB busy bit */
802 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
803 /* Clear IRV valid bit */
804 azx_writew(chip, IRS, azx_readw(chip, IRS) |
806 azx_writel(chip, IC, val);
807 azx_writew(chip, IRS, azx_readw(chip, IRS) |
809 return azx_single_wait_for_response(chip, addr);
813 if (printk_ratelimit())
814 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
815 azx_readw(chip, IRS), val);
819 /* receive a response */
820 static unsigned int azx_single_get_response(struct hda_bus *bus,
823 struct azx *chip = bus->private_data;
824 return chip->rirb.res[addr];
828 * The below are the main callbacks from hda_codec.
830 * They are just the skeleton to call sub-callbacks according to the
831 * current setting of chip->single_cmd.
835 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
837 struct azx *chip = bus->private_data;
839 chip->last_cmd[azx_command_addr(val)] = val;
840 if (chip->single_cmd)
841 return azx_single_send_cmd(bus, val);
843 return azx_corb_send_cmd(bus, val);
847 static unsigned int azx_get_response(struct hda_bus *bus,
850 struct azx *chip = bus->private_data;
851 if (chip->single_cmd)
852 return azx_single_get_response(bus, addr);
854 return azx_rirb_get_response(bus, addr);
857 #ifdef CONFIG_SND_HDA_POWER_SAVE
858 static void azx_power_notify(struct hda_bus *bus);
861 /* reset codec link */
862 static int azx_reset(struct azx *chip)
867 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
869 /* reset controller */
870 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
873 while (azx_readb(chip, GCTL) && --count)
876 /* delay for >= 100us for codec PLL to settle per spec
877 * Rev 0.9 section 5.5.1
881 /* Bring controller out of reset */
882 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
885 while (!azx_readb(chip, GCTL) && --count)
888 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
891 /* check to see if controller is ready */
892 if (!azx_readb(chip, GCTL)) {
893 snd_printd(SFX "azx_reset: controller not ready!\n");
897 /* Accept unsolicited responses */
898 if (!chip->single_cmd)
899 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
903 if (!chip->codec_mask) {
904 chip->codec_mask = azx_readw(chip, STATESTS);
905 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
916 /* enable interrupts */
917 static void azx_int_enable(struct azx *chip)
919 /* enable controller CIE and GIE */
920 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
921 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
924 /* disable interrupts */
925 static void azx_int_disable(struct azx *chip)
929 /* disable interrupts in stream descriptor */
930 for (i = 0; i < chip->num_streams; i++) {
931 struct azx_dev *azx_dev = &chip->azx_dev[i];
932 azx_sd_writeb(azx_dev, SD_CTL,
933 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
936 /* disable SIE for all streams */
937 azx_writeb(chip, INTCTL, 0);
939 /* disable controller CIE and GIE */
940 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
941 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
944 /* clear interrupts */
945 static void azx_int_clear(struct azx *chip)
949 /* clear stream status */
950 for (i = 0; i < chip->num_streams; i++) {
951 struct azx_dev *azx_dev = &chip->azx_dev[i];
952 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
956 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
958 /* clear rirb status */
959 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
961 /* clear int status */
962 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
966 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
969 * Before stream start, initialize parameter
971 azx_dev->insufficient = 1;
974 azx_writeb(chip, INTCTL,
975 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
976 /* set DMA start and interrupt mask */
977 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
978 SD_CTL_DMA_START | SD_INT_MASK);
982 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
984 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
985 ~(SD_CTL_DMA_START | SD_INT_MASK));
986 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
990 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
992 azx_stream_clear(chip, azx_dev);
994 azx_writeb(chip, INTCTL,
995 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
1000 * reset and start the controller registers
1002 static void azx_init_chip(struct azx *chip)
1004 if (chip->initialized)
1007 /* reset controller */
1010 /* initialize interrupts */
1011 azx_int_clear(chip);
1012 azx_int_enable(chip);
1014 /* initialize the codec command I/O */
1015 if (!chip->single_cmd)
1016 azx_init_cmd_io(chip);
1018 /* program the position buffer */
1019 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1020 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1022 chip->initialized = 1;
1026 * initialize the PCI registers
1028 /* update bits in a PCI register byte */
1029 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1030 unsigned char mask, unsigned char val)
1034 pci_read_config_byte(pci, reg, &data);
1036 data |= (val & mask);
1037 pci_write_config_byte(pci, reg, data);
1040 static void azx_init_pci(struct azx *chip)
1042 unsigned short snoop;
1044 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1045 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1046 * Ensuring these bits are 0 clears playback static on some HD Audio
1049 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1051 switch (chip->driver_type) {
1052 case AZX_DRIVER_ATI:
1053 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1054 update_pci_byte(chip->pci,
1055 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1056 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1058 case AZX_DRIVER_NVIDIA:
1059 /* For NVIDIA HDA, enable snoop */
1060 update_pci_byte(chip->pci,
1061 NVIDIA_HDA_TRANSREG_ADDR,
1062 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1063 update_pci_byte(chip->pci,
1064 NVIDIA_HDA_ISTRM_COH,
1065 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1066 update_pci_byte(chip->pci,
1067 NVIDIA_HDA_OSTRM_COH,
1068 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1070 case AZX_DRIVER_SCH:
1071 case AZX_DRIVER_PCH:
1072 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1073 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1074 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1075 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1076 pci_read_config_word(chip->pci,
1077 INTEL_SCH_HDA_DEVC, &snoop);
1078 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1079 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1088 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1093 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1095 struct azx *chip = dev_id;
1096 struct azx_dev *azx_dev;
1100 spin_lock(&chip->reg_lock);
1102 status = azx_readl(chip, INTSTS);
1104 spin_unlock(&chip->reg_lock);
1108 for (i = 0; i < chip->num_streams; i++) {
1109 azx_dev = &chip->azx_dev[i];
1110 if (status & azx_dev->sd_int_sta_mask) {
1111 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1112 if (!azx_dev->substream || !azx_dev->running)
1114 /* check whether this IRQ is really acceptable */
1115 ok = azx_position_ok(chip, azx_dev);
1117 azx_dev->irq_pending = 0;
1118 spin_unlock(&chip->reg_lock);
1119 snd_pcm_period_elapsed(azx_dev->substream);
1120 spin_lock(&chip->reg_lock);
1121 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1122 /* bogus IRQ, process it later */
1123 azx_dev->irq_pending = 1;
1124 queue_work(chip->bus->workq,
1125 &chip->irq_pending_work);
1130 /* clear rirb int */
1131 status = azx_readb(chip, RIRBSTS);
1132 if (status & RIRB_INT_MASK) {
1133 if (status & RIRB_INT_RESPONSE)
1134 azx_update_rirb(chip);
1135 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1139 /* clear state status int */
1140 if (azx_readb(chip, STATESTS) & 0x04)
1141 azx_writeb(chip, STATESTS, 0x04);
1143 spin_unlock(&chip->reg_lock);
1150 * set up a BDL entry
1152 static int setup_bdle(struct snd_pcm_substream *substream,
1153 struct azx_dev *azx_dev, u32 **bdlp,
1154 int ofs, int size, int with_ioc)
1162 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1165 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1166 /* program the address field of the BDL entry */
1167 bdl[0] = cpu_to_le32((u32)addr);
1168 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1169 /* program the size field of the BDL entry */
1170 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1171 bdl[2] = cpu_to_le32(chunk);
1172 /* program the IOC to enable interrupt
1173 * only when the whole fragment is processed
1176 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1186 * set up BDL entries
1188 static int azx_setup_periods(struct azx *chip,
1189 struct snd_pcm_substream *substream,
1190 struct azx_dev *azx_dev)
1193 int i, ofs, periods, period_bytes;
1196 /* reset BDL address */
1197 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1198 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1200 period_bytes = azx_dev->period_bytes;
1201 periods = azx_dev->bufsize / period_bytes;
1203 /* program the initial BDL entries */
1204 bdl = (u32 *)azx_dev->bdl.area;
1207 pos_adj = bdl_pos_adj[chip->dev_index];
1209 struct snd_pcm_runtime *runtime = substream->runtime;
1210 int pos_align = pos_adj;
1211 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1213 pos_adj = pos_align;
1215 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1217 pos_adj = frames_to_bytes(runtime, pos_adj);
1218 if (pos_adj >= period_bytes) {
1219 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1220 bdl_pos_adj[chip->dev_index]);
1223 ofs = setup_bdle(substream, azx_dev,
1224 &bdl, ofs, pos_adj, 1);
1230 for (i = 0; i < periods; i++) {
1231 if (i == periods - 1 && pos_adj)
1232 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1233 period_bytes - pos_adj, 0);
1235 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1243 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1244 azx_dev->bufsize, period_bytes);
1249 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1254 azx_stream_clear(chip, azx_dev);
1256 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1257 SD_CTL_STREAM_RESET);
1260 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1263 val &= ~SD_CTL_STREAM_RESET;
1264 azx_sd_writeb(azx_dev, SD_CTL, val);
1268 /* waiting for hardware to report that the stream is out of reset */
1269 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1273 /* reset first position - may not be synced with hw at this time */
1274 *azx_dev->posbuf = 0;
1278 * set up the SD for streaming
1280 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1282 /* make sure the run bit is zero for SD */
1283 azx_stream_clear(chip, azx_dev);
1284 /* program the stream_tag */
1285 azx_sd_writel(azx_dev, SD_CTL,
1286 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1287 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1289 /* program the length of samples in cyclic buffer */
1290 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1292 /* program the stream format */
1293 /* this value needs to be the same as the one programmed */
1294 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1296 /* program the stream LVI (last valid index) of the BDL */
1297 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1299 /* program the BDL address */
1300 /* lower BDL address */
1301 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1302 /* upper BDL address */
1303 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1305 /* enable the position buffer */
1306 if (chip->position_fix == POS_FIX_POSBUF ||
1307 chip->position_fix == POS_FIX_AUTO ||
1308 chip->via_dmapos_patch) {
1309 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1310 azx_writel(chip, DPLBASE,
1311 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1314 /* set the interrupt enable bits in the descriptor control register */
1315 azx_sd_writel(azx_dev, SD_CTL,
1316 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1322 * Probe the given codec address
1324 static int probe_codec(struct azx *chip, int addr)
1326 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1327 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1330 mutex_lock(&chip->bus->cmd_mutex);
1332 azx_send_cmd(chip->bus, cmd);
1333 res = azx_get_response(chip->bus, addr);
1335 mutex_unlock(&chip->bus->cmd_mutex);
1338 snd_printdd(SFX "codec #%d probed OK\n", addr);
1342 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1343 struct hda_pcm *cpcm);
1344 static void azx_stop_chip(struct azx *chip);
1346 static void azx_bus_reset(struct hda_bus *bus)
1348 struct azx *chip = bus->private_data;
1351 azx_stop_chip(chip);
1352 azx_init_chip(chip);
1354 if (chip->initialized) {
1357 for (i = 0; i < AZX_MAX_PCMS; i++)
1358 snd_pcm_suspend_all(chip->pcm[i]);
1359 snd_hda_suspend(chip->bus);
1360 snd_hda_resume(chip->bus);
1367 * Codec initialization
1370 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1371 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1372 [AZX_DRIVER_TERA] = 1,
1375 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1377 struct hda_bus_template bus_temp;
1381 memset(&bus_temp, 0, sizeof(bus_temp));
1382 bus_temp.private_data = chip;
1383 bus_temp.modelname = model;
1384 bus_temp.pci = chip->pci;
1385 bus_temp.ops.command = azx_send_cmd;
1386 bus_temp.ops.get_response = azx_get_response;
1387 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1388 bus_temp.ops.bus_reset = azx_bus_reset;
1389 #ifdef CONFIG_SND_HDA_POWER_SAVE
1390 bus_temp.power_save = &power_save;
1391 bus_temp.ops.pm_notify = azx_power_notify;
1394 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1398 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1399 chip->bus->needs_damn_long_delay = 1;
1402 max_slots = azx_max_codecs[chip->driver_type];
1404 max_slots = AZX_MAX_CODECS;
1406 /* First try to probe all given codec slots */
1407 for (c = 0; c < max_slots; c++) {
1408 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1409 if (probe_codec(chip, c) < 0) {
1410 /* Some BIOSen give you wrong codec addresses
1413 snd_printk(KERN_WARNING SFX
1414 "Codec #%d probe error; "
1415 "disabling it...\n", c);
1416 chip->codec_mask &= ~(1 << c);
1417 /* More badly, accessing to a non-existing
1418 * codec often screws up the controller chip,
1419 * and distrubs the further communications.
1420 * Thus if an error occurs during probing,
1421 * better to reset the controller chip to
1422 * get back to the sanity state.
1424 azx_stop_chip(chip);
1425 azx_init_chip(chip);
1430 /* Then create codec instances */
1431 for (c = 0; c < max_slots; c++) {
1432 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1433 struct hda_codec *codec;
1434 err = snd_hda_codec_new(chip->bus, c, &codec);
1437 codec->beep_mode = chip->beep_mode;
1442 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1448 /* configure each codec instance */
1449 static int __devinit azx_codec_configure(struct azx *chip)
1451 struct hda_codec *codec;
1452 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1453 snd_hda_codec_configure(codec);
1463 /* assign a stream for the PCM */
1464 static inline struct azx_dev *
1465 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1468 struct azx_dev *res = NULL;
1470 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1471 dev = chip->playback_index_offset;
1472 nums = chip->playback_streams;
1474 dev = chip->capture_index_offset;
1475 nums = chip->capture_streams;
1477 for (i = 0; i < nums; i++, dev++)
1478 if (!chip->azx_dev[dev].opened) {
1479 res = &chip->azx_dev[dev];
1480 if (res->device == substream->pcm->device)
1485 res->device = substream->pcm->device;
1490 /* release the assigned stream */
1491 static inline void azx_release_device(struct azx_dev *azx_dev)
1493 azx_dev->opened = 0;
1496 static struct snd_pcm_hardware azx_pcm_hw = {
1497 .info = (SNDRV_PCM_INFO_MMAP |
1498 SNDRV_PCM_INFO_INTERLEAVED |
1499 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1500 SNDRV_PCM_INFO_MMAP_VALID |
1501 /* No full-resume yet implemented */
1502 /* SNDRV_PCM_INFO_RESUME |*/
1503 SNDRV_PCM_INFO_PAUSE |
1504 SNDRV_PCM_INFO_SYNC_START),
1505 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1506 .rates = SNDRV_PCM_RATE_48000,
1511 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1512 .period_bytes_min = 128,
1513 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1515 .periods_max = AZX_MAX_FRAG,
1521 struct hda_codec *codec;
1522 struct hda_pcm_stream *hinfo[2];
1525 static int azx_pcm_open(struct snd_pcm_substream *substream)
1527 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1528 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1529 struct azx *chip = apcm->chip;
1530 struct azx_dev *azx_dev;
1531 struct snd_pcm_runtime *runtime = substream->runtime;
1532 unsigned long flags;
1535 mutex_lock(&chip->open_mutex);
1536 azx_dev = azx_assign_device(chip, substream);
1537 if (azx_dev == NULL) {
1538 mutex_unlock(&chip->open_mutex);
1541 runtime->hw = azx_pcm_hw;
1542 runtime->hw.channels_min = hinfo->channels_min;
1543 runtime->hw.channels_max = hinfo->channels_max;
1544 runtime->hw.formats = hinfo->formats;
1545 runtime->hw.rates = hinfo->rates;
1546 snd_pcm_limit_hw_rates(runtime);
1547 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1548 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1550 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1552 snd_hda_power_up(apcm->codec);
1553 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1555 azx_release_device(azx_dev);
1556 snd_hda_power_down(apcm->codec);
1557 mutex_unlock(&chip->open_mutex);
1560 snd_pcm_limit_hw_rates(runtime);
1562 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1563 snd_BUG_ON(!runtime->hw.channels_max) ||
1564 snd_BUG_ON(!runtime->hw.formats) ||
1565 snd_BUG_ON(!runtime->hw.rates)) {
1566 azx_release_device(azx_dev);
1567 hinfo->ops.close(hinfo, apcm->codec, substream);
1568 snd_hda_power_down(apcm->codec);
1569 mutex_unlock(&chip->open_mutex);
1572 spin_lock_irqsave(&chip->reg_lock, flags);
1573 azx_dev->substream = substream;
1574 azx_dev->running = 0;
1575 spin_unlock_irqrestore(&chip->reg_lock, flags);
1577 runtime->private_data = azx_dev;
1578 snd_pcm_set_sync(substream);
1579 mutex_unlock(&chip->open_mutex);
1583 static int azx_pcm_close(struct snd_pcm_substream *substream)
1585 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1586 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1587 struct azx *chip = apcm->chip;
1588 struct azx_dev *azx_dev = get_azx_dev(substream);
1589 unsigned long flags;
1591 mutex_lock(&chip->open_mutex);
1592 spin_lock_irqsave(&chip->reg_lock, flags);
1593 azx_dev->substream = NULL;
1594 azx_dev->running = 0;
1595 spin_unlock_irqrestore(&chip->reg_lock, flags);
1596 azx_release_device(azx_dev);
1597 hinfo->ops.close(hinfo, apcm->codec, substream);
1598 snd_hda_power_down(apcm->codec);
1599 mutex_unlock(&chip->open_mutex);
1603 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1604 struct snd_pcm_hw_params *hw_params)
1606 struct azx_dev *azx_dev = get_azx_dev(substream);
1608 azx_dev->bufsize = 0;
1609 azx_dev->period_bytes = 0;
1610 azx_dev->format_val = 0;
1611 return snd_pcm_lib_malloc_pages(substream,
1612 params_buffer_bytes(hw_params));
1615 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1617 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1618 struct azx_dev *azx_dev = get_azx_dev(substream);
1619 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1621 /* reset BDL address */
1622 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1623 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1624 azx_sd_writel(azx_dev, SD_CTL, 0);
1625 azx_dev->bufsize = 0;
1626 azx_dev->period_bytes = 0;
1627 azx_dev->format_val = 0;
1629 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1631 return snd_pcm_lib_free_pages(substream);
1634 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1636 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1637 struct azx *chip = apcm->chip;
1638 struct azx_dev *azx_dev = get_azx_dev(substream);
1639 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1640 struct snd_pcm_runtime *runtime = substream->runtime;
1641 unsigned int bufsize, period_bytes, format_val;
1644 azx_stream_reset(chip, azx_dev);
1645 format_val = snd_hda_calc_stream_format(runtime->rate,
1650 snd_printk(KERN_ERR SFX
1651 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1652 runtime->rate, runtime->channels, runtime->format);
1656 bufsize = snd_pcm_lib_buffer_bytes(substream);
1657 period_bytes = snd_pcm_lib_period_bytes(substream);
1659 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1660 bufsize, format_val);
1662 if (bufsize != azx_dev->bufsize ||
1663 period_bytes != azx_dev->period_bytes ||
1664 format_val != azx_dev->format_val) {
1665 azx_dev->bufsize = bufsize;
1666 azx_dev->period_bytes = period_bytes;
1667 azx_dev->format_val = format_val;
1668 err = azx_setup_periods(chip, substream, azx_dev);
1673 azx_dev->min_jiffies = (runtime->period_size * HZ) /
1674 (runtime->rate * 2);
1675 azx_setup_controller(chip, azx_dev);
1676 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1677 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1679 azx_dev->fifo_size = 0;
1681 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1682 azx_dev->format_val, substream);
1685 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1687 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1688 struct azx *chip = apcm->chip;
1689 struct azx_dev *azx_dev;
1690 struct snd_pcm_substream *s;
1691 int rstart = 0, start, nsync = 0, sbits = 0;
1695 case SNDRV_PCM_TRIGGER_START:
1697 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1698 case SNDRV_PCM_TRIGGER_RESUME:
1701 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1702 case SNDRV_PCM_TRIGGER_SUSPEND:
1703 case SNDRV_PCM_TRIGGER_STOP:
1710 snd_pcm_group_for_each_entry(s, substream) {
1711 if (s->pcm->card != substream->pcm->card)
1713 azx_dev = get_azx_dev(s);
1714 sbits |= 1 << azx_dev->index;
1716 snd_pcm_trigger_done(s, substream);
1719 spin_lock(&chip->reg_lock);
1721 /* first, set SYNC bits of corresponding streams */
1722 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1724 snd_pcm_group_for_each_entry(s, substream) {
1725 if (s->pcm->card != substream->pcm->card)
1727 azx_dev = get_azx_dev(s);
1729 azx_dev->start_flag = 1;
1730 azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1733 azx_stream_start(chip, azx_dev);
1735 azx_stream_stop(chip, azx_dev);
1736 azx_dev->running = start;
1738 spin_unlock(&chip->reg_lock);
1742 /* wait until all FIFOs get ready */
1743 for (timeout = 5000; timeout; timeout--) {
1745 snd_pcm_group_for_each_entry(s, substream) {
1746 if (s->pcm->card != substream->pcm->card)
1748 azx_dev = get_azx_dev(s);
1749 if (!(azx_sd_readb(azx_dev, SD_STS) &
1758 /* wait until all RUN bits are cleared */
1759 for (timeout = 5000; timeout; timeout--) {
1761 snd_pcm_group_for_each_entry(s, substream) {
1762 if (s->pcm->card != substream->pcm->card)
1764 azx_dev = get_azx_dev(s);
1765 if (azx_sd_readb(azx_dev, SD_CTL) &
1775 spin_lock(&chip->reg_lock);
1776 /* reset SYNC bits */
1777 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1778 spin_unlock(&chip->reg_lock);
1783 /* get the current DMA position with correction on VIA chips */
1784 static unsigned int azx_via_get_position(struct azx *chip,
1785 struct azx_dev *azx_dev)
1787 unsigned int link_pos, mini_pos, bound_pos;
1788 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1789 unsigned int fifo_size;
1791 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1792 if (azx_dev->index >= 4) {
1793 /* Playback, no problem using link position */
1799 * use mod to get the DMA position just like old chipset
1801 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1802 mod_dma_pos %= azx_dev->period_bytes;
1804 /* azx_dev->fifo_size can't get FIFO size of in stream.
1805 * Get from base address + offset.
1807 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1809 if (azx_dev->insufficient) {
1810 /* Link position never gather than FIFO size */
1811 if (link_pos <= fifo_size)
1814 azx_dev->insufficient = 0;
1817 if (link_pos <= fifo_size)
1818 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1820 mini_pos = link_pos - fifo_size;
1822 /* Find nearest previous boudary */
1823 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1824 mod_link_pos = link_pos % azx_dev->period_bytes;
1825 if (mod_link_pos >= fifo_size)
1826 bound_pos = link_pos - mod_link_pos;
1827 else if (mod_dma_pos >= mod_mini_pos)
1828 bound_pos = mini_pos - mod_mini_pos;
1830 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1831 if (bound_pos >= azx_dev->bufsize)
1835 /* Calculate real DMA position we want */
1836 return bound_pos + mod_dma_pos;
1839 static unsigned int azx_get_position(struct azx *chip,
1840 struct azx_dev *azx_dev)
1844 if (chip->via_dmapos_patch)
1845 pos = azx_via_get_position(chip, azx_dev);
1846 else if (chip->position_fix == POS_FIX_POSBUF ||
1847 chip->position_fix == POS_FIX_AUTO) {
1848 /* use the position buffer */
1849 pos = le32_to_cpu(*azx_dev->posbuf);
1852 pos = azx_sd_readl(azx_dev, SD_LPIB);
1854 if (pos >= azx_dev->bufsize)
1859 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1861 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1862 struct azx *chip = apcm->chip;
1863 struct azx_dev *azx_dev = get_azx_dev(substream);
1864 return bytes_to_frames(substream->runtime,
1865 azx_get_position(chip, azx_dev));
1869 * Check whether the current DMA position is acceptable for updating
1870 * periods. Returns non-zero if it's OK.
1872 * Many HD-audio controllers appear pretty inaccurate about
1873 * the update-IRQ timing. The IRQ is issued before actually the
1874 * data is processed. So, we need to process it afterwords in a
1877 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1881 if (azx_dev->start_flag &&
1882 time_before_eq(jiffies, azx_dev->start_jiffies))
1883 return -1; /* bogus (too early) interrupt */
1884 azx_dev->start_flag = 0;
1886 pos = azx_get_position(chip, azx_dev);
1887 if (chip->position_fix == POS_FIX_AUTO) {
1890 "hda-intel: Invalid position buffer, "
1891 "using LPIB read method instead.\n");
1892 chip->position_fix = POS_FIX_LPIB;
1893 pos = azx_get_position(chip, azx_dev);
1895 chip->position_fix = POS_FIX_POSBUF;
1898 if (!bdl_pos_adj[chip->dev_index])
1899 return 1; /* no delayed ack */
1900 if (WARN_ONCE(!azx_dev->period_bytes,
1901 "hda-intel: zero azx_dev->period_bytes"))
1902 return 0; /* this shouldn't happen! */
1903 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1904 return 0; /* NG - it's below the period boundary */
1905 return 1; /* OK, it's fine */
1909 * The work for pending PCM period updates.
1911 static void azx_irq_pending_work(struct work_struct *work)
1913 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1916 if (!chip->irq_pending_warned) {
1918 "hda-intel: IRQ timing workaround is activated "
1919 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1920 chip->card->number);
1921 chip->irq_pending_warned = 1;
1926 spin_lock_irq(&chip->reg_lock);
1927 for (i = 0; i < chip->num_streams; i++) {
1928 struct azx_dev *azx_dev = &chip->azx_dev[i];
1929 if (!azx_dev->irq_pending ||
1930 !azx_dev->substream ||
1933 if (azx_position_ok(chip, azx_dev)) {
1934 azx_dev->irq_pending = 0;
1935 spin_unlock(&chip->reg_lock);
1936 snd_pcm_period_elapsed(azx_dev->substream);
1937 spin_lock(&chip->reg_lock);
1941 spin_unlock_irq(&chip->reg_lock);
1948 /* clear irq_pending flags and assure no on-going workq */
1949 static void azx_clear_irq_pending(struct azx *chip)
1953 spin_lock_irq(&chip->reg_lock);
1954 for (i = 0; i < chip->num_streams; i++)
1955 chip->azx_dev[i].irq_pending = 0;
1956 spin_unlock_irq(&chip->reg_lock);
1959 static struct snd_pcm_ops azx_pcm_ops = {
1960 .open = azx_pcm_open,
1961 .close = azx_pcm_close,
1962 .ioctl = snd_pcm_lib_ioctl,
1963 .hw_params = azx_pcm_hw_params,
1964 .hw_free = azx_pcm_hw_free,
1965 .prepare = azx_pcm_prepare,
1966 .trigger = azx_pcm_trigger,
1967 .pointer = azx_pcm_pointer,
1968 .page = snd_pcm_sgbuf_ops_page,
1971 static void azx_pcm_free(struct snd_pcm *pcm)
1973 struct azx_pcm *apcm = pcm->private_data;
1975 apcm->chip->pcm[pcm->device] = NULL;
1981 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1982 struct hda_pcm *cpcm)
1984 struct azx *chip = bus->private_data;
1985 struct snd_pcm *pcm;
1986 struct azx_pcm *apcm;
1987 int pcm_dev = cpcm->device;
1990 if (pcm_dev >= AZX_MAX_PCMS) {
1991 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1995 if (chip->pcm[pcm_dev]) {
1996 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1999 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2000 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2001 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2005 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2006 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2010 apcm->codec = codec;
2011 pcm->private_data = apcm;
2012 pcm->private_free = azx_pcm_free;
2013 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2014 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2015 chip->pcm[pcm_dev] = pcm;
2017 for (s = 0; s < 2; s++) {
2018 apcm->hinfo[s] = &cpcm->stream[s];
2019 if (cpcm->stream[s].substreams)
2020 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2022 /* buffer pre-allocation */
2023 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2024 snd_dma_pci_data(chip->pci),
2025 1024 * 64, 32 * 1024 * 1024);
2030 * mixer creation - all stuff is implemented in hda module
2032 static int __devinit azx_mixer_create(struct azx *chip)
2034 return snd_hda_build_controls(chip->bus);
2039 * initialize SD streams
2041 static int __devinit azx_init_stream(struct azx *chip)
2045 /* initialize each stream (aka device)
2046 * assign the starting bdl address to each stream (device)
2049 for (i = 0; i < chip->num_streams; i++) {
2050 struct azx_dev *azx_dev = &chip->azx_dev[i];
2051 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2052 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2053 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2054 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2055 azx_dev->sd_int_sta_mask = 1 << i;
2056 /* stream tag: must be non-zero and unique */
2058 azx_dev->stream_tag = i + 1;
2064 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2066 if (request_irq(chip->pci->irq, azx_interrupt,
2067 chip->msi ? 0 : IRQF_SHARED,
2068 "hda_intel", chip)) {
2069 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2070 "disabling device\n", chip->pci->irq);
2072 snd_card_disconnect(chip->card);
2075 chip->irq = chip->pci->irq;
2076 pci_intx(chip->pci, !chip->msi);
2081 static void azx_stop_chip(struct azx *chip)
2083 if (!chip->initialized)
2086 /* disable interrupts */
2087 azx_int_disable(chip);
2088 azx_int_clear(chip);
2090 /* disable CORB/RIRB */
2091 azx_free_cmd_io(chip);
2093 /* disable position buffer */
2094 azx_writel(chip, DPLBASE, 0);
2095 azx_writel(chip, DPUBASE, 0);
2097 chip->initialized = 0;
2100 #ifdef CONFIG_SND_HDA_POWER_SAVE
2101 /* power-up/down the controller */
2102 static void azx_power_notify(struct hda_bus *bus)
2104 struct azx *chip = bus->private_data;
2105 struct hda_codec *c;
2108 list_for_each_entry(c, &bus->codec_list, list) {
2115 azx_init_chip(chip);
2116 else if (chip->running && power_save_controller &&
2117 !bus->power_keep_link_on)
2118 azx_stop_chip(chip);
2120 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2127 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2129 struct hda_codec *codec;
2131 list_for_each_entry(codec, &bus->codec_list, list) {
2132 if (snd_hda_codec_needs_resume(codec))
2138 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2140 struct snd_card *card = pci_get_drvdata(pci);
2141 struct azx *chip = card->private_data;
2144 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2145 azx_clear_irq_pending(chip);
2146 for (i = 0; i < AZX_MAX_PCMS; i++)
2147 snd_pcm_suspend_all(chip->pcm[i]);
2148 if (chip->initialized)
2149 snd_hda_suspend(chip->bus);
2150 azx_stop_chip(chip);
2151 if (chip->irq >= 0) {
2152 free_irq(chip->irq, chip);
2156 pci_disable_msi(chip->pci);
2157 pci_disable_device(pci);
2158 pci_save_state(pci);
2159 pci_set_power_state(pci, pci_choose_state(pci, state));
2163 static int azx_resume(struct pci_dev *pci)
2165 struct snd_card *card = pci_get_drvdata(pci);
2166 struct azx *chip = card->private_data;
2168 pci_set_power_state(pci, PCI_D0);
2169 pci_restore_state(pci);
2170 if (pci_enable_device(pci) < 0) {
2171 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2172 "disabling device\n");
2173 snd_card_disconnect(card);
2176 pci_set_master(pci);
2178 if (pci_enable_msi(pci) < 0)
2180 if (azx_acquire_irq(chip, 1) < 0)
2184 if (snd_hda_codecs_inuse(chip->bus))
2185 azx_init_chip(chip);
2187 snd_hda_resume(chip->bus);
2188 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2191 #endif /* CONFIG_PM */
2195 * reboot notifier for hang-up problem at power-down
2197 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2199 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2200 snd_hda_bus_reboot_notify(chip->bus);
2201 azx_stop_chip(chip);
2205 static void azx_notifier_register(struct azx *chip)
2207 chip->reboot_notifier.notifier_call = azx_halt;
2208 register_reboot_notifier(&chip->reboot_notifier);
2211 static void azx_notifier_unregister(struct azx *chip)
2213 if (chip->reboot_notifier.notifier_call)
2214 unregister_reboot_notifier(&chip->reboot_notifier);
2220 static int azx_free(struct azx *chip)
2224 azx_notifier_unregister(chip);
2226 if (chip->initialized) {
2227 azx_clear_irq_pending(chip);
2228 for (i = 0; i < chip->num_streams; i++)
2229 azx_stream_stop(chip, &chip->azx_dev[i]);
2230 azx_stop_chip(chip);
2234 free_irq(chip->irq, (void*)chip);
2236 pci_disable_msi(chip->pci);
2237 if (chip->remap_addr)
2238 iounmap(chip->remap_addr);
2240 if (chip->azx_dev) {
2241 for (i = 0; i < chip->num_streams; i++)
2242 if (chip->azx_dev[i].bdl.area)
2243 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2246 snd_dma_free_pages(&chip->rb);
2247 if (chip->posbuf.area)
2248 snd_dma_free_pages(&chip->posbuf);
2249 pci_release_regions(chip->pci);
2250 pci_disable_device(chip->pci);
2251 kfree(chip->azx_dev);
2257 static int azx_dev_free(struct snd_device *device)
2259 return azx_free(device->device_data);
2263 * white/black-listing for position_fix
2265 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2266 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2267 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2268 SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2269 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2270 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2271 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2272 SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
2273 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2274 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2275 SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
2276 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2277 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2278 SND_PCI_QUIRK(0x8086, 0xd601, "eMachines T5212", POS_FIX_LPIB),
2282 static int __devinit check_position_fix(struct azx *chip, int fix)
2284 const struct snd_pci_quirk *q;
2288 case POS_FIX_POSBUF:
2292 /* Check VIA/ATI HD Audio Controller exist */
2293 switch (chip->driver_type) {
2294 case AZX_DRIVER_VIA:
2295 case AZX_DRIVER_ATI:
2296 chip->via_dmapos_patch = 1;
2297 /* Use link position directly, avoid any transfer problem. */
2298 return POS_FIX_LPIB;
2300 chip->via_dmapos_patch = 0;
2302 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2305 "hda_intel: position_fix set to %d "
2306 "for device %04x:%04x\n",
2307 q->value, q->subvendor, q->subdevice);
2310 return POS_FIX_AUTO;
2314 * black-lists for probe_mask
2316 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2317 /* Thinkpad often breaks the controller communication when accessing
2318 * to the non-working (or non-existing) modem codec slot.
2320 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2321 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2322 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2324 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2325 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2326 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2327 /* forced codec slots */
2328 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2329 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2333 #define AZX_FORCE_CODEC_MASK 0x100
2335 static void __devinit check_probe_mask(struct azx *chip, int dev)
2337 const struct snd_pci_quirk *q;
2339 chip->codec_probe_mask = probe_mask[dev];
2340 if (chip->codec_probe_mask == -1) {
2341 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2344 "hda_intel: probe_mask set to 0x%x "
2345 "for device %04x:%04x\n",
2346 q->value, q->subvendor, q->subdevice);
2347 chip->codec_probe_mask = q->value;
2351 /* check forced option */
2352 if (chip->codec_probe_mask != -1 &&
2353 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2354 chip->codec_mask = chip->codec_probe_mask & 0xff;
2355 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2361 * white/black-list for enable_msi
2363 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2364 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2365 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2366 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2367 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2368 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2372 static void __devinit check_msi(struct azx *chip)
2374 const struct snd_pci_quirk *q;
2376 if (enable_msi >= 0) {
2377 chip->msi = !!enable_msi;
2380 chip->msi = 1; /* enable MSI as default */
2381 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2384 "hda_intel: msi for device %04x:%04x set to %d\n",
2385 q->subvendor, q->subdevice, q->value);
2386 chip->msi = q->value;
2390 /* NVidia chipsets seem to cause troubles with MSI */
2391 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
2392 printk(KERN_INFO "hda_intel: Disable MSI for Nvidia chipset\n");
2401 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2402 int dev, int driver_type,
2407 unsigned short gcap;
2408 static struct snd_device_ops ops = {
2409 .dev_free = azx_dev_free,
2414 err = pci_enable_device(pci);
2418 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2420 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2421 pci_disable_device(pci);
2425 spin_lock_init(&chip->reg_lock);
2426 mutex_init(&chip->open_mutex);
2430 chip->driver_type = driver_type;
2432 chip->dev_index = dev;
2433 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2435 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2436 check_probe_mask(chip, dev);
2438 chip->single_cmd = single_cmd;
2440 if (bdl_pos_adj[dev] < 0) {
2441 switch (chip->driver_type) {
2442 case AZX_DRIVER_ICH:
2443 case AZX_DRIVER_PCH:
2444 bdl_pos_adj[dev] = 1;
2447 bdl_pos_adj[dev] = 32;
2452 #if BITS_PER_LONG != 64
2453 /* Fix up base address on ULI M5461 */
2454 if (chip->driver_type == AZX_DRIVER_ULI) {
2456 pci_read_config_word(pci, 0x40, &tmp3);
2457 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2458 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2462 err = pci_request_regions(pci, "ICH HD audio");
2465 pci_disable_device(pci);
2469 chip->addr = pci_resource_start(pci, 0);
2470 chip->remap_addr = pci_ioremap_bar(pci, 0);
2471 if (chip->remap_addr == NULL) {
2472 snd_printk(KERN_ERR SFX "ioremap error\n");
2478 if (pci_enable_msi(pci) < 0)
2481 if (azx_acquire_irq(chip, 0) < 0) {
2486 pci_set_master(pci);
2487 synchronize_irq(chip->irq);
2489 gcap = azx_readw(chip, GCAP);
2490 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2492 /* disable SB600 64bit support for safety */
2493 if ((chip->driver_type == AZX_DRIVER_ATI) ||
2494 (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2495 struct pci_dev *p_smbus;
2496 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2497 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2500 if (p_smbus->revision < 0x30)
2501 gcap &= ~ICH6_GCAP_64OK;
2502 pci_dev_put(p_smbus);
2506 /* disable 64bit DMA address for Teradici */
2507 /* it does not work with device 6549:1200 subsys e4a2:040b */
2508 if (chip->driver_type == AZX_DRIVER_TERA)
2509 gcap &= ~ICH6_GCAP_64OK;
2511 /* allow 64bit DMA address if supported by H/W */
2512 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2513 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2515 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2516 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2519 /* read number of streams from GCAP register instead of using
2522 chip->capture_streams = (gcap >> 8) & 0x0f;
2523 chip->playback_streams = (gcap >> 12) & 0x0f;
2524 if (!chip->playback_streams && !chip->capture_streams) {
2525 /* gcap didn't give any info, switching to old method */
2527 switch (chip->driver_type) {
2528 case AZX_DRIVER_ULI:
2529 chip->playback_streams = ULI_NUM_PLAYBACK;
2530 chip->capture_streams = ULI_NUM_CAPTURE;
2532 case AZX_DRIVER_ATIHDMI:
2533 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2534 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2536 case AZX_DRIVER_GENERIC:
2538 chip->playback_streams = ICH6_NUM_PLAYBACK;
2539 chip->capture_streams = ICH6_NUM_CAPTURE;
2543 chip->capture_index_offset = 0;
2544 chip->playback_index_offset = chip->capture_streams;
2545 chip->num_streams = chip->playback_streams + chip->capture_streams;
2546 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2548 if (!chip->azx_dev) {
2549 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2553 for (i = 0; i < chip->num_streams; i++) {
2554 /* allocate memory for the BDL for each stream */
2555 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2556 snd_dma_pci_data(chip->pci),
2557 BDL_SIZE, &chip->azx_dev[i].bdl);
2559 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2563 /* allocate memory for the position buffer */
2564 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2565 snd_dma_pci_data(chip->pci),
2566 chip->num_streams * 8, &chip->posbuf);
2568 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2571 /* allocate CORB/RIRB */
2572 err = azx_alloc_cmd_io(chip);
2576 /* initialize streams */
2577 azx_init_stream(chip);
2579 /* initialize chip */
2581 azx_init_chip(chip);
2583 /* codec detection */
2584 if (!chip->codec_mask) {
2585 snd_printk(KERN_ERR SFX "no codecs found!\n");
2590 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2592 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2596 strcpy(card->driver, "HDA-Intel");
2597 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2598 sizeof(card->shortname));
2599 snprintf(card->longname, sizeof(card->longname),
2600 "%s at 0x%lx irq %i",
2601 card->shortname, chip->addr, chip->irq);
2611 static void power_down_all_codecs(struct azx *chip)
2613 #ifdef CONFIG_SND_HDA_POWER_SAVE
2614 /* The codecs were powered up in snd_hda_codec_new().
2615 * Now all initialization done, so turn them down if possible
2617 struct hda_codec *codec;
2618 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2619 snd_hda_power_down(codec);
2624 static int __devinit azx_probe(struct pci_dev *pci,
2625 const struct pci_device_id *pci_id)
2628 struct snd_card *card;
2632 if (dev >= SNDRV_CARDS)
2639 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2641 snd_printk(KERN_ERR SFX "Error creating card!\n");
2645 /* set this here since it's referred in snd_hda_load_patch() */
2646 snd_card_set_dev(card, &pci->dev);
2648 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2651 card->private_data = chip;
2653 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2654 chip->beep_mode = beep_mode[dev];
2657 /* create codec instances */
2658 err = azx_codec_create(chip, model[dev]);
2661 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2663 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2665 err = snd_hda_load_patch(chip->bus, patch[dev]);
2670 if (!probe_only[dev]) {
2671 err = azx_codec_configure(chip);
2676 /* create PCM streams */
2677 err = snd_hda_build_pcms(chip->bus);
2681 /* create mixer controls */
2682 err = azx_mixer_create(chip);
2686 err = snd_card_register(card);
2690 pci_set_drvdata(pci, card);
2692 power_down_all_codecs(chip);
2693 azx_notifier_register(chip);
2698 snd_card_free(card);
2702 static void __devexit azx_remove(struct pci_dev *pci)
2704 snd_card_free(pci_get_drvdata(pci));
2705 pci_set_drvdata(pci, NULL);
2709 static struct pci_device_id azx_ids[] = {
2711 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2712 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2713 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2714 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2715 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2716 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2717 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2718 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2719 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2721 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2722 { PCI_DEVICE(0x8086, 0x3b57), .driver_data = AZX_DRIVER_ICH },
2724 { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
2726 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2727 /* ATI SB 450/600 */
2728 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2729 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2731 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2732 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2733 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2734 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2735 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2736 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2737 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2738 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2739 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2740 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2741 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2742 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2743 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2744 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2745 /* VIA VT8251/VT8237A */
2746 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2748 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2750 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2752 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2753 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2754 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2755 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2756 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2757 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2758 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2759 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2760 { PCI_DEVICE(0x10de, 0x0590), .driver_data = AZX_DRIVER_NVIDIA },
2761 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2762 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2763 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2764 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2765 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2766 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2767 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2768 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2769 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2770 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2771 { PCI_DEVICE(0x10de, 0x0be2), .driver_data = AZX_DRIVER_NVIDIA },
2772 { PCI_DEVICE(0x10de, 0x0be3), .driver_data = AZX_DRIVER_NVIDIA },
2773 { PCI_DEVICE(0x10de, 0x0be4), .driver_data = AZX_DRIVER_NVIDIA },
2774 { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2775 { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2776 { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2777 { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2779 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2780 /* Creative X-Fi (CA0110-IBG) */
2781 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2782 /* the following entry conflicts with snd-ctxfi driver,
2783 * as ctxfi driver mutates from HD-audio to native mode with
2784 * a special command sequence.
2786 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2787 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2788 .class_mask = 0xffffff,
2789 .driver_data = AZX_DRIVER_GENERIC },
2791 /* this entry seems still valid -- i.e. without emu20kx chip */
2792 { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2794 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2795 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2796 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2797 .class_mask = 0xffffff,
2798 .driver_data = AZX_DRIVER_GENERIC },
2799 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2800 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2801 .class_mask = 0xffffff,
2802 .driver_data = AZX_DRIVER_GENERIC },
2805 MODULE_DEVICE_TABLE(pci, azx_ids);
2807 /* pci_driver definition */
2808 static struct pci_driver driver = {
2809 .name = "HDA Intel",
2810 .id_table = azx_ids,
2812 .remove = __devexit_p(azx_remove),
2814 .suspend = azx_suspend,
2815 .resume = azx_resume,
2819 static int __init alsa_card_azx_init(void)
2821 return pci_register_driver(&driver);
2824 static void __exit alsa_card_azx_exit(void)
2826 pci_unregister_driver(&driver);
2829 module_init(alsa_card_azx_init)
2830 module_exit(alsa_card_azx_exit)