3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
69 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
70 static char *model[SNDRV_CARDS];
71 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
72 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int probe_only[SNDRV_CARDS];
75 static int jackpoll_ms[SNDRV_CARDS];
76 static bool single_cmd;
77 static int enable_msi = -1;
78 #ifdef CONFIG_SND_HDA_PATCH_LOADER
79 static char *patch[SNDRV_CARDS];
81 #ifdef CONFIG_SND_HDA_INPUT_BEEP
82 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
83 CONFIG_SND_HDA_INPUT_BEEP_MODE};
86 module_param_array(index, int, NULL, 0444);
87 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
88 module_param_array(id, charp, NULL, 0444);
89 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
90 module_param_array(enable, bool, NULL, 0444);
91 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
92 module_param_array(model, charp, NULL, 0444);
93 MODULE_PARM_DESC(model, "Use the given board model.");
94 module_param_array(position_fix, int, NULL, 0444);
95 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
96 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
97 module_param_array(bdl_pos_adj, int, NULL, 0644);
98 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
99 module_param_array(probe_mask, int, NULL, 0444);
100 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
101 module_param_array(probe_only, int, NULL, 0444);
102 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
103 module_param_array(jackpoll_ms, int, NULL, 0444);
104 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
105 module_param(single_cmd, bool, 0444);
106 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
107 "(for debugging only).");
108 module_param(enable_msi, bint, 0444);
109 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
110 #ifdef CONFIG_SND_HDA_PATCH_LOADER
111 module_param_array(patch, charp, NULL, 0444);
112 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
114 #ifdef CONFIG_SND_HDA_INPUT_BEEP
115 module_param_array(beep_mode, bool, NULL, 0444);
116 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
117 "(0=off, 1=on) (default=1).");
121 static int param_set_xint(const char *val, const struct kernel_param *kp);
122 static struct kernel_param_ops param_ops_xint = {
123 .set = param_set_xint,
124 .get = param_get_int,
126 #define param_check_xint param_check_int
128 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
129 module_param(power_save, xint, 0644);
130 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
131 "(in second, 0 = disable).");
133 /* reset the HD-audio controller in power save mode.
134 * this may give more power-saving, but will take longer time to
137 static bool power_save_controller = 1;
138 module_param(power_save_controller, bool, 0644);
139 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
140 #endif /* CONFIG_PM */
142 static int align_buffer_size = -1;
143 module_param(align_buffer_size, bint, 0644);
144 MODULE_PARM_DESC(align_buffer_size,
145 "Force buffer and period sizes to be multiple of 128 bytes.");
148 static bool hda_snoop = true;
149 module_param_named(snoop, hda_snoop, bool, 0444);
150 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
151 #define azx_snoop(chip) (chip)->snoop
153 #define hda_snoop true
154 #define azx_snoop(chip) true
158 MODULE_LICENSE("GPL");
159 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
190 MODULE_DESCRIPTION("Intel HDA driver");
192 #ifdef CONFIG_SND_VERBOSE_PRINTK
193 #define SFX /* nop */
195 #define SFX "hda-intel "
198 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
199 #ifdef CONFIG_SND_HDA_CODEC_HDMI
200 #define SUPPORT_VGA_SWITCHEROO
208 #define ICH6_REG_GCAP 0x00
209 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
210 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
211 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
212 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
213 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
214 #define ICH6_REG_VMIN 0x02
215 #define ICH6_REG_VMAJ 0x03
216 #define ICH6_REG_OUTPAY 0x04
217 #define ICH6_REG_INPAY 0x06
218 #define ICH6_REG_GCTL 0x08
219 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
220 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
221 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
222 #define ICH6_REG_WAKEEN 0x0c
223 #define ICH6_REG_STATESTS 0x0e
224 #define ICH6_REG_GSTS 0x10
225 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
226 #define ICH6_REG_INTCTL 0x20
227 #define ICH6_REG_INTSTS 0x24
228 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
229 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
230 #define ICH6_REG_SSYNC 0x38
231 #define ICH6_REG_CORBLBASE 0x40
232 #define ICH6_REG_CORBUBASE 0x44
233 #define ICH6_REG_CORBWP 0x48
234 #define ICH6_REG_CORBRP 0x4a
235 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
236 #define ICH6_REG_CORBCTL 0x4c
237 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
238 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
239 #define ICH6_REG_CORBSTS 0x4d
240 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
241 #define ICH6_REG_CORBSIZE 0x4e
243 #define ICH6_REG_RIRBLBASE 0x50
244 #define ICH6_REG_RIRBUBASE 0x54
245 #define ICH6_REG_RIRBWP 0x58
246 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
247 #define ICH6_REG_RINTCNT 0x5a
248 #define ICH6_REG_RIRBCTL 0x5c
249 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
250 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
251 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
252 #define ICH6_REG_RIRBSTS 0x5d
253 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
254 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
255 #define ICH6_REG_RIRBSIZE 0x5e
257 #define ICH6_REG_IC 0x60
258 #define ICH6_REG_IR 0x64
259 #define ICH6_REG_IRS 0x68
260 #define ICH6_IRS_VALID (1<<1)
261 #define ICH6_IRS_BUSY (1<<0)
263 #define ICH6_REG_DPLBASE 0x70
264 #define ICH6_REG_DPUBASE 0x74
265 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
267 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
268 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
270 /* stream register offsets from stream base */
271 #define ICH6_REG_SD_CTL 0x00
272 #define ICH6_REG_SD_STS 0x03
273 #define ICH6_REG_SD_LPIB 0x04
274 #define ICH6_REG_SD_CBL 0x08
275 #define ICH6_REG_SD_LVI 0x0c
276 #define ICH6_REG_SD_FIFOW 0x0e
277 #define ICH6_REG_SD_FIFOSIZE 0x10
278 #define ICH6_REG_SD_FORMAT 0x12
279 #define ICH6_REG_SD_BDLPL 0x18
280 #define ICH6_REG_SD_BDLPU 0x1c
283 #define ICH6_PCIREG_TCSEL 0x44
289 /* max number of SDs */
290 /* ICH, ATI and VIA have 4 playback and 4 capture */
291 #define ICH6_NUM_CAPTURE 4
292 #define ICH6_NUM_PLAYBACK 4
294 /* ULI has 6 playback and 5 capture */
295 #define ULI_NUM_CAPTURE 5
296 #define ULI_NUM_PLAYBACK 6
298 /* ATI HDMI has 1 playback and 0 capture */
299 #define ATIHDMI_NUM_CAPTURE 0
300 #define ATIHDMI_NUM_PLAYBACK 1
302 /* TERA has 4 playback and 3 capture */
303 #define TERA_NUM_CAPTURE 3
304 #define TERA_NUM_PLAYBACK 4
306 /* this number is statically defined for simplicity */
307 #define MAX_AZX_DEV 16
309 /* max number of fragments - we may use more if allocating more pages for BDL */
310 #define BDL_SIZE 4096
311 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
312 #define AZX_MAX_FRAG 32
313 /* max buffer size - no h/w limit, you can increase as you like */
314 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
316 /* RIRB int mask: overrun[2], response[0] */
317 #define RIRB_INT_RESPONSE 0x01
318 #define RIRB_INT_OVERRUN 0x04
319 #define RIRB_INT_MASK 0x05
321 /* STATESTS int mask: S3,SD2,SD1,SD0 */
322 #define AZX_MAX_CODECS 8
323 #define AZX_DEFAULT_CODECS 4
324 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
327 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
328 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
329 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
330 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
331 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
332 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
333 #define SD_CTL_STREAM_TAG_SHIFT 20
335 /* SD_CTL and SD_STS */
336 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
337 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
338 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
339 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
343 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
345 /* INTCTL and INTSTS */
346 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
347 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
348 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
350 /* below are so far hardcoded - should read registers in future */
351 #define ICH6_MAX_CORB_ENTRIES 256
352 #define ICH6_MAX_RIRB_ENTRIES 256
354 /* position fix mode */
363 /* Defines for ATI HD Audio support in SB450 south bridge */
364 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
365 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
367 /* Defines for Nvidia HDA support */
368 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
369 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
370 #define NVIDIA_HDA_ISTRM_COH 0x4d
371 #define NVIDIA_HDA_OSTRM_COH 0x4c
372 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
374 /* Defines for Intel SCH HDA snoop control */
375 #define INTEL_SCH_HDA_DEVC 0x78
376 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
378 /* Define IN stream 0 FIFO size offset in VIA controller */
379 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
380 /* Define VIA HD Audio Device ID*/
381 #define VIA_HDAC_DEVICE_ID 0x3288
383 /* HD Audio class code */
384 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
390 struct snd_dma_buffer bdl; /* BDL buffer */
391 u32 *posbuf; /* position buffer pointer */
393 unsigned int bufsize; /* size of the play buffer in bytes */
394 unsigned int period_bytes; /* size of the period in bytes */
395 unsigned int frags; /* number for period in the play buffer */
396 unsigned int fifo_size; /* FIFO size */
397 unsigned long start_wallclk; /* start + minimum wallclk */
398 unsigned long period_wallclk; /* wallclk for period */
400 void __iomem *sd_addr; /* stream descriptor pointer */
402 u32 sd_int_sta_mask; /* stream int status mask */
405 struct snd_pcm_substream *substream; /* assigned substream,
408 unsigned int format_val; /* format value to be set in the
409 * controller and the codec
411 unsigned char stream_tag; /* assigned stream */
412 unsigned char index; /* stream index */
413 int assigned_key; /* last device# key assigned to */
415 unsigned int opened :1;
416 unsigned int running :1;
417 unsigned int irq_pending :1;
418 unsigned int prepared:1;
419 unsigned int locked:1;
422 * A flag to ensure DMA position is 0
423 * when link position is not greater than FIFO size
425 unsigned int insufficient :1;
426 unsigned int wc_marked:1;
427 unsigned int no_period_wakeup:1;
429 struct timecounter azx_tc;
430 struct cyclecounter azx_cc;
432 #ifdef CONFIG_SND_HDA_DSP_LOADER
433 struct mutex dsp_mutex;
437 /* DSP lock helpers */
438 #ifdef CONFIG_SND_HDA_DSP_LOADER
439 #define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
440 #define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
441 #define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
442 #define dsp_is_locked(dev) ((dev)->locked)
444 #define dsp_lock_init(dev) do {} while (0)
445 #define dsp_lock(dev) do {} while (0)
446 #define dsp_unlock(dev) do {} while (0)
447 #define dsp_is_locked(dev) 0
452 u32 *buf; /* CORB/RIRB buffer
453 * Each CORB entry is 4byte, RIRB is 8byte
455 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
457 unsigned short rp, wp; /* read/write pointers */
458 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
459 u32 res[AZX_MAX_CODECS]; /* last read value */
465 struct hda_codec *codec;
466 struct hda_pcm_stream *hinfo[2];
467 struct list_head list;
471 struct snd_card *card;
475 /* chip type specific */
477 unsigned int driver_caps;
478 int playback_streams;
479 int playback_index_offset;
481 int capture_index_offset;
486 void __iomem *remap_addr;
491 struct mutex open_mutex;
492 struct completion probe_wait;
494 /* streams (x num_streams) */
495 struct azx_dev *azx_dev;
498 struct list_head pcm_list; /* azx_pcm list */
501 unsigned short codec_mask;
502 int codec_probe_mask; /* copied from probe_mask option */
504 unsigned int beep_mode;
510 /* CORB/RIRB and position buffers */
511 struct snd_dma_buffer rb;
512 struct snd_dma_buffer posbuf;
514 #ifdef CONFIG_SND_HDA_PATCH_LOADER
515 const struct firmware *fw;
519 int position_fix[2]; /* for both playback/capture streams */
521 unsigned int running :1;
522 unsigned int initialized :1;
523 unsigned int single_cmd :1;
524 unsigned int polling_mode :1;
526 unsigned int irq_pending_warned :1;
527 unsigned int probing :1; /* codec probing phase */
528 unsigned int snoop:1;
529 unsigned int align_buffer_size:1;
530 unsigned int region_requested:1;
532 /* VGA-switcheroo setup */
533 unsigned int use_vga_switcheroo:1;
534 unsigned int vga_switcheroo_registered:1;
535 unsigned int init_failed:1; /* delayed init failed */
536 unsigned int disabled:1; /* disabled by VGA-switcher */
539 unsigned int last_cmd[AZX_MAX_CODECS];
541 /* for pending irqs */
542 struct work_struct irq_pending_work;
544 /* reboot notifier (for mysterious hangup problem at power-down) */
545 struct notifier_block reboot_notifier;
547 /* card list (for power_save trigger) */
548 struct list_head list;
550 #ifdef CONFIG_SND_HDA_DSP_LOADER
551 struct azx_dev saved_azx_dev;
555 #define CREATE_TRACE_POINTS
556 #include "hda_intel_trace.h"
565 AZX_DRIVER_ATIHDMI_NS,
574 AZX_NUM_DRIVERS, /* keep this as last entry */
577 /* driver quirks (capabilities) */
578 /* bits 0-7 are used for indicating driver type */
579 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
580 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
581 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
582 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
583 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
584 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
585 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
586 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
587 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
588 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
589 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
590 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
591 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
592 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
593 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22) /* buffer size alignment */
594 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
595 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
596 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
598 /* quirks for Intel PCH */
599 #define AZX_DCAPS_INTEL_PCH_NOPM \
600 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
601 AZX_DCAPS_COUNT_LPIB_DELAY)
603 #define AZX_DCAPS_INTEL_PCH \
604 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
606 /* quirks for ATI SB / AMD Hudson */
607 #define AZX_DCAPS_PRESET_ATI_SB \
608 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
609 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
611 /* quirks for ATI/AMD HDMI */
612 #define AZX_DCAPS_PRESET_ATI_HDMI \
613 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
615 /* quirks for Nvidia */
616 #define AZX_DCAPS_PRESET_NVIDIA \
617 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
618 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
620 #define AZX_DCAPS_PRESET_CTHDA \
621 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
624 * VGA-switcher support
626 #ifdef SUPPORT_VGA_SWITCHEROO
627 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
629 #define use_vga_switcheroo(chip) 0
632 static char *driver_short_names[] = {
633 [AZX_DRIVER_ICH] = "HDA Intel",
634 [AZX_DRIVER_PCH] = "HDA Intel PCH",
635 [AZX_DRIVER_SCH] = "HDA Intel MID",
636 [AZX_DRIVER_ATI] = "HDA ATI SB",
637 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
638 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
639 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
640 [AZX_DRIVER_SIS] = "HDA SIS966",
641 [AZX_DRIVER_ULI] = "HDA ULI M5461",
642 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
643 [AZX_DRIVER_TERA] = "HDA Teradici",
644 [AZX_DRIVER_CTX] = "HDA Creative",
645 [AZX_DRIVER_CTHDA] = "HDA Creative",
646 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
650 * macros for easy use
652 #define azx_writel(chip,reg,value) \
653 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
654 #define azx_readl(chip,reg) \
655 readl((chip)->remap_addr + ICH6_REG_##reg)
656 #define azx_writew(chip,reg,value) \
657 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
658 #define azx_readw(chip,reg) \
659 readw((chip)->remap_addr + ICH6_REG_##reg)
660 #define azx_writeb(chip,reg,value) \
661 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
662 #define azx_readb(chip,reg) \
663 readb((chip)->remap_addr + ICH6_REG_##reg)
665 #define azx_sd_writel(dev,reg,value) \
666 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
667 #define azx_sd_readl(dev,reg) \
668 readl((dev)->sd_addr + ICH6_REG_##reg)
669 #define azx_sd_writew(dev,reg,value) \
670 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
671 #define azx_sd_readw(dev,reg) \
672 readw((dev)->sd_addr + ICH6_REG_##reg)
673 #define azx_sd_writeb(dev,reg,value) \
674 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
675 #define azx_sd_readb(dev,reg) \
676 readb((dev)->sd_addr + ICH6_REG_##reg)
678 /* for pcm support */
679 #define get_azx_dev(substream) (substream->runtime->private_data)
682 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
688 if (!dmab || !dmab->area || !dmab->bytes)
691 #ifdef CONFIG_SND_DMA_SGBUF
692 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
693 struct snd_sg_buf *sgbuf = dmab->private_data;
695 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
697 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
702 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
704 set_memory_wc((unsigned long)dmab->area, pages);
706 set_memory_wb((unsigned long)dmab->area, pages);
709 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
712 __mark_pages_wc(chip, buf, on);
714 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
715 struct snd_pcm_substream *substream, bool on)
717 if (azx_dev->wc_marked != on) {
718 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
719 azx_dev->wc_marked = on;
723 /* NOP for other archs */
724 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
728 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
729 struct snd_pcm_substream *substream, bool on)
734 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
735 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
737 * Interface for HD codec
741 * CORB / RIRB interface
743 static int azx_alloc_cmd_io(struct azx *chip)
747 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
748 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
749 snd_dma_pci_data(chip->pci),
750 PAGE_SIZE, &chip->rb);
752 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
755 mark_pages_wc(chip, &chip->rb, true);
759 static void azx_init_cmd_io(struct azx *chip)
761 spin_lock_irq(&chip->reg_lock);
763 chip->corb.addr = chip->rb.addr;
764 chip->corb.buf = (u32 *)chip->rb.area;
765 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
766 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
768 /* set the corb size to 256 entries (ULI requires explicitly) */
769 azx_writeb(chip, CORBSIZE, 0x02);
770 /* set the corb write pointer to 0 */
771 azx_writew(chip, CORBWP, 0);
772 /* reset the corb hw read pointer */
773 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
774 /* enable corb dma */
775 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
778 chip->rirb.addr = chip->rb.addr + 2048;
779 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
780 chip->rirb.wp = chip->rirb.rp = 0;
781 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
782 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
783 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
785 /* set the rirb size to 256 entries (ULI requires explicitly) */
786 azx_writeb(chip, RIRBSIZE, 0x02);
787 /* reset the rirb hw write pointer */
788 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
789 /* set N=1, get RIRB response interrupt for new entry */
790 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
791 azx_writew(chip, RINTCNT, 0xc0);
793 azx_writew(chip, RINTCNT, 1);
794 /* enable rirb dma and response irq */
795 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
796 spin_unlock_irq(&chip->reg_lock);
799 static void azx_free_cmd_io(struct azx *chip)
801 spin_lock_irq(&chip->reg_lock);
802 /* disable ringbuffer DMAs */
803 azx_writeb(chip, RIRBCTL, 0);
804 azx_writeb(chip, CORBCTL, 0);
805 spin_unlock_irq(&chip->reg_lock);
808 static unsigned int azx_command_addr(u32 cmd)
810 unsigned int addr = cmd >> 28;
812 if (addr >= AZX_MAX_CODECS) {
820 static unsigned int azx_response_addr(u32 res)
822 unsigned int addr = res & 0xf;
824 if (addr >= AZX_MAX_CODECS) {
833 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
835 struct azx *chip = bus->private_data;
836 unsigned int addr = azx_command_addr(val);
839 spin_lock_irq(&chip->reg_lock);
841 /* add command to corb */
842 wp = azx_readw(chip, CORBWP);
844 /* something wrong, controller likely turned to D3 */
845 spin_unlock_irq(&chip->reg_lock);
849 wp %= ICH6_MAX_CORB_ENTRIES;
851 rp = azx_readw(chip, CORBRP);
853 /* oops, it's full */
854 spin_unlock_irq(&chip->reg_lock);
858 chip->rirb.cmds[addr]++;
859 chip->corb.buf[wp] = cpu_to_le32(val);
860 azx_writel(chip, CORBWP, wp);
862 spin_unlock_irq(&chip->reg_lock);
867 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
869 /* retrieve RIRB entry - called from interrupt handler */
870 static void azx_update_rirb(struct azx *chip)
876 wp = azx_readw(chip, RIRBWP);
878 /* something wrong, controller likely turned to D3 */
882 if (wp == chip->rirb.wp)
886 while (chip->rirb.rp != wp) {
888 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
890 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
891 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
892 res = le32_to_cpu(chip->rirb.buf[rp]);
893 addr = azx_response_addr(res_ex);
894 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
895 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
896 else if (chip->rirb.cmds[addr]) {
897 chip->rirb.res[addr] = res;
899 chip->rirb.cmds[addr]--;
901 snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
905 chip->last_cmd[addr]);
909 /* receive a response */
910 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
913 struct azx *chip = bus->private_data;
914 unsigned long timeout;
915 unsigned long loopcounter;
919 timeout = jiffies + msecs_to_jiffies(1000);
921 for (loopcounter = 0;; loopcounter++) {
922 if (chip->polling_mode || do_poll) {
923 spin_lock_irq(&chip->reg_lock);
924 azx_update_rirb(chip);
925 spin_unlock_irq(&chip->reg_lock);
927 if (!chip->rirb.cmds[addr]) {
932 chip->poll_count = 0;
933 return chip->rirb.res[addr]; /* the last value */
935 if (time_after(jiffies, timeout))
937 if (bus->needs_damn_long_delay || loopcounter > 3000)
938 msleep(2); /* temporary workaround */
945 if (!bus->no_response_fallback)
948 if (!chip->polling_mode && chip->poll_count < 2) {
949 snd_printdd(SFX "%s: azx_get_response timeout, "
950 "polling the codec once: last cmd=0x%08x\n",
951 pci_name(chip->pci), chip->last_cmd[addr]);
958 if (!chip->polling_mode) {
959 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
960 "switching to polling mode: last cmd=0x%08x\n",
961 pci_name(chip->pci), chip->last_cmd[addr]);
962 chip->polling_mode = 1;
967 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
968 "disabling MSI: last cmd=0x%08x\n",
969 pci_name(chip->pci), chip->last_cmd[addr]);
970 free_irq(chip->irq, chip);
972 pci_disable_msi(chip->pci);
974 if (azx_acquire_irq(chip, 1) < 0) {
982 /* If this critical timeout happens during the codec probing
983 * phase, this is likely an access to a non-existing codec
984 * slot. Better to return an error and reset the system.
989 /* a fatal communication error; need either to reset or to fallback
990 * to the single_cmd mode
993 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
994 bus->response_reset = 1;
995 return -1; /* give a chance to retry */
998 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
999 "switching to single_cmd mode: last cmd=0x%08x\n",
1000 chip->last_cmd[addr]);
1001 chip->single_cmd = 1;
1002 bus->response_reset = 0;
1003 /* release CORB/RIRB */
1004 azx_free_cmd_io(chip);
1005 /* disable unsolicited responses */
1006 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1011 * Use the single immediate command instead of CORB/RIRB for simplicity
1013 * Note: according to Intel, this is not preferred use. The command was
1014 * intended for the BIOS only, and may get confused with unsolicited
1015 * responses. So, we shouldn't use it for normal operation from the
1017 * I left the codes, however, for debugging/testing purposes.
1020 /* receive a response */
1021 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1026 /* check IRV busy bit */
1027 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1028 /* reuse rirb.res as the response return value */
1029 chip->rirb.res[addr] = azx_readl(chip, IR);
1034 if (printk_ratelimit())
1035 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1036 pci_name(chip->pci), azx_readw(chip, IRS));
1037 chip->rirb.res[addr] = -1;
1041 /* send a command */
1042 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1044 struct azx *chip = bus->private_data;
1045 unsigned int addr = azx_command_addr(val);
1048 bus->rirb_error = 0;
1050 /* check ICB busy bit */
1051 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1052 /* Clear IRV valid bit */
1053 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1055 azx_writel(chip, IC, val);
1056 azx_writew(chip, IRS, azx_readw(chip, IRS) |
1058 return azx_single_wait_for_response(chip, addr);
1062 if (printk_ratelimit())
1063 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1064 pci_name(chip->pci), azx_readw(chip, IRS), val);
1068 /* receive a response */
1069 static unsigned int azx_single_get_response(struct hda_bus *bus,
1072 struct azx *chip = bus->private_data;
1073 return chip->rirb.res[addr];
1077 * The below are the main callbacks from hda_codec.
1079 * They are just the skeleton to call sub-callbacks according to the
1080 * current setting of chip->single_cmd.
1083 /* send a command */
1084 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1086 struct azx *chip = bus->private_data;
1090 chip->last_cmd[azx_command_addr(val)] = val;
1091 if (chip->single_cmd)
1092 return azx_single_send_cmd(bus, val);
1094 return azx_corb_send_cmd(bus, val);
1097 /* get a response */
1098 static unsigned int azx_get_response(struct hda_bus *bus,
1101 struct azx *chip = bus->private_data;
1104 if (chip->single_cmd)
1105 return azx_single_get_response(bus, addr);
1107 return azx_rirb_get_response(bus, addr);
1111 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1114 #ifdef CONFIG_SND_HDA_DSP_LOADER
1115 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1116 unsigned int byte_size,
1117 struct snd_dma_buffer *bufp);
1118 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1119 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1120 struct snd_dma_buffer *dmab);
1123 /* enter link reset */
1124 static void azx_enter_link_reset(struct azx *chip)
1126 unsigned long timeout;
1128 /* reset controller */
1129 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1131 timeout = jiffies + msecs_to_jiffies(100);
1132 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
1133 time_before(jiffies, timeout))
1134 usleep_range(500, 1000);
1137 /* exit link reset */
1138 static void azx_exit_link_reset(struct azx *chip)
1140 unsigned long timeout;
1142 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1144 timeout = jiffies + msecs_to_jiffies(100);
1145 while (!azx_readb(chip, GCTL) &&
1146 time_before(jiffies, timeout))
1147 usleep_range(500, 1000);
1150 /* reset codec link */
1151 static int azx_reset(struct azx *chip, int full_reset)
1156 /* clear STATESTS */
1157 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1159 /* reset controller */
1160 azx_enter_link_reset(chip);
1162 /* delay for >= 100us for codec PLL to settle per spec
1163 * Rev 0.9 section 5.5.1
1165 usleep_range(500, 1000);
1167 /* Bring controller out of reset */
1168 azx_exit_link_reset(chip);
1170 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1171 usleep_range(1000, 1200);
1174 /* check to see if controller is ready */
1175 if (!azx_readb(chip, GCTL)) {
1176 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1180 /* Accept unsolicited responses */
1181 if (!chip->single_cmd)
1182 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1186 if (!chip->codec_mask) {
1187 chip->codec_mask = azx_readw(chip, STATESTS);
1188 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1196 * Lowlevel interface
1199 /* enable interrupts */
1200 static void azx_int_enable(struct azx *chip)
1202 /* enable controller CIE and GIE */
1203 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1204 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1207 /* disable interrupts */
1208 static void azx_int_disable(struct azx *chip)
1212 /* disable interrupts in stream descriptor */
1213 for (i = 0; i < chip->num_streams; i++) {
1214 struct azx_dev *azx_dev = &chip->azx_dev[i];
1215 azx_sd_writeb(azx_dev, SD_CTL,
1216 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1219 /* disable SIE for all streams */
1220 azx_writeb(chip, INTCTL, 0);
1222 /* disable controller CIE and GIE */
1223 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1224 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1227 /* clear interrupts */
1228 static void azx_int_clear(struct azx *chip)
1232 /* clear stream status */
1233 for (i = 0; i < chip->num_streams; i++) {
1234 struct azx_dev *azx_dev = &chip->azx_dev[i];
1235 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1238 /* clear STATESTS */
1239 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1241 /* clear rirb status */
1242 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1244 /* clear int status */
1245 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1248 /* start a stream */
1249 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1252 * Before stream start, initialize parameter
1254 azx_dev->insufficient = 1;
1257 azx_writel(chip, INTCTL,
1258 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1259 /* set DMA start and interrupt mask */
1260 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1261 SD_CTL_DMA_START | SD_INT_MASK);
1265 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1267 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1268 ~(SD_CTL_DMA_START | SD_INT_MASK));
1269 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1273 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1275 azx_stream_clear(chip, azx_dev);
1277 azx_writel(chip, INTCTL,
1278 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1283 * reset and start the controller registers
1285 static void azx_init_chip(struct azx *chip, int full_reset)
1287 if (chip->initialized)
1290 /* reset controller */
1291 azx_reset(chip, full_reset);
1293 /* initialize interrupts */
1294 azx_int_clear(chip);
1295 azx_int_enable(chip);
1297 /* initialize the codec command I/O */
1298 if (!chip->single_cmd)
1299 azx_init_cmd_io(chip);
1301 /* program the position buffer */
1302 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1303 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1305 chip->initialized = 1;
1309 * initialize the PCI registers
1311 /* update bits in a PCI register byte */
1312 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1313 unsigned char mask, unsigned char val)
1317 pci_read_config_byte(pci, reg, &data);
1319 data |= (val & mask);
1320 pci_write_config_byte(pci, reg, data);
1323 static void azx_init_pci(struct azx *chip)
1325 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1326 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1327 * Ensuring these bits are 0 clears playback static on some HD Audio
1329 * The PCI register TCSEL is defined in the Intel manuals.
1331 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1332 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1333 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1336 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1337 * we need to enable snoop.
1339 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1340 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1341 update_pci_byte(chip->pci,
1342 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1343 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1346 /* For NVIDIA HDA, enable snoop */
1347 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1348 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1349 update_pci_byte(chip->pci,
1350 NVIDIA_HDA_TRANSREG_ADDR,
1351 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1352 update_pci_byte(chip->pci,
1353 NVIDIA_HDA_ISTRM_COH,
1354 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1355 update_pci_byte(chip->pci,
1356 NVIDIA_HDA_OSTRM_COH,
1357 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1360 /* Enable SCH/PCH snoop if needed */
1361 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1362 unsigned short snoop;
1363 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1364 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1365 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1366 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1367 if (!azx_snoop(chip))
1368 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1369 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1370 pci_read_config_word(chip->pci,
1371 INTEL_SCH_HDA_DEVC, &snoop);
1373 snd_printdd(SFX "%s: SCH snoop: %s\n",
1374 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1375 ? "Disabled" : "Enabled");
1380 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1385 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1387 struct azx *chip = dev_id;
1388 struct azx_dev *azx_dev;
1393 #ifdef CONFIG_PM_RUNTIME
1394 if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1398 spin_lock(&chip->reg_lock);
1400 if (chip->disabled) {
1401 spin_unlock(&chip->reg_lock);
1405 status = azx_readl(chip, INTSTS);
1407 spin_unlock(&chip->reg_lock);
1411 for (i = 0; i < chip->num_streams; i++) {
1412 azx_dev = &chip->azx_dev[i];
1413 if (status & azx_dev->sd_int_sta_mask) {
1414 sd_status = azx_sd_readb(azx_dev, SD_STS);
1415 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1416 if (!azx_dev->substream || !azx_dev->running ||
1417 !(sd_status & SD_INT_COMPLETE))
1419 /* check whether this IRQ is really acceptable */
1420 ok = azx_position_ok(chip, azx_dev);
1422 azx_dev->irq_pending = 0;
1423 spin_unlock(&chip->reg_lock);
1424 snd_pcm_period_elapsed(azx_dev->substream);
1425 spin_lock(&chip->reg_lock);
1426 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1427 /* bogus IRQ, process it later */
1428 azx_dev->irq_pending = 1;
1429 queue_work(chip->bus->workq,
1430 &chip->irq_pending_work);
1435 /* clear rirb int */
1436 status = azx_readb(chip, RIRBSTS);
1437 if (status & RIRB_INT_MASK) {
1438 if (status & RIRB_INT_RESPONSE) {
1439 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1441 azx_update_rirb(chip);
1443 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1447 /* clear state status int */
1448 if (azx_readb(chip, STATESTS) & 0x04)
1449 azx_writeb(chip, STATESTS, 0x04);
1451 spin_unlock(&chip->reg_lock);
1458 * set up a BDL entry
1460 static int setup_bdle(struct azx *chip,
1461 struct snd_dma_buffer *dmab,
1462 struct azx_dev *azx_dev, u32 **bdlp,
1463 int ofs, int size, int with_ioc)
1471 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1474 addr = snd_sgbuf_get_addr(dmab, ofs);
1475 /* program the address field of the BDL entry */
1476 bdl[0] = cpu_to_le32((u32)addr);
1477 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1478 /* program the size field of the BDL entry */
1479 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1480 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1481 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1482 u32 remain = 0x1000 - (ofs & 0xfff);
1486 bdl[2] = cpu_to_le32(chunk);
1487 /* program the IOC to enable interrupt
1488 * only when the whole fragment is processed
1491 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1501 * set up BDL entries
1503 static int azx_setup_periods(struct azx *chip,
1504 struct snd_pcm_substream *substream,
1505 struct azx_dev *azx_dev)
1508 int i, ofs, periods, period_bytes;
1511 /* reset BDL address */
1512 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1513 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1515 period_bytes = azx_dev->period_bytes;
1516 periods = azx_dev->bufsize / period_bytes;
1518 /* program the initial BDL entries */
1519 bdl = (u32 *)azx_dev->bdl.area;
1522 pos_adj = bdl_pos_adj[chip->dev_index];
1523 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1524 struct snd_pcm_runtime *runtime = substream->runtime;
1525 int pos_align = pos_adj;
1526 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1528 pos_adj = pos_align;
1530 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1532 pos_adj = frames_to_bytes(runtime, pos_adj);
1533 if (pos_adj >= period_bytes) {
1534 snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1535 pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1538 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1540 &bdl, ofs, pos_adj, true);
1546 for (i = 0; i < periods; i++) {
1547 if (i == periods - 1 && pos_adj)
1548 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1550 period_bytes - pos_adj, 0);
1552 ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1555 !azx_dev->no_period_wakeup);
1562 snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1563 pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1568 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1573 azx_stream_clear(chip, azx_dev);
1575 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1576 SD_CTL_STREAM_RESET);
1579 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1582 val &= ~SD_CTL_STREAM_RESET;
1583 azx_sd_writeb(azx_dev, SD_CTL, val);
1587 /* waiting for hardware to report that the stream is out of reset */
1588 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1592 /* reset first position - may not be synced with hw at this time */
1593 *azx_dev->posbuf = 0;
1597 * set up the SD for streaming
1599 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1602 /* make sure the run bit is zero for SD */
1603 azx_stream_clear(chip, azx_dev);
1604 /* program the stream_tag */
1605 val = azx_sd_readl(azx_dev, SD_CTL);
1606 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1607 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1608 if (!azx_snoop(chip))
1609 val |= SD_CTL_TRAFFIC_PRIO;
1610 azx_sd_writel(azx_dev, SD_CTL, val);
1612 /* program the length of samples in cyclic buffer */
1613 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1615 /* program the stream format */
1616 /* this value needs to be the same as the one programmed */
1617 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1619 /* program the stream LVI (last valid index) of the BDL */
1620 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1622 /* program the BDL address */
1623 /* lower BDL address */
1624 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1625 /* upper BDL address */
1626 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1628 /* enable the position buffer */
1629 if (chip->position_fix[0] != POS_FIX_LPIB ||
1630 chip->position_fix[1] != POS_FIX_LPIB) {
1631 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1632 azx_writel(chip, DPLBASE,
1633 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1636 /* set the interrupt enable bits in the descriptor control register */
1637 azx_sd_writel(azx_dev, SD_CTL,
1638 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1644 * Probe the given codec address
1646 static int probe_codec(struct azx *chip, int addr)
1648 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1649 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1652 mutex_lock(&chip->bus->cmd_mutex);
1654 azx_send_cmd(chip->bus, cmd);
1655 res = azx_get_response(chip->bus, addr);
1657 mutex_unlock(&chip->bus->cmd_mutex);
1660 snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1664 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1665 struct hda_pcm *cpcm);
1666 static void azx_stop_chip(struct azx *chip);
1668 static void azx_bus_reset(struct hda_bus *bus)
1670 struct azx *chip = bus->private_data;
1673 azx_stop_chip(chip);
1674 azx_init_chip(chip, 1);
1676 if (chip->initialized) {
1678 list_for_each_entry(p, &chip->pcm_list, list)
1679 snd_pcm_suspend_all(p->pcm);
1680 snd_hda_suspend(chip->bus);
1681 snd_hda_resume(chip->bus);
1687 static int get_jackpoll_interval(struct azx *chip)
1689 int i = jackpoll_ms[chip->dev_index];
1693 if (i < 50 || i > 60000)
1696 j = msecs_to_jiffies(i);
1698 snd_printk(KERN_WARNING SFX
1699 "jackpoll_ms value out of range: %d\n", i);
1704 * Codec initialization
1707 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1708 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1709 [AZX_DRIVER_NVIDIA] = 8,
1710 [AZX_DRIVER_TERA] = 1,
1713 static int azx_codec_create(struct azx *chip, const char *model)
1715 struct hda_bus_template bus_temp;
1719 memset(&bus_temp, 0, sizeof(bus_temp));
1720 bus_temp.private_data = chip;
1721 bus_temp.modelname = model;
1722 bus_temp.pci = chip->pci;
1723 bus_temp.ops.command = azx_send_cmd;
1724 bus_temp.ops.get_response = azx_get_response;
1725 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1726 bus_temp.ops.bus_reset = azx_bus_reset;
1728 bus_temp.power_save = &power_save;
1729 bus_temp.ops.pm_notify = azx_power_notify;
1731 #ifdef CONFIG_SND_HDA_DSP_LOADER
1732 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1733 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1734 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1737 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1741 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1742 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1743 chip->bus->needs_damn_long_delay = 1;
1747 max_slots = azx_max_codecs[chip->driver_type];
1749 max_slots = AZX_DEFAULT_CODECS;
1751 /* First try to probe all given codec slots */
1752 for (c = 0; c < max_slots; c++) {
1753 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1754 if (probe_codec(chip, c) < 0) {
1755 /* Some BIOSen give you wrong codec addresses
1758 snd_printk(KERN_WARNING SFX
1759 "%s: Codec #%d probe error; "
1760 "disabling it...\n", pci_name(chip->pci), c);
1761 chip->codec_mask &= ~(1 << c);
1762 /* More badly, accessing to a non-existing
1763 * codec often screws up the controller chip,
1764 * and disturbs the further communications.
1765 * Thus if an error occurs during probing,
1766 * better to reset the controller chip to
1767 * get back to the sanity state.
1769 azx_stop_chip(chip);
1770 azx_init_chip(chip, 1);
1775 /* AMD chipsets often cause the communication stalls upon certain
1776 * sequence like the pin-detection. It seems that forcing the synced
1777 * access works around the stall. Grrr...
1779 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1780 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1781 pci_name(chip->pci));
1782 chip->bus->sync_write = 1;
1783 chip->bus->allow_bus_reset = 1;
1786 /* Then create codec instances */
1787 for (c = 0; c < max_slots; c++) {
1788 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1789 struct hda_codec *codec;
1790 err = snd_hda_codec_new(chip->bus, c, &codec);
1793 codec->jackpoll_interval = get_jackpoll_interval(chip);
1794 codec->beep_mode = chip->beep_mode;
1799 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1805 /* configure each codec instance */
1806 static int azx_codec_configure(struct azx *chip)
1808 struct hda_codec *codec;
1809 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1810 snd_hda_codec_configure(codec);
1820 /* assign a stream for the PCM */
1821 static inline struct azx_dev *
1822 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1825 struct azx_dev *res = NULL;
1826 /* make a non-zero unique key for the substream */
1827 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1828 (substream->stream + 1);
1830 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1831 dev = chip->playback_index_offset;
1832 nums = chip->playback_streams;
1834 dev = chip->capture_index_offset;
1835 nums = chip->capture_streams;
1837 for (i = 0; i < nums; i++, dev++) {
1838 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1840 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1842 if (res->assigned_key == key) {
1844 res->assigned_key = key;
1845 dsp_unlock(azx_dev);
1849 dsp_unlock(azx_dev);
1854 res->assigned_key = key;
1860 /* release the assigned stream */
1861 static inline void azx_release_device(struct azx_dev *azx_dev)
1863 azx_dev->opened = 0;
1866 static cycle_t azx_cc_read(const struct cyclecounter *cc)
1868 struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
1869 struct snd_pcm_substream *substream = azx_dev->substream;
1870 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1871 struct azx *chip = apcm->chip;
1873 return azx_readl(chip, WALLCLK);
1876 static void azx_timecounter_init(struct snd_pcm_substream *substream,
1877 bool force, cycle_t last)
1879 struct azx_dev *azx_dev = get_azx_dev(substream);
1880 struct timecounter *tc = &azx_dev->azx_tc;
1881 struct cyclecounter *cc = &azx_dev->azx_cc;
1884 cc->read = azx_cc_read;
1885 cc->mask = CLOCKSOURCE_MASK(32);
1888 * Converting from 24 MHz to ns means applying a 125/3 factor.
1889 * To avoid any saturation issues in intermediate operations,
1890 * the 125 factor is applied first. The division is applied
1891 * last after reading the timecounter value.
1892 * Applying the 1/3 factor as part of the multiplication
1893 * requires at least 20 bits for a decent precision, however
1894 * overflows occur after about 4 hours or less, not a option.
1897 cc->mult = 125; /* saturation after 195 years */
1900 nsec = 0; /* audio time is elapsed time since trigger */
1901 timecounter_init(tc, cc, nsec);
1904 * force timecounter to use predefined value,
1905 * used for synchronized starts
1907 tc->cycle_last = last;
1910 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
1913 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1914 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1915 u64 codec_frames, codec_nsecs;
1917 if (!hinfo->ops.get_delay)
1920 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
1921 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1922 substream->runtime->rate);
1924 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1925 return nsec + codec_nsecs;
1927 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1930 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
1931 struct timespec *ts)
1933 struct azx_dev *azx_dev = get_azx_dev(substream);
1936 nsec = timecounter_read(&azx_dev->azx_tc);
1937 nsec = div_u64(nsec, 3); /* can be optimized */
1938 nsec = azx_adjust_codec_delay(substream, nsec);
1940 *ts = ns_to_timespec(nsec);
1945 static struct snd_pcm_hardware azx_pcm_hw = {
1946 .info = (SNDRV_PCM_INFO_MMAP |
1947 SNDRV_PCM_INFO_INTERLEAVED |
1948 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1949 SNDRV_PCM_INFO_MMAP_VALID |
1950 /* No full-resume yet implemented */
1951 /* SNDRV_PCM_INFO_RESUME |*/
1952 SNDRV_PCM_INFO_PAUSE |
1953 SNDRV_PCM_INFO_SYNC_START |
1954 SNDRV_PCM_INFO_HAS_WALL_CLOCK |
1955 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1956 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1957 .rates = SNDRV_PCM_RATE_48000,
1962 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1963 .period_bytes_min = 128,
1964 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1966 .periods_max = AZX_MAX_FRAG,
1970 static int azx_pcm_open(struct snd_pcm_substream *substream)
1972 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1973 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1974 struct azx *chip = apcm->chip;
1975 struct azx_dev *azx_dev;
1976 struct snd_pcm_runtime *runtime = substream->runtime;
1977 unsigned long flags;
1981 mutex_lock(&chip->open_mutex);
1982 azx_dev = azx_assign_device(chip, substream);
1983 if (azx_dev == NULL) {
1984 mutex_unlock(&chip->open_mutex);
1987 runtime->hw = azx_pcm_hw;
1988 runtime->hw.channels_min = hinfo->channels_min;
1989 runtime->hw.channels_max = hinfo->channels_max;
1990 runtime->hw.formats = hinfo->formats;
1991 runtime->hw.rates = hinfo->rates;
1992 snd_pcm_limit_hw_rates(runtime);
1993 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1995 /* avoid wrap-around with wall-clock */
1996 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2000 if (chip->align_buffer_size)
2001 /* constrain buffer sizes to be multiple of 128
2002 bytes. This is more efficient in terms of memory
2003 access but isn't required by the HDA spec and
2004 prevents users from specifying exact period/buffer
2005 sizes. For example for 44.1kHz, a period size set
2006 to 20ms will be rounded to 19.59ms. */
2009 /* Don't enforce steps on buffer sizes, still need to
2010 be multiple of 4 bytes (HDA spec). Tested on Intel
2011 HDA controllers, may not work on all devices where
2012 option needs to be disabled */
2015 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2017 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2019 snd_hda_power_up_d3wait(apcm->codec);
2020 err = hinfo->ops.open(hinfo, apcm->codec, substream);
2022 azx_release_device(azx_dev);
2023 snd_hda_power_down(apcm->codec);
2024 mutex_unlock(&chip->open_mutex);
2027 snd_pcm_limit_hw_rates(runtime);
2029 if (snd_BUG_ON(!runtime->hw.channels_min) ||
2030 snd_BUG_ON(!runtime->hw.channels_max) ||
2031 snd_BUG_ON(!runtime->hw.formats) ||
2032 snd_BUG_ON(!runtime->hw.rates)) {
2033 azx_release_device(azx_dev);
2034 hinfo->ops.close(hinfo, apcm->codec, substream);
2035 snd_hda_power_down(apcm->codec);
2036 mutex_unlock(&chip->open_mutex);
2040 /* disable WALLCLOCK timestamps for capture streams
2041 until we figure out how to handle digital inputs */
2042 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2043 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2045 spin_lock_irqsave(&chip->reg_lock, flags);
2046 azx_dev->substream = substream;
2047 azx_dev->running = 0;
2048 spin_unlock_irqrestore(&chip->reg_lock, flags);
2050 runtime->private_data = azx_dev;
2051 snd_pcm_set_sync(substream);
2052 mutex_unlock(&chip->open_mutex);
2056 static int azx_pcm_close(struct snd_pcm_substream *substream)
2058 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2059 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2060 struct azx *chip = apcm->chip;
2061 struct azx_dev *azx_dev = get_azx_dev(substream);
2062 unsigned long flags;
2064 mutex_lock(&chip->open_mutex);
2065 spin_lock_irqsave(&chip->reg_lock, flags);
2066 azx_dev->substream = NULL;
2067 azx_dev->running = 0;
2068 spin_unlock_irqrestore(&chip->reg_lock, flags);
2069 azx_release_device(azx_dev);
2070 hinfo->ops.close(hinfo, apcm->codec, substream);
2071 snd_hda_power_down(apcm->codec);
2072 mutex_unlock(&chip->open_mutex);
2076 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2077 struct snd_pcm_hw_params *hw_params)
2079 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2080 struct azx *chip = apcm->chip;
2081 struct azx_dev *azx_dev = get_azx_dev(substream);
2085 if (dsp_is_locked(azx_dev)) {
2090 mark_runtime_wc(chip, azx_dev, substream, false);
2091 azx_dev->bufsize = 0;
2092 azx_dev->period_bytes = 0;
2093 azx_dev->format_val = 0;
2094 ret = snd_pcm_lib_malloc_pages(substream,
2095 params_buffer_bytes(hw_params));
2098 mark_runtime_wc(chip, azx_dev, substream, true);
2100 dsp_unlock(azx_dev);
2104 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2106 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2107 struct azx_dev *azx_dev = get_azx_dev(substream);
2108 struct azx *chip = apcm->chip;
2109 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2111 /* reset BDL address */
2113 if (!dsp_is_locked(azx_dev)) {
2114 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2115 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2116 azx_sd_writel(azx_dev, SD_CTL, 0);
2117 azx_dev->bufsize = 0;
2118 azx_dev->period_bytes = 0;
2119 azx_dev->format_val = 0;
2122 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2124 mark_runtime_wc(chip, azx_dev, substream, false);
2125 azx_dev->prepared = 0;
2126 dsp_unlock(azx_dev);
2127 return snd_pcm_lib_free_pages(substream);
2130 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2132 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2133 struct azx *chip = apcm->chip;
2134 struct azx_dev *azx_dev = get_azx_dev(substream);
2135 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2136 struct snd_pcm_runtime *runtime = substream->runtime;
2137 unsigned int bufsize, period_bytes, format_val, stream_tag;
2139 struct hda_spdif_out *spdif =
2140 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2141 unsigned short ctls = spdif ? spdif->ctls : 0;
2144 if (dsp_is_locked(azx_dev)) {
2149 azx_stream_reset(chip, azx_dev);
2150 format_val = snd_hda_calc_stream_format(runtime->rate,
2156 snd_printk(KERN_ERR SFX
2157 "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2158 pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2163 bufsize = snd_pcm_lib_buffer_bytes(substream);
2164 period_bytes = snd_pcm_lib_period_bytes(substream);
2166 snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2167 pci_name(chip->pci), bufsize, format_val);
2169 if (bufsize != azx_dev->bufsize ||
2170 period_bytes != azx_dev->period_bytes ||
2171 format_val != azx_dev->format_val ||
2172 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2173 azx_dev->bufsize = bufsize;
2174 azx_dev->period_bytes = period_bytes;
2175 azx_dev->format_val = format_val;
2176 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2177 err = azx_setup_periods(chip, substream, azx_dev);
2182 /* wallclk has 24Mhz clock source */
2183 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2184 runtime->rate) * 1000);
2185 azx_setup_controller(chip, azx_dev);
2186 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2187 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2189 azx_dev->fifo_size = 0;
2191 stream_tag = azx_dev->stream_tag;
2192 /* CA-IBG chips need the playback stream starting from 1 */
2193 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2194 stream_tag > chip->capture_streams)
2195 stream_tag -= chip->capture_streams;
2196 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2197 azx_dev->format_val, substream);
2201 azx_dev->prepared = 1;
2202 dsp_unlock(azx_dev);
2206 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2208 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2209 struct azx *chip = apcm->chip;
2210 struct azx_dev *azx_dev;
2211 struct snd_pcm_substream *s;
2212 int rstart = 0, start, nsync = 0, sbits = 0;
2215 azx_dev = get_azx_dev(substream);
2216 trace_azx_pcm_trigger(chip, azx_dev, cmd);
2218 if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2222 case SNDRV_PCM_TRIGGER_START:
2224 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2225 case SNDRV_PCM_TRIGGER_RESUME:
2228 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2229 case SNDRV_PCM_TRIGGER_SUSPEND:
2230 case SNDRV_PCM_TRIGGER_STOP:
2237 snd_pcm_group_for_each_entry(s, substream) {
2238 if (s->pcm->card != substream->pcm->card)
2240 azx_dev = get_azx_dev(s);
2241 sbits |= 1 << azx_dev->index;
2243 snd_pcm_trigger_done(s, substream);
2246 spin_lock(&chip->reg_lock);
2248 /* first, set SYNC bits of corresponding streams */
2249 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2250 azx_writel(chip, OLD_SSYNC,
2251 azx_readl(chip, OLD_SSYNC) | sbits);
2253 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2255 snd_pcm_group_for_each_entry(s, substream) {
2256 if (s->pcm->card != substream->pcm->card)
2258 azx_dev = get_azx_dev(s);
2260 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2262 azx_dev->start_wallclk -=
2263 azx_dev->period_wallclk;
2264 azx_stream_start(chip, azx_dev);
2266 azx_stream_stop(chip, azx_dev);
2268 azx_dev->running = start;
2270 spin_unlock(&chip->reg_lock);
2272 /* wait until all FIFOs get ready */
2273 for (timeout = 5000; timeout; timeout--) {
2275 snd_pcm_group_for_each_entry(s, substream) {
2276 if (s->pcm->card != substream->pcm->card)
2278 azx_dev = get_azx_dev(s);
2279 if (!(azx_sd_readb(azx_dev, SD_STS) &
2288 /* wait until all RUN bits are cleared */
2289 for (timeout = 5000; timeout; timeout--) {
2291 snd_pcm_group_for_each_entry(s, substream) {
2292 if (s->pcm->card != substream->pcm->card)
2294 azx_dev = get_azx_dev(s);
2295 if (azx_sd_readb(azx_dev, SD_CTL) &
2304 spin_lock(&chip->reg_lock);
2305 /* reset SYNC bits */
2306 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2307 azx_writel(chip, OLD_SSYNC,
2308 azx_readl(chip, OLD_SSYNC) & ~sbits);
2310 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2312 azx_timecounter_init(substream, 0, 0);
2316 /* same start cycle for master and group */
2317 azx_dev = get_azx_dev(substream);
2318 cycle_last = azx_dev->azx_tc.cycle_last;
2320 snd_pcm_group_for_each_entry(s, substream) {
2321 if (s->pcm->card != substream->pcm->card)
2323 azx_timecounter_init(s, 1, cycle_last);
2327 spin_unlock(&chip->reg_lock);
2331 /* get the current DMA position with correction on VIA chips */
2332 static unsigned int azx_via_get_position(struct azx *chip,
2333 struct azx_dev *azx_dev)
2335 unsigned int link_pos, mini_pos, bound_pos;
2336 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2337 unsigned int fifo_size;
2339 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2340 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2341 /* Playback, no problem using link position */
2347 * use mod to get the DMA position just like old chipset
2349 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2350 mod_dma_pos %= azx_dev->period_bytes;
2352 /* azx_dev->fifo_size can't get FIFO size of in stream.
2353 * Get from base address + offset.
2355 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2357 if (azx_dev->insufficient) {
2358 /* Link position never gather than FIFO size */
2359 if (link_pos <= fifo_size)
2362 azx_dev->insufficient = 0;
2365 if (link_pos <= fifo_size)
2366 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2368 mini_pos = link_pos - fifo_size;
2370 /* Find nearest previous boudary */
2371 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2372 mod_link_pos = link_pos % azx_dev->period_bytes;
2373 if (mod_link_pos >= fifo_size)
2374 bound_pos = link_pos - mod_link_pos;
2375 else if (mod_dma_pos >= mod_mini_pos)
2376 bound_pos = mini_pos - mod_mini_pos;
2378 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2379 if (bound_pos >= azx_dev->bufsize)
2383 /* Calculate real DMA position we want */
2384 return bound_pos + mod_dma_pos;
2387 static unsigned int azx_get_position(struct azx *chip,
2388 struct azx_dev *azx_dev,
2391 struct snd_pcm_substream *substream = azx_dev->substream;
2392 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2394 int stream = substream->stream;
2395 struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2398 switch (chip->position_fix[stream]) {
2401 pos = azx_sd_readl(azx_dev, SD_LPIB);
2403 case POS_FIX_VIACOMBO:
2404 pos = azx_via_get_position(chip, azx_dev);
2407 /* use the position buffer */
2408 pos = le32_to_cpu(*azx_dev->posbuf);
2409 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2410 if (!pos || pos == (u32)-1) {
2412 "hda-intel: Invalid position buffer, "
2413 "using LPIB read method instead.\n");
2414 chip->position_fix[stream] = POS_FIX_LPIB;
2415 pos = azx_sd_readl(azx_dev, SD_LPIB);
2417 chip->position_fix[stream] = POS_FIX_POSBUF;
2422 if (pos >= azx_dev->bufsize)
2425 /* calculate runtime delay from LPIB */
2426 if (substream->runtime &&
2427 chip->position_fix[stream] == POS_FIX_POSBUF &&
2428 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2429 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2430 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2431 delay = pos - lpib_pos;
2433 delay = lpib_pos - pos;
2435 delay += azx_dev->bufsize;
2436 if (delay >= azx_dev->period_bytes) {
2437 snd_printk(KERN_WARNING SFX
2438 "%s: Unstable LPIB (%d >= %d); "
2439 "disabling LPIB delay counting\n",
2440 pci_name(chip->pci), delay, azx_dev->period_bytes);
2442 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2444 delay = bytes_to_frames(substream->runtime, delay);
2447 if (substream->runtime) {
2448 if (hinfo->ops.get_delay)
2449 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2451 substream->runtime->delay = delay;
2454 trace_azx_get_position(chip, azx_dev, pos, delay);
2458 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2460 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2461 struct azx *chip = apcm->chip;
2462 struct azx_dev *azx_dev = get_azx_dev(substream);
2463 return bytes_to_frames(substream->runtime,
2464 azx_get_position(chip, azx_dev, false));
2468 * Check whether the current DMA position is acceptable for updating
2469 * periods. Returns non-zero if it's OK.
2471 * Many HD-audio controllers appear pretty inaccurate about
2472 * the update-IRQ timing. The IRQ is issued before actually the
2473 * data is processed. So, we need to process it afterwords in a
2476 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2481 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2482 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2483 return -1; /* bogus (too early) interrupt */
2485 pos = azx_get_position(chip, azx_dev, true);
2487 if (WARN_ONCE(!azx_dev->period_bytes,
2488 "hda-intel: zero azx_dev->period_bytes"))
2489 return -1; /* this shouldn't happen! */
2490 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2491 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2492 /* NG - it's below the first next period boundary */
2493 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2494 azx_dev->start_wallclk += wallclk;
2495 return 1; /* OK, it's fine */
2499 * The work for pending PCM period updates.
2501 static void azx_irq_pending_work(struct work_struct *work)
2503 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2506 if (!chip->irq_pending_warned) {
2508 "hda-intel: IRQ timing workaround is activated "
2509 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2510 chip->card->number);
2511 chip->irq_pending_warned = 1;
2516 spin_lock_irq(&chip->reg_lock);
2517 for (i = 0; i < chip->num_streams; i++) {
2518 struct azx_dev *azx_dev = &chip->azx_dev[i];
2519 if (!azx_dev->irq_pending ||
2520 !azx_dev->substream ||
2523 ok = azx_position_ok(chip, azx_dev);
2525 azx_dev->irq_pending = 0;
2526 spin_unlock(&chip->reg_lock);
2527 snd_pcm_period_elapsed(azx_dev->substream);
2528 spin_lock(&chip->reg_lock);
2529 } else if (ok < 0) {
2530 pending = 0; /* too early */
2534 spin_unlock_irq(&chip->reg_lock);
2541 /* clear irq_pending flags and assure no on-going workq */
2542 static void azx_clear_irq_pending(struct azx *chip)
2546 spin_lock_irq(&chip->reg_lock);
2547 for (i = 0; i < chip->num_streams; i++)
2548 chip->azx_dev[i].irq_pending = 0;
2549 spin_unlock_irq(&chip->reg_lock);
2553 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2554 struct vm_area_struct *area)
2556 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2557 struct azx *chip = apcm->chip;
2558 if (!azx_snoop(chip))
2559 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2560 return snd_pcm_lib_default_mmap(substream, area);
2563 #define azx_pcm_mmap NULL
2566 static struct snd_pcm_ops azx_pcm_ops = {
2567 .open = azx_pcm_open,
2568 .close = azx_pcm_close,
2569 .ioctl = snd_pcm_lib_ioctl,
2570 .hw_params = azx_pcm_hw_params,
2571 .hw_free = azx_pcm_hw_free,
2572 .prepare = azx_pcm_prepare,
2573 .trigger = azx_pcm_trigger,
2574 .pointer = azx_pcm_pointer,
2575 .wall_clock = azx_get_wallclock_tstamp,
2576 .mmap = azx_pcm_mmap,
2577 .page = snd_pcm_sgbuf_ops_page,
2580 static void azx_pcm_free(struct snd_pcm *pcm)
2582 struct azx_pcm *apcm = pcm->private_data;
2584 list_del(&apcm->list);
2589 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2592 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2593 struct hda_pcm *cpcm)
2595 struct azx *chip = bus->private_data;
2596 struct snd_pcm *pcm;
2597 struct azx_pcm *apcm;
2598 int pcm_dev = cpcm->device;
2602 list_for_each_entry(apcm, &chip->pcm_list, list) {
2603 if (apcm->pcm->device == pcm_dev) {
2604 snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2605 pci_name(chip->pci), pcm_dev);
2609 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2610 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2611 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2615 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2616 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2621 apcm->codec = codec;
2622 pcm->private_data = apcm;
2623 pcm->private_free = azx_pcm_free;
2624 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2625 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2626 list_add_tail(&apcm->list, &chip->pcm_list);
2628 for (s = 0; s < 2; s++) {
2629 apcm->hinfo[s] = &cpcm->stream[s];
2630 if (cpcm->stream[s].substreams)
2631 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2633 /* buffer pre-allocation */
2634 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2635 if (size > MAX_PREALLOC_SIZE)
2636 size = MAX_PREALLOC_SIZE;
2637 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2638 snd_dma_pci_data(chip->pci),
2639 size, MAX_PREALLOC_SIZE);
2644 * mixer creation - all stuff is implemented in hda module
2646 static int azx_mixer_create(struct azx *chip)
2648 return snd_hda_build_controls(chip->bus);
2653 * initialize SD streams
2655 static int azx_init_stream(struct azx *chip)
2659 /* initialize each stream (aka device)
2660 * assign the starting bdl address to each stream (device)
2663 for (i = 0; i < chip->num_streams; i++) {
2664 struct azx_dev *azx_dev = &chip->azx_dev[i];
2665 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2666 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2667 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2668 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2669 azx_dev->sd_int_sta_mask = 1 << i;
2670 /* stream tag: must be non-zero and unique */
2672 azx_dev->stream_tag = i + 1;
2678 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2680 if (request_irq(chip->pci->irq, azx_interrupt,
2681 chip->msi ? 0 : IRQF_SHARED,
2682 KBUILD_MODNAME, chip)) {
2683 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2684 "disabling device\n", chip->pci->irq);
2686 snd_card_disconnect(chip->card);
2689 chip->irq = chip->pci->irq;
2690 pci_intx(chip->pci, !chip->msi);
2695 static void azx_stop_chip(struct azx *chip)
2697 if (!chip->initialized)
2700 /* disable interrupts */
2701 azx_int_disable(chip);
2702 azx_int_clear(chip);
2704 /* disable CORB/RIRB */
2705 azx_free_cmd_io(chip);
2707 /* disable position buffer */
2708 azx_writel(chip, DPLBASE, 0);
2709 azx_writel(chip, DPUBASE, 0);
2711 chip->initialized = 0;
2714 #ifdef CONFIG_SND_HDA_DSP_LOADER
2716 * DSP loading code (e.g. for CA0132)
2719 /* use the first stream for loading DSP */
2720 static struct azx_dev *
2721 azx_get_dsp_loader_dev(struct azx *chip)
2723 return &chip->azx_dev[chip->playback_index_offset];
2726 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2727 unsigned int byte_size,
2728 struct snd_dma_buffer *bufp)
2731 struct azx *chip = bus->private_data;
2732 struct azx_dev *azx_dev;
2735 azx_dev = azx_get_dsp_loader_dev(chip);
2738 spin_lock_irq(&chip->reg_lock);
2739 if (azx_dev->running || azx_dev->locked) {
2740 spin_unlock_irq(&chip->reg_lock);
2744 azx_dev->prepared = 0;
2745 chip->saved_azx_dev = *azx_dev;
2746 azx_dev->locked = 1;
2747 spin_unlock_irq(&chip->reg_lock);
2749 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2750 snd_dma_pci_data(chip->pci),
2755 mark_pages_wc(chip, bufp, true);
2756 azx_dev->bufsize = byte_size;
2757 azx_dev->period_bytes = byte_size;
2758 azx_dev->format_val = format;
2760 azx_stream_reset(chip, azx_dev);
2762 /* reset BDL address */
2763 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2764 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2767 bdl = (u32 *)azx_dev->bdl.area;
2768 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2772 azx_setup_controller(chip, azx_dev);
2773 dsp_unlock(azx_dev);
2774 return azx_dev->stream_tag;
2777 mark_pages_wc(chip, bufp, false);
2778 snd_dma_free_pages(bufp);
2780 spin_lock_irq(&chip->reg_lock);
2781 if (azx_dev->opened)
2782 *azx_dev = chip->saved_azx_dev;
2783 azx_dev->locked = 0;
2784 spin_unlock_irq(&chip->reg_lock);
2786 dsp_unlock(azx_dev);
2790 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2792 struct azx *chip = bus->private_data;
2793 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2796 azx_stream_start(chip, azx_dev);
2798 azx_stream_stop(chip, azx_dev);
2799 azx_dev->running = start;
2802 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2803 struct snd_dma_buffer *dmab)
2805 struct azx *chip = bus->private_data;
2806 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2808 if (!dmab->area || !azx_dev->locked)
2812 /* reset BDL address */
2813 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2814 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2815 azx_sd_writel(azx_dev, SD_CTL, 0);
2816 azx_dev->bufsize = 0;
2817 azx_dev->period_bytes = 0;
2818 azx_dev->format_val = 0;
2820 mark_pages_wc(chip, dmab, false);
2821 snd_dma_free_pages(dmab);
2824 spin_lock_irq(&chip->reg_lock);
2825 if (azx_dev->opened)
2826 *azx_dev = chip->saved_azx_dev;
2827 azx_dev->locked = 0;
2828 spin_unlock_irq(&chip->reg_lock);
2829 dsp_unlock(azx_dev);
2831 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2834 /* power-up/down the controller */
2835 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2837 struct azx *chip = bus->private_data;
2839 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2843 pm_runtime_get_sync(&chip->pci->dev);
2845 pm_runtime_put_sync(&chip->pci->dev);
2848 static DEFINE_MUTEX(card_list_lock);
2849 static LIST_HEAD(card_list);
2851 static void azx_add_card_list(struct azx *chip)
2853 mutex_lock(&card_list_lock);
2854 list_add(&chip->list, &card_list);
2855 mutex_unlock(&card_list_lock);
2858 static void azx_del_card_list(struct azx *chip)
2860 mutex_lock(&card_list_lock);
2861 list_del_init(&chip->list);
2862 mutex_unlock(&card_list_lock);
2865 /* trigger power-save check at writing parameter */
2866 static int param_set_xint(const char *val, const struct kernel_param *kp)
2869 struct hda_codec *c;
2870 int prev = power_save;
2871 int ret = param_set_int(val, kp);
2873 if (ret || prev == power_save)
2876 mutex_lock(&card_list_lock);
2877 list_for_each_entry(chip, &card_list, list) {
2878 if (!chip->bus || chip->disabled)
2880 list_for_each_entry(c, &chip->bus->codec_list, list)
2881 snd_hda_power_sync(c);
2883 mutex_unlock(&card_list_lock);
2887 #define azx_add_card_list(chip) /* NOP */
2888 #define azx_del_card_list(chip) /* NOP */
2889 #endif /* CONFIG_PM */
2891 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
2895 static int azx_suspend(struct device *dev)
2897 struct pci_dev *pci = to_pci_dev(dev);
2898 struct snd_card *card = dev_get_drvdata(dev);
2899 struct azx *chip = card->private_data;
2905 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2906 azx_clear_irq_pending(chip);
2907 list_for_each_entry(p, &chip->pcm_list, list)
2908 snd_pcm_suspend_all(p->pcm);
2909 if (chip->initialized)
2910 snd_hda_suspend(chip->bus);
2911 azx_stop_chip(chip);
2912 azx_enter_link_reset(chip);
2913 if (chip->irq >= 0) {
2914 free_irq(chip->irq, chip);
2918 pci_disable_msi(chip->pci);
2919 pci_disable_device(pci);
2920 pci_save_state(pci);
2921 pci_set_power_state(pci, PCI_D3hot);
2925 static int azx_resume(struct device *dev)
2927 struct pci_dev *pci = to_pci_dev(dev);
2928 struct snd_card *card = dev_get_drvdata(dev);
2929 struct azx *chip = card->private_data;
2934 pci_set_power_state(pci, PCI_D0);
2935 pci_restore_state(pci);
2936 if (pci_enable_device(pci) < 0) {
2937 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2938 "disabling device\n");
2939 snd_card_disconnect(card);
2942 pci_set_master(pci);
2944 if (pci_enable_msi(pci) < 0)
2946 if (azx_acquire_irq(chip, 1) < 0)
2950 azx_init_chip(chip, 1);
2952 snd_hda_resume(chip->bus);
2953 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2956 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
2958 #ifdef CONFIG_PM_RUNTIME
2959 static int azx_runtime_suspend(struct device *dev)
2961 struct snd_card *card = dev_get_drvdata(dev);
2962 struct azx *chip = card->private_data;
2964 azx_stop_chip(chip);
2965 azx_enter_link_reset(chip);
2966 azx_clear_irq_pending(chip);
2970 static int azx_runtime_resume(struct device *dev)
2972 struct snd_card *card = dev_get_drvdata(dev);
2973 struct azx *chip = card->private_data;
2976 azx_init_chip(chip, 1);
2980 static int azx_runtime_idle(struct device *dev)
2982 struct snd_card *card = dev_get_drvdata(dev);
2983 struct azx *chip = card->private_data;
2985 if (!power_save_controller ||
2986 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2992 #endif /* CONFIG_PM_RUNTIME */
2995 static const struct dev_pm_ops azx_pm = {
2996 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
2997 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
3000 #define AZX_PM_OPS &azx_pm
3002 #define AZX_PM_OPS NULL
3003 #endif /* CONFIG_PM */
3007 * reboot notifier for hang-up problem at power-down
3009 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3011 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
3012 snd_hda_bus_reboot_notify(chip->bus);
3013 azx_stop_chip(chip);
3017 static void azx_notifier_register(struct azx *chip)
3019 chip->reboot_notifier.notifier_call = azx_halt;
3020 register_reboot_notifier(&chip->reboot_notifier);
3023 static void azx_notifier_unregister(struct azx *chip)
3025 if (chip->reboot_notifier.notifier_call)
3026 unregister_reboot_notifier(&chip->reboot_notifier);
3029 static int azx_first_init(struct azx *chip);
3030 static int azx_probe_continue(struct azx *chip);
3032 #ifdef SUPPORT_VGA_SWITCHEROO
3033 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
3035 static void azx_vs_set_state(struct pci_dev *pci,
3036 enum vga_switcheroo_state state)
3038 struct snd_card *card = pci_get_drvdata(pci);
3039 struct azx *chip = card->private_data;
3042 wait_for_completion(&chip->probe_wait);
3043 if (chip->init_failed)
3046 disabled = (state == VGA_SWITCHEROO_OFF);
3047 if (chip->disabled == disabled)
3051 chip->disabled = disabled;
3053 snd_printk(KERN_INFO SFX
3054 "%s: Start delayed initialization\n",
3055 pci_name(chip->pci));
3056 if (azx_first_init(chip) < 0 ||
3057 azx_probe_continue(chip) < 0) {
3058 snd_printk(KERN_ERR SFX
3059 "%s: initialization error\n",
3060 pci_name(chip->pci));
3061 chip->init_failed = true;
3065 snd_printk(KERN_INFO SFX
3066 "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3067 disabled ? "Disabling" : "Enabling");
3069 azx_suspend(&pci->dev);
3070 chip->disabled = true;
3071 if (snd_hda_lock_devices(chip->bus))
3072 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3073 pci_name(chip->pci));
3075 snd_hda_unlock_devices(chip->bus);
3076 chip->disabled = false;
3077 azx_resume(&pci->dev);
3082 static bool azx_vs_can_switch(struct pci_dev *pci)
3084 struct snd_card *card = pci_get_drvdata(pci);
3085 struct azx *chip = card->private_data;
3087 wait_for_completion(&chip->probe_wait);
3088 if (chip->init_failed)
3090 if (chip->disabled || !chip->bus)
3092 if (snd_hda_lock_devices(chip->bus))
3094 snd_hda_unlock_devices(chip->bus);
3098 static void init_vga_switcheroo(struct azx *chip)
3100 struct pci_dev *p = get_bound_vga(chip->pci);
3102 snd_printk(KERN_INFO SFX
3103 "%s: Handle VGA-switcheroo audio client\n",
3104 pci_name(chip->pci));
3105 chip->use_vga_switcheroo = 1;
3110 static const struct vga_switcheroo_client_ops azx_vs_ops = {
3111 .set_gpu_state = azx_vs_set_state,
3112 .can_switch = azx_vs_can_switch,
3115 static int register_vga_switcheroo(struct azx *chip)
3119 if (!chip->use_vga_switcheroo)
3121 /* FIXME: currently only handling DIS controller
3122 * is there any machine with two switchable HDMI audio controllers?
3124 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3129 chip->vga_switcheroo_registered = 1;
3133 #define init_vga_switcheroo(chip) /* NOP */
3134 #define register_vga_switcheroo(chip) 0
3135 #define check_hdmi_disabled(pci) false
3136 #endif /* SUPPORT_VGA_SWITCHER */
3141 static int azx_free(struct azx *chip)
3145 azx_del_card_list(chip);
3147 azx_notifier_unregister(chip);
3149 chip->init_failed = 1; /* to be sure */
3150 complete_all(&chip->probe_wait);
3152 if (use_vga_switcheroo(chip)) {
3153 if (chip->disabled && chip->bus)
3154 snd_hda_unlock_devices(chip->bus);
3155 if (chip->vga_switcheroo_registered)
3156 vga_switcheroo_unregister_client(chip->pci);
3159 if (chip->initialized) {
3160 azx_clear_irq_pending(chip);
3161 for (i = 0; i < chip->num_streams; i++)
3162 azx_stream_stop(chip, &chip->azx_dev[i]);
3163 azx_stop_chip(chip);
3167 free_irq(chip->irq, (void*)chip);
3169 pci_disable_msi(chip->pci);
3170 if (chip->remap_addr)
3171 iounmap(chip->remap_addr);
3173 if (chip->azx_dev) {
3174 for (i = 0; i < chip->num_streams; i++)
3175 if (chip->azx_dev[i].bdl.area) {
3176 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
3177 snd_dma_free_pages(&chip->azx_dev[i].bdl);
3180 if (chip->rb.area) {
3181 mark_pages_wc(chip, &chip->rb, false);
3182 snd_dma_free_pages(&chip->rb);
3184 if (chip->posbuf.area) {
3185 mark_pages_wc(chip, &chip->posbuf, false);
3186 snd_dma_free_pages(&chip->posbuf);
3188 if (chip->region_requested)
3189 pci_release_regions(chip->pci);
3190 pci_disable_device(chip->pci);
3191 kfree(chip->azx_dev);
3192 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3194 release_firmware(chip->fw);
3201 static int azx_dev_free(struct snd_device *device)
3203 return azx_free(device->device_data);
3206 #ifdef SUPPORT_VGA_SWITCHEROO
3208 * Check of disabled HDMI controller by vga-switcheroo
3210 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3214 /* check only discrete GPU */
3215 switch (pci->vendor) {
3216 case PCI_VENDOR_ID_ATI:
3217 case PCI_VENDOR_ID_AMD:
3218 case PCI_VENDOR_ID_NVIDIA:
3219 if (pci->devfn == 1) {
3220 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3221 pci->bus->number, 0);
3223 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3233 static bool check_hdmi_disabled(struct pci_dev *pci)
3235 bool vga_inactive = false;
3236 struct pci_dev *p = get_bound_vga(pci);
3239 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3240 vga_inactive = true;
3243 return vga_inactive;
3245 #endif /* SUPPORT_VGA_SWITCHEROO */
3248 * white/black-listing for position_fix
3250 static struct snd_pci_quirk position_fix_list[] = {
3251 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3252 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3253 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3254 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3255 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3256 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3257 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3258 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3259 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3260 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3261 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3262 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3263 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3264 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3268 static int check_position_fix(struct azx *chip, int fix)
3270 const struct snd_pci_quirk *q;
3275 case POS_FIX_POSBUF:
3276 case POS_FIX_VIACOMBO:
3281 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3284 "hda_intel: position_fix set to %d "
3285 "for device %04x:%04x\n",
3286 q->value, q->subvendor, q->subdevice);
3290 /* Check VIA/ATI HD Audio Controller exist */
3291 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3292 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3293 return POS_FIX_VIACOMBO;
3295 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3296 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3297 return POS_FIX_LPIB;
3299 return POS_FIX_AUTO;
3303 * black-lists for probe_mask
3305 static struct snd_pci_quirk probe_mask_list[] = {
3306 /* Thinkpad often breaks the controller communication when accessing
3307 * to the non-working (or non-existing) modem codec slot.
3309 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3310 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3311 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3313 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3314 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3315 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3316 /* forced codec slots */
3317 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3318 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3319 /* WinFast VP200 H (Teradici) user reported broken communication */
3320 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3324 #define AZX_FORCE_CODEC_MASK 0x100
3326 static void check_probe_mask(struct azx *chip, int dev)
3328 const struct snd_pci_quirk *q;
3330 chip->codec_probe_mask = probe_mask[dev];
3331 if (chip->codec_probe_mask == -1) {
3332 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3335 "hda_intel: probe_mask set to 0x%x "
3336 "for device %04x:%04x\n",
3337 q->value, q->subvendor, q->subdevice);
3338 chip->codec_probe_mask = q->value;
3342 /* check forced option */
3343 if (chip->codec_probe_mask != -1 &&
3344 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3345 chip->codec_mask = chip->codec_probe_mask & 0xff;
3346 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3352 * white/black-list for enable_msi
3354 static struct snd_pci_quirk msi_black_list[] = {
3355 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3356 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3357 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3358 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3359 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3363 static void check_msi(struct azx *chip)
3365 const struct snd_pci_quirk *q;
3367 if (enable_msi >= 0) {
3368 chip->msi = !!enable_msi;
3371 chip->msi = 1; /* enable MSI as default */
3372 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3375 "hda_intel: msi for device %04x:%04x set to %d\n",
3376 q->subvendor, q->subdevice, q->value);
3377 chip->msi = q->value;
3381 /* NVidia chipsets seem to cause troubles with MSI */
3382 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3383 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3388 /* check the snoop mode availability */
3389 static void azx_check_snoop_available(struct azx *chip)
3391 bool snoop = chip->snoop;
3393 switch (chip->driver_type) {
3394 case AZX_DRIVER_VIA:
3395 /* force to non-snoop mode for a new VIA controller
3400 pci_read_config_byte(chip->pci, 0x42, &val);
3401 if (!(val & 0x80) && chip->pci->revision == 0x30)
3405 case AZX_DRIVER_ATIHDMI_NS:
3406 /* new ATI HDMI requires non-snoop */
3409 case AZX_DRIVER_CTHDA:
3414 if (snoop != chip->snoop) {
3415 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3416 pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3417 chip->snoop = snoop;
3424 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3425 int dev, unsigned int driver_caps,
3428 static struct snd_device_ops ops = {
3429 .dev_free = azx_dev_free,
3436 err = pci_enable_device(pci);
3440 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3442 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3443 pci_disable_device(pci);
3447 spin_lock_init(&chip->reg_lock);
3448 mutex_init(&chip->open_mutex);
3452 chip->driver_caps = driver_caps;
3453 chip->driver_type = driver_caps & 0xff;
3455 chip->dev_index = dev;
3456 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3457 INIT_LIST_HEAD(&chip->pcm_list);
3458 INIT_LIST_HEAD(&chip->list);
3459 init_vga_switcheroo(chip);
3460 init_completion(&chip->probe_wait);
3462 chip->position_fix[0] = chip->position_fix[1] =
3463 check_position_fix(chip, position_fix[dev]);
3464 /* combo mode uses LPIB for playback */
3465 if (chip->position_fix[0] == POS_FIX_COMBO) {
3466 chip->position_fix[0] = POS_FIX_LPIB;
3467 chip->position_fix[1] = POS_FIX_AUTO;
3470 check_probe_mask(chip, dev);
3472 chip->single_cmd = single_cmd;
3473 chip->snoop = hda_snoop;
3474 azx_check_snoop_available(chip);
3476 if (bdl_pos_adj[dev] < 0) {
3477 switch (chip->driver_type) {
3478 case AZX_DRIVER_ICH:
3479 case AZX_DRIVER_PCH:
3480 bdl_pos_adj[dev] = 1;
3483 bdl_pos_adj[dev] = 32;
3488 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3490 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3491 pci_name(chip->pci));
3500 static int azx_first_init(struct azx *chip)
3502 int dev = chip->dev_index;
3503 struct pci_dev *pci = chip->pci;
3504 struct snd_card *card = chip->card;
3506 unsigned short gcap;
3508 #if BITS_PER_LONG != 64
3509 /* Fix up base address on ULI M5461 */
3510 if (chip->driver_type == AZX_DRIVER_ULI) {
3512 pci_read_config_word(pci, 0x40, &tmp3);
3513 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3514 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3518 err = pci_request_regions(pci, "ICH HD audio");
3521 chip->region_requested = 1;
3523 chip->addr = pci_resource_start(pci, 0);
3524 chip->remap_addr = pci_ioremap_bar(pci, 0);
3525 if (chip->remap_addr == NULL) {
3526 snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3531 if (pci_enable_msi(pci) < 0)
3534 if (azx_acquire_irq(chip, 0) < 0)
3537 pci_set_master(pci);
3538 synchronize_irq(chip->irq);
3540 gcap = azx_readw(chip, GCAP);
3541 snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3543 /* disable SB600 64bit support for safety */
3544 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3545 struct pci_dev *p_smbus;
3546 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3547 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3550 if (p_smbus->revision < 0x30)
3551 gcap &= ~ICH6_GCAP_64OK;
3552 pci_dev_put(p_smbus);
3556 /* disable 64bit DMA address on some devices */
3557 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3558 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3559 gcap &= ~ICH6_GCAP_64OK;
3562 /* disable buffer size rounding to 128-byte multiples if supported */
3563 if (align_buffer_size >= 0)
3564 chip->align_buffer_size = !!align_buffer_size;
3566 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3567 chip->align_buffer_size = 0;
3568 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3569 chip->align_buffer_size = 1;
3571 chip->align_buffer_size = 1;
3574 /* allow 64bit DMA address if supported by H/W */
3575 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3576 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3578 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3579 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3582 /* read number of streams from GCAP register instead of using
3585 chip->capture_streams = (gcap >> 8) & 0x0f;
3586 chip->playback_streams = (gcap >> 12) & 0x0f;
3587 if (!chip->playback_streams && !chip->capture_streams) {
3588 /* gcap didn't give any info, switching to old method */
3590 switch (chip->driver_type) {
3591 case AZX_DRIVER_ULI:
3592 chip->playback_streams = ULI_NUM_PLAYBACK;
3593 chip->capture_streams = ULI_NUM_CAPTURE;
3595 case AZX_DRIVER_ATIHDMI:
3596 case AZX_DRIVER_ATIHDMI_NS:
3597 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3598 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3600 case AZX_DRIVER_GENERIC:
3602 chip->playback_streams = ICH6_NUM_PLAYBACK;
3603 chip->capture_streams = ICH6_NUM_CAPTURE;
3607 chip->capture_index_offset = 0;
3608 chip->playback_index_offset = chip->capture_streams;
3609 chip->num_streams = chip->playback_streams + chip->capture_streams;
3610 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3612 if (!chip->azx_dev) {
3613 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3617 for (i = 0; i < chip->num_streams; i++) {
3618 dsp_lock_init(&chip->azx_dev[i]);
3619 /* allocate memory for the BDL for each stream */
3620 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3621 snd_dma_pci_data(chip->pci),
3622 BDL_SIZE, &chip->azx_dev[i].bdl);
3624 snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3627 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3629 /* allocate memory for the position buffer */
3630 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3631 snd_dma_pci_data(chip->pci),
3632 chip->num_streams * 8, &chip->posbuf);
3634 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3637 mark_pages_wc(chip, &chip->posbuf, true);
3638 /* allocate CORB/RIRB */
3639 err = azx_alloc_cmd_io(chip);
3643 /* initialize streams */
3644 azx_init_stream(chip);
3646 /* initialize chip */
3648 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3650 /* codec detection */
3651 if (!chip->codec_mask) {
3652 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3656 strcpy(card->driver, "HDA-Intel");
3657 strlcpy(card->shortname, driver_short_names[chip->driver_type],
3658 sizeof(card->shortname));
3659 snprintf(card->longname, sizeof(card->longname),
3660 "%s at 0x%lx irq %i",
3661 card->shortname, chip->addr, chip->irq);
3666 static void power_down_all_codecs(struct azx *chip)
3669 /* The codecs were powered up in snd_hda_codec_new().
3670 * Now all initialization done, so turn them down if possible
3672 struct hda_codec *codec;
3673 list_for_each_entry(codec, &chip->bus->codec_list, list) {
3674 snd_hda_power_down(codec);
3679 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3680 /* callback from request_firmware_nowait() */
3681 static void azx_firmware_cb(const struct firmware *fw, void *context)
3683 struct snd_card *card = context;
3684 struct azx *chip = card->private_data;
3685 struct pci_dev *pci = chip->pci;
3688 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3689 pci_name(chip->pci));
3694 if (!chip->disabled) {
3695 /* continue probing */
3696 if (azx_probe_continue(chip))
3702 snd_card_free(card);
3703 pci_set_drvdata(pci, NULL);
3707 static int azx_probe(struct pci_dev *pci,
3708 const struct pci_device_id *pci_id)
3711 struct snd_card *card;
3716 if (dev >= SNDRV_CARDS)
3723 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
3725 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
3729 snd_card_set_dev(card, &pci->dev);
3731 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
3734 card->private_data = chip;
3736 pci_set_drvdata(pci, card);
3738 err = register_vga_switcheroo(chip);
3740 snd_printk(KERN_ERR SFX
3741 "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
3745 if (check_hdmi_disabled(pci)) {
3746 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
3748 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
3749 chip->disabled = true;
3752 probe_now = !chip->disabled;
3754 err = azx_first_init(chip);
3759 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3760 if (patch[dev] && *patch[dev]) {
3761 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
3762 pci_name(pci), patch[dev]);
3763 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
3764 &pci->dev, GFP_KERNEL, card,
3768 probe_now = false; /* continued in azx_firmware_cb() */
3770 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
3773 err = azx_probe_continue(chip);
3778 if (pci_dev_run_wake(pci))
3779 pm_runtime_put_noidle(&pci->dev);
3782 complete_all(&chip->probe_wait);
3786 snd_card_free(card);
3790 static int azx_probe_continue(struct azx *chip)
3792 int dev = chip->dev_index;
3795 #ifdef CONFIG_SND_HDA_INPUT_BEEP
3796 chip->beep_mode = beep_mode[dev];
3799 /* create codec instances */
3800 err = azx_codec_create(chip, model[dev]);
3803 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3805 err = snd_hda_load_patch(chip->bus, chip->fw->size,
3810 release_firmware(chip->fw); /* no longer needed */
3815 if ((probe_only[dev] & 1) == 0) {
3816 err = azx_codec_configure(chip);
3821 /* create PCM streams */
3822 err = snd_hda_build_pcms(chip->bus);
3826 /* create mixer controls */
3827 err = azx_mixer_create(chip);
3831 err = snd_card_register(chip->card);
3836 power_down_all_codecs(chip);
3837 azx_notifier_register(chip);
3838 azx_add_card_list(chip);
3843 chip->init_failed = 1;
3847 static void azx_remove(struct pci_dev *pci)
3849 struct snd_card *card = pci_get_drvdata(pci);
3851 if (pci_dev_run_wake(pci))
3852 pm_runtime_get_noresume(&pci->dev);
3855 snd_card_free(card);
3859 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
3861 { PCI_DEVICE(0x8086, 0x1c20),
3862 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3864 { PCI_DEVICE(0x8086, 0x1d20),
3865 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3867 { PCI_DEVICE(0x8086, 0x1e20),
3868 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3870 { PCI_DEVICE(0x8086, 0x8c20),
3871 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3873 { PCI_DEVICE(0x8086, 0x8d20),
3874 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3875 { PCI_DEVICE(0x8086, 0x8d21),
3876 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3878 { PCI_DEVICE(0x8086, 0x9c20),
3879 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3881 { PCI_DEVICE(0x8086, 0x9c21),
3882 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
3884 { PCI_DEVICE(0x8086, 0x0a0c),
3885 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3886 { PCI_DEVICE(0x8086, 0x0c0c),
3887 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3888 { PCI_DEVICE(0x8086, 0x0d0c),
3889 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
3891 { PCI_DEVICE(0x8086, 0x3b56),
3892 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3894 { PCI_DEVICE(0x8086, 0x811b),
3895 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3897 { PCI_DEVICE(0x8086, 0x080a),
3898 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
3900 { PCI_DEVICE(0x8086, 0x0f04),
3901 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
3903 { PCI_DEVICE(0x8086, 0x2668),
3904 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3905 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3906 { PCI_DEVICE(0x8086, 0x27d8),
3907 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3908 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3909 { PCI_DEVICE(0x8086, 0x269a),
3910 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3911 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3912 { PCI_DEVICE(0x8086, 0x284b),
3913 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3914 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3915 { PCI_DEVICE(0x8086, 0x293e),
3916 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3917 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3918 { PCI_DEVICE(0x8086, 0x293f),
3919 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3920 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3921 { PCI_DEVICE(0x8086, 0x3a3e),
3922 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3923 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3924 { PCI_DEVICE(0x8086, 0x3a6e),
3925 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3926 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3928 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3929 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3930 .class_mask = 0xffffff,
3931 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3932 /* ATI SB 450/600/700/800/900 */
3933 { PCI_DEVICE(0x1002, 0x437b),
3934 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3935 { PCI_DEVICE(0x1002, 0x4383),
3936 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3938 { PCI_DEVICE(0x1022, 0x780d),
3939 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3941 { PCI_DEVICE(0x1002, 0x793b),
3942 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3943 { PCI_DEVICE(0x1002, 0x7919),
3944 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3945 { PCI_DEVICE(0x1002, 0x960f),
3946 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3947 { PCI_DEVICE(0x1002, 0x970f),
3948 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3949 { PCI_DEVICE(0x1002, 0xaa00),
3950 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3951 { PCI_DEVICE(0x1002, 0xaa08),
3952 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3953 { PCI_DEVICE(0x1002, 0xaa10),
3954 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3955 { PCI_DEVICE(0x1002, 0xaa18),
3956 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3957 { PCI_DEVICE(0x1002, 0xaa20),
3958 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3959 { PCI_DEVICE(0x1002, 0xaa28),
3960 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3961 { PCI_DEVICE(0x1002, 0xaa30),
3962 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3963 { PCI_DEVICE(0x1002, 0xaa38),
3964 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3965 { PCI_DEVICE(0x1002, 0xaa40),
3966 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3967 { PCI_DEVICE(0x1002, 0xaa48),
3968 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3969 { PCI_DEVICE(0x1002, 0x9902),
3970 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3971 { PCI_DEVICE(0x1002, 0xaaa0),
3972 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3973 { PCI_DEVICE(0x1002, 0xaaa8),
3974 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3975 { PCI_DEVICE(0x1002, 0xaab0),
3976 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3977 /* VIA VT8251/VT8237A */
3978 { PCI_DEVICE(0x1106, 0x3288),
3979 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3980 /* VIA GFX VT7122/VX900 */
3981 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
3982 /* VIA GFX VT6122/VX11 */
3983 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
3985 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3987 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3989 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3990 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3991 .class_mask = 0xffffff,
3992 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3994 { PCI_DEVICE(0x6549, 0x1200),
3995 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3996 { PCI_DEVICE(0x6549, 0x2200),
3997 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3998 /* Creative X-Fi (CA0110-IBG) */
4000 { PCI_DEVICE(0x1102, 0x0010),
4001 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4002 { PCI_DEVICE(0x1102, 0x0012),
4003 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4004 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4005 /* the following entry conflicts with snd-ctxfi driver,
4006 * as ctxfi driver mutates from HD-audio to native mode with
4007 * a special command sequence.
4009 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4010 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4011 .class_mask = 0xffffff,
4012 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4013 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4015 /* this entry seems still valid -- i.e. without emu20kx chip */
4016 { PCI_DEVICE(0x1102, 0x0009),
4017 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4018 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4021 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
4022 /* VMware HDAudio */
4023 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
4024 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
4025 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4026 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4027 .class_mask = 0xffffff,
4028 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4029 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4030 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4031 .class_mask = 0xffffff,
4032 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4035 MODULE_DEVICE_TABLE(pci, azx_ids);
4037 /* pci_driver definition */
4038 static struct pci_driver azx_driver = {
4039 .name = KBUILD_MODNAME,
4040 .id_table = azx_ids,
4042 .remove = azx_remove,
4048 module_pci_driver(azx_driver);