sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <sound/core.h>
  48 #include <sound/initval.h>
  49 #include "hda_codec.h"
  50
  51
  52 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  53 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  54 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  55 static char *model[SNDRV_CARDS];
  56 static int position_fix[SNDRV_CARDS];
  57 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  58 static int single_cmd;
  59 static int enable_msi;
  60
  61 module_param_array(index, int, NULL, 0444);
  62 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  63 module_param_array(id, charp, NULL, 0444);
  64 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  65 module_param_array(enable, bool, NULL, 0444);
  66 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  67 module_param_array(model, charp, NULL, 0444);
  68 MODULE_PARM_DESC(model, "Use the given board model.");
  69 module_param_array(position_fix, int, NULL, 0444);
  70 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  71                  "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
  72 module_param_array(probe_mask, int, NULL, 0444);
  73 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  74 module_param(single_cmd, bool, 0444);
  75 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  76                  "(for debugging only).");
  77 module_param(enable_msi, int, 0444);
  78 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  79
  80 #ifdef CONFIG_SND_HDA_POWER_SAVE
  81 /* power_save option is defined in hda_codec.c */
  82
  83 /* reset the HD-audio controller in power save mode.
  84  * this may give more power-saving, but will take longer time to
  85  * wake up.
  86  */
  87 static int power_save_controller = 1;
  88 module_param(power_save_controller, bool, 0644);
  89 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
  90 #endif
  91
  92 MODULE_LICENSE("GPL");
  93 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  94                          "{Intel, ICH6M},"
  95                          "{Intel, ICH7},"
  96                          "{Intel, ESB2},"
  97                          "{Intel, ICH8},"
  98                          "{Intel, ICH9},"
  99                          "{Intel, ICH10},"
 100                          "{Intel, SCH},"
 101                          "{ATI, SB450},"
 102                          "{ATI, SB600},"
 103                          "{ATI, RS600},"
 104                          "{ATI, RS690},"
 105                          "{ATI, RS780},"
 106                          "{ATI, R600},"
 107                          "{ATI, RV630},"
 108                          "{ATI, RV610},"
 109                          "{ATI, RV670},"
 110                          "{ATI, RV635},"
 111                          "{ATI, RV620},"
 112                          "{ATI, RV770},"
 113                          "{VIA, VT8251},"
 114                          "{VIA, VT8237A},"
 115                          "{SiS, SIS966},"
 116                          "{ULI, M5461}}");
 117 MODULE_DESCRIPTION("Intel HDA driver");
 118
 119 #define SFX     "hda-intel: "
 120
 121
 122 /*
 123  * registers
 124  */
 125 #define ICH6_REG_GCAP                   0x00
 126 #define ICH6_REG_VMIN                   0x02
 127 #define ICH6_REG_VMAJ                   0x03
 128 #define ICH6_REG_OUTPAY                 0x04
 129 #define ICH6_REG_INPAY                  0x06
 130 #define ICH6_REG_GCTL                   0x08
 131 #define ICH6_REG_WAKEEN                 0x0c
 132 #define ICH6_REG_STATESTS               0x0e
 133 #define ICH6_REG_GSTS                   0x10
 134 #define ICH6_REG_INTCTL                 0x20
 135 #define ICH6_REG_INTSTS                 0x24
 136 #define ICH6_REG_WALCLK                 0x30
 137 #define ICH6_REG_SYNC                   0x34
 138 #define ICH6_REG_CORBLBASE              0x40
 139 #define ICH6_REG_CORBUBASE              0x44
 140 #define ICH6_REG_CORBWP                 0x48
 141 #define ICH6_REG_CORBRP                 0x4A
 142 #define ICH6_REG_CORBCTL                0x4c
 143 #define ICH6_REG_CORBSTS                0x4d
 144 #define ICH6_REG_CORBSIZE               0x4e
 145
 146 #define ICH6_REG_RIRBLBASE              0x50
 147 #define ICH6_REG_RIRBUBASE              0x54
 148 #define ICH6_REG_RIRBWP                 0x58
 149 #define ICH6_REG_RINTCNT                0x5a
 150 #define ICH6_REG_RIRBCTL                0x5c
 151 #define ICH6_REG_RIRBSTS                0x5d
 152 #define ICH6_REG_RIRBSIZE               0x5e
 153
 154 #define ICH6_REG_IC                     0x60
 155 #define ICH6_REG_IR                     0x64
 156 #define ICH6_REG_IRS                    0x68
 157 #define   ICH6_IRS_VALID        (1<<1)
 158 #define   ICH6_IRS_BUSY         (1<<0)
 159
 160 #define ICH6_REG_DPLBASE                0x70
 161 #define ICH6_REG_DPUBASE                0x74
 162 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 163
 164 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 165 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 166
 167 /* stream register offsets from stream base */
 168 #define ICH6_REG_SD_CTL                 0x00
 169 #define ICH6_REG_SD_STS                 0x03
 170 #define ICH6_REG_SD_LPIB                0x04
 171 #define ICH6_REG_SD_CBL                 0x08
 172 #define ICH6_REG_SD_LVI                 0x0c
 173 #define ICH6_REG_SD_FIFOW               0x0e
 174 #define ICH6_REG_SD_FIFOSIZE            0x10
 175 #define ICH6_REG_SD_FORMAT              0x12
 176 #define ICH6_REG_SD_BDLPL               0x18
 177 #define ICH6_REG_SD_BDLPU               0x1c
 178
 179 /* PCI space */
 180 #define ICH6_PCIREG_TCSEL       0x44
 181
 182 /*
 183  * other constants
 184  */
 185
 186 /* max number of SDs */
 187 /* ICH, ATI and VIA have 4 playback and 4 capture */
 188 #define ICH6_CAPTURE_INDEX      0
 189 #define ICH6_NUM_CAPTURE        4
 190 #define ICH6_PLAYBACK_INDEX     4
 191 #define ICH6_NUM_PLAYBACK       4
 192
 193 /* ULI has 6 playback and 5 capture */
 194 #define ULI_CAPTURE_INDEX       0
 195 #define ULI_NUM_CAPTURE         5
 196 #define ULI_PLAYBACK_INDEX      5
 197 #define ULI_NUM_PLAYBACK        6
 198
 199 /* ATI HDMI has 1 playback and 0 capture */
 200 #define ATIHDMI_CAPTURE_INDEX   0
 201 #define ATIHDMI_NUM_CAPTURE     0
 202 #define ATIHDMI_PLAYBACK_INDEX  0
 203 #define ATIHDMI_NUM_PLAYBACK    1
 204
 205 /* this number is statically defined for simplicity */
 206 #define MAX_AZX_DEV             16
 207
 208 /* max number of fragments - we may use more if allocating more pages for BDL */
 209 #define BDL_SIZE                PAGE_ALIGN(8192)
 210 #define AZX_MAX_FRAG            (BDL_SIZE / (MAX_AZX_DEV * 16))
 211 /* max buffer size - no h/w limit, you can increase as you like */
 212 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 213 /* max number of PCM devics per card */
 214 #define AZX_MAX_PCMS            8
 215
 216 /* RIRB int mask: overrun[2], response[0] */
 217 #define RIRB_INT_RESPONSE       0x01
 218 #define RIRB_INT_OVERRUN        0x04
 219 #define RIRB_INT_MASK           0x05
 220
 221 /* STATESTS int mask: SD2,SD1,SD0 */
 222 #define AZX_MAX_CODECS          3
 223 #define STATESTS_INT_MASK       0x07
 224
 225 /* SD_CTL bits */
 226 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 227 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 228 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 229 #define SD_CTL_STREAM_TAG_SHIFT 20
 230
 231 /* SD_CTL and SD_STS */
 232 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 233 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 234 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 235 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 236                                  SD_INT_COMPLETE)
 237
 238 /* SD_STS */
 239 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 240
 241 /* INTCTL and INTSTS */
 242 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 243 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 244 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 245
 246 /* GCTL unsolicited response enable bit */
 247 #define ICH6_GCTL_UREN          (1<<8)
 248
 249 /* GCTL reset bit */
 250 #define ICH6_GCTL_RESET         (1<<0)
 251
 252 /* CORB/RIRB control, read/write pointer */
 253 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 254 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 255 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 256 /* below are so far hardcoded - should read registers in future */
 257 #define ICH6_MAX_CORB_ENTRIES   256
 258 #define ICH6_MAX_RIRB_ENTRIES   256
 259
 260 /* position fix mode */
 261 enum {
 262         POS_FIX_AUTO,
 263         POS_FIX_NONE,
 264         POS_FIX_POSBUF,
 265         POS_FIX_FIFO,
 266 };
 267
 268 /* Defines for ATI HD Audio support in SB450 south bridge */
 269 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 270 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 271
 272 /* Defines for Nvidia HDA support */
 273 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 274 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 275
 276 /* Defines for Intel SCH HDA snoop control */
 277 #define INTEL_SCH_HDA_DEVC      0x78
 278 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 279
 280
 281 /*
 282  */
 283
 284 struct azx_dev {
 285         u32 *bdl;               /* virtual address of the BDL */
 286         dma_addr_t bdl_addr;    /* physical address of the BDL */
 287         u32 *posbuf;            /* position buffer pointer */
 288
 289         unsigned int bufsize;   /* size of the play buffer in bytes */
 290         unsigned int fragsize;  /* size of each period in bytes */
 291         unsigned int frags;     /* number for period in the play buffer */
 292         unsigned int fifo_size; /* FIFO size */
 293
 294         void __iomem *sd_addr;  /* stream descriptor pointer */
 295
 296         u32 sd_int_sta_mask;    /* stream int status mask */
 297
 298         /* pcm support */
 299         struct snd_pcm_substream *substream;    /* assigned substream,
 300                                                  * set in PCM open
 301                                                  */
 302         unsigned int format_val;        /* format value to be set in the
 303                                          * controller and the codec
 304                                          */
 305         unsigned char stream_tag;       /* assigned stream */
 306         unsigned char index;            /* stream index */
 307         /* for sanity check of position buffer */
 308         unsigned int period_intr;
 309
 310         unsigned int opened :1;
 311         unsigned int running :1;
 312 };
 313
 314 /* CORB/RIRB */
 315 struct azx_rb {
 316         u32 *buf;               /* CORB/RIRB buffer
 317                                  * Each CORB entry is 4byte, RIRB is 8byte
 318                                  */
 319         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 320         /* for RIRB */
 321         unsigned short rp, wp;  /* read/write pointers */
 322         int cmds;               /* number of pending requests */
 323         u32 res;                /* last read value */
 324 };
 325
 326 struct azx {
 327         struct snd_card *card;
 328         struct pci_dev *pci;
 329
 330         /* chip type specific */
 331         int driver_type;
 332         int playback_streams;
 333         int playback_index_offset;
 334         int capture_streams;
 335         int capture_index_offset;
 336         int num_streams;
 337
 338         /* pci resources */
 339         unsigned long addr;
 340         void __iomem *remap_addr;
 341         int irq;
 342
 343         /* locks */
 344         spinlock_t reg_lock;
 345         struct mutex open_mutex;
 346
 347         /* streams (x num_streams) */
 348         struct azx_dev *azx_dev;
 349
 350         /* PCM */
 351         struct snd_pcm *pcm[AZX_MAX_PCMS];
 352
 353         /* HD codec */
 354         unsigned short codec_mask;
 355         struct hda_bus *bus;
 356
 357         /* CORB/RIRB */
 358         struct azx_rb corb;
 359         struct azx_rb rirb;
 360
 361         /* BDL, CORB/RIRB and position buffers */
 362         struct snd_dma_buffer bdl;
 363         struct snd_dma_buffer rb;
 364         struct snd_dma_buffer posbuf;
 365
 366         /* flags */
 367         int position_fix;
 368         unsigned int running :1;
 369         unsigned int initialized :1;
 370         unsigned int single_cmd :1;
 371         unsigned int polling_mode :1;
 372         unsigned int msi :1;
 373
 374         /* for debugging */
 375         unsigned int last_cmd;  /* last issued command (to sync) */
 376 };
 377
 378 /* driver types */
 379 enum {
 380         AZX_DRIVER_ICH,
 381         AZX_DRIVER_SCH,
 382         AZX_DRIVER_ATI,
 383         AZX_DRIVER_ATIHDMI,
 384         AZX_DRIVER_VIA,
 385         AZX_DRIVER_SIS,
 386         AZX_DRIVER_ULI,
 387         AZX_DRIVER_NVIDIA,
 388 };
 389
 390 static char *driver_short_names[] __devinitdata = {
 391         [AZX_DRIVER_ICH] = "HDA Intel",
 392         [AZX_DRIVER_SCH] = "HDA Intel MID",
 393         [AZX_DRIVER_ATI] = "HDA ATI SB",
 394         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 395         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 396         [AZX_DRIVER_SIS] = "HDA SIS966",
 397         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 398         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 399 };
 400
 401 /*
 402  * macros for easy use
 403  */
 404 #define azx_writel(chip,reg,value) \
 405         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 406 #define azx_readl(chip,reg) \
 407         readl((chip)->remap_addr + ICH6_REG_##reg)
 408 #define azx_writew(chip,reg,value) \
 409         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 410 #define azx_readw(chip,reg) \
 411         readw((chip)->remap_addr + ICH6_REG_##reg)
 412 #define azx_writeb(chip,reg,value) \
 413         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 414 #define azx_readb(chip,reg) \
 415         readb((chip)->remap_addr + ICH6_REG_##reg)
 416
 417 #define azx_sd_writel(dev,reg,value) \
 418         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 419 #define azx_sd_readl(dev,reg) \
 420         readl((dev)->sd_addr + ICH6_REG_##reg)
 421 #define azx_sd_writew(dev,reg,value) \
 422         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 423 #define azx_sd_readw(dev,reg) \
 424         readw((dev)->sd_addr + ICH6_REG_##reg)
 425 #define azx_sd_writeb(dev,reg,value) \
 426         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 427 #define azx_sd_readb(dev,reg) \
 428         readb((dev)->sd_addr + ICH6_REG_##reg)
 429
 430 /* for pcm support */
 431 #define get_azx_dev(substream) (substream->runtime->private_data)
 432
 433 /* Get the upper 32bit of the given dma_addr_t
 434  * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
 435  */
 436 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
 437
 438 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 439
 440 /*
 441  * Interface for HD codec
 442  */
 443
 444 /*
 445  * CORB / RIRB interface
 446  */
 447 static int azx_alloc_cmd_io(struct azx *chip)
 448 {
 449         int err;
 450
 451         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 452         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 453                                   snd_dma_pci_data(chip->pci),
 454                                   PAGE_SIZE, &chip->rb);
 455         if (err < 0) {
 456                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 457                 return err;
 458         }
 459         return 0;
 460 }
 461
 462 static void azx_init_cmd_io(struct azx *chip)
 463 {
 464         /* CORB set up */
 465         chip->corb.addr = chip->rb.addr;
 466         chip->corb.buf = (u32 *)chip->rb.area;
 467         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 468         azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
 469
 470         /* set the corb size to 256 entries (ULI requires explicitly) */
 471         azx_writeb(chip, CORBSIZE, 0x02);
 472         /* set the corb write pointer to 0 */
 473         azx_writew(chip, CORBWP, 0);
 474         /* reset the corb hw read pointer */
 475         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 476         /* enable corb dma */
 477         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 478
 479         /* RIRB set up */
 480         chip->rirb.addr = chip->rb.addr + 2048;
 481         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 482         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 483         azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
 484
 485         /* set the rirb size to 256 entries (ULI requires explicitly) */
 486         azx_writeb(chip, RIRBSIZE, 0x02);
 487         /* reset the rirb hw write pointer */
 488         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 489         /* set N=1, get RIRB response interrupt for new entry */
 490         azx_writew(chip, RINTCNT, 1);
 491         /* enable rirb dma and response irq */
 492         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 493         chip->rirb.rp = chip->rirb.cmds = 0;
 494 }
 495
 496 static void azx_free_cmd_io(struct azx *chip)
 497 {
 498         /* disable ringbuffer DMAs */
 499         azx_writeb(chip, RIRBCTL, 0);
 500         azx_writeb(chip, CORBCTL, 0);
 501 }
 502
 503 /* send a command */
 504 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
 505 {
 506         struct azx *chip = codec->bus->private_data;
 507         unsigned int wp;
 508
 509         /* add command to corb */
 510         wp = azx_readb(chip, CORBWP);
 511         wp++;
 512         wp %= ICH6_MAX_CORB_ENTRIES;
 513
 514         spin_lock_irq(&chip->reg_lock);
 515         chip->rirb.cmds++;
 516         chip->corb.buf[wp] = cpu_to_le32(val);
 517         azx_writel(chip, CORBWP, wp);
 518         spin_unlock_irq(&chip->reg_lock);
 519
 520         return 0;
 521 }
 522
 523 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 524
 525 /* retrieve RIRB entry - called from interrupt handler */
 526 static void azx_update_rirb(struct azx *chip)
 527 {
 528         unsigned int rp, wp;
 529         u32 res, res_ex;
 530
 531         wp = azx_readb(chip, RIRBWP);
 532         if (wp == chip->rirb.wp)
 533                 return;
 534         chip->rirb.wp = wp;
 535
 536         while (chip->rirb.rp != wp) {
 537                 chip->rirb.rp++;
 538                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 539
 540                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 541                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 542                 res = le32_to_cpu(chip->rirb.buf[rp]);
 543                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 544                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 545                 else if (chip->rirb.cmds) {
 546                         chip->rirb.cmds--;
 547                         chip->rirb.res = res;
 548                 }
 549         }
 550 }
 551
 552 /* receive a response */
 553 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
 554 {
 555         struct azx *chip = codec->bus->private_data;
 556         unsigned long timeout;
 557
 558  again:
 559         timeout = jiffies + msecs_to_jiffies(1000);
 560         for (;;) {
 561                 if (chip->polling_mode) {
 562                         spin_lock_irq(&chip->reg_lock);
 563                         azx_update_rirb(chip);
 564                         spin_unlock_irq(&chip->reg_lock);
 565                 }
 566                 if (!chip->rirb.cmds)
 567                         return chip->rirb.res; /* the last value */
 568                 if (time_after(jiffies, timeout))
 569                         break;
 570                 if (codec->bus->needs_damn_long_delay)
 571                         msleep(2); /* temporary workaround */
 572                 else {
 573                         udelay(10);
 574                         cond_resched();
 575                 }
 576         }
 577
 578         if (chip->msi) {
 579                 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
 580                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 581                 free_irq(chip->irq, chip);
 582                 chip->irq = -1;
 583                 pci_disable_msi(chip->pci);
 584                 chip->msi = 0;
 585                 if (azx_acquire_irq(chip, 1) < 0)
 586                         return -1;
 587                 goto again;
 588         }
 589
 590         if (!chip->polling_mode) {
 591                 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
 592                            "switching to polling mode: last cmd=0x%08x\n",
 593                            chip->last_cmd);
 594                 chip->polling_mode = 1;
 595                 goto again;
 596         }
 597
 598         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 599                    "switching to single_cmd mode: last cmd=0x%08x\n",
 600                    chip->last_cmd);
 601         chip->rirb.rp = azx_readb(chip, RIRBWP);
 602         chip->rirb.cmds = 0;
 603         /* switch to single_cmd mode */
 604         chip->single_cmd = 1;
 605         azx_free_cmd_io(chip);
 606         return -1;
 607 }
 608
 609 /*
 610  * Use the single immediate command instead of CORB/RIRB for simplicity
 611  *
 612  * Note: according to Intel, this is not preferred use.  The command was
 613  *       intended for the BIOS only, and may get confused with unsolicited
 614  *       responses.  So, we shouldn't use it for normal operation from the
 615  *       driver.
 616  *       I left the codes, however, for debugging/testing purposes.
 617  */
 618
 619 /* send a command */
 620 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
 621 {
 622         struct azx *chip = codec->bus->private_data;
 623         int timeout = 50;
 624
 625         while (timeout--) {
 626                 /* check ICB busy bit */
 627                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 628                         /* Clear IRV valid bit */
 629                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 630                                    ICH6_IRS_VALID);
 631                         azx_writel(chip, IC, val);
 632                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 633                                    ICH6_IRS_BUSY);
 634                         return 0;
 635                 }
 636                 udelay(1);
 637         }
 638         if (printk_ratelimit())
 639                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 640                            azx_readw(chip, IRS), val);
 641         return -EIO;
 642 }
 643
 644 /* receive a response */
 645 static unsigned int azx_single_get_response(struct hda_codec *codec)
 646 {
 647         struct azx *chip = codec->bus->private_data;
 648         int timeout = 50;
 649
 650         while (timeout--) {
 651                 /* check IRV busy bit */
 652                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 653                         return azx_readl(chip, IR);
 654                 udelay(1);
 655         }
 656         if (printk_ratelimit())
 657                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 658                            azx_readw(chip, IRS));
 659         return (unsigned int)-1;
 660 }
 661
 662 /*
 663  * The below are the main callbacks from hda_codec.
 664  *
 665  * They are just the skeleton to call sub-callbacks according to the
 666  * current setting of chip->single_cmd.
 667  */
 668
 669 /* send a command */
 670 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
 671                         int direct, unsigned int verb,
 672                         unsigned int para)
 673 {
 674         struct azx *chip = codec->bus->private_data;
 675         u32 val;
 676
 677         val = (u32)(codec->addr & 0x0f) << 28;
 678         val |= (u32)direct << 27;
 679         val |= (u32)nid << 20;
 680         val |= verb << 8;
 681         val |= para;
 682         chip->last_cmd = val;
 683
 684         if (chip->single_cmd)
 685                 return azx_single_send_cmd(codec, val);
 686         else
 687                 return azx_corb_send_cmd(codec, val);
 688 }
 689
 690 /* get a response */
 691 static unsigned int azx_get_response(struct hda_codec *codec)
 692 {
 693         struct azx *chip = codec->bus->private_data;
 694         if (chip->single_cmd)
 695                 return azx_single_get_response(codec);
 696         else
 697                 return azx_rirb_get_response(codec);
 698 }
 699
 700 #ifdef CONFIG_SND_HDA_POWER_SAVE
 701 static void azx_power_notify(struct hda_codec *codec);
 702 #endif
 703
 704 /* reset codec link */
 705 static int azx_reset(struct azx *chip)
 706 {
 707         int count;
 708
 709         /* clear STATESTS */
 710         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 711
 712         /* reset controller */
 713         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 714
 715         count = 50;
 716         while (azx_readb(chip, GCTL) && --count)
 717                 msleep(1);
 718
 719         /* delay for >= 100us for codec PLL to settle per spec
 720          * Rev 0.9 section 5.5.1
 721          */
 722         msleep(1);
 723
 724         /* Bring controller out of reset */
 725         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 726
 727         count = 50;
 728         while (!azx_readb(chip, GCTL) && --count)
 729                 msleep(1);
 730
 731         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 732         msleep(1);
 733
 734         /* check to see if controller is ready */
 735         if (!azx_readb(chip, GCTL)) {
 736                 snd_printd("azx_reset: controller not ready!\n");
 737                 return -EBUSY;
 738         }
 739
 740         /* Accept unsolicited responses */
 741         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
 742
 743         /* detect codecs */
 744         if (!chip->codec_mask) {
 745                 chip->codec_mask = azx_readw(chip, STATESTS);
 746                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 747         }
 748
 749         return 0;
 750 }
 751
 752
 753 /*
 754  * Lowlevel interface
 755  */
 756
 757 /* enable interrupts */
 758 static void azx_int_enable(struct azx *chip)
 759 {
 760         /* enable controller CIE and GIE */
 761         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 762                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 763 }
 764
 765 /* disable interrupts */
 766 static void azx_int_disable(struct azx *chip)
 767 {
 768         int i;
 769
 770         /* disable interrupts in stream descriptor */
 771         for (i = 0; i < chip->num_streams; i++) {
 772                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 773                 azx_sd_writeb(azx_dev, SD_CTL,
 774                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 775         }
 776
 777         /* disable SIE for all streams */
 778         azx_writeb(chip, INTCTL, 0);
 779
 780         /* disable controller CIE and GIE */
 781         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 782                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 783 }
 784
 785 /* clear interrupts */
 786 static void azx_int_clear(struct azx *chip)
 787 {
 788         int i;
 789
 790         /* clear stream status */
 791         for (i = 0; i < chip->num_streams; i++) {
 792                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 793                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 794         }
 795
 796         /* clear STATESTS */
 797         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 798
 799         /* clear rirb status */
 800         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 801
 802         /* clear int status */
 803         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 804 }
 805
 806 /* start a stream */
 807 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 808 {
 809         /* enable SIE */
 810         azx_writeb(chip, INTCTL,
 811                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 812         /* set DMA start and interrupt mask */
 813         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 814                       SD_CTL_DMA_START | SD_INT_MASK);
 815 }
 816
 817 /* stop a stream */
 818 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 819 {
 820         /* stop DMA */
 821         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 822                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 823         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 824         /* disable SIE */
 825         azx_writeb(chip, INTCTL,
 826                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 827 }
 828
 829
 830 /*
 831  * reset and start the controller registers
 832  */
 833 static void azx_init_chip(struct azx *chip)
 834 {
 835         if (chip->initialized)
 836                 return;
 837
 838         /* reset controller */
 839         azx_reset(chip);
 840
 841         /* initialize interrupts */
 842         azx_int_clear(chip);
 843         azx_int_enable(chip);
 844
 845         /* initialize the codec command I/O */
 846         if (!chip->single_cmd)
 847                 azx_init_cmd_io(chip);
 848
 849         /* program the position buffer */
 850         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 851         azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
 852
 853         chip->initialized = 1;
 854 }
 855
 856 /*
 857  * initialize the PCI registers
 858  */
 859 /* update bits in a PCI register byte */
 860 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 861                             unsigned char mask, unsigned char val)
 862 {
 863         unsigned char data;
 864
 865         pci_read_config_byte(pci, reg, &data);
 866         data &= ~mask;
 867         data |= (val & mask);
 868         pci_write_config_byte(pci, reg, data);
 869 }
 870
 871 static void azx_init_pci(struct azx *chip)
 872 {
 873         unsigned short snoop;
 874
 875         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 876          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 877          * Ensuring these bits are 0 clears playback static on some HD Audio
 878          * codecs
 879          */
 880         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 881
 882         switch (chip->driver_type) {
 883         case AZX_DRIVER_ATI:
 884                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 885                 update_pci_byte(chip->pci,
 886                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 887                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 888                 break;
 889         case AZX_DRIVER_NVIDIA:
 890                 /* For NVIDIA HDA, enable snoop */
 891                 update_pci_byte(chip->pci,
 892                                 NVIDIA_HDA_TRANSREG_ADDR,
 893                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 894                 break;
 895         case AZX_DRIVER_SCH:
 896                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 897                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 898                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
 899                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 900                         pci_read_config_word(chip->pci,
 901                                 INTEL_SCH_HDA_DEVC, &snoop);
 902                         snd_printdd("HDA snoop disabled, enabling ... %s\n",\
 903                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
 904                                 ? "Failed" : "OK");
 905                 }
 906                 break;
 907
 908         }
 909 }
 910
 911
 912 /*
 913  * interrupt handler
 914  */
 915 static irqreturn_t azx_interrupt(int irq, void *dev_id)
 916 {
 917         struct azx *chip = dev_id;
 918         struct azx_dev *azx_dev;
 919         u32 status;
 920         int i;
 921
 922         spin_lock(&chip->reg_lock);
 923
 924         status = azx_readl(chip, INTSTS);
 925         if (status == 0) {
 926                 spin_unlock(&chip->reg_lock);
 927                 return IRQ_NONE;
 928         }
 929
 930         for (i = 0; i < chip->num_streams; i++) {
 931                 azx_dev = &chip->azx_dev[i];
 932                 if (status & azx_dev->sd_int_sta_mask) {
 933                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 934                         if (azx_dev->substream && azx_dev->running) {
 935                                 azx_dev->period_intr++;
 936                                 spin_unlock(&chip->reg_lock);
 937                                 snd_pcm_period_elapsed(azx_dev->substream);
 938                                 spin_lock(&chip->reg_lock);
 939                         }
 940                 }
 941         }
 942
 943         /* clear rirb int */
 944         status = azx_readb(chip, RIRBSTS);
 945         if (status & RIRB_INT_MASK) {
 946                 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
 947                         azx_update_rirb(chip);
 948                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 949         }
 950
 951 #if 0
 952         /* clear state status int */
 953         if (azx_readb(chip, STATESTS) & 0x04)
 954                 azx_writeb(chip, STATESTS, 0x04);
 955 #endif
 956         spin_unlock(&chip->reg_lock);
 957
 958         return IRQ_HANDLED;
 959 }
 960
 961
 962 /*
 963  * set up BDL entries
 964  */
 965 static void azx_setup_periods(struct azx_dev *azx_dev)
 966 {
 967         u32 *bdl = azx_dev->bdl;
 968         dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
 969         int idx;
 970
 971         /* reset BDL address */
 972         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 973         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 974
 975         /* program the initial BDL entries */
 976         for (idx = 0; idx < azx_dev->frags; idx++) {
 977                 unsigned int off = idx << 2; /* 4 dword step */
 978                 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
 979                 /* program the address field of the BDL entry */
 980                 bdl[off] = cpu_to_le32((u32)addr);
 981                 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
 982
 983                 /* program the size field of the BDL entry */
 984                 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
 985
 986                 /* program the IOC to enable interrupt when buffer completes */
 987                 bdl[off+3] = cpu_to_le32(0x01);
 988         }
 989 }
 990
 991 /*
 992  * set up the SD for streaming
 993  */
 994 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
 995 {
 996         unsigned char val;
 997         int timeout;
 998
 999         /* make sure the run bit is zero for SD */
1000         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1001                       ~SD_CTL_DMA_START);
1002         /* reset stream */
1003         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1004                       SD_CTL_STREAM_RESET);
1005         udelay(3);
1006         timeout = 300;
1007         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1008                --timeout)
1009                 ;
1010         val &= ~SD_CTL_STREAM_RESET;
1011         azx_sd_writeb(azx_dev, SD_CTL, val);
1012         udelay(3);
1013
1014         timeout = 300;
1015         /* waiting for hardware to report that the stream is out of reset */
1016         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1017                --timeout)
1018                 ;
1019
1020         /* program the stream_tag */
1021         azx_sd_writel(azx_dev, SD_CTL,
1022                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1023                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1024
1025         /* program the length of samples in cyclic buffer */
1026         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1027
1028         /* program the stream format */
1029         /* this value needs to be the same as the one programmed */
1030         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1031
1032         /* program the stream LVI (last valid index) of the BDL */
1033         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1034
1035         /* program the BDL address */
1036         /* lower BDL address */
1037         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
1038         /* upper BDL address */
1039         azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
1040
1041         /* enable the position buffer */
1042         if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1043                 azx_writel(chip, DPLBASE,
1044                            (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
1045
1046         /* set the interrupt enable bits in the descriptor control register */
1047         azx_sd_writel(azx_dev, SD_CTL,
1048                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1049
1050         return 0;
1051 }
1052
1053
1054 /*
1055  * Codec initialization
1056  */
1057
1058 static unsigned int azx_max_codecs[] __devinitdata = {
1059         [AZX_DRIVER_ICH] = 3,
1060         [AZX_DRIVER_SCH] = 3,
1061         [AZX_DRIVER_ATI] = 4,
1062         [AZX_DRIVER_ATIHDMI] = 4,
1063         [AZX_DRIVER_VIA] = 3,           /* FIXME: correct? */
1064         [AZX_DRIVER_SIS] = 3,           /* FIXME: correct? */
1065         [AZX_DRIVER_ULI] = 3,           /* FIXME: correct? */
1066         [AZX_DRIVER_NVIDIA] = 3,        /* FIXME: correct? */
1067 };
1068
1069 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1070                                       unsigned int codec_probe_mask)
1071 {
1072         struct hda_bus_template bus_temp;
1073         int c, codecs, audio_codecs, err;
1074
1075         memset(&bus_temp, 0, sizeof(bus_temp));
1076         bus_temp.private_data = chip;
1077         bus_temp.modelname = model;
1078         bus_temp.pci = chip->pci;
1079         bus_temp.ops.command = azx_send_cmd;
1080         bus_temp.ops.get_response = azx_get_response;
1081 #ifdef CONFIG_SND_HDA_POWER_SAVE
1082         bus_temp.ops.pm_notify = azx_power_notify;
1083 #endif
1084
1085         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1086         if (err < 0)
1087                 return err;
1088
1089         codecs = audio_codecs = 0;
1090         for (c = 0; c < AZX_MAX_CODECS; c++) {
1091                 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1092                         struct hda_codec *codec;
1093                         err = snd_hda_codec_new(chip->bus, c, &codec);
1094                         if (err < 0)
1095                                 continue;
1096                         codecs++;
1097                         if (codec->afg)
1098                                 audio_codecs++;
1099                 }
1100         }
1101         if (!audio_codecs) {
1102                 /* probe additional slots if no codec is found */
1103                 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1104                         if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1105                                 err = snd_hda_codec_new(chip->bus, c, NULL);
1106                                 if (err < 0)
1107                                         continue;
1108                                 codecs++;
1109                         }
1110                 }
1111         }
1112         if (!codecs) {
1113                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1114                 return -ENXIO;
1115         }
1116
1117         return 0;
1118 }
1119
1120
1121 /*
1122  * PCM support
1123  */
1124
1125 /* assign a stream for the PCM */
1126 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1127 {
1128         int dev, i, nums;
1129         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1130                 dev = chip->playback_index_offset;
1131                 nums = chip->playback_streams;
1132         } else {
1133                 dev = chip->capture_index_offset;
1134                 nums = chip->capture_streams;
1135         }
1136         for (i = 0; i < nums; i++, dev++)
1137                 if (!chip->azx_dev[dev].opened) {
1138                         chip->azx_dev[dev].opened = 1;
1139                         return &chip->azx_dev[dev];
1140                 }
1141         return NULL;
1142 }
1143
1144 /* release the assigned stream */
1145 static inline void azx_release_device(struct azx_dev *azx_dev)
1146 {
1147         azx_dev->opened = 0;
1148 }
1149
1150 static struct snd_pcm_hardware azx_pcm_hw = {
1151         .info =                 (SNDRV_PCM_INFO_MMAP |
1152                                  SNDRV_PCM_INFO_INTERLEAVED |
1153                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1154                                  SNDRV_PCM_INFO_MMAP_VALID |
1155                                  /* No full-resume yet implemented */
1156                                  /* SNDRV_PCM_INFO_RESUME |*/
1157                                  SNDRV_PCM_INFO_PAUSE),
1158         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1159         .rates =                SNDRV_PCM_RATE_48000,
1160         .rate_min =             48000,
1161         .rate_max =             48000,
1162         .channels_min =         2,
1163         .channels_max =         2,
1164         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1165         .period_bytes_min =     128,
1166         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1167         .periods_min =          2,
1168         .periods_max =          AZX_MAX_FRAG,
1169         .fifo_size =            0,
1170 };
1171
1172 struct azx_pcm {
1173         struct azx *chip;
1174         struct hda_codec *codec;
1175         struct hda_pcm_stream *hinfo[2];
1176 };
1177
1178 static int azx_pcm_open(struct snd_pcm_substream *substream)
1179 {
1180         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1181         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1182         struct azx *chip = apcm->chip;
1183         struct azx_dev *azx_dev;
1184         struct snd_pcm_runtime *runtime = substream->runtime;
1185         unsigned long flags;
1186         int err;
1187
1188         mutex_lock(&chip->open_mutex);
1189         azx_dev = azx_assign_device(chip, substream->stream);
1190         if (azx_dev == NULL) {
1191                 mutex_unlock(&chip->open_mutex);
1192                 return -EBUSY;
1193         }
1194         runtime->hw = azx_pcm_hw;
1195         runtime->hw.channels_min = hinfo->channels_min;
1196         runtime->hw.channels_max = hinfo->channels_max;
1197         runtime->hw.formats = hinfo->formats;
1198         runtime->hw.rates = hinfo->rates;
1199         snd_pcm_limit_hw_rates(runtime);
1200         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1201         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1202                                    128);
1203         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1204                                    128);
1205         snd_hda_power_up(apcm->codec);
1206         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1207         if (err < 0) {
1208                 azx_release_device(azx_dev);
1209                 snd_hda_power_down(apcm->codec);
1210                 mutex_unlock(&chip->open_mutex);
1211                 return err;
1212         }
1213         spin_lock_irqsave(&chip->reg_lock, flags);
1214         azx_dev->substream = substream;
1215         azx_dev->running = 0;
1216         spin_unlock_irqrestore(&chip->reg_lock, flags);
1217
1218         runtime->private_data = azx_dev;
1219         mutex_unlock(&chip->open_mutex);
1220         return 0;
1221 }
1222
1223 static int azx_pcm_close(struct snd_pcm_substream *substream)
1224 {
1225         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1226         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1227         struct azx *chip = apcm->chip;
1228         struct azx_dev *azx_dev = get_azx_dev(substream);
1229         unsigned long flags;
1230
1231         mutex_lock(&chip->open_mutex);
1232         spin_lock_irqsave(&chip->reg_lock, flags);
1233         azx_dev->substream = NULL;
1234         azx_dev->running = 0;
1235         spin_unlock_irqrestore(&chip->reg_lock, flags);
1236         azx_release_device(azx_dev);
1237         hinfo->ops.close(hinfo, apcm->codec, substream);
1238         snd_hda_power_down(apcm->codec);
1239         mutex_unlock(&chip->open_mutex);
1240         return 0;
1241 }
1242
1243 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1244                              struct snd_pcm_hw_params *hw_params)
1245 {
1246         return snd_pcm_lib_malloc_pages(substream,
1247                                         params_buffer_bytes(hw_params));
1248 }
1249
1250 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1251 {
1252         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1253         struct azx_dev *azx_dev = get_azx_dev(substream);
1254         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1255
1256         /* reset BDL address */
1257         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1258         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1259         azx_sd_writel(azx_dev, SD_CTL, 0);
1260
1261         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1262
1263         return snd_pcm_lib_free_pages(substream);
1264 }
1265
1266 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1267 {
1268         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1269         struct azx *chip = apcm->chip;
1270         struct azx_dev *azx_dev = get_azx_dev(substream);
1271         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1272         struct snd_pcm_runtime *runtime = substream->runtime;
1273
1274         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1275         azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1276         azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1277         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1278                                                          runtime->channels,
1279                                                          runtime->format,
1280                                                          hinfo->maxbps);
1281         if (!azx_dev->format_val) {
1282                 snd_printk(KERN_ERR SFX
1283                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1284                            runtime->rate, runtime->channels, runtime->format);
1285                 return -EINVAL;
1286         }
1287
1288         snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, "
1289                     "format=0x%x\n",
1290                     azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1291         azx_setup_periods(azx_dev);
1292         azx_setup_controller(chip, azx_dev);
1293         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1294                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1295         else
1296                 azx_dev->fifo_size = 0;
1297
1298         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1299                                   azx_dev->format_val, substream);
1300 }
1301
1302 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1303 {
1304         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1305         struct azx_dev *azx_dev = get_azx_dev(substream);
1306         struct azx *chip = apcm->chip;
1307         int err = 0;
1308
1309         spin_lock(&chip->reg_lock);
1310         switch (cmd) {
1311         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1312         case SNDRV_PCM_TRIGGER_RESUME:
1313         case SNDRV_PCM_TRIGGER_START:
1314                 azx_stream_start(chip, azx_dev);
1315                 azx_dev->running = 1;
1316                 break;
1317         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1318         case SNDRV_PCM_TRIGGER_SUSPEND:
1319         case SNDRV_PCM_TRIGGER_STOP:
1320                 azx_stream_stop(chip, azx_dev);
1321                 azx_dev->running = 0;
1322                 break;
1323         default:
1324                 err = -EINVAL;
1325         }
1326         spin_unlock(&chip->reg_lock);
1327         if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1328             cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1329             cmd == SNDRV_PCM_TRIGGER_STOP) {
1330                 int timeout = 5000;
1331                 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1332                        --timeout)
1333                         ;
1334         }
1335         return err;
1336 }
1337
1338 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1339 {
1340         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1341         struct azx *chip = apcm->chip;
1342         struct azx_dev *azx_dev = get_azx_dev(substream);
1343         unsigned int pos;
1344
1345         if (chip->position_fix == POS_FIX_POSBUF ||
1346             chip->position_fix == POS_FIX_AUTO) {
1347                 /* use the position buffer */
1348                 pos = le32_to_cpu(*azx_dev->posbuf);
1349                 if (chip->position_fix == POS_FIX_AUTO &&
1350                     azx_dev->period_intr == 1 && !pos) {
1351                         printk(KERN_WARNING
1352                                "hda-intel: Invalid position buffer, "
1353                                "using LPIB read method instead.\n");
1354                         chip->position_fix = POS_FIX_NONE;
1355                         goto read_lpib;
1356                 }
1357         } else {
1358         read_lpib:
1359                 /* read LPIB */
1360                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1361                 if (chip->position_fix == POS_FIX_FIFO)
1362                         pos += azx_dev->fifo_size;
1363         }
1364         if (pos >= azx_dev->bufsize)
1365                 pos = 0;
1366         return bytes_to_frames(substream->runtime, pos);
1367 }
1368
1369 static struct snd_pcm_ops azx_pcm_ops = {
1370         .open = azx_pcm_open,
1371         .close = azx_pcm_close,
1372         .ioctl = snd_pcm_lib_ioctl,
1373         .hw_params = azx_pcm_hw_params,
1374         .hw_free = azx_pcm_hw_free,
1375         .prepare = azx_pcm_prepare,
1376         .trigger = azx_pcm_trigger,
1377         .pointer = azx_pcm_pointer,
1378 };
1379
1380 static void azx_pcm_free(struct snd_pcm *pcm)
1381 {
1382         kfree(pcm->private_data);
1383 }
1384
1385 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1386                                       struct hda_pcm *cpcm)
1387 {
1388         int err;
1389         struct snd_pcm *pcm;
1390         struct azx_pcm *apcm;
1391
1392         /* if no substreams are defined for both playback and capture,
1393          * it's just a placeholder.  ignore it.
1394          */
1395         if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1396                 return 0;
1397
1398         snd_assert(cpcm->name, return -EINVAL);
1399
1400         err = snd_pcm_new(chip->card, cpcm->name, cpcm->device,
1401                           cpcm->stream[0].substreams,
1402                           cpcm->stream[1].substreams,
1403                           &pcm);
1404         if (err < 0)
1405                 return err;
1406         strcpy(pcm->name, cpcm->name);
1407         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1408         if (apcm == NULL)
1409                 return -ENOMEM;
1410         apcm->chip = chip;
1411         apcm->codec = codec;
1412         apcm->hinfo[0] = &cpcm->stream[0];
1413         apcm->hinfo[1] = &cpcm->stream[1];
1414         pcm->private_data = apcm;
1415         pcm->private_free = azx_pcm_free;
1416         if (cpcm->stream[0].substreams)
1417                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1418         if (cpcm->stream[1].substreams)
1419                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1420         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1421                                               snd_dma_pci_data(chip->pci),
1422                                               1024 * 64, 1024 * 1024);
1423         chip->pcm[cpcm->device] = pcm;
1424         return 0;
1425 }
1426
1427 static int __devinit azx_pcm_create(struct azx *chip)
1428 {
1429         static const char *dev_name[HDA_PCM_NTYPES] = {
1430                 "Audio", "SPDIF", "HDMI", "Modem"
1431         };
1432         /* starting device index for each PCM type */
1433         static int dev_idx[HDA_PCM_NTYPES] = {
1434                 [HDA_PCM_TYPE_AUDIO] = 0,
1435                 [HDA_PCM_TYPE_SPDIF] = 1,
1436                 [HDA_PCM_TYPE_HDMI] = 3,
1437                 [HDA_PCM_TYPE_MODEM] = 6
1438         };
1439         /* normal audio device indices; not linear to keep compatibility */
1440         static int audio_idx[4] = { 0, 2, 4, 5 };
1441         struct hda_codec *codec;
1442         int c, err;
1443         int num_devs[HDA_PCM_NTYPES];
1444
1445         err = snd_hda_build_pcms(chip->bus);
1446         if (err < 0)
1447                 return err;
1448
1449         /* create audio PCMs */
1450         memset(num_devs, 0, sizeof(num_devs));
1451         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1452                 for (c = 0; c < codec->num_pcms; c++) {
1453                         struct hda_pcm *cpcm = &codec->pcm_info[c];
1454                         int type = cpcm->pcm_type;
1455                         switch (type) {
1456                         case HDA_PCM_TYPE_AUDIO:
1457                                 if (num_devs[type] >= ARRAY_SIZE(audio_idx)) {
1458                                         snd_printk(KERN_WARNING
1459                                                    "Too many audio devices\n");
1460                                         continue;
1461                                 }
1462                                 cpcm->device = audio_idx[num_devs[type]];
1463                                 break;
1464                         case HDA_PCM_TYPE_SPDIF:
1465                         case HDA_PCM_TYPE_HDMI:
1466                         case HDA_PCM_TYPE_MODEM:
1467                                 if (num_devs[type]) {
1468                                         snd_printk(KERN_WARNING
1469                                                    "%s already defined\n",
1470                                                    dev_name[type]);
1471                                         continue;
1472                                 }
1473                                 cpcm->device = dev_idx[type];
1474                                 break;
1475                         default:
1476                                 snd_printk(KERN_WARNING
1477                                            "Invalid PCM type %d\n", type);
1478                                 continue;
1479                         }
1480                         num_devs[type]++;
1481                         err = create_codec_pcm(chip, codec, cpcm);
1482                         if (err < 0)
1483                                 return err;
1484                 }
1485         }
1486         return 0;
1487 }
1488
1489 /*
1490  * mixer creation - all stuff is implemented in hda module
1491  */
1492 static int __devinit azx_mixer_create(struct azx *chip)
1493 {
1494         return snd_hda_build_controls(chip->bus);
1495 }
1496
1497
1498 /*
1499  * initialize SD streams
1500  */
1501 static int __devinit azx_init_stream(struct azx *chip)
1502 {
1503         int i;
1504
1505         /* initialize each stream (aka device)
1506          * assign the starting bdl address to each stream (device)
1507          * and initialize
1508          */
1509         for (i = 0; i < chip->num_streams; i++) {
1510                 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1511                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1512                 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1513                 azx_dev->bdl_addr = chip->bdl.addr + off;
1514                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1515                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1516                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1517                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1518                 azx_dev->sd_int_sta_mask = 1 << i;
1519                 /* stream tag: must be non-zero and unique */
1520                 azx_dev->index = i;
1521                 azx_dev->stream_tag = i + 1;
1522         }
1523
1524         return 0;
1525 }
1526
1527 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1528 {
1529         if (request_irq(chip->pci->irq, azx_interrupt,
1530                         chip->msi ? 0 : IRQF_SHARED,
1531                         "HDA Intel", chip)) {
1532                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1533                        "disabling device\n", chip->pci->irq);
1534                 if (do_disconnect)
1535                         snd_card_disconnect(chip->card);
1536                 return -1;
1537         }
1538         chip->irq = chip->pci->irq;
1539         pci_intx(chip->pci, !chip->msi);
1540         return 0;
1541 }
1542
1543
1544 static void azx_stop_chip(struct azx *chip)
1545 {
1546         if (!chip->initialized)
1547                 return;
1548
1549         /* disable interrupts */
1550         azx_int_disable(chip);
1551         azx_int_clear(chip);
1552
1553         /* disable CORB/RIRB */
1554         azx_free_cmd_io(chip);
1555
1556         /* disable position buffer */
1557         azx_writel(chip, DPLBASE, 0);
1558         azx_writel(chip, DPUBASE, 0);
1559
1560         chip->initialized = 0;
1561 }
1562
1563 #ifdef CONFIG_SND_HDA_POWER_SAVE
1564 /* power-up/down the controller */
1565 static void azx_power_notify(struct hda_codec *codec)
1566 {
1567         struct azx *chip = codec->bus->private_data;
1568         struct hda_codec *c;
1569         int power_on = 0;
1570
1571         list_for_each_entry(c, &codec->bus->codec_list, list) {
1572                 if (c->power_on) {
1573                         power_on = 1;
1574                         break;
1575                 }
1576         }
1577         if (power_on)
1578                 azx_init_chip(chip);
1579         else if (chip->running && power_save_controller)
1580                 azx_stop_chip(chip);
1581 }
1582 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1583
1584 #ifdef CONFIG_PM
1585 /*
1586  * power management
1587  */
1588 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1589 {
1590         struct snd_card *card = pci_get_drvdata(pci);
1591         struct azx *chip = card->private_data;
1592         int i;
1593
1594         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1595         for (i = 0; i < AZX_MAX_PCMS; i++)
1596                 snd_pcm_suspend_all(chip->pcm[i]);
1597         if (chip->initialized)
1598                 snd_hda_suspend(chip->bus, state);
1599         azx_stop_chip(chip);
1600         if (chip->irq >= 0) {
1601                 synchronize_irq(chip->irq);
1602                 free_irq(chip->irq, chip);
1603                 chip->irq = -1;
1604         }
1605         if (chip->msi)
1606                 pci_disable_msi(chip->pci);
1607         pci_disable_device(pci);
1608         pci_save_state(pci);
1609         pci_set_power_state(pci, pci_choose_state(pci, state));
1610         return 0;
1611 }
1612
1613 static int azx_resume(struct pci_dev *pci)
1614 {
1615         struct snd_card *card = pci_get_drvdata(pci);
1616         struct azx *chip = card->private_data;
1617
1618         pci_set_power_state(pci, PCI_D0);
1619         pci_restore_state(pci);
1620         if (pci_enable_device(pci) < 0) {
1621                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1622                        "disabling device\n");
1623                 snd_card_disconnect(card);
1624                 return -EIO;
1625         }
1626         pci_set_master(pci);
1627         if (chip->msi)
1628                 if (pci_enable_msi(pci) < 0)
1629                         chip->msi = 0;
1630         if (azx_acquire_irq(chip, 1) < 0)
1631                 return -EIO;
1632         azx_init_pci(chip);
1633
1634         if (snd_hda_codecs_inuse(chip->bus))
1635                 azx_init_chip(chip);
1636
1637         snd_hda_resume(chip->bus);
1638         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1639         return 0;
1640 }
1641 #endif /* CONFIG_PM */
1642
1643
1644 /*
1645  * destructor
1646  */
1647 static int azx_free(struct azx *chip)
1648 {
1649         if (chip->initialized) {
1650                 int i;
1651                 for (i = 0; i < chip->num_streams; i++)
1652                         azx_stream_stop(chip, &chip->azx_dev[i]);
1653                 azx_stop_chip(chip);
1654         }
1655
1656         if (chip->irq >= 0) {
1657                 synchronize_irq(chip->irq);
1658                 free_irq(chip->irq, (void*)chip);
1659         }
1660         if (chip->msi)
1661                 pci_disable_msi(chip->pci);
1662         if (chip->remap_addr)
1663                 iounmap(chip->remap_addr);
1664
1665         if (chip->bdl.area)
1666                 snd_dma_free_pages(&chip->bdl);
1667         if (chip->rb.area)
1668                 snd_dma_free_pages(&chip->rb);
1669         if (chip->posbuf.area)
1670                 snd_dma_free_pages(&chip->posbuf);
1671         pci_release_regions(chip->pci);
1672         pci_disable_device(chip->pci);
1673         kfree(chip->azx_dev);
1674         kfree(chip);
1675
1676         return 0;
1677 }
1678
1679 static int azx_dev_free(struct snd_device *device)
1680 {
1681         return azx_free(device->device_data);
1682 }
1683
1684 /*
1685  * white/black-listing for position_fix
1686  */
1687 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1688         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1689         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1690         {}
1691 };
1692
1693 static int __devinit check_position_fix(struct azx *chip, int fix)
1694 {
1695         const struct snd_pci_quirk *q;
1696
1697         if (fix == POS_FIX_AUTO) {
1698                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1699                 if (q) {
1700                         printk(KERN_INFO
1701                                     "hda_intel: position_fix set to %d "
1702                                     "for device %04x:%04x\n",
1703                                     q->value, q->subvendor, q->subdevice);
1704                         return q->value;
1705                 }
1706         }
1707         return fix;
1708 }
1709
1710 /*
1711  * black-lists for probe_mask
1712  */
1713 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1714         /* Thinkpad often breaks the controller communication when accessing
1715          * to the non-working (or non-existing) modem codec slot.
1716          */
1717         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1718         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1719         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1720         {}
1721 };
1722
1723 static void __devinit check_probe_mask(struct azx *chip, int dev)
1724 {
1725         const struct snd_pci_quirk *q;
1726
1727         if (probe_mask[dev] == -1) {
1728                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1729                 if (q) {
1730                         printk(KERN_INFO
1731                                "hda_intel: probe_mask set to 0x%x "
1732                                "for device %04x:%04x\n",
1733                                q->value, q->subvendor, q->subdevice);
1734                         probe_mask[dev] = q->value;
1735                 }
1736         }
1737 }
1738
1739
1740 /*
1741  * constructor
1742  */
1743 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1744                                 int dev, int driver_type,
1745                                 struct azx **rchip)
1746 {
1747         struct azx *chip;
1748         int err;
1749         unsigned short gcap;
1750         static struct snd_device_ops ops = {
1751                 .dev_free = azx_dev_free,
1752         };
1753
1754         *rchip = NULL;
1755
1756         err = pci_enable_device(pci);
1757         if (err < 0)
1758                 return err;
1759
1760         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1761         if (!chip) {
1762                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1763                 pci_disable_device(pci);
1764                 return -ENOMEM;
1765         }
1766
1767         spin_lock_init(&chip->reg_lock);
1768         mutex_init(&chip->open_mutex);
1769         chip->card = card;
1770         chip->pci = pci;
1771         chip->irq = -1;
1772         chip->driver_type = driver_type;
1773         chip->msi = enable_msi;
1774
1775         chip->position_fix = check_position_fix(chip, position_fix[dev]);
1776         check_probe_mask(chip, dev);
1777
1778         chip->single_cmd = single_cmd;
1779
1780 #if BITS_PER_LONG != 64
1781         /* Fix up base address on ULI M5461 */
1782         if (chip->driver_type == AZX_DRIVER_ULI) {
1783                 u16 tmp3;
1784                 pci_read_config_word(pci, 0x40, &tmp3);
1785                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1786                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1787         }
1788 #endif
1789
1790         err = pci_request_regions(pci, "ICH HD audio");
1791         if (err < 0) {
1792                 kfree(chip);
1793                 pci_disable_device(pci);
1794                 return err;
1795         }
1796
1797         chip->addr = pci_resource_start(pci, 0);
1798         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1799         if (chip->remap_addr == NULL) {
1800                 snd_printk(KERN_ERR SFX "ioremap error\n");
1801                 err = -ENXIO;
1802                 goto errout;
1803         }
1804
1805         if (chip->msi)
1806                 if (pci_enable_msi(pci) < 0)
1807                         chip->msi = 0;
1808
1809         if (azx_acquire_irq(chip, 0) < 0) {
1810                 err = -EBUSY;
1811                 goto errout;
1812         }
1813
1814         pci_set_master(pci);
1815         synchronize_irq(chip->irq);
1816
1817         gcap = azx_readw(chip, GCAP);
1818         snd_printdd("chipset global capabilities = 0x%x\n", gcap);
1819
1820         if (gcap) {
1821                 /* read number of streams from GCAP register instead of using
1822                  * hardcoded value
1823                  */
1824                 chip->playback_streams = (gcap & (0xF << 12)) >> 12;
1825                 chip->capture_streams = (gcap & (0xF << 8)) >> 8;
1826                 chip->playback_index_offset = chip->capture_streams;
1827                 chip->capture_index_offset = 0;
1828         } else {
1829                 /* gcap didn't give any info, switching to old method */
1830
1831                 switch (chip->driver_type) {
1832                 case AZX_DRIVER_ULI:
1833                         chip->playback_streams = ULI_NUM_PLAYBACK;
1834                         chip->capture_streams = ULI_NUM_CAPTURE;
1835                         chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1836                         chip->capture_index_offset = ULI_CAPTURE_INDEX;
1837                         break;
1838                 case AZX_DRIVER_ATIHDMI:
1839                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1840                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1841                         chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1842                         chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1843                         break;
1844                 default:
1845                         chip->playback_streams = ICH6_NUM_PLAYBACK;
1846                         chip->capture_streams = ICH6_NUM_CAPTURE;
1847                         chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1848                         chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1849                         break;
1850                 }
1851         }
1852         chip->num_streams = chip->playback_streams + chip->capture_streams;
1853         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1854                                 GFP_KERNEL);
1855         if (!chip->azx_dev) {
1856                 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1857                 goto errout;
1858         }
1859
1860         /* allocate memory for the BDL for each stream */
1861         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1862                                   snd_dma_pci_data(chip->pci),
1863                                   BDL_SIZE, &chip->bdl);
1864         if (err < 0) {
1865                 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1866                 goto errout;
1867         }
1868         /* allocate memory for the position buffer */
1869         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1870                                   snd_dma_pci_data(chip->pci),
1871                                   chip->num_streams * 8, &chip->posbuf);
1872         if (err < 0) {
1873                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1874                 goto errout;
1875         }
1876         /* allocate CORB/RIRB */
1877         if (!chip->single_cmd) {
1878                 err = azx_alloc_cmd_io(chip);
1879                 if (err < 0)
1880                         goto errout;
1881         }
1882
1883         /* initialize streams */
1884         azx_init_stream(chip);
1885
1886         /* initialize chip */
1887         azx_init_pci(chip);
1888         azx_init_chip(chip);
1889
1890         /* codec detection */
1891         if (!chip->codec_mask) {
1892                 snd_printk(KERN_ERR SFX "no codecs found!\n");
1893                 err = -ENODEV;
1894                 goto errout;
1895         }
1896
1897         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1898         if (err <0) {
1899                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1900                 goto errout;
1901         }
1902
1903         strcpy(card->driver, "HDA-Intel");
1904         strcpy(card->shortname, driver_short_names[chip->driver_type]);
1905         sprintf(card->longname, "%s at 0x%lx irq %i",
1906                 card->shortname, chip->addr, chip->irq);
1907
1908         *rchip = chip;
1909         return 0;
1910
1911  errout:
1912         azx_free(chip);
1913         return err;
1914 }
1915
1916 static void power_down_all_codecs(struct azx *chip)
1917 {
1918 #ifdef CONFIG_SND_HDA_POWER_SAVE
1919         /* The codecs were powered up in snd_hda_codec_new().
1920          * Now all initialization done, so turn them down if possible
1921          */
1922         struct hda_codec *codec;
1923         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1924                 snd_hda_power_down(codec);
1925         }
1926 #endif
1927 }
1928
1929 static int __devinit azx_probe(struct pci_dev *pci,
1930                                const struct pci_device_id *pci_id)
1931 {
1932         static int dev;
1933         struct snd_card *card;
1934         struct azx *chip;
1935         int err;
1936
1937         if (dev >= SNDRV_CARDS)
1938                 return -ENODEV;
1939         if (!enable[dev]) {
1940                 dev++;
1941                 return -ENOENT;
1942         }
1943
1944         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1945         if (!card) {
1946                 snd_printk(KERN_ERR SFX "Error creating card!\n");
1947                 return -ENOMEM;
1948         }
1949
1950         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1951         if (err < 0) {
1952                 snd_card_free(card);
1953                 return err;
1954         }
1955         card->private_data = chip;
1956
1957         /* create codec instances */
1958         err = azx_codec_create(chip, model[dev], probe_mask[dev]);
1959         if (err < 0) {
1960                 snd_card_free(card);
1961                 return err;
1962         }
1963
1964         /* create PCM streams */
1965         err = azx_pcm_create(chip);
1966         if (err < 0) {
1967                 snd_card_free(card);
1968                 return err;
1969         }
1970
1971         /* create mixer controls */
1972         err = azx_mixer_create(chip);
1973         if (err < 0) {
1974                 snd_card_free(card);
1975                 return err;
1976         }
1977
1978         snd_card_set_dev(card, &pci->dev);
1979
1980         err = snd_card_register(card);
1981         if (err < 0) {
1982                 snd_card_free(card);
1983                 return err;
1984         }
1985
1986         pci_set_drvdata(pci, card);
1987         chip->running = 1;
1988         power_down_all_codecs(chip);
1989
1990         dev++;
1991         return err;
1992 }
1993
1994 static void __devexit azx_remove(struct pci_dev *pci)
1995 {
1996         snd_card_free(pci_get_drvdata(pci));
1997         pci_set_drvdata(pci, NULL);
1998 }
1999
2000 /* PCI IDs */
2001 static struct pci_device_id azx_ids[] = {
2002         { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
2003         { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
2004         { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
2005         { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
2006         { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
2007         { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
2008         { 0x8086, 0x3a3e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
2009         { 0x8086, 0x3a6e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
2010         { 0x8086, 0x811b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SCH }, /* SCH*/
2011         { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
2012         { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
2013         { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
2014         { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
2015         { 0x1002, 0x960f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
2016         { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
2017         { 0x1002, 0xaa08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV630 HDMI */
2018         { 0x1002, 0xaa10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV610 HDMI */
2019         { 0x1002, 0xaa18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV670 HDMI */
2020         { 0x1002, 0xaa20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV635 HDMI */
2021         { 0x1002, 0xaa28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV620 HDMI */
2022         { 0x1002, 0xaa30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV770 HDMI */
2023         { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
2024         { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
2025         { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
2026         { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
2027         { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
2028         { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2029         { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2030         { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2031         { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2032         { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2033         { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2034         { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2035         { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2036         { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2037         { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2038         { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2039         { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2040         { 0x10de, 0x0ac0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2041         { 0x10de, 0x0ac1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2042         { 0x10de, 0x0ac2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2043         { 0x10de, 0x0ac3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2044         { 0, }
2045 };
2046 MODULE_DEVICE_TABLE(pci, azx_ids);
2047
2048 /* pci_driver definition */
2049 static struct pci_driver driver = {
2050         .name = "HDA Intel",
2051         .id_table = azx_ids,
2052         .probe = azx_probe,
2053         .remove = __devexit_p(azx_remove),
2054 #ifdef CONFIG_PM
2055         .suspend = azx_suspend,
2056         .resume = azx_resume,
2057 #endif
2058 };
2059
2060 static int __init alsa_card_azx_init(void)
2061 {
2062         return pci_register_driver(&driver);
2063 }
2064
2065 static void __exit alsa_card_azx_exit(void)
2066 {
2067         pci_unregister_driver(&driver);
2068 }
2069
2070 module_init(alsa_card_azx_init)
2071 module_exit(alsa_card_azx_exit)