3 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/clk.h>
20 #include <linux/clocksource.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mutex.h>
31 #include <linux/of_device.h>
32 #include <linux/slab.h>
33 #include <linux/time.h>
35 #include <sound/core.h>
36 #include <sound/initval.h>
38 #include "hda_codec.h"
39 #include "hda_controller.h"
41 /* Defines for Nvidia Tegra HDA support */
42 #define HDA_BAR0 0x8000
44 #define HDA_CFG_CMD 0x1004
45 #define HDA_CFG_BAR0 0x1010
47 #define HDA_ENABLE_IO_SPACE (1 << 0)
48 #define HDA_ENABLE_MEM_SPACE (1 << 1)
49 #define HDA_ENABLE_BUS_MASTER (1 << 2)
50 #define HDA_ENABLE_SERR (1 << 8)
51 #define HDA_DISABLE_INTR (1 << 10)
52 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
53 #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
56 #define HDA_IPFS_CONFIG 0x180
57 #define HDA_IPFS_EN_FPCI 0x1
59 #define HDA_IPFS_FPCI_BAR0 0x80
60 #define HDA_FPCI_BAR0_START 0x40
62 #define HDA_IPFS_INTR_MASK 0x188
63 #define HDA_IPFS_EN_INTR (1 << 16)
65 /* max number of SDs */
66 #define NUM_CAPTURE_SD 1
67 #define NUM_PLAYBACK_SD 1
73 struct clk *hda2codec_2x_clk;
74 struct clk *hda2hdmi_clk;
79 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
80 module_param(power_save, bint, 0644);
81 MODULE_PARM_DESC(power_save,
82 "Automatic power-saving timeout (in seconds, 0 = disable).");
88 * DMA page allocation ops.
90 static int dma_alloc_pages(struct hdac_bus *bus, int type, size_t size,
91 struct snd_dma_buffer *buf)
93 return snd_dma_alloc_pages(type, bus->dev, size, buf);
96 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
98 snd_dma_free_pages(buf);
101 static int substream_alloc_pages(struct azx *chip,
102 struct snd_pcm_substream *substream,
105 return snd_pcm_lib_malloc_pages(substream, size);
108 static int substream_free_pages(struct azx *chip,
109 struct snd_pcm_substream *substream)
111 return snd_pcm_lib_free_pages(substream);
115 * Register access ops. Tegra HDA register access is DWORD only.
117 static void hda_tegra_writel(u32 value, u32 *addr)
122 static u32 hda_tegra_readl(u32 *addr)
127 static void hda_tegra_writew(u16 value, u16 *addr)
129 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
130 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
133 v = readl(dword_addr);
134 v &= ~(0xffff << shift);
136 writel(v, dword_addr);
139 static u16 hda_tegra_readw(u16 *addr)
141 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
142 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
145 v = readl(dword_addr);
146 return (v >> shift) & 0xffff;
149 static void hda_tegra_writeb(u8 value, u8 *addr)
151 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
152 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
155 v = readl(dword_addr);
156 v &= ~(0xff << shift);
158 writel(v, dword_addr);
161 static u8 hda_tegra_readb(u8 *addr)
163 unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
164 void *dword_addr = (void *)((unsigned long)(addr) & ~0x3);
167 v = readl(dword_addr);
168 return (v >> shift) & 0xff;
171 static const struct hdac_io_ops hda_tegra_io_ops = {
172 .reg_writel = hda_tegra_writel,
173 .reg_readl = hda_tegra_readl,
174 .reg_writew = hda_tegra_writew,
175 .reg_readw = hda_tegra_readw,
176 .reg_writeb = hda_tegra_writeb,
177 .reg_readb = hda_tegra_readb,
178 .dma_alloc_pages = dma_alloc_pages,
179 .dma_free_pages = dma_free_pages,
182 static const struct hda_controller_ops hda_tegra_ops = {
183 .substream_alloc_pages = substream_alloc_pages,
184 .substream_free_pages = substream_free_pages,
187 static void hda_tegra_init(struct hda_tegra *hda)
191 /* Enable PCI access */
192 v = readl(hda->regs + HDA_IPFS_CONFIG);
193 v |= HDA_IPFS_EN_FPCI;
194 writel(v, hda->regs + HDA_IPFS_CONFIG);
196 /* Enable MEM/IO space and bus master */
197 v = readl(hda->regs + HDA_CFG_CMD);
198 v &= ~HDA_DISABLE_INTR;
199 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
200 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
201 writel(v, hda->regs + HDA_CFG_CMD);
203 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
204 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
205 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
207 v = readl(hda->regs + HDA_IPFS_INTR_MASK);
208 v |= HDA_IPFS_EN_INTR;
209 writel(v, hda->regs + HDA_IPFS_INTR_MASK);
212 static int hda_tegra_enable_clocks(struct hda_tegra *data)
216 rc = clk_prepare_enable(data->hda_clk);
219 rc = clk_prepare_enable(data->hda2codec_2x_clk);
222 rc = clk_prepare_enable(data->hda2hdmi_clk);
224 goto disable_codec_2x;
229 clk_disable_unprepare(data->hda2codec_2x_clk);
231 clk_disable_unprepare(data->hda_clk);
235 #ifdef CONFIG_PM_SLEEP
236 static void hda_tegra_disable_clocks(struct hda_tegra *data)
238 clk_disable_unprepare(data->hda2hdmi_clk);
239 clk_disable_unprepare(data->hda2codec_2x_clk);
240 clk_disable_unprepare(data->hda_clk);
246 static int hda_tegra_suspend(struct device *dev)
248 struct snd_card *card = dev_get_drvdata(dev);
249 struct azx *chip = card->private_data;
250 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
252 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
255 azx_enter_link_reset(chip);
256 hda_tegra_disable_clocks(hda);
261 static int hda_tegra_resume(struct device *dev)
263 struct snd_card *card = dev_get_drvdata(dev);
264 struct azx *chip = card->private_data;
265 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
267 hda_tegra_enable_clocks(hda);
271 azx_init_chip(chip, 1);
273 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
277 #endif /* CONFIG_PM_SLEEP */
279 static const struct dev_pm_ops hda_tegra_pm = {
280 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
283 static int hda_tegra_dev_disconnect(struct snd_device *device)
285 struct azx *chip = device->device_data;
287 chip->bus.shutdown = 1;
294 static int hda_tegra_dev_free(struct snd_device *device)
296 struct azx *chip = device->device_data;
298 if (azx_bus(chip)->chip_init) {
299 azx_stop_all_streams(chip);
303 azx_free_stream_pages(chip);
304 azx_free_streams(chip);
305 snd_hdac_bus_exit(azx_bus(chip));
310 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
312 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
313 struct hdac_bus *bus = azx_bus(chip);
314 struct device *dev = hda->dev;
315 struct resource *res;
318 hda->hda_clk = devm_clk_get(dev, "hda");
319 if (IS_ERR(hda->hda_clk)) {
320 dev_err(dev, "failed to get hda clock\n");
321 return PTR_ERR(hda->hda_clk);
323 hda->hda2codec_2x_clk = devm_clk_get(dev, "hda2codec_2x");
324 if (IS_ERR(hda->hda2codec_2x_clk)) {
325 dev_err(dev, "failed to get hda2codec_2x clock\n");
326 return PTR_ERR(hda->hda2codec_2x_clk);
328 hda->hda2hdmi_clk = devm_clk_get(dev, "hda2hdmi");
329 if (IS_ERR(hda->hda2hdmi_clk)) {
330 dev_err(dev, "failed to get hda2hdmi clock\n");
331 return PTR_ERR(hda->hda2hdmi_clk);
334 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
335 hda->regs = devm_ioremap_resource(dev, res);
336 if (IS_ERR(hda->regs))
337 return PTR_ERR(hda->regs);
339 bus->remap_addr = hda->regs + HDA_BAR0;
340 bus->addr = res->start + HDA_BAR0;
342 err = hda_tegra_enable_clocks(hda);
344 dev_err(dev, "failed to get enable clocks\n");
353 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
355 struct hdac_bus *bus = azx_bus(chip);
356 struct snd_card *card = chip->card;
359 int irq_id = platform_get_irq(pdev, 0);
361 err = hda_tegra_init_chip(chip, pdev);
365 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
366 IRQF_SHARED, KBUILD_MODNAME, chip);
368 dev_err(chip->card->dev,
369 "unable to request IRQ %d, disabling device\n",
375 synchronize_irq(bus->irq);
377 gcap = azx_readw(chip, GCAP);
378 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
380 /* read number of streams from GCAP register instead of using
383 chip->capture_streams = (gcap >> 8) & 0x0f;
384 chip->playback_streams = (gcap >> 12) & 0x0f;
385 if (!chip->playback_streams && !chip->capture_streams) {
386 /* gcap didn't give any info, switching to old method */
387 chip->playback_streams = NUM_PLAYBACK_SD;
388 chip->capture_streams = NUM_CAPTURE_SD;
390 chip->capture_index_offset = 0;
391 chip->playback_index_offset = chip->capture_streams;
392 chip->num_streams = chip->playback_streams + chip->capture_streams;
394 /* initialize streams */
395 err = azx_init_streams(chip);
397 dev_err(card->dev, "failed to initialize streams: %d\n", err);
401 err = azx_alloc_stream_pages(chip);
403 dev_err(card->dev, "failed to allocate stream pages: %d\n",
408 /* initialize chip */
409 azx_init_chip(chip, 1);
411 /* codec detection */
412 if (!bus->codec_mask) {
413 dev_err(card->dev, "no codecs found!\n");
417 strcpy(card->driver, "tegra-hda");
418 strcpy(card->shortname, "tegra-hda");
419 snprintf(card->longname, sizeof(card->longname),
420 "%s at 0x%lx irq %i",
421 card->shortname, bus->addr, bus->irq);
429 static int hda_tegra_create(struct snd_card *card,
430 unsigned int driver_caps,
431 struct hda_tegra *hda)
433 static struct snd_device_ops ops = {
434 .dev_disconnect = hda_tegra_dev_disconnect,
435 .dev_free = hda_tegra_dev_free,
442 mutex_init(&chip->open_mutex);
444 chip->ops = &hda_tegra_ops;
445 chip->driver_caps = driver_caps;
446 chip->driver_type = driver_caps & 0xff;
448 INIT_LIST_HEAD(&chip->pcm_list);
450 chip->codec_probe_mask = -1;
452 chip->single_cmd = false;
455 err = azx_bus_init(chip, NULL, &hda_tegra_io_ops);
459 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
461 dev_err(card->dev, "Error creating device\n");
468 static const struct of_device_id hda_tegra_match[] = {
469 { .compatible = "nvidia,tegra30-hda" },
472 MODULE_DEVICE_TABLE(of, hda_tegra_match);
474 static int hda_tegra_probe(struct platform_device *pdev)
476 const unsigned int driver_flags = AZX_DCAPS_RIRB_DELAY |
477 AZX_DCAPS_CORBRP_SELF_CLEAR;
478 struct snd_card *card;
480 struct hda_tegra *hda;
483 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
486 hda->dev = &pdev->dev;
489 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
490 THIS_MODULE, 0, &card);
492 dev_err(&pdev->dev, "Error creating card!\n");
496 err = hda_tegra_create(card, driver_flags, hda);
499 card->private_data = chip;
501 dev_set_drvdata(&pdev->dev, card);
503 err = hda_tegra_first_init(chip, pdev);
507 /* create codec instances */
508 err = azx_probe_codecs(chip, 0);
512 err = azx_codec_configure(chip);
516 err = snd_card_register(chip->card);
521 snd_hda_set_power_save(&chip->bus, power_save * 1000);
530 static int hda_tegra_remove(struct platform_device *pdev)
532 return snd_card_free(dev_get_drvdata(&pdev->dev));
535 static void hda_tegra_shutdown(struct platform_device *pdev)
537 struct snd_card *card = dev_get_drvdata(&pdev->dev);
542 chip = card->private_data;
543 if (chip && chip->running)
547 static struct platform_driver tegra_platform_hda = {
551 .of_match_table = hda_tegra_match,
553 .probe = hda_tegra_probe,
554 .remove = hda_tegra_remove,
555 .shutdown = hda_tegra_shutdown,
557 module_platform_driver(tegra_platform_hda);
559 MODULE_DESCRIPTION("Tegra HDA bus driver");
560 MODULE_LICENSE("GPL v2");