2 * HD audio interface patch for Creative CA0132 chip
4 * Copyright (c) 2011, Creative Technology Ltd.
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/mutex.h>
28 #include <linux/module.h>
29 #include <linux/firmware.h>
30 #include <sound/core.h>
31 #include "hda_codec.h"
32 #include "hda_local.h"
33 #include "hda_auto_parser.h"
36 #include "ca0132_regs.h"
38 /* Enable this to see controls for tuning purpose. */
39 /*#define ENABLE_TUNING_CONTROLS*/
41 #define FLOAT_ZERO 0x00000000
42 #define FLOAT_ONE 0x3f800000
43 #define FLOAT_TWO 0x40000000
44 #define FLOAT_MINUS_5 0xc0a00000
46 #define UNSOL_TAG_DSP 0x16
48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
55 #define MASTERCONTROL 0x80
56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
59 #define WIDGET_CHIP_CTRL 0x15
60 #define WIDGET_DSP_CTRL 0x16
62 #define MEM_CONNID_MICIN1 3
63 #define MEM_CONNID_MICIN2 5
64 #define MEM_CONNID_MICOUT1 12
65 #define MEM_CONNID_MICOUT2 14
66 #define MEM_CONNID_WUH 10
67 #define MEM_CONNID_DSP 16
68 #define MEM_CONNID_DMIC 100
73 #define EFX_FILE "ctefx.bin"
75 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
76 MODULE_FIRMWARE(EFX_FILE);
79 static char *dirstr[2] = { "Playback", "Capture" };
92 #define VNODE_START_NID 0x80
93 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
100 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
102 #define EFFECT_START_NID 0x90
103 #define OUT_EFFECT_START_NID EFFECT_START_NID
104 SURROUND = OUT_EFFECT_START_NID,
111 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
113 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
114 ECHO_CANCELLATION = IN_EFFECT_START_NID,
119 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
121 VOICEFX = IN_EFFECT_END_NID,
125 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
128 /* Effects values size*/
129 #define EFFECT_VALS_MAX_COUNT 12
131 /* Latency introduced by DSP blocks in milliseconds. */
132 #define DSP_CAPTURE_INIT_LATENCY 0
133 #define DSP_CRYSTAL_VOICE_LATENCY 124
134 #define DSP_PLAYBACK_INIT_LATENCY 13
135 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
136 #define DSP_SPEAKER_OUT_LATENCY 7
139 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
141 int mid; /*effect module ID*/
142 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
143 int direct; /* 0:output; 1:input*/
144 int params; /* number of default non-on/off params */
145 /*effect default values, 1st is on/off. */
146 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
149 #define EFX_DIR_OUT 0
152 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
153 { .name = "Surround",
157 .direct = EFX_DIR_OUT,
159 .def_vals = {0x3F800000, 0x3F2B851F}
161 { .name = "Crystalizer",
165 .direct = EFX_DIR_OUT,
167 .def_vals = {0x3F800000, 0x3F266666}
169 { .name = "Dialog Plus",
173 .direct = EFX_DIR_OUT,
175 .def_vals = {0x00000000, 0x3F000000}
177 { .name = "Smart Volume",
181 .direct = EFX_DIR_OUT,
183 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
188 .reqs = {24, 23, 25},
189 .direct = EFX_DIR_OUT,
191 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
193 { .name = "Equalizer",
196 .reqs = {9, 10, 11, 12, 13, 14,
197 15, 16, 17, 18, 19, 20},
198 .direct = EFX_DIR_OUT,
200 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
201 0x00000000, 0x00000000, 0x00000000, 0x00000000,
202 0x00000000, 0x00000000, 0x00000000, 0x00000000}
204 { .name = "Echo Cancellation",
205 .nid = ECHO_CANCELLATION,
207 .reqs = {0, 1, 2, 3},
208 .direct = EFX_DIR_IN,
210 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
212 { .name = "Voice Focus",
215 .reqs = {6, 7, 8, 9},
216 .direct = EFX_DIR_IN,
218 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
224 .direct = EFX_DIR_IN,
226 .def_vals = {0x00000000, 0x3F3D70A4}
228 { .name = "Noise Reduction",
229 .nid = NOISE_REDUCTION,
232 .direct = EFX_DIR_IN,
234 .def_vals = {0x3F800000, 0x3F000000}
239 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
240 .direct = EFX_DIR_IN,
242 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
243 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
248 /* Tuning controls */
249 #ifdef ENABLE_TUNING_CONTROLS
252 #define TUNING_CTL_START_NID 0xC0
253 WEDGE_ANGLE = TUNING_CTL_START_NID,
266 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
269 struct ct_tuning_ctl {
270 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
271 hda_nid_t parent_nid;
273 int mid; /*effect module ID*/
274 int req; /*effect module request*/
275 int direct; /* 0:output; 1:input*/
276 unsigned int def_val;/*effect default values*/
279 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
280 { .name = "Wedge Angle",
281 .parent_nid = VOICE_FOCUS,
285 .direct = EFX_DIR_IN,
286 .def_val = 0x41F00000
288 { .name = "SVM Level",
289 .parent_nid = MIC_SVM,
293 .direct = EFX_DIR_IN,
294 .def_val = 0x3F3D70A4
296 { .name = "EQ Band0",
297 .parent_nid = EQUALIZER,
298 .nid = EQUALIZER_BAND_0,
301 .direct = EFX_DIR_OUT,
302 .def_val = 0x00000000
304 { .name = "EQ Band1",
305 .parent_nid = EQUALIZER,
306 .nid = EQUALIZER_BAND_1,
309 .direct = EFX_DIR_OUT,
310 .def_val = 0x00000000
312 { .name = "EQ Band2",
313 .parent_nid = EQUALIZER,
314 .nid = EQUALIZER_BAND_2,
317 .direct = EFX_DIR_OUT,
318 .def_val = 0x00000000
320 { .name = "EQ Band3",
321 .parent_nid = EQUALIZER,
322 .nid = EQUALIZER_BAND_3,
325 .direct = EFX_DIR_OUT,
326 .def_val = 0x00000000
328 { .name = "EQ Band4",
329 .parent_nid = EQUALIZER,
330 .nid = EQUALIZER_BAND_4,
333 .direct = EFX_DIR_OUT,
334 .def_val = 0x00000000
336 { .name = "EQ Band5",
337 .parent_nid = EQUALIZER,
338 .nid = EQUALIZER_BAND_5,
341 .direct = EFX_DIR_OUT,
342 .def_val = 0x00000000
344 { .name = "EQ Band6",
345 .parent_nid = EQUALIZER,
346 .nid = EQUALIZER_BAND_6,
349 .direct = EFX_DIR_OUT,
350 .def_val = 0x00000000
352 { .name = "EQ Band7",
353 .parent_nid = EQUALIZER,
354 .nid = EQUALIZER_BAND_7,
357 .direct = EFX_DIR_OUT,
358 .def_val = 0x00000000
360 { .name = "EQ Band8",
361 .parent_nid = EQUALIZER,
362 .nid = EQUALIZER_BAND_8,
365 .direct = EFX_DIR_OUT,
366 .def_val = 0x00000000
368 { .name = "EQ Band9",
369 .parent_nid = EQUALIZER,
370 .nid = EQUALIZER_BAND_9,
373 .direct = EFX_DIR_OUT,
374 .def_val = 0x00000000
379 /* Voice FX Presets */
380 #define VOICEFX_MAX_PARAM_COUNT 9
386 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
389 struct ct_voicefx_preset {
390 char *name; /*preset name*/
391 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
394 static struct ct_voicefx ca0132_voicefx = {
395 .name = "VoiceFX Capture Switch",
398 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
401 static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
403 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
404 0x44FA0000, 0x3F800000, 0x3F800000,
405 0x3F800000, 0x00000000, 0x00000000 }
407 { .name = "Female2Male",
408 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
409 0x44FA0000, 0x3F19999A, 0x3F866666,
410 0x3F800000, 0x00000000, 0x00000000 }
412 { .name = "Male2Female",
413 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
414 0x450AC000, 0x4017AE14, 0x3F6B851F,
415 0x3F800000, 0x00000000, 0x00000000 }
417 { .name = "ScrappyKid",
418 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
419 0x44FA0000, 0x40400000, 0x3F28F5C3,
420 0x3F800000, 0x00000000, 0x00000000 }
423 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
424 0x44E10000, 0x3FB33333, 0x3FB9999A,
425 0x3F800000, 0x3E3A2E43, 0x00000000 }
428 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
429 0x45098000, 0x3F266666, 0x3FC00000,
430 0x3F800000, 0x00000000, 0x00000000 }
433 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
434 0x45193000, 0x3F8E147B, 0x3F75C28F,
435 0x3F800000, 0x00000000, 0x00000000 }
438 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
439 0x45007000, 0x3F451EB8, 0x3F7851EC,
440 0x3F800000, 0x00000000, 0x00000000 }
442 { .name = "AlienBrute",
443 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
444 0x451F6000, 0x3F266666, 0x3FA7D945,
445 0x3F800000, 0x3CF5C28F, 0x00000000 }
448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449 0x44FA0000, 0x3FB2718B, 0x3F800000,
450 0xBC07010E, 0x00000000, 0x00000000 }
453 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
454 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
455 0x3F0A3D71, 0x00000000, 0x00000000 }
458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459 0x44FA0000, 0x3F800000, 0x3F800000,
460 0x3E4CCCCD, 0x00000000, 0x00000000 }
462 { .name = "DeepVoice",
463 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
464 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
465 0x3F800000, 0x00000000, 0x00000000 }
467 { .name = "Munchkin",
468 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
469 0x44FA0000, 0x3F800000, 0x3F1A043C,
470 0x3F800000, 0x00000000, 0x00000000 }
474 enum hda_cmd_vendor_io {
476 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
477 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
479 VENDOR_DSPIO_STATUS = 0xF01,
480 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
481 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
482 VENDOR_DSPIO_DSP_INIT = 0x703,
483 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
484 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
486 /* for ChipIO node */
487 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
488 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
489 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
490 VENDOR_CHIPIO_DATA_LOW = 0x300,
491 VENDOR_CHIPIO_DATA_HIGH = 0x400,
493 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
494 VENDOR_CHIPIO_STATUS = 0xF01,
495 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
496 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
498 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
499 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
501 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
502 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
504 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
505 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
506 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
507 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
508 VENDOR_CHIPIO_FLAG_SET = 0x70F,
509 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
510 VENDOR_CHIPIO_PARAM_SET = 0x710,
511 VENDOR_CHIPIO_PARAM_GET = 0xF10,
513 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
514 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
515 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
516 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
518 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
519 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
520 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
521 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
523 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
524 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
525 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
526 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
527 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
528 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
530 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
536 enum control_flag_id {
537 /* Connection manager stream setup is bypassed/enabled */
538 CONTROL_FLAG_C_MGR = 0,
539 /* DSP DMA is bypassed/enabled */
540 CONTROL_FLAG_DMA = 1,
541 /* 8051 'idle' mode is disabled/enabled */
542 CONTROL_FLAG_IDLE_ENABLE = 2,
543 /* Tracker for the SPDIF-in path is bypassed/enabled */
544 CONTROL_FLAG_TRACKER = 3,
545 /* DigitalOut to Spdif2Out connection is disabled/enabled */
546 CONTROL_FLAG_SPDIF2OUT = 4,
547 /* Digital Microphone is disabled/enabled */
548 CONTROL_FLAG_DMIC = 5,
549 /* ADC_B rate is 48 kHz/96 kHz */
550 CONTROL_FLAG_ADC_B_96KHZ = 6,
551 /* ADC_C rate is 48 kHz/96 kHz */
552 CONTROL_FLAG_ADC_C_96KHZ = 7,
553 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
554 CONTROL_FLAG_DAC_96KHZ = 8,
555 /* DSP rate is 48 kHz/96 kHz */
556 CONTROL_FLAG_DSP_96KHZ = 9,
557 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
558 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
559 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
560 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
561 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
562 CONTROL_FLAG_DECODE_LOOP = 12,
563 /* De-emphasis filter on DAC-1 disabled/enabled */
564 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
565 /* De-emphasis filter on DAC-2 disabled/enabled */
566 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
567 /* De-emphasis filter on DAC-3 disabled/enabled */
568 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
569 /* High-pass filter on ADC_B disabled/enabled */
570 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
571 /* High-pass filter on ADC_C disabled/enabled */
572 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
573 /* Common mode on Port_A disabled/enabled */
574 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
575 /* Common mode on Port_D disabled/enabled */
576 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
577 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
578 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
579 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
580 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
581 /* ASI rate is 48kHz/96kHz */
582 CONTROL_FLAG_ASI_96KHZ = 22,
583 /* DAC power settings able to control attached ports no/yes */
584 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
585 /* Clock Stop OK reporting is disabled/enabled */
586 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
587 /* Number of control flags */
588 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
592 * Control parameter IDs
594 enum control_param_id {
595 /* 0: None, 1: Mic1In*/
596 CONTROL_PARAM_VIP_SOURCE = 1,
597 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
598 CONTROL_PARAM_SPDIF1_SOURCE = 2,
599 /* Port A output stage gain setting to use when 16 Ohm output
600 * impedance is selected*/
601 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
602 /* Port D output stage gain setting to use when 16 Ohm output
603 * impedance is selected*/
604 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
608 /* Select stream with the given ID */
609 CONTROL_PARAM_STREAM_ID = 24,
610 /* Source connection point for the selected stream */
611 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
612 /* Destination connection point for the selected stream */
613 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
614 /* Number of audio channels in the selected stream */
615 CONTROL_PARAM_STREAMS_CHANNELS = 27,
616 /*Enable control for the selected stream */
617 CONTROL_PARAM_STREAM_CONTROL = 28,
619 /* Connection Point Control */
621 /* Select connection point with the given ID */
622 CONTROL_PARAM_CONN_POINT_ID = 29,
623 /* Connection point sample rate */
624 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
628 /* Select HDA node with the given ID */
629 CONTROL_PARAM_NODE_ID = 31
633 * Dsp Io Status codes
635 enum hda_vendor_status_dspio {
637 VENDOR_STATUS_DSPIO_OK = 0x00,
638 /* Busy, unable to accept new command, the host must retry */
639 VENDOR_STATUS_DSPIO_BUSY = 0x01,
640 /* SCP command queue is full */
641 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
642 /* SCP response queue is empty */
643 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
647 * Chip Io Status codes
649 enum hda_vendor_status_chipio {
651 VENDOR_STATUS_CHIPIO_OK = 0x00,
652 /* Busy, unable to accept new command, the host must retry */
653 VENDOR_STATUS_CHIPIO_BUSY = 0x01
659 enum ca0132_sample_rate {
679 SR_RATE_UNKNOWN = 0x1F
682 enum dsp_download_state {
683 DSP_DOWNLOAD_FAILED = -1,
684 DSP_DOWNLOAD_INIT = 0,
689 /* retrieve parameters from hda format */
690 #define get_hdafmt_chs(fmt) (fmt & 0xf)
691 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
692 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
693 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
700 struct snd_kcontrol_new *mixers[5];
701 unsigned int num_mixers;
702 const struct hda_verb *base_init_verbs;
703 const struct hda_verb *base_exit_verbs;
704 const struct hda_verb *chip_init_verbs;
705 struct hda_verb *spec_init_verbs;
706 struct auto_pin_cfg autocfg;
708 /* Nodes configurations */
709 struct hda_multi_out multiout;
710 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
711 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
712 unsigned int num_outputs;
713 hda_nid_t input_pins[AUTO_PIN_LAST];
714 hda_nid_t adcs[AUTO_PIN_LAST];
717 unsigned int num_inputs;
718 hda_nid_t shared_mic_nid;
719 hda_nid_t shared_out_nid;
720 hda_nid_t unsol_tag_hp;
721 hda_nid_t unsol_tag_amic1;
724 struct mutex chipio_mutex; /* chip access mutex */
727 /* DSP download related */
728 enum dsp_download_state dsp_state;
729 unsigned int dsp_stream_id;
730 unsigned int wait_scp;
731 unsigned int wait_scp_header;
732 unsigned int wait_num_data;
733 unsigned int scp_resp_header;
734 unsigned int scp_resp_data[4];
735 unsigned int scp_resp_count;
737 /* mixer and effects related */
738 unsigned char dmic_ctl;
741 long vnode_lvol[VNODES_COUNT];
742 long vnode_rvol[VNODES_COUNT];
743 long vnode_lswitch[VNODES_COUNT];
744 long vnode_rswitch[VNODES_COUNT];
745 long effects_switch[EFFECTS_COUNT];
749 struct hda_codec *codec;
750 struct delayed_work unsol_hp_work;
753 #ifdef ENABLE_TUNING_CONTROLS
754 long cur_ctl_vals[TUNING_CTLS_COUNT];
759 * CA0132 quirks table
766 static const struct hda_pintbl alienware_pincfgs[] = {
767 { 0x0b, 0x90170110 }, /* Builtin Speaker */
768 { 0x0c, 0x411111f0 }, /* N/A */
769 { 0x0d, 0x411111f0 }, /* N/A */
770 { 0x0e, 0x411111f0 }, /* N/A */
771 { 0x0f, 0x0321101f }, /* HP */
772 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
773 { 0x11, 0x03a11021 }, /* Mic */
774 { 0x12, 0xd5a30140 }, /* Builtin Mic */
775 { 0x13, 0x411111f0 }, /* N/A */
776 { 0x18, 0x411111f0 }, /* N/A */
780 static const struct snd_pci_quirk ca0132_quirks[] = {
781 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
782 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
783 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
788 * CA0132 codec access
790 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
791 unsigned int verb, unsigned int parm, unsigned int *res)
793 unsigned int response;
794 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
797 return ((response == -1) ? -1 : 0);
800 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
801 unsigned short converter_format, unsigned int *res)
803 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
804 converter_format & 0xffff, res);
807 static int codec_set_converter_stream_channel(struct hda_codec *codec,
808 hda_nid_t nid, unsigned char stream,
809 unsigned char channel, unsigned int *res)
811 unsigned char converter_stream_channel = 0;
813 converter_stream_channel = (stream << 4) | (channel & 0x0f);
814 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
815 converter_stream_channel, res);
818 /* Chip access helper function */
819 static int chipio_send(struct hda_codec *codec,
824 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
826 /* send bits of data specified by reg */
828 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
830 if (res == VENDOR_STATUS_CHIPIO_OK)
833 } while (time_before(jiffies, timeout));
839 * Write chip address through the vendor widget -- NOT protected by the Mutex!
841 static int chipio_write_address(struct hda_codec *codec,
842 unsigned int chip_addx)
844 struct ca0132_spec *spec = codec->spec;
847 if (spec->curr_chip_addx == chip_addx)
850 /* send low 16 bits of the address */
851 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
855 /* send high 16 bits of the address */
856 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
860 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
866 * Write data through the vendor widget -- NOT protected by the Mutex!
868 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
870 struct ca0132_spec *spec = codec->spec;
873 /* send low 16 bits of the data */
874 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
877 /* send high 16 bits of the data */
878 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
882 /*If no error encountered, automatically increment the address
883 as per chip behaviour*/
884 spec->curr_chip_addx = (res != -EIO) ?
885 (spec->curr_chip_addx + 4) : ~0U;
890 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
892 static int chipio_write_data_multiple(struct hda_codec *codec,
899 codec_dbg(codec, "chipio_write_data null ptr\n");
903 while ((count-- != 0) && (status == 0))
904 status = chipio_write_data(codec, *data++);
911 * Read data through the vendor widget -- NOT protected by the Mutex!
913 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
915 struct ca0132_spec *spec = codec->spec;
919 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
923 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
928 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
929 VENDOR_CHIPIO_HIC_READ_DATA,
933 /*If no error encountered, automatically increment the address
934 as per chip behaviour*/
935 spec->curr_chip_addx = (res != -EIO) ?
936 (spec->curr_chip_addx + 4) : ~0U;
941 * Write given value to the given address through the chip I/O widget.
942 * protected by the Mutex
944 static int chipio_write(struct hda_codec *codec,
945 unsigned int chip_addx, const unsigned int data)
947 struct ca0132_spec *spec = codec->spec;
950 mutex_lock(&spec->chipio_mutex);
952 /* write the address, and if successful proceed to write data */
953 err = chipio_write_address(codec, chip_addx);
957 err = chipio_write_data(codec, data);
962 mutex_unlock(&spec->chipio_mutex);
967 * Write multiple values to the given address through the chip I/O widget.
968 * protected by the Mutex
970 static int chipio_write_multiple(struct hda_codec *codec,
975 struct ca0132_spec *spec = codec->spec;
978 mutex_lock(&spec->chipio_mutex);
979 status = chipio_write_address(codec, chip_addx);
983 status = chipio_write_data_multiple(codec, data, count);
985 mutex_unlock(&spec->chipio_mutex);
991 * Read the given address through the chip I/O widget
992 * protected by the Mutex
994 static int chipio_read(struct hda_codec *codec,
995 unsigned int chip_addx, unsigned int *data)
997 struct ca0132_spec *spec = codec->spec;
1000 mutex_lock(&spec->chipio_mutex);
1002 /* write the address, and if successful proceed to write data */
1003 err = chipio_write_address(codec, chip_addx);
1007 err = chipio_read_data(codec, data);
1012 mutex_unlock(&spec->chipio_mutex);
1017 * Set chip control flags through the chip I/O widget.
1019 static void chipio_set_control_flag(struct hda_codec *codec,
1020 enum control_flag_id flag_id,
1024 unsigned int flag_bit;
1026 flag_bit = (flag_state ? 1 : 0);
1027 val = (flag_bit << 7) | (flag_id);
1028 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1029 VENDOR_CHIPIO_FLAG_SET, val);
1033 * Set chip parameters through the chip I/O widget.
1035 static void chipio_set_control_param(struct hda_codec *codec,
1036 enum control_param_id param_id, int param_val)
1038 struct ca0132_spec *spec = codec->spec;
1041 if ((param_id < 32) && (param_val < 8)) {
1042 val = (param_val << 5) | (param_id);
1043 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1044 VENDOR_CHIPIO_PARAM_SET, val);
1046 mutex_lock(&spec->chipio_mutex);
1047 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1048 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1049 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1051 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1052 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1055 mutex_unlock(&spec->chipio_mutex);
1060 * Set sampling rate of the connection point.
1062 static void chipio_set_conn_rate(struct hda_codec *codec,
1063 int connid, enum ca0132_sample_rate rate)
1065 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1066 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1073 static void chipio_enable_clocks(struct hda_codec *codec)
1075 struct ca0132_spec *spec = codec->spec;
1077 mutex_lock(&spec->chipio_mutex);
1078 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1079 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1080 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1081 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1082 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1083 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1084 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1085 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1086 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1087 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1088 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1089 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1090 mutex_unlock(&spec->chipio_mutex);
1094 * CA0132 DSP IO stuffs
1096 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1100 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1102 /* send bits of data specified by reg to dsp */
1104 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1105 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1108 } while (time_before(jiffies, timeout));
1114 * Wait for DSP to be ready for commands
1116 static void dspio_write_wait(struct hda_codec *codec)
1119 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1122 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1123 VENDOR_DSPIO_STATUS, 0);
1124 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1125 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1128 } while (time_before(jiffies, timeout));
1132 * Write SCP data to DSP
1134 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1136 struct ca0132_spec *spec = codec->spec;
1139 dspio_write_wait(codec);
1141 mutex_lock(&spec->chipio_mutex);
1142 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1147 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1152 /* OK, now check if the write itself has executed*/
1153 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1154 VENDOR_DSPIO_STATUS, 0);
1156 mutex_unlock(&spec->chipio_mutex);
1158 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1163 * Write multiple SCP data to DSP
1165 static int dspio_write_multiple(struct hda_codec *codec,
1166 unsigned int *buffer, unsigned int size)
1175 while (count < size) {
1176 status = dspio_write(codec, *buffer++);
1185 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1189 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1193 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1194 if (status == -EIO ||
1195 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1198 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1199 VENDOR_DSPIO_SCP_READ_DATA, 0);
1204 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1205 unsigned int *buf_size, unsigned int size_count)
1208 unsigned int size = *buf_size;
1210 unsigned int skip_count;
1217 while (count < size && count < size_count) {
1218 status = dspio_read(codec, buffer++);
1226 while (skip_count < size) {
1227 status = dspio_read(codec, &dummy);
1239 * Construct the SCP header using corresponding fields
1241 static inline unsigned int
1242 make_scp_header(unsigned int target_id, unsigned int source_id,
1243 unsigned int get_flag, unsigned int req,
1244 unsigned int device_flag, unsigned int resp_flag,
1245 unsigned int error_flag, unsigned int data_size)
1247 unsigned int header = 0;
1249 header = (data_size & 0x1f) << 27;
1250 header |= (error_flag & 0x01) << 26;
1251 header |= (resp_flag & 0x01) << 25;
1252 header |= (device_flag & 0x01) << 24;
1253 header |= (req & 0x7f) << 17;
1254 header |= (get_flag & 0x01) << 16;
1255 header |= (source_id & 0xff) << 8;
1256 header |= target_id & 0xff;
1262 * Extract corresponding fields from SCP header
1265 extract_scp_header(unsigned int header,
1266 unsigned int *target_id, unsigned int *source_id,
1267 unsigned int *get_flag, unsigned int *req,
1268 unsigned int *device_flag, unsigned int *resp_flag,
1269 unsigned int *error_flag, unsigned int *data_size)
1272 *data_size = (header >> 27) & 0x1f;
1274 *error_flag = (header >> 26) & 0x01;
1276 *resp_flag = (header >> 25) & 0x01;
1278 *device_flag = (header >> 24) & 0x01;
1280 *req = (header >> 17) & 0x7f;
1282 *get_flag = (header >> 16) & 0x01;
1284 *source_id = (header >> 8) & 0xff;
1286 *target_id = header & 0xff;
1289 #define SCP_MAX_DATA_WORDS (16)
1291 /* Structure to contain any SCP message */
1294 unsigned int data[SCP_MAX_DATA_WORDS];
1297 static void dspio_clear_response_queue(struct hda_codec *codec)
1299 unsigned int dummy = 0;
1302 /* clear all from the response queue */
1304 status = dspio_read(codec, &dummy);
1305 } while (status == 0);
1308 static int dspio_get_response_data(struct hda_codec *codec)
1310 struct ca0132_spec *spec = codec->spec;
1311 unsigned int data = 0;
1314 if (dspio_read(codec, &data) < 0)
1317 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1318 spec->scp_resp_header = data;
1319 spec->scp_resp_count = data >> 27;
1320 count = spec->wait_num_data;
1321 dspio_read_multiple(codec, spec->scp_resp_data,
1322 &spec->scp_resp_count, count);
1330 * Send SCP message to DSP
1332 static int dspio_send_scp_message(struct hda_codec *codec,
1333 unsigned char *send_buf,
1334 unsigned int send_buf_size,
1335 unsigned char *return_buf,
1336 unsigned int return_buf_size,
1337 unsigned int *bytes_returned)
1339 struct ca0132_spec *spec = codec->spec;
1341 unsigned int scp_send_size = 0;
1342 unsigned int total_size;
1343 bool waiting_for_resp = false;
1344 unsigned int header;
1345 struct scp_msg *ret_msg;
1346 unsigned int resp_src_id, resp_target_id;
1347 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1350 *bytes_returned = 0;
1352 /* get scp header from buffer */
1353 header = *((unsigned int *)send_buf);
1354 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1355 &device_flag, NULL, NULL, &data_size);
1356 scp_send_size = data_size + 1;
1357 total_size = (scp_send_size * 4);
1359 if (send_buf_size < total_size)
1362 if (get_flag || device_flag) {
1363 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1366 spec->wait_scp_header = *((unsigned int *)send_buf);
1368 /* swap source id with target id */
1369 resp_target_id = src_id;
1370 resp_src_id = target_id;
1371 spec->wait_scp_header &= 0xffff0000;
1372 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1373 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1375 waiting_for_resp = true;
1378 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1385 if (waiting_for_resp) {
1386 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1387 memset(return_buf, 0, return_buf_size);
1390 } while (spec->wait_scp && time_before(jiffies, timeout));
1391 waiting_for_resp = false;
1392 if (!spec->wait_scp) {
1393 ret_msg = (struct scp_msg *)return_buf;
1394 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1395 memcpy(&ret_msg->data, spec->scp_resp_data,
1396 spec->wait_num_data);
1397 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1409 * Prepare and send the SCP message to DSP
1410 * @codec: the HDA codec
1411 * @mod_id: ID of the DSP module to send the command
1412 * @req: ID of request to send to the DSP module
1414 * @data: pointer to the data to send with the request, request specific
1415 * @len: length of the data, in bytes
1416 * @reply: point to the buffer to hold data returned for a reply
1417 * @reply_len: length of the reply buffer returned from GET
1419 * Returns zero or a negative error code.
1421 static int dspio_scp(struct hda_codec *codec,
1422 int mod_id, int req, int dir, void *data, unsigned int len,
1423 void *reply, unsigned int *reply_len)
1426 struct scp_msg scp_send, scp_reply;
1427 unsigned int ret_bytes, send_size, ret_size;
1428 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1429 unsigned int reply_data_size;
1431 memset(&scp_send, 0, sizeof(scp_send));
1432 memset(&scp_reply, 0, sizeof(scp_reply));
1434 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1437 if (dir == SCP_GET && reply == NULL) {
1438 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1442 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1443 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1447 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1448 0, 0, 0, len/sizeof(unsigned int));
1449 if (data != NULL && len > 0) {
1450 len = min((unsigned int)(sizeof(scp_send.data)), len);
1451 memcpy(scp_send.data, data, len);
1455 send_size = sizeof(unsigned int) + len;
1456 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1457 send_size, (unsigned char *)&scp_reply,
1458 sizeof(scp_reply), &ret_bytes);
1461 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1465 /* extract send and reply headers members */
1466 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1467 NULL, NULL, NULL, NULL, NULL);
1468 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1469 &reply_resp_flag, &reply_error_flag,
1475 if (reply_resp_flag && !reply_error_flag) {
1476 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1477 / sizeof(unsigned int);
1479 if (*reply_len < ret_size*sizeof(unsigned int)) {
1480 codec_dbg(codec, "reply too long for buf\n");
1482 } else if (ret_size != reply_data_size) {
1483 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1485 } else if (!reply) {
1486 codec_dbg(codec, "NULL reply\n");
1489 *reply_len = ret_size*sizeof(unsigned int);
1490 memcpy(reply, scp_reply.data, *reply_len);
1493 codec_dbg(codec, "reply ill-formed or errflag set\n");
1501 * Set DSP parameters
1503 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1504 int req, void *data, unsigned int len)
1506 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1509 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1510 int req, unsigned int data)
1512 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1516 * Allocate a DSP DMA channel via an SCP message
1518 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1521 unsigned int size = sizeof(dma_chan);
1523 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
1524 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1525 SCP_GET, NULL, 0, dma_chan, &size);
1528 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1532 if ((*dma_chan + 1) == 0) {
1533 codec_dbg(codec, "no free dma channels to allocate\n");
1537 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1538 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
1544 * Free a DSP DMA via an SCP message
1546 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1549 unsigned int dummy = 0;
1551 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1552 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1554 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1555 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1558 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1562 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
1570 static int dsp_set_run_state(struct hda_codec *codec)
1572 unsigned int dbg_ctrl_reg;
1573 unsigned int halt_state;
1576 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1580 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1581 DSP_DBGCNTL_STATE_LOBIT;
1583 if (halt_state != 0) {
1584 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1585 DSP_DBGCNTL_SS_MASK);
1586 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1591 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1592 DSP_DBGCNTL_EXEC_MASK;
1593 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1605 static int dsp_reset(struct hda_codec *codec)
1610 codec_dbg(codec, "dsp_reset\n");
1612 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1614 } while (res == -EIO && retry);
1617 codec_dbg(codec, "dsp_reset timeout\n");
1625 * Convert chip address to DSP address
1627 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1628 bool *code, bool *yram)
1630 *code = *yram = false;
1632 if (UC_RANGE(chip_addx, 1)) {
1634 return UC_OFF(chip_addx);
1635 } else if (X_RANGE_ALL(chip_addx, 1)) {
1636 return X_OFF(chip_addx);
1637 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1639 return Y_OFF(chip_addx);
1642 return INVALID_CHIP_ADDRESS;
1646 * Check if the DSP DMA is active
1648 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1650 unsigned int dma_chnlstart_reg;
1652 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1654 return ((dma_chnlstart_reg & (1 <<
1655 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1658 static int dsp_dma_setup_common(struct hda_codec *codec,
1659 unsigned int chip_addx,
1660 unsigned int dma_chan,
1661 unsigned int port_map_mask,
1665 unsigned int chnl_prop;
1666 unsigned int dsp_addx;
1667 unsigned int active;
1670 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
1672 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1673 codec_dbg(codec, "dma chan num invalid\n");
1677 if (dsp_is_dma_active(codec, dma_chan)) {
1678 codec_dbg(codec, "dma already active\n");
1682 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1684 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1685 codec_dbg(codec, "invalid chip addr\n");
1689 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1692 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
1695 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1699 codec_dbg(codec, "read CHNLPROP Reg fail\n");
1702 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
1706 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1708 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1710 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1712 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1714 codec_dbg(codec, "write CHNLPROP Reg fail\n");
1717 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
1720 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1724 codec_dbg(codec, "read ACTIVE Reg fail\n");
1727 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
1730 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1731 DSPDMAC_ACTIVE_AAR_MASK;
1733 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1735 codec_dbg(codec, "write ACTIVE Reg fail\n");
1739 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
1741 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1744 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
1747 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
1749 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1750 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1752 codec_dbg(codec, "write IRQCNT Reg fail\n");
1755 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
1758 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1759 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1760 chip_addx, dsp_addx, dma_chan,
1761 port_map_mask, chnl_prop, active);
1763 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
1769 * Setup the DSP DMA per-transfer-specific registers
1771 static int dsp_dma_setup(struct hda_codec *codec,
1772 unsigned int chip_addx,
1774 unsigned int dma_chan)
1778 unsigned int dsp_addx;
1779 unsigned int addr_field;
1780 unsigned int incr_field;
1781 unsigned int base_cnt;
1782 unsigned int cur_cnt;
1783 unsigned int dma_cfg = 0;
1784 unsigned int adr_ofs = 0;
1785 unsigned int xfr_cnt = 0;
1786 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1787 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1789 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
1791 if (count > max_dma_count) {
1792 codec_dbg(codec, "count too big\n");
1796 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1797 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1798 codec_dbg(codec, "invalid chip addr\n");
1802 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
1804 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1810 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1812 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1815 dma_cfg = addr_field + incr_field;
1816 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1819 codec_dbg(codec, "write DMACFG Reg fail\n");
1822 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
1824 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1827 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1830 codec_dbg(codec, "write DSPADROFS Reg fail\n");
1833 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
1835 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1837 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1839 xfr_cnt = base_cnt | cur_cnt;
1841 status = chipio_write(codec,
1842 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1844 codec_dbg(codec, "write XFRCNT Reg fail\n");
1847 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
1850 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1851 "ADROFS=0x%x, XFRCNT=0x%x\n",
1852 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1854 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
1862 static int dsp_dma_start(struct hda_codec *codec,
1863 unsigned int dma_chan, bool ovly)
1865 unsigned int reg = 0;
1868 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
1871 status = chipio_read(codec,
1872 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
1875 codec_dbg(codec, "read CHNLSTART reg fail\n");
1878 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
1880 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1881 DSPDMAC_CHNLSTART_DIS_MASK);
1884 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1885 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1887 codec_dbg(codec, "write CHNLSTART reg fail\n");
1890 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
1898 static int dsp_dma_stop(struct hda_codec *codec,
1899 unsigned int dma_chan, bool ovly)
1901 unsigned int reg = 0;
1904 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
1907 status = chipio_read(codec,
1908 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
1911 codec_dbg(codec, "read CHNLSTART reg fail\n");
1914 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
1915 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1916 DSPDMAC_CHNLSTART_DIS_MASK);
1919 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1920 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1922 codec_dbg(codec, "write CHNLSTART reg fail\n");
1925 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
1931 * Allocate router ports
1933 * @codec: the HDA codec
1934 * @num_chans: number of channels in the stream
1935 * @ports_per_channel: number of ports per channel
1936 * @start_device: start device
1937 * @port_map: pointer to the port list to hold the allocated ports
1939 * Returns zero or a negative error code.
1941 static int dsp_allocate_router_ports(struct hda_codec *codec,
1942 unsigned int num_chans,
1943 unsigned int ports_per_channel,
1944 unsigned int start_device,
1945 unsigned int *port_map)
1951 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1955 val = start_device << 6;
1956 val |= (ports_per_channel - 1) << 4;
1957 val |= num_chans - 1;
1959 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1960 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1963 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1964 VENDOR_CHIPIO_PORT_ALLOC_SET,
1967 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1971 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1972 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1976 return (res < 0) ? res : 0;
1982 static int dsp_free_router_ports(struct hda_codec *codec)
1986 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1990 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1991 VENDOR_CHIPIO_PORT_FREE_SET,
1994 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2000 * Allocate DSP ports for the download stream
2002 static int dsp_allocate_ports(struct hda_codec *codec,
2003 unsigned int num_chans,
2004 unsigned int rate_multi, unsigned int *port_map)
2008 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2010 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2011 codec_dbg(codec, "bad rate multiple\n");
2015 status = dsp_allocate_router_ports(codec, num_chans,
2016 rate_multi, 0, port_map);
2018 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2023 static int dsp_allocate_ports_format(struct hda_codec *codec,
2024 const unsigned short fmt,
2025 unsigned int *port_map)
2028 unsigned int num_chans;
2030 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2031 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2032 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2034 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2035 codec_dbg(codec, "bad rate multiple\n");
2039 num_chans = get_hdafmt_chs(fmt) + 1;
2041 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2049 static int dsp_free_ports(struct hda_codec *codec)
2053 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2055 status = dsp_free_router_ports(codec);
2057 codec_dbg(codec, "free router ports fail\n");
2060 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2066 * HDA DMA engine stuffs for DSP code download
2069 struct hda_codec *codec;
2070 unsigned short m_converter_format;
2071 struct snd_dma_buffer *dmab;
2072 unsigned int buf_size;
2081 static int dma_convert_to_hda_format(struct hda_codec *codec,
2082 unsigned int sample_rate,
2083 unsigned short channels,
2084 unsigned short *hda_format)
2086 unsigned int format_val;
2088 format_val = snd_hdac_calc_stream_format(sample_rate,
2089 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2092 *hda_format = (unsigned short)format_val;
2098 * Reset DMA for DSP download
2100 static int dma_reset(struct dma_engine *dma)
2102 struct hda_codec *codec = dma->codec;
2103 struct ca0132_spec *spec = codec->spec;
2106 if (dma->dmab->area)
2107 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2109 status = snd_hda_codec_load_dsp_prepare(codec,
2110 dma->m_converter_format,
2115 spec->dsp_stream_id = status;
2119 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2124 case DMA_STATE_STOP:
2134 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2138 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2140 return dma->dmab->bytes;
2143 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2145 return dma->dmab->area;
2148 static int dma_xfer(struct dma_engine *dma,
2149 const unsigned int *data,
2152 memcpy(dma->dmab->area, data, count);
2156 static void dma_get_converter_format(
2157 struct dma_engine *dma,
2158 unsigned short *format)
2161 *format = dma->m_converter_format;
2164 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2166 struct ca0132_spec *spec = dma->codec->spec;
2168 return spec->dsp_stream_id;
2171 struct dsp_image_seg {
2178 static const u32 g_magic_value = 0x4c46584d;
2179 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2181 static bool is_valid(const struct dsp_image_seg *p)
2183 return p->magic == g_magic_value;
2186 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2188 return g_chip_addr_magic_value == p->chip_addr;
2191 static bool is_last(const struct dsp_image_seg *p)
2193 return p->count == 0;
2196 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2198 return sizeof(*p) + p->count*sizeof(u32);
2201 static const struct dsp_image_seg *get_next_seg_ptr(
2202 const struct dsp_image_seg *p)
2204 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2208 * CA0132 chip DSP transfer stuffs. For DSP download.
2210 #define INVALID_DMA_CHANNEL (~0U)
2213 * Program a list of address/data pairs via the ChipIO widget.
2214 * The segment data is in the format of successive pairs of words.
2215 * These are repeated as indicated by the segment's count field.
2217 static int dspxfr_hci_write(struct hda_codec *codec,
2218 const struct dsp_image_seg *fls)
2224 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2225 codec_dbg(codec, "hci_write invalid params\n");
2230 data = (u32 *)(fls->data);
2231 while (count >= 2) {
2232 status = chipio_write(codec, data[0], data[1]);
2234 codec_dbg(codec, "hci_write chipio failed\n");
2244 * Write a block of data into DSP code or data RAM using pre-allocated
2247 * @codec: the HDA codec
2248 * @fls: pointer to a fast load image
2249 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2251 * @dma_engine: pointer to DMA engine to be used for DSP download
2252 * @dma_chan: The number of DMA channels used for DSP download
2253 * @port_map_mask: port mapping
2254 * @ovly: TRUE if overlay format is required
2256 * Returns zero or a negative error code.
2258 static int dspxfr_one_seg(struct hda_codec *codec,
2259 const struct dsp_image_seg *fls,
2261 struct dma_engine *dma_engine,
2262 unsigned int dma_chan,
2263 unsigned int port_map_mask,
2267 bool comm_dma_setup_done = false;
2268 const unsigned int *data;
2269 unsigned int chip_addx;
2270 unsigned int words_to_write;
2271 unsigned int buffer_size_words;
2272 unsigned char *buffer_addx;
2273 unsigned short hda_format;
2274 unsigned int sample_rate_div;
2275 unsigned int sample_rate_mul;
2276 unsigned int num_chans;
2277 unsigned int hda_frame_size_words;
2278 unsigned int remainder_words;
2279 const u32 *data_remainder;
2280 u32 chip_addx_remainder;
2281 unsigned int run_size_words;
2282 const struct dsp_image_seg *hci_write = NULL;
2283 unsigned long timeout;
2288 if (is_hci_prog_list_seg(fls)) {
2290 fls = get_next_seg_ptr(fls);
2293 if (hci_write && (!fls || is_last(fls))) {
2294 codec_dbg(codec, "hci_write\n");
2295 return dspxfr_hci_write(codec, hci_write);
2298 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2299 codec_dbg(codec, "Invalid Params\n");
2304 chip_addx = fls->chip_addr,
2305 words_to_write = fls->count;
2307 if (!words_to_write)
2308 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2310 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2312 if (!UC_RANGE(chip_addx, words_to_write) &&
2313 !X_RANGE_ALL(chip_addx, words_to_write) &&
2314 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2315 codec_dbg(codec, "Invalid chip_addx Params\n");
2319 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2322 buffer_addx = dma_get_buffer_addr(dma_engine);
2324 if (buffer_addx == NULL) {
2325 codec_dbg(codec, "dma_engine buffer NULL\n");
2329 dma_get_converter_format(dma_engine, &hda_format);
2330 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2331 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2332 num_chans = get_hdafmt_chs(hda_format) + 1;
2334 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2335 (num_chans * sample_rate_mul / sample_rate_div));
2337 if (hda_frame_size_words == 0) {
2338 codec_dbg(codec, "frmsz zero\n");
2342 buffer_size_words = min(buffer_size_words,
2343 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2345 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2347 "chpadr=0x%08x frmsz=%u nchan=%u "
2348 "rate_mul=%u div=%u bufsz=%u\n",
2349 chip_addx, hda_frame_size_words, num_chans,
2350 sample_rate_mul, sample_rate_div, buffer_size_words);
2352 if (buffer_size_words < hda_frame_size_words) {
2353 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2357 remainder_words = words_to_write % hda_frame_size_words;
2358 data_remainder = data;
2359 chip_addx_remainder = chip_addx;
2361 data += remainder_words;
2362 chip_addx += remainder_words*sizeof(u32);
2363 words_to_write -= remainder_words;
2365 while (words_to_write != 0) {
2366 run_size_words = min(buffer_size_words, words_to_write);
2367 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2368 words_to_write, run_size_words, remainder_words);
2369 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2370 if (!comm_dma_setup_done) {
2371 status = dsp_dma_stop(codec, dma_chan, ovly);
2374 status = dsp_dma_setup_common(codec, chip_addx,
2375 dma_chan, port_map_mask, ovly);
2378 comm_dma_setup_done = true;
2381 status = dsp_dma_setup(codec, chip_addx,
2382 run_size_words, dma_chan);
2385 status = dsp_dma_start(codec, dma_chan, ovly);
2388 if (!dsp_is_dma_active(codec, dma_chan)) {
2389 codec_dbg(codec, "dspxfr:DMA did not start\n");
2392 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2395 if (remainder_words != 0) {
2396 status = chipio_write_multiple(codec,
2397 chip_addx_remainder,
2402 remainder_words = 0;
2405 status = dspxfr_hci_write(codec, hci_write);
2411 timeout = jiffies + msecs_to_jiffies(2000);
2413 dma_active = dsp_is_dma_active(codec, dma_chan);
2417 } while (time_before(jiffies, timeout));
2421 codec_dbg(codec, "+++++ DMA complete\n");
2422 dma_set_state(dma_engine, DMA_STATE_STOP);
2423 status = dma_reset(dma_engine);
2428 data += run_size_words;
2429 chip_addx += run_size_words*sizeof(u32);
2430 words_to_write -= run_size_words;
2433 if (remainder_words != 0) {
2434 status = chipio_write_multiple(codec, chip_addx_remainder,
2435 data_remainder, remainder_words);
2442 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2444 * @codec: the HDA codec
2445 * @fls_data: pointer to a fast load image
2446 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2448 * @sample_rate: sampling rate of the stream used for DSP download
2449 * @channels: channels of the stream used for DSP download
2450 * @ovly: TRUE if overlay format is required
2452 * Returns zero or a negative error code.
2454 static int dspxfr_image(struct hda_codec *codec,
2455 const struct dsp_image_seg *fls_data,
2457 unsigned int sample_rate,
2458 unsigned short channels,
2461 struct ca0132_spec *spec = codec->spec;
2463 unsigned short hda_format = 0;
2464 unsigned int response;
2465 unsigned char stream_id = 0;
2466 struct dma_engine *dma_engine;
2467 unsigned int dma_chan;
2468 unsigned int port_map_mask;
2470 if (fls_data == NULL)
2473 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2477 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2478 if (!dma_engine->dmab) {
2483 dma_engine->codec = codec;
2484 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2485 dma_engine->m_converter_format = hda_format;
2486 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2487 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2489 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2491 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2492 hda_format, &response);
2495 codec_dbg(codec, "set converter format fail\n");
2499 status = snd_hda_codec_load_dsp_prepare(codec,
2500 dma_engine->m_converter_format,
2501 dma_engine->buf_size,
2505 spec->dsp_stream_id = status;
2508 status = dspio_alloc_dma_chan(codec, &dma_chan);
2510 codec_dbg(codec, "alloc dmachan fail\n");
2511 dma_chan = INVALID_DMA_CHANNEL;
2517 status = dsp_allocate_ports_format(codec, hda_format,
2520 codec_dbg(codec, "alloc ports fail\n");
2524 stream_id = dma_get_stream_id(dma_engine);
2525 status = codec_set_converter_stream_channel(codec,
2526 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2528 codec_dbg(codec, "set stream chan fail\n");
2532 while ((fls_data != NULL) && !is_last(fls_data)) {
2533 if (!is_valid(fls_data)) {
2534 codec_dbg(codec, "FLS check fail\n");
2538 status = dspxfr_one_seg(codec, fls_data, reloc,
2539 dma_engine, dma_chan,
2540 port_map_mask, ovly);
2544 if (is_hci_prog_list_seg(fls_data))
2545 fls_data = get_next_seg_ptr(fls_data);
2547 if ((fls_data != NULL) && !is_last(fls_data))
2548 fls_data = get_next_seg_ptr(fls_data);
2551 if (port_map_mask != 0)
2552 status = dsp_free_ports(codec);
2557 status = codec_set_converter_stream_channel(codec,
2558 WIDGET_CHIP_CTRL, 0, 0, &response);
2561 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2562 dspio_free_dma_chan(codec, dma_chan);
2564 if (dma_engine->dmab->area)
2565 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2566 kfree(dma_engine->dmab);
2573 * CA0132 DSP download stuffs.
2575 static void dspload_post_setup(struct hda_codec *codec)
2577 codec_dbg(codec, "---- dspload_post_setup ------\n");
2579 /*set DSP speaker to 2.0 configuration*/
2580 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2581 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2583 /*update write pointer*/
2584 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2588 * dspload_image - Download DSP from a DSP Image Fast Load structure.
2590 * @codec: the HDA codec
2591 * @fls: pointer to a fast load image
2592 * @ovly: TRUE if overlay format is required
2593 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2595 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2596 * @router_chans: number of audio router channels to be allocated (0 means use
2597 * internal defaults; max is 32)
2599 * Download DSP from a DSP Image Fast Load structure. This structure is a
2600 * linear, non-constant sized element array of structures, each of which
2601 * contain the count of the data to be loaded, the data itself, and the
2602 * corresponding starting chip address of the starting data location.
2603 * Returns zero or a negative error code.
2605 static int dspload_image(struct hda_codec *codec,
2606 const struct dsp_image_seg *fls,
2613 unsigned int sample_rate;
2614 unsigned short channels;
2616 codec_dbg(codec, "---- dspload_image begin ------\n");
2617 if (router_chans == 0) {
2619 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2621 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2624 sample_rate = 48000;
2625 channels = (unsigned short)router_chans;
2627 while (channels > 16) {
2633 codec_dbg(codec, "Ready to program DMA\n");
2635 status = dsp_reset(codec);
2640 codec_dbg(codec, "dsp_reset() complete\n");
2641 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2647 codec_dbg(codec, "dspxfr_image() complete\n");
2648 if (autostart && !ovly) {
2649 dspload_post_setup(codec);
2650 status = dsp_set_run_state(codec);
2653 codec_dbg(codec, "LOAD FINISHED\n");
2659 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
2660 static bool dspload_is_loaded(struct hda_codec *codec)
2662 unsigned int data = 0;
2665 status = chipio_read(codec, 0x40004, &data);
2666 if ((status < 0) || (data != 1))
2672 #define dspload_is_loaded(codec) false
2675 static bool dspload_wait_loaded(struct hda_codec *codec)
2677 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
2680 if (dspload_is_loaded(codec)) {
2681 codec_info(codec, "ca0132 DSP downloaded and running\n");
2685 } while (time_before(jiffies, timeout));
2687 codec_err(codec, "ca0132 failed to download DSP\n");
2694 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2695 struct hda_codec *codec,
2696 unsigned int stream_tag,
2697 unsigned int format,
2698 struct snd_pcm_substream *substream)
2700 struct ca0132_spec *spec = codec->spec;
2702 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2707 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2708 struct hda_codec *codec,
2709 struct snd_pcm_substream *substream)
2711 struct ca0132_spec *spec = codec->spec;
2713 if (spec->dsp_state == DSP_DOWNLOADING)
2716 /*If Playback effects are on, allow stream some time to flush
2718 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2721 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
2726 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2727 struct hda_codec *codec,
2728 struct snd_pcm_substream *substream)
2730 struct ca0132_spec *spec = codec->spec;
2731 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2732 struct snd_pcm_runtime *runtime = substream->runtime;
2734 if (spec->dsp_state != DSP_DOWNLOADED)
2737 /* Add latency if playback enhancement and either effect is enabled. */
2738 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2739 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2740 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2741 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2744 /* Applying Speaker EQ adds latency as well. */
2745 if (spec->cur_out_type == SPEAKER_OUT)
2746 latency += DSP_SPEAKER_OUT_LATENCY;
2748 return (latency * runtime->rate) / 1000;
2754 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2755 struct hda_codec *codec,
2756 struct snd_pcm_substream *substream)
2758 struct ca0132_spec *spec = codec->spec;
2759 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2762 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2763 struct hda_codec *codec,
2764 unsigned int stream_tag,
2765 unsigned int format,
2766 struct snd_pcm_substream *substream)
2768 struct ca0132_spec *spec = codec->spec;
2769 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2770 stream_tag, format, substream);
2773 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2774 struct hda_codec *codec,
2775 struct snd_pcm_substream *substream)
2777 struct ca0132_spec *spec = codec->spec;
2778 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
2781 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2782 struct hda_codec *codec,
2783 struct snd_pcm_substream *substream)
2785 struct ca0132_spec *spec = codec->spec;
2786 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2792 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2793 struct hda_codec *codec,
2794 unsigned int stream_tag,
2795 unsigned int format,
2796 struct snd_pcm_substream *substream)
2798 snd_hda_codec_setup_stream(codec, hinfo->nid,
2799 stream_tag, 0, format);
2804 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2805 struct hda_codec *codec,
2806 struct snd_pcm_substream *substream)
2808 struct ca0132_spec *spec = codec->spec;
2810 if (spec->dsp_state == DSP_DOWNLOADING)
2813 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2817 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2818 struct hda_codec *codec,
2819 struct snd_pcm_substream *substream)
2821 struct ca0132_spec *spec = codec->spec;
2822 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2823 struct snd_pcm_runtime *runtime = substream->runtime;
2825 if (spec->dsp_state != DSP_DOWNLOADED)
2828 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2829 latency += DSP_CRYSTAL_VOICE_LATENCY;
2831 return (latency * runtime->rate) / 1000;
2839 * Mixer controls helpers.
2841 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2842 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2844 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2845 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2846 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2847 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2848 .info = ca0132_volume_info, \
2849 .get = ca0132_volume_get, \
2850 .put = ca0132_volume_put, \
2851 .tlv = { .c = ca0132_volume_tlv }, \
2852 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2854 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2855 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2857 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2858 .info = snd_hda_mixer_amp_switch_info, \
2859 .get = ca0132_switch_get, \
2860 .put = ca0132_switch_put, \
2861 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2864 #define CA0132_CODEC_VOL(xname, nid, dir) \
2865 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2866 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2867 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2869 /* The following are for tuning of products */
2870 #ifdef ENABLE_TUNING_CONTROLS
2872 static unsigned int voice_focus_vals_lookup[] = {
2873 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2874 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2875 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2876 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2877 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2878 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2879 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2880 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2881 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2882 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2883 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2884 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2885 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2886 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2887 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2888 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2889 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2890 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2891 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2892 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2893 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2894 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2895 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2896 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2897 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2898 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2899 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2902 static unsigned int mic_svm_vals_lookup[] = {
2903 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2904 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2905 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2906 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2907 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2908 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2909 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2910 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2911 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2912 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2913 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2914 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2915 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2916 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2917 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2918 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2919 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2922 static unsigned int equalizer_vals_lookup[] = {
2923 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2924 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2925 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2926 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2927 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2928 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2929 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2930 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2934 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2935 unsigned int *lookup, int idx)
2939 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2940 if (nid == ca0132_tuning_ctls[i].nid)
2943 snd_hda_power_up(codec);
2944 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2945 ca0132_tuning_ctls[i].req,
2946 &(lookup[idx]), sizeof(unsigned int));
2947 snd_hda_power_down(codec);
2952 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2953 struct snd_ctl_elem_value *ucontrol)
2955 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2956 struct ca0132_spec *spec = codec->spec;
2957 hda_nid_t nid = get_amp_nid(kcontrol);
2958 long *valp = ucontrol->value.integer.value;
2959 int idx = nid - TUNING_CTL_START_NID;
2961 *valp = spec->cur_ctl_vals[idx];
2965 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2966 struct snd_ctl_elem_info *uinfo)
2968 int chs = get_amp_channels(kcontrol);
2969 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2970 uinfo->count = chs == 3 ? 2 : 1;
2971 uinfo->value.integer.min = 20;
2972 uinfo->value.integer.max = 180;
2973 uinfo->value.integer.step = 1;
2978 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2979 struct snd_ctl_elem_value *ucontrol)
2981 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2982 struct ca0132_spec *spec = codec->spec;
2983 hda_nid_t nid = get_amp_nid(kcontrol);
2984 long *valp = ucontrol->value.integer.value;
2987 idx = nid - TUNING_CTL_START_NID;
2989 if (spec->cur_ctl_vals[idx] == *valp)
2992 spec->cur_ctl_vals[idx] = *valp;
2995 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3000 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3001 struct snd_ctl_elem_info *uinfo)
3003 int chs = get_amp_channels(kcontrol);
3004 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3005 uinfo->count = chs == 3 ? 2 : 1;
3006 uinfo->value.integer.min = 0;
3007 uinfo->value.integer.max = 100;
3008 uinfo->value.integer.step = 1;
3013 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3014 struct snd_ctl_elem_value *ucontrol)
3016 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3017 struct ca0132_spec *spec = codec->spec;
3018 hda_nid_t nid = get_amp_nid(kcontrol);
3019 long *valp = ucontrol->value.integer.value;
3022 idx = nid - TUNING_CTL_START_NID;
3024 if (spec->cur_ctl_vals[idx] == *valp)
3027 spec->cur_ctl_vals[idx] = *valp;
3030 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3035 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3036 struct snd_ctl_elem_info *uinfo)
3038 int chs = get_amp_channels(kcontrol);
3039 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3040 uinfo->count = chs == 3 ? 2 : 1;
3041 uinfo->value.integer.min = 0;
3042 uinfo->value.integer.max = 48;
3043 uinfo->value.integer.step = 1;
3048 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3049 struct snd_ctl_elem_value *ucontrol)
3051 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3052 struct ca0132_spec *spec = codec->spec;
3053 hda_nid_t nid = get_amp_nid(kcontrol);
3054 long *valp = ucontrol->value.integer.value;
3057 idx = nid - TUNING_CTL_START_NID;
3059 if (spec->cur_ctl_vals[idx] == *valp)
3062 spec->cur_ctl_vals[idx] = *valp;
3065 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3070 static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3071 static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3073 static int add_tuning_control(struct hda_codec *codec,
3074 hda_nid_t pnid, hda_nid_t nid,
3075 const char *name, int dir)
3077 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3078 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3079 struct snd_kcontrol_new knew =
3080 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3082 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3083 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3088 knew.info = voice_focus_ctl_info;
3089 knew.get = tuning_ctl_get;
3090 knew.put = voice_focus_ctl_put;
3091 knew.tlv.p = voice_focus_db_scale;
3094 knew.info = mic_svm_ctl_info;
3095 knew.get = tuning_ctl_get;
3096 knew.put = mic_svm_ctl_put;
3099 knew.info = equalizer_ctl_info;
3100 knew.get = tuning_ctl_get;
3101 knew.put = equalizer_ctl_put;
3102 knew.tlv.p = eq_db_scale;
3107 knew.private_value =
3108 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3109 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3110 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3113 static int add_tuning_ctls(struct hda_codec *codec)
3118 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3119 err = add_tuning_control(codec,
3120 ca0132_tuning_ctls[i].parent_nid,
3121 ca0132_tuning_ctls[i].nid,
3122 ca0132_tuning_ctls[i].name,
3123 ca0132_tuning_ctls[i].direct);
3131 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3133 struct ca0132_spec *spec = codec->spec;
3136 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3137 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3138 /* SVM level defaults to 0.74. */
3139 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3141 /* EQ defaults to 0dB. */
3142 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3143 spec->cur_ctl_vals[i] = 24;
3145 #endif /*ENABLE_TUNING_CONTROLS*/
3148 * Select the active output.
3149 * If autodetect is enabled, output will be selected based on jack detection.
3150 * If jack inserted, headphone will be selected, else built-in speakers
3151 * If autodetect is disabled, output will be selected based on selection.
3153 static int ca0132_select_out(struct hda_codec *codec)
3155 struct ca0132_spec *spec = codec->spec;
3156 unsigned int pin_ctl;
3162 codec_dbg(codec, "ca0132_select_out\n");
3164 snd_hda_power_up_pm(codec);
3166 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3169 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
3172 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3175 spec->cur_out_type = HEADPHONE_OUT;
3177 spec->cur_out_type = SPEAKER_OUT;
3179 if (spec->cur_out_type == SPEAKER_OUT) {
3180 codec_dbg(codec, "ca0132_select_out speaker\n");
3181 /*speaker out config*/
3183 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3186 /*enable speaker EQ*/
3188 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3193 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3194 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3195 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3196 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3197 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3198 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3199 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3200 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3202 /* disable headphone node */
3203 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3204 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3205 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3207 /* enable speaker node */
3208 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3209 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3210 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3213 codec_dbg(codec, "ca0132_select_out hp\n");
3214 /*headphone out config*/
3216 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3219 /*disable speaker EQ*/
3221 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3226 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3227 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3228 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3229 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3230 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3231 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3232 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3233 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3235 /* disable speaker*/
3236 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3237 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3238 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3240 /* enable headphone*/
3241 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3242 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3243 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3248 snd_hda_power_down_pm(codec);
3250 return err < 0 ? err : 0;
3253 static void ca0132_unsol_hp_delayed(struct work_struct *work)
3255 struct ca0132_spec *spec = container_of(
3256 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
3257 struct hda_jack_tbl *jack;
3259 ca0132_select_out(spec->codec);
3260 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
3262 jack->block_report = 0;
3263 snd_hda_jack_report_sync(spec->codec);
3267 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3268 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3269 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3272 * Select the active VIP source
3274 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3276 struct ca0132_spec *spec = codec->spec;
3279 if (spec->dsp_state != DSP_DOWNLOADED)
3282 /* if CrystalVoice if off, vipsource should be 0 */
3283 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3285 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3286 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3287 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3288 if (spec->cur_mic_type == DIGITAL_MIC)
3292 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3294 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3296 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3297 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3298 if (spec->cur_mic_type == DIGITAL_MIC)
3302 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3304 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3306 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3313 * Select the active microphone.
3314 * If autodetect is enabled, mic will be selected based on jack detection.
3315 * If jack inserted, ext.mic will be selected, else built-in mic
3316 * If autodetect is disabled, mic will be selected based on selection.
3318 static int ca0132_select_mic(struct hda_codec *codec)
3320 struct ca0132_spec *spec = codec->spec;
3324 codec_dbg(codec, "ca0132_select_mic\n");
3326 snd_hda_power_up_pm(codec);
3328 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3331 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
3334 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3337 spec->cur_mic_type = LINE_MIC_IN;
3339 spec->cur_mic_type = DIGITAL_MIC;
3341 if (spec->cur_mic_type == DIGITAL_MIC) {
3342 /* enable digital Mic */
3343 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3344 ca0132_set_dmic(codec, 1);
3345 ca0132_mic_boost_set(codec, 0);
3346 /* set voice focus */
3347 ca0132_effects_set(codec, VOICE_FOCUS,
3348 spec->effects_switch
3349 [VOICE_FOCUS - EFFECT_START_NID]);
3351 /* disable digital Mic */
3352 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3353 ca0132_set_dmic(codec, 0);
3354 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3355 /* disable voice focus */
3356 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3359 snd_hda_power_down_pm(codec);
3365 * Check if VNODE settings take effect immediately.
3367 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3369 hda_nid_t *shared_nid)
3371 struct ca0132_spec *spec = codec->spec;
3376 nid = spec->shared_out_nid;
3379 nid = spec->shared_mic_nid;
3392 * The following functions are control change helpers.
3393 * They return 0 if no changed. Return 1 if changed.
3395 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3397 struct ca0132_spec *spec = codec->spec;
3400 /* based on CrystalVoice state to enable VoiceFX. */
3402 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3403 FLOAT_ONE : FLOAT_ZERO;
3408 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3409 ca0132_voicefx.reqs[0], tmp);
3415 * Set the effects parameters
3417 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3419 struct ca0132_spec *spec = codec->spec;
3421 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3423 int idx = nid - EFFECT_START_NID;
3425 if ((idx < 0) || (idx >= num_fx))
3426 return 0; /* no changed */
3428 /* for out effect, qualify with PE */
3429 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3430 /* if PE if off, turn off out effects. */
3431 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3435 /* for in effect, qualify with CrystalVoice */
3436 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3437 /* if CrystalVoice if off, turn off in effects. */
3438 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3441 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3442 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3446 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
3449 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3450 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3451 ca0132_effects[idx].reqs[0], on);
3454 return 0; /* no changed */
3460 * Turn on/off Playback Enhancements
3462 static int ca0132_pe_switch_set(struct hda_codec *codec)
3464 struct ca0132_spec *spec = codec->spec;
3468 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
3469 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3471 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3472 nid = OUT_EFFECT_START_NID;
3473 /* PE affects all out effects */
3474 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3475 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3480 /* Check if Mic1 is streaming, if so, stop streaming */
3481 static int stop_mic1(struct hda_codec *codec)
3483 struct ca0132_spec *spec = codec->spec;
3484 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3485 AC_VERB_GET_CONV, 0);
3487 snd_hda_codec_write(codec, spec->adcs[0], 0,
3488 AC_VERB_SET_CHANNEL_STREAMID,
3493 /* Resume Mic1 streaming if it was stopped. */
3494 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3496 struct ca0132_spec *spec = codec->spec;
3497 /* Restore the previous stream and channel */
3499 snd_hda_codec_write(codec, spec->adcs[0], 0,
3500 AC_VERB_SET_CHANNEL_STREAMID,
3505 * Turn on/off CrystalVoice
3507 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3509 struct ca0132_spec *spec = codec->spec;
3512 unsigned int oldval;
3514 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
3515 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3517 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3518 nid = IN_EFFECT_START_NID;
3519 /* CrystalVoice affects all in effects */
3520 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3521 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3523 /* including VoiceFX */
3524 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3526 /* set correct vipsource */
3527 oldval = stop_mic1(codec);
3528 ret |= ca0132_set_vipsource(codec, 1);
3529 resume_mic1(codec, oldval);
3533 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3535 struct ca0132_spec *spec = codec->spec;
3539 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3540 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3542 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3543 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3548 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3549 struct snd_ctl_elem_value *ucontrol)
3551 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3552 hda_nid_t nid = get_amp_nid(kcontrol);
3553 hda_nid_t shared_nid = 0;
3556 struct ca0132_spec *spec = codec->spec;
3559 if (nid == VNID_HP_SEL) {
3561 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3563 ca0132_select_out(codec);
3567 if (nid == VNID_AMIC1_SEL) {
3569 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3571 ca0132_select_mic(codec);
3575 if (nid == VNID_HP_ASEL) {
3576 ca0132_select_out(codec);
3580 if (nid == VNID_AMIC1_ASEL) {
3581 ca0132_select_mic(codec);
3585 /* if effective conditions, then update hw immediately. */
3586 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3588 int dir = get_amp_direction(kcontrol);
3589 int ch = get_amp_channels(kcontrol);
3592 mutex_lock(&codec->control_mutex);
3593 pval = kcontrol->private_value;
3594 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3596 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3597 kcontrol->private_value = pval;
3598 mutex_unlock(&codec->control_mutex);
3603 /* End of control change helpers. */
3605 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3606 struct snd_ctl_elem_info *uinfo)
3608 unsigned int items = sizeof(ca0132_voicefx_presets)
3609 / sizeof(struct ct_voicefx_preset);
3611 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3613 uinfo->value.enumerated.items = items;
3614 if (uinfo->value.enumerated.item >= items)
3615 uinfo->value.enumerated.item = items - 1;
3616 strcpy(uinfo->value.enumerated.name,
3617 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3621 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3622 struct snd_ctl_elem_value *ucontrol)
3624 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3625 struct ca0132_spec *spec = codec->spec;
3627 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3631 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3632 struct snd_ctl_elem_value *ucontrol)
3634 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3635 struct ca0132_spec *spec = codec->spec;
3637 int sel = ucontrol->value.enumerated.item[0];
3638 unsigned int items = sizeof(ca0132_voicefx_presets)
3639 / sizeof(struct ct_voicefx_preset);
3644 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
3645 sel, ca0132_voicefx_presets[sel].name);
3649 * Default needs to qualify with CrystalVoice state.
3651 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3652 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3653 ca0132_voicefx.reqs[i],
3654 ca0132_voicefx_presets[sel].vals[i]);
3660 spec->voicefx_val = sel;
3661 /* enable voice fx */
3662 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3668 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3669 struct snd_ctl_elem_value *ucontrol)
3671 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3672 struct ca0132_spec *spec = codec->spec;
3673 hda_nid_t nid = get_amp_nid(kcontrol);
3674 int ch = get_amp_channels(kcontrol);
3675 long *valp = ucontrol->value.integer.value;
3678 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3680 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3684 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3690 /* effects, include PE and CrystalVoice */
3691 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3692 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3697 if (nid == spec->input_pins[0]) {
3698 *valp = spec->cur_mic_boost;
3705 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3706 struct snd_ctl_elem_value *ucontrol)
3708 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3709 struct ca0132_spec *spec = codec->spec;
3710 hda_nid_t nid = get_amp_nid(kcontrol);
3711 int ch = get_amp_channels(kcontrol);
3712 long *valp = ucontrol->value.integer.value;
3715 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
3718 snd_hda_power_up(codec);
3720 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3722 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3726 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3729 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3734 if (nid == PLAY_ENHANCEMENT) {
3735 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3736 changed = ca0132_pe_switch_set(codec);
3741 if (nid == CRYSTAL_VOICE) {
3742 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3743 changed = ca0132_cvoice_switch_set(codec);
3747 /* out and in effects */
3748 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3749 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3750 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3751 changed = ca0132_effects_set(codec, nid, *valp);
3756 if (nid == spec->input_pins[0]) {
3757 spec->cur_mic_boost = *valp;
3759 /* Mic boost does not apply to Digital Mic */
3760 if (spec->cur_mic_type != DIGITAL_MIC)
3761 changed = ca0132_mic_boost_set(codec, *valp);
3766 snd_hda_power_down(codec);
3773 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3774 struct snd_ctl_elem_info *uinfo)
3776 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3777 struct ca0132_spec *spec = codec->spec;
3778 hda_nid_t nid = get_amp_nid(kcontrol);
3779 int ch = get_amp_channels(kcontrol);
3780 int dir = get_amp_direction(kcontrol);
3786 /* follow shared_out info */
3787 nid = spec->shared_out_nid;
3788 mutex_lock(&codec->control_mutex);
3789 pval = kcontrol->private_value;
3790 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3791 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3792 kcontrol->private_value = pval;
3793 mutex_unlock(&codec->control_mutex);
3796 /* follow shared_mic info */
3797 nid = spec->shared_mic_nid;
3798 mutex_lock(&codec->control_mutex);
3799 pval = kcontrol->private_value;
3800 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3801 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3802 kcontrol->private_value = pval;
3803 mutex_unlock(&codec->control_mutex);
3806 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3811 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3812 struct snd_ctl_elem_value *ucontrol)
3814 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3815 struct ca0132_spec *spec = codec->spec;
3816 hda_nid_t nid = get_amp_nid(kcontrol);
3817 int ch = get_amp_channels(kcontrol);
3818 long *valp = ucontrol->value.integer.value;
3820 /* store the left and right volume */
3822 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3826 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3832 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3833 struct snd_ctl_elem_value *ucontrol)
3835 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3836 struct ca0132_spec *spec = codec->spec;
3837 hda_nid_t nid = get_amp_nid(kcontrol);
3838 int ch = get_amp_channels(kcontrol);
3839 long *valp = ucontrol->value.integer.value;
3840 hda_nid_t shared_nid = 0;
3844 /* store the left and right volume */
3846 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3850 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3854 /* if effective conditions, then update hw immediately. */
3855 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3857 int dir = get_amp_direction(kcontrol);
3860 snd_hda_power_up(codec);
3861 mutex_lock(&codec->control_mutex);
3862 pval = kcontrol->private_value;
3863 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3865 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3866 kcontrol->private_value = pval;
3867 mutex_unlock(&codec->control_mutex);
3868 snd_hda_power_down(codec);
3874 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3875 unsigned int size, unsigned int __user *tlv)
3877 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3878 struct ca0132_spec *spec = codec->spec;
3879 hda_nid_t nid = get_amp_nid(kcontrol);
3880 int ch = get_amp_channels(kcontrol);
3881 int dir = get_amp_direction(kcontrol);
3887 /* follow shared_out tlv */
3888 nid = spec->shared_out_nid;
3889 mutex_lock(&codec->control_mutex);
3890 pval = kcontrol->private_value;
3891 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3892 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3893 kcontrol->private_value = pval;
3894 mutex_unlock(&codec->control_mutex);
3897 /* follow shared_mic tlv */
3898 nid = spec->shared_mic_nid;
3899 mutex_lock(&codec->control_mutex);
3900 pval = kcontrol->private_value;
3901 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3902 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3903 kcontrol->private_value = pval;
3904 mutex_unlock(&codec->control_mutex);
3907 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3912 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3913 const char *pfx, int dir)
3915 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3916 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3917 struct snd_kcontrol_new knew =
3918 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3919 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3920 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3923 static int add_voicefx(struct hda_codec *codec)
3925 struct snd_kcontrol_new knew =
3926 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3927 VOICEFX, 1, 0, HDA_INPUT);
3928 knew.info = ca0132_voicefx_info;
3929 knew.get = ca0132_voicefx_get;
3930 knew.put = ca0132_voicefx_put;
3931 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3935 * When changing Node IDs for Mixer Controls below, make sure to update
3936 * Node IDs in ca0132_config() as well.
3938 static struct snd_kcontrol_new ca0132_mixer[] = {
3939 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3940 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3941 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3942 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3943 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3944 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3945 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3946 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3947 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3948 0x12, 1, HDA_INPUT),
3949 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3950 VNID_HP_SEL, 1, HDA_OUTPUT),
3951 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3952 VNID_AMIC1_SEL, 1, HDA_INPUT),
3953 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3954 VNID_HP_ASEL, 1, HDA_OUTPUT),
3955 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3956 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3960 static int ca0132_build_controls(struct hda_codec *codec)
3962 struct ca0132_spec *spec = codec->spec;
3966 /* Add Mixer controls */
3967 for (i = 0; i < spec->num_mixers; i++) {
3968 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3973 /* Add in and out effects controls.
3974 * VoiceFX, PE and CrystalVoice are added separately.
3976 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3977 for (i = 0; i < num_fx; i++) {
3978 err = add_fx_switch(codec, ca0132_effects[i].nid,
3979 ca0132_effects[i].name,
3980 ca0132_effects[i].direct);
3985 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3989 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3995 #ifdef ENABLE_TUNING_CONTROLS
3996 add_tuning_ctls(codec);
3999 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
4003 if (spec->dig_out) {
4004 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
4008 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
4011 /* spec->multiout.share_spdif = 1; */
4015 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4025 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
4030 .prepare = ca0132_playback_pcm_prepare,
4031 .cleanup = ca0132_playback_pcm_cleanup,
4032 .get_delay = ca0132_playback_pcm_delay,
4036 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
4041 .prepare = ca0132_capture_pcm_prepare,
4042 .cleanup = ca0132_capture_pcm_cleanup,
4043 .get_delay = ca0132_capture_pcm_delay,
4047 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
4052 .open = ca0132_dig_playback_pcm_open,
4053 .close = ca0132_dig_playback_pcm_close,
4054 .prepare = ca0132_dig_playback_pcm_prepare,
4055 .cleanup = ca0132_dig_playback_pcm_cleanup
4059 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
4065 static int ca0132_build_pcms(struct hda_codec *codec)
4067 struct ca0132_spec *spec = codec->spec;
4068 struct hda_pcm *info;
4070 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
4073 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4074 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4075 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4076 spec->multiout.max_channels;
4077 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4078 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4079 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4081 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
4084 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4085 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4086 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4088 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
4091 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4092 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4093 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4095 if (!spec->dig_out && !spec->dig_in)
4098 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
4101 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4102 if (spec->dig_out) {
4103 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4104 ca0132_pcm_digital_playback;
4105 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4108 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4109 ca0132_pcm_digital_capture;
4110 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4116 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4119 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
4120 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4121 snd_hda_codec_write(codec, pin, 0,
4122 AC_VERB_SET_AMP_GAIN_MUTE,
4125 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4126 snd_hda_codec_write(codec, dac, 0,
4127 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4130 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4133 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
4134 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4135 snd_hda_codec_write(codec, pin, 0,
4136 AC_VERB_SET_AMP_GAIN_MUTE,
4139 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4140 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4143 /* init to 0 dB and unmute. */
4144 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4145 HDA_AMP_VOLMASK, 0x5a);
4146 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4151 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4155 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4156 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4157 snd_hda_override_amp_caps(codec, nid, dir, caps);
4161 * Switch between Digital built-in mic and analog mic.
4163 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4165 struct ca0132_spec *spec = codec->spec;
4168 unsigned int oldval;
4170 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
4172 oldval = stop_mic1(codec);
4173 ca0132_set_vipsource(codec, 0);
4175 /* set DMic input as 2-ch */
4177 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4179 val = spec->dmic_ctl;
4181 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4182 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4184 if (!(spec->dmic_ctl & 0x20))
4185 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4187 /* set AMic input as mono */
4189 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4191 val = spec->dmic_ctl;
4192 /* clear bit7 and bit5 to disable dmic */
4194 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4195 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4197 if (!(spec->dmic_ctl & 0x20))
4198 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4200 ca0132_set_vipsource(codec, 1);
4201 resume_mic1(codec, oldval);
4205 * Initialization for Digital Mic.
4207 static void ca0132_init_dmic(struct hda_codec *codec)
4209 struct ca0132_spec *spec = codec->spec;
4212 /* Setup Digital Mic here, but don't enable.
4213 * Enable based on jack detect.
4216 /* MCLK uses MPIO1, set to enable.
4217 * Bit 2-0: MPIO select
4218 * Bit 3: set to disable
4222 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4223 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4225 /* Data1 uses MPIO3. Data2 not use
4226 * Bit 2-0: Data1 MPIO select
4227 * Bit 3: set disable Data1
4228 * Bit 6-4: Data2 MPIO select
4229 * Bit 7: set disable Data2
4232 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4233 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4235 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4236 * Bit 3-0: Channel mask
4237 * Bit 4: set for 48KHz, clear for 32KHz
4239 * Bit 6: set to select Data2, clear for Data1
4240 * Bit 7: set to enable DMic, clear for AMic
4243 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4244 spec->dmic_ctl = val;
4245 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4246 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4250 * Initialization for Analog Mic 2
4252 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4254 struct ca0132_spec *spec = codec->spec;
4256 mutex_lock(&spec->chipio_mutex);
4257 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4258 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4259 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4260 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4261 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4262 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4263 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4264 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4265 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4266 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4267 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4268 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4269 mutex_unlock(&spec->chipio_mutex);
4272 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4274 struct ca0132_spec *spec = codec->spec;
4277 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
4278 snd_hda_codec_update_widgets(codec);
4280 for (i = 0; i < spec->multiout.num_dacs; i++)
4281 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4283 for (i = 0; i < spec->num_outputs; i++)
4284 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4286 for (i = 0; i < spec->num_inputs; i++) {
4287 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4288 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4293 * Setup default parameters for DSP
4295 static void ca0132_setup_defaults(struct hda_codec *codec)
4297 struct ca0132_spec *spec = codec->spec;
4302 if (spec->dsp_state != DSP_DOWNLOADED)
4305 /* out, in effects + voicefx */
4306 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4307 for (idx = 0; idx < num_fx; idx++) {
4308 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4309 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4310 ca0132_effects[idx].reqs[i],
4311 ca0132_effects[idx].def_vals[i]);
4315 /*remove DSP headroom*/
4317 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4319 /*set speaker EQ bypass attenuation*/
4320 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4322 /* set AMic1 and AMic2 as mono mic */
4324 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4325 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4327 /* set AMic1 as CrystalVoice input */
4329 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4331 /* set WUH source */
4333 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4337 * Initialization of flags in chip
4339 static void ca0132_init_flags(struct hda_codec *codec)
4341 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4342 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4343 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4344 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4345 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4346 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4350 * Initialization of parameters in chip
4352 static void ca0132_init_params(struct hda_codec *codec)
4354 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4355 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4358 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4360 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4361 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4362 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4363 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4364 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4365 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4367 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4368 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4369 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4372 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4374 bool dsp_loaded = false;
4375 const struct dsp_image_seg *dsp_os_image;
4376 const struct firmware *fw_entry;
4378 if (request_firmware(&fw_entry, EFX_FILE, codec->card->dev) != 0)
4381 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
4382 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
4383 codec_err(codec, "ca0132 DSP load image failed\n");
4387 dsp_loaded = dspload_wait_loaded(codec);
4390 release_firmware(fw_entry);
4395 static void ca0132_download_dsp(struct hda_codec *codec)
4397 struct ca0132_spec *spec = codec->spec;
4399 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4403 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
4404 return; /* don't retry failures */
4406 chipio_enable_clocks(codec);
4407 spec->dsp_state = DSP_DOWNLOADING;
4408 if (!ca0132_download_dsp_images(codec))
4409 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4411 spec->dsp_state = DSP_DOWNLOADED;
4413 if (spec->dsp_state == DSP_DOWNLOADED)
4414 ca0132_set_dsp_msr(codec, true);
4417 static void ca0132_process_dsp_response(struct hda_codec *codec,
4418 struct hda_jack_callback *callback)
4420 struct ca0132_spec *spec = codec->spec;
4422 codec_dbg(codec, "ca0132_process_dsp_response\n");
4423 if (spec->wait_scp) {
4424 if (dspio_get_response_data(codec) >= 0)
4428 dspio_clear_response_queue(codec);
4431 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4433 struct ca0132_spec *spec = codec->spec;
4434 struct hda_jack_tbl *tbl;
4436 /* Delay enabling the HP amp, to let the mic-detection
4437 * state machine run.
4439 cancel_delayed_work_sync(&spec->unsol_hp_work);
4440 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
4441 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
4443 tbl->block_report = 1;
4446 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
4448 ca0132_select_mic(codec);
4451 static void ca0132_init_unsol(struct hda_codec *codec)
4453 struct ca0132_spec *spec = codec->spec;
4454 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
4455 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
4457 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
4458 ca0132_process_dsp_response);
4465 /* Sends before DSP download. */
4466 static struct hda_verb ca0132_base_init_verbs[] = {
4467 /*enable ct extension*/
4468 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4473 static struct hda_verb ca0132_base_exit_verbs[] = {
4475 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4476 /*disable ct extension*/
4477 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4481 /* Other verbs tables. Sends after DSP download. */
4482 static struct hda_verb ca0132_init_verbs0[] = {
4483 /* chip init verbs */
4484 {0x15, 0x70D, 0xF0},
4485 {0x15, 0x70E, 0xFE},
4486 {0x15, 0x707, 0x75},
4487 {0x15, 0x707, 0xD3},
4488 {0x15, 0x707, 0x09},
4489 {0x15, 0x707, 0x53},
4490 {0x15, 0x707, 0xD4},
4491 {0x15, 0x707, 0xEF},
4492 {0x15, 0x707, 0x75},
4493 {0x15, 0x707, 0xD3},
4494 {0x15, 0x707, 0x09},
4495 {0x15, 0x707, 0x02},
4496 {0x15, 0x707, 0x37},
4497 {0x15, 0x707, 0x78},
4498 {0x15, 0x53C, 0xCE},
4499 {0x15, 0x575, 0xC9},
4500 {0x15, 0x53D, 0xCE},
4501 {0x15, 0x5B7, 0xC9},
4502 {0x15, 0x70D, 0xE8},
4503 {0x15, 0x70E, 0xFE},
4504 {0x15, 0x707, 0x02},
4505 {0x15, 0x707, 0x68},
4506 {0x15, 0x707, 0x62},
4507 {0x15, 0x53A, 0xCE},
4508 {0x15, 0x546, 0xC9},
4509 {0x15, 0x53B, 0xCE},
4510 {0x15, 0x5E8, 0xC9},
4511 {0x15, 0x717, 0x0D},
4512 {0x15, 0x718, 0x20},
4516 static void ca0132_init_chip(struct hda_codec *codec)
4518 struct ca0132_spec *spec = codec->spec;
4523 mutex_init(&spec->chipio_mutex);
4525 spec->cur_out_type = SPEAKER_OUT;
4526 spec->cur_mic_type = DIGITAL_MIC;
4527 spec->cur_mic_boost = 0;
4529 for (i = 0; i < VNODES_COUNT; i++) {
4530 spec->vnode_lvol[i] = 0x5a;
4531 spec->vnode_rvol[i] = 0x5a;
4532 spec->vnode_lswitch[i] = 0;
4533 spec->vnode_rswitch[i] = 0;
4537 * Default states for effects are in ca0132_effects[].
4539 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4540 for (i = 0; i < num_fx; i++) {
4541 on = (unsigned int)ca0132_effects[i].reqs[0];
4542 spec->effects_switch[i] = on ? 1 : 0;
4545 spec->voicefx_val = 0;
4546 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4547 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4549 #ifdef ENABLE_TUNING_CONTROLS
4550 ca0132_init_tuning_defaults(codec);
4554 static void ca0132_exit_chip(struct hda_codec *codec)
4556 /* put any chip cleanup stuffs here. */
4558 if (dspload_is_loaded(codec))
4562 static int ca0132_init(struct hda_codec *codec)
4564 struct ca0132_spec *spec = codec->spec;
4565 struct auto_pin_cfg *cfg = &spec->autocfg;
4568 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
4569 spec->dsp_state = DSP_DOWNLOAD_INIT;
4570 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
4572 snd_hda_power_up_pm(codec);
4574 ca0132_init_unsol(codec);
4576 ca0132_init_params(codec);
4577 ca0132_init_flags(codec);
4578 snd_hda_sequence_write(codec, spec->base_init_verbs);
4579 ca0132_download_dsp(codec);
4580 ca0132_refresh_widget_caps(codec);
4581 ca0132_setup_defaults(codec);
4582 ca0132_init_analog_mic2(codec);
4583 ca0132_init_dmic(codec);
4585 for (i = 0; i < spec->num_outputs; i++)
4586 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4588 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4590 for (i = 0; i < spec->num_inputs; i++)
4591 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4593 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4595 snd_hda_sequence_write(codec, spec->chip_init_verbs);
4596 snd_hda_sequence_write(codec, spec->spec_init_verbs);
4598 ca0132_select_out(codec);
4599 ca0132_select_mic(codec);
4601 snd_hda_jack_report_sync(codec);
4603 snd_hda_power_down_pm(codec);
4608 static void ca0132_free(struct hda_codec *codec)
4610 struct ca0132_spec *spec = codec->spec;
4612 cancel_delayed_work_sync(&spec->unsol_hp_work);
4613 snd_hda_power_up(codec);
4614 snd_hda_sequence_write(codec, spec->base_exit_verbs);
4615 ca0132_exit_chip(codec);
4616 snd_hda_power_down(codec);
4617 kfree(spec->spec_init_verbs);
4621 static const struct hda_codec_ops ca0132_patch_ops = {
4622 .build_controls = ca0132_build_controls,
4623 .build_pcms = ca0132_build_pcms,
4624 .init = ca0132_init,
4625 .free = ca0132_free,
4626 .unsol_event = snd_hda_jack_unsol_event,
4629 static void ca0132_config(struct hda_codec *codec)
4631 struct ca0132_spec *spec = codec->spec;
4632 struct auto_pin_cfg *cfg = &spec->autocfg;
4634 spec->dacs[0] = 0x2;
4635 spec->dacs[1] = 0x3;
4636 spec->dacs[2] = 0x4;
4638 spec->multiout.dac_nids = spec->dacs;
4639 spec->multiout.num_dacs = 3;
4640 spec->multiout.max_channels = 2;
4642 if (spec->quirk == QUIRK_ALIENWARE) {
4643 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
4644 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
4646 spec->num_outputs = 2;
4647 spec->out_pins[0] = 0x0b; /* speaker out */
4648 spec->out_pins[1] = 0x0f;
4649 spec->shared_out_nid = 0x2;
4650 spec->unsol_tag_hp = 0x0f;
4652 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4653 spec->adcs[1] = 0x8; /* analog mic2 */
4654 spec->adcs[2] = 0xa; /* what u hear */
4656 spec->num_inputs = 3;
4657 spec->input_pins[0] = 0x12;
4658 spec->input_pins[1] = 0x11;
4659 spec->input_pins[2] = 0x13;
4660 spec->shared_mic_nid = 0x7;
4661 spec->unsol_tag_amic1 = 0x11;
4663 spec->num_outputs = 2;
4664 spec->out_pins[0] = 0x0b; /* speaker out */
4665 spec->out_pins[1] = 0x10; /* headphone out */
4666 spec->shared_out_nid = 0x2;
4667 spec->unsol_tag_hp = spec->out_pins[1];
4669 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4670 spec->adcs[1] = 0x8; /* analog mic2 */
4671 spec->adcs[2] = 0xa; /* what u hear */
4673 spec->num_inputs = 3;
4674 spec->input_pins[0] = 0x12;
4675 spec->input_pins[1] = 0x11;
4676 spec->input_pins[2] = 0x13;
4677 spec->shared_mic_nid = 0x7;
4678 spec->unsol_tag_amic1 = spec->input_pins[0];
4681 spec->dig_out = 0x05;
4682 spec->multiout.dig_out_nid = spec->dig_out;
4683 cfg->dig_out_pins[0] = 0x0c;
4685 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4686 spec->dig_in = 0x09;
4687 cfg->dig_in_pin = 0x0e;
4688 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4692 static int ca0132_prepare_verbs(struct hda_codec *codec)
4694 /* Verbs + terminator (an empty element) */
4695 #define NUM_SPEC_VERBS 4
4696 struct ca0132_spec *spec = codec->spec;
4698 spec->chip_init_verbs = ca0132_init_verbs0;
4699 spec->spec_init_verbs = kzalloc(sizeof(struct hda_verb) * NUM_SPEC_VERBS, GFP_KERNEL);
4700 if (!spec->spec_init_verbs)
4703 /* HP jack autodetection */
4704 spec->spec_init_verbs[0].nid = spec->unsol_tag_hp;
4705 spec->spec_init_verbs[0].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4706 spec->spec_init_verbs[0].verb = AC_USRSP_EN | spec->unsol_tag_hp;
4708 /* MIC1 jack autodetection */
4709 spec->spec_init_verbs[1].nid = spec->unsol_tag_amic1;
4710 spec->spec_init_verbs[1].param = AC_VERB_SET_UNSOLICITED_ENABLE;
4711 spec->spec_init_verbs[1].verb = AC_USRSP_EN | spec->unsol_tag_amic1;
4714 spec->spec_init_verbs[2].nid = 0x0b;
4715 spec->spec_init_verbs[2].param = 0x78D;
4716 spec->spec_init_verbs[2].verb = 0x00;
4718 /* Previously commented configuration */
4720 spec->spec_init_verbs[3].nid = 0x0b;
4721 spec->spec_init_verbs[3].param = AC_VERB_SET_EAPD_BTLENABLE;
4722 spec->spec_init_verbs[3].verb = 0x02;
4724 spec->spec_init_verbs[4].nid = 0x10;
4725 spec->spec_init_verbs[4].param = 0x78D;
4726 spec->spec_init_verbs[4].verb = 0x02;
4728 spec->spec_init_verbs[5].nid = 0x10;
4729 spec->spec_init_verbs[5].param = AC_VERB_SET_EAPD_BTLENABLE;
4730 spec->spec_init_verbs[5].verb = 0x02;
4733 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
4737 static int patch_ca0132(struct hda_codec *codec)
4739 struct ca0132_spec *spec;
4741 const struct snd_pci_quirk *quirk;
4743 codec_dbg(codec, "patch_ca0132\n");
4745 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4749 spec->codec = codec;
4751 codec->patch_ops = ca0132_patch_ops;
4752 codec->pcm_format_first = 1;
4753 codec->no_sticky_stream = 1;
4755 /* Detect codec quirk */
4756 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
4758 spec->quirk = quirk->value;
4760 spec->quirk = QUIRK_NONE;
4762 spec->dsp_state = DSP_DOWNLOAD_INIT;
4763 spec->num_mixers = 1;
4764 spec->mixers[0] = ca0132_mixer;
4766 spec->base_init_verbs = ca0132_base_init_verbs;
4767 spec->base_exit_verbs = ca0132_base_exit_verbs;
4769 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4771 ca0132_init_chip(codec);
4773 ca0132_config(codec);
4775 err = ca0132_prepare_verbs(codec);
4779 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4789 static struct hda_device_id snd_hda_id_ca0132[] = {
4790 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
4793 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
4795 MODULE_LICENSE("GPL");
4796 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4798 static struct hda_codec_driver ca0132_driver = {
4799 .id = snd_hda_id_ca0132,
4802 module_hda_codec_driver(ca0132_driver);