3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
12 * Wu Fengguang <wfg@linux.intel.com>
15 * Wu Fengguang <wfg@linux.intel.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include <sound/hda_chmap.h>
43 #include "hda_codec.h"
44 #include "hda_local.h"
47 static bool static_hdmi_pcm;
48 module_param(static_hdmi_pcm, bool, 0644);
49 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
51 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
52 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
53 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
54 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
55 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
56 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
57 || is_skylake(codec) || is_broxton(codec) \
58 || is_kabylake(codec))
60 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
61 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
62 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
64 struct hdmi_spec_per_cvt {
67 unsigned int channels_min;
68 unsigned int channels_max;
74 /* max. connections to a widget */
75 #define HDA_MAX_CONNECTIONS 32
77 struct hdmi_spec_per_pin {
79 /* pin idx, different device entries on the same pin use the same idx */
82 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
86 struct hda_codec *codec;
87 struct hdmi_eld sink_eld;
89 struct delayed_work work;
90 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
91 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
93 bool setup; /* the stream has been set up by prepare callback */
94 int channels; /* current number of channels */
96 bool chmap_set; /* channel-map override by ALSA API? */
97 unsigned char chmap[8]; /* ALSA API channel-map */
98 #ifdef CONFIG_SND_PROC_FS
99 struct snd_info_entry *proc_entry;
103 /* operations used by generic code that can be overridden by patches */
105 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
106 unsigned char *buf, int *eld_size);
108 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
109 int ca, int active_channels, int conn_type);
111 /* enable/disable HBR (HD passthrough) */
112 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
114 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
115 hda_nid_t pin_nid, u32 stream_tag, int format);
121 struct snd_jack *jack;
122 struct snd_kcontrol *eld_ctl;
127 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
128 hda_nid_t cvt_nids[4]; /* only for haswell fix */
131 struct snd_array pins; /* struct hdmi_spec_per_pin */
132 struct hdmi_pcm pcm_rec[16];
133 struct mutex pcm_lock;
134 /* pcm_bitmap means which pcms have been assigned to pins*/
135 unsigned long pcm_bitmap;
136 int pcm_used; /* counter of pcm_rec[] */
137 /* bitmap shows whether the pcm is opened in user space
138 * bit 0 means the first playback PCM (PCM3);
139 * bit 1 means the second playback PCM, and so on.
141 unsigned long pcm_in_use;
143 struct hdmi_eld temp_eld;
149 * Non-generic VIA/NVIDIA specific
151 struct hda_multi_out multiout;
152 struct hda_pcm_stream pcm_playback;
154 /* i915/powerwell (Haswell+/Valleyview+) specific */
155 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
156 struct i915_audio_component_audio_ops i915_audio_ops;
157 bool i915_bound; /* was i915 bound in this driver? */
159 struct hdac_chmap chmap;
162 #ifdef CONFIG_SND_HDA_I915
163 static inline bool codec_has_acomp(struct hda_codec *codec)
165 struct hdmi_spec *spec = codec->spec;
166 return spec->use_acomp_notifier;
169 #define codec_has_acomp(codec) false
172 struct hdmi_audio_infoframe {
179 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
183 u8 LFEPBL01_LSV36_DM_INH7;
186 struct dp_audio_infoframe {
189 u8 ver; /* 0x11 << 2 */
191 u8 CC02_CT47; /* match with HDMI infoframe from this on */
195 u8 LFEPBL01_LSV36_DM_INH7;
198 union audio_infoframe {
199 struct hdmi_audio_infoframe hdmi;
200 struct dp_audio_infoframe dp;
208 #define get_pin(spec, idx) \
209 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
210 #define get_cvt(spec, idx) \
211 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
212 /* obtain hdmi_pcm object assigned to idx */
213 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
214 /* obtain hda_pcm object assigned to idx */
215 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
217 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
219 struct hdmi_spec *spec = codec->spec;
222 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
223 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
226 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
230 static int hinfo_to_pcm_index(struct hda_codec *codec,
231 struct hda_pcm_stream *hinfo)
233 struct hdmi_spec *spec = codec->spec;
236 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
237 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
240 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
244 static int hinfo_to_pin_index(struct hda_codec *codec,
245 struct hda_pcm_stream *hinfo)
247 struct hdmi_spec *spec = codec->spec;
248 struct hdmi_spec_per_pin *per_pin;
251 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
252 per_pin = get_pin(spec, pin_idx);
254 per_pin->pcm->pcm->stream == hinfo)
258 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
262 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
266 struct hdmi_spec_per_pin *per_pin;
268 for (i = 0; i < spec->num_pins; i++) {
269 per_pin = get_pin(spec, i);
270 if (per_pin->pcm_idx == pcm_idx)
276 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
278 struct hdmi_spec *spec = codec->spec;
281 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
282 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
285 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
289 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
290 struct snd_ctl_elem_info *uinfo)
292 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
293 struct hdmi_spec *spec = codec->spec;
294 struct hdmi_spec_per_pin *per_pin;
295 struct hdmi_eld *eld;
298 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
300 pcm_idx = kcontrol->private_value;
301 mutex_lock(&spec->pcm_lock);
302 per_pin = pcm_idx_to_pin(spec, pcm_idx);
304 /* no pin is bound to the pcm */
306 mutex_unlock(&spec->pcm_lock);
309 eld = &per_pin->sink_eld;
310 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
311 mutex_unlock(&spec->pcm_lock);
316 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
317 struct snd_ctl_elem_value *ucontrol)
319 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
320 struct hdmi_spec *spec = codec->spec;
321 struct hdmi_spec_per_pin *per_pin;
322 struct hdmi_eld *eld;
325 pcm_idx = kcontrol->private_value;
326 mutex_lock(&spec->pcm_lock);
327 per_pin = pcm_idx_to_pin(spec, pcm_idx);
329 /* no pin is bound to the pcm */
330 memset(ucontrol->value.bytes.data, 0,
331 ARRAY_SIZE(ucontrol->value.bytes.data));
332 mutex_unlock(&spec->pcm_lock);
335 eld = &per_pin->sink_eld;
337 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
338 eld->eld_size > ELD_MAX_SIZE) {
339 mutex_unlock(&spec->pcm_lock);
344 memset(ucontrol->value.bytes.data, 0,
345 ARRAY_SIZE(ucontrol->value.bytes.data));
347 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
349 mutex_unlock(&spec->pcm_lock);
354 static struct snd_kcontrol_new eld_bytes_ctl = {
355 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
356 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
358 .info = hdmi_eld_ctl_info,
359 .get = hdmi_eld_ctl_get,
362 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
365 struct snd_kcontrol *kctl;
366 struct hdmi_spec *spec = codec->spec;
369 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
372 kctl->private_value = pcm_idx;
373 kctl->id.device = device;
375 /* no pin nid is associated with the kctl now
376 * tbd: associate pin nid to eld ctl later
378 err = snd_hda_ctl_add(codec, 0, kctl);
382 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
387 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
388 int *packet_index, int *byte_index)
392 val = snd_hda_codec_read(codec, pin_nid, 0,
393 AC_VERB_GET_HDMI_DIP_INDEX, 0);
395 *packet_index = val >> 5;
396 *byte_index = val & 0x1f;
400 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
401 int packet_index, int byte_index)
405 val = (packet_index << 5) | (byte_index & 0x1f);
407 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
410 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
413 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
416 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
418 struct hdmi_spec *spec = codec->spec;
422 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
423 snd_hda_codec_write(codec, pin_nid, 0,
424 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
426 if (spec->dyn_pin_out)
427 /* Disable pin out until stream is active */
430 /* Enable pin out: some machines with GM965 gets broken output
431 * when the pin is disabled or changed while using with HDMI
435 snd_hda_codec_write(codec, pin_nid, 0,
436 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
443 #ifdef CONFIG_SND_PROC_FS
444 static void print_eld_info(struct snd_info_entry *entry,
445 struct snd_info_buffer *buffer)
447 struct hdmi_spec_per_pin *per_pin = entry->private_data;
449 mutex_lock(&per_pin->lock);
450 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
451 mutex_unlock(&per_pin->lock);
454 static void write_eld_info(struct snd_info_entry *entry,
455 struct snd_info_buffer *buffer)
457 struct hdmi_spec_per_pin *per_pin = entry->private_data;
459 mutex_lock(&per_pin->lock);
460 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
461 mutex_unlock(&per_pin->lock);
464 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
467 struct hda_codec *codec = per_pin->codec;
468 struct snd_info_entry *entry;
471 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
472 err = snd_card_proc_new(codec->card, name, &entry);
476 snd_info_set_text_ops(entry, per_pin, print_eld_info);
477 entry->c.text.write = write_eld_info;
478 entry->mode |= S_IWUSR;
479 per_pin->proc_entry = entry;
484 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
486 if (!per_pin->codec->bus->shutdown) {
487 snd_info_free_entry(per_pin->proc_entry);
488 per_pin->proc_entry = NULL;
492 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
497 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
503 * Audio InfoFrame routines
507 * Enable Audio InfoFrame Transmission
509 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
512 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
513 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
518 * Disable Audio InfoFrame Transmission
520 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
523 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
524 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
528 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
530 #ifdef CONFIG_SND_DEBUG_VERBOSE
534 size = snd_hdmi_get_eld_size(codec, pin_nid);
535 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
537 for (i = 0; i < 8; i++) {
538 size = snd_hda_codec_read(codec, pin_nid, 0,
539 AC_VERB_GET_HDMI_DIP_SIZE, i);
540 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
545 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
551 for (i = 0; i < 8; i++) {
552 size = snd_hda_codec_read(codec, pin_nid, 0,
553 AC_VERB_GET_HDMI_DIP_SIZE, i);
557 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
558 for (j = 1; j < 1000; j++) {
559 hdmi_write_dip_byte(codec, pin_nid, 0x0);
560 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
562 codec_dbg(codec, "dip index %d: %d != %d\n",
564 if (bi == 0) /* byte index wrapped around */
568 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
574 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
576 u8 *bytes = (u8 *)hdmi_ai;
580 hdmi_ai->checksum = 0;
582 for (i = 0; i < sizeof(*hdmi_ai); i++)
585 hdmi_ai->checksum = -sum;
588 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
594 hdmi_debug_dip_size(codec, pin_nid);
595 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
597 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
598 for (i = 0; i < size; i++)
599 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
602 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
608 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
612 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
613 for (i = 0; i < size; i++) {
614 val = snd_hda_codec_read(codec, pin_nid, 0,
615 AC_VERB_GET_HDMI_DIP_DATA, 0);
623 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
625 int ca, int active_channels,
628 union audio_infoframe ai;
630 memset(&ai, 0, sizeof(ai));
631 if (conn_type == 0) { /* HDMI */
632 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
634 hdmi_ai->type = 0x84;
637 hdmi_ai->CC02_CT47 = active_channels - 1;
639 hdmi_checksum_audio_infoframe(hdmi_ai);
640 } else if (conn_type == 1) { /* DisplayPort */
641 struct dp_audio_infoframe *dp_ai = &ai.dp;
645 dp_ai->ver = 0x11 << 2;
646 dp_ai->CC02_CT47 = active_channels - 1;
649 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
655 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
656 * sizeof(*dp_ai) to avoid partial match/update problems when
657 * the user switches between HDMI/DP monitors.
659 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
662 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
664 active_channels, ca);
665 hdmi_stop_infoframe_trans(codec, pin_nid);
666 hdmi_fill_audio_infoframe(codec, pin_nid,
667 ai.bytes, sizeof(ai));
668 hdmi_start_infoframe_trans(codec, pin_nid);
672 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
673 struct hdmi_spec_per_pin *per_pin,
676 struct hdmi_spec *spec = codec->spec;
677 struct hdac_chmap *chmap = &spec->chmap;
678 hda_nid_t pin_nid = per_pin->pin_nid;
679 int channels = per_pin->channels;
681 struct hdmi_eld *eld;
687 if (is_haswell_plus(codec))
688 snd_hda_codec_write(codec, pin_nid, 0,
689 AC_VERB_SET_AMP_GAIN_MUTE,
692 eld = &per_pin->sink_eld;
694 ca = snd_hdac_channel_allocation(&codec->core,
695 eld->info.spk_alloc, channels,
696 per_pin->chmap_set, non_pcm, per_pin->chmap);
698 active_channels = snd_hdac_get_active_channels(ca);
700 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
704 * always configure channel mapping, it may have been changed by the
705 * user in the meantime
707 snd_hdac_setup_channel_mapping(&spec->chmap,
708 pin_nid, non_pcm, ca, channels,
709 per_pin->chmap, per_pin->chmap_set);
711 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
712 eld->info.conn_type);
714 per_pin->non_pcm = non_pcm;
721 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
723 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
725 struct hdmi_spec *spec = codec->spec;
726 int pin_idx = pin_nid_to_pin_index(codec, nid);
730 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
731 snd_hda_jack_report_sync(codec);
734 static void jack_callback(struct hda_codec *codec,
735 struct hda_jack_callback *jack)
737 check_presence_and_report(codec, jack->nid);
740 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
742 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
743 struct hda_jack_tbl *jack;
744 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
746 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
749 jack->jack_dirty = 1;
752 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
753 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
754 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
756 check_presence_and_report(codec, jack->nid);
759 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
761 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
762 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
763 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
764 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
767 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
782 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
784 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
785 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
787 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
788 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
793 hdmi_intrinsic_event(codec, res);
795 hdmi_non_intrinsic_event(codec, res);
798 static void haswell_verify_D0(struct hda_codec *codec,
799 hda_nid_t cvt_nid, hda_nid_t nid)
803 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
804 * thus pins could only choose converter 0 for use. Make sure the
805 * converters are in correct power state */
806 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
807 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
809 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
810 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
813 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
814 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
815 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
823 /* HBR should be Non-PCM, 8 channels */
824 #define is_hbr_format(format) \
825 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
827 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
830 int pinctl, new_pinctl;
832 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
833 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
834 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
837 return hbr ? -EINVAL : 0;
839 new_pinctl = pinctl & ~AC_PINCTL_EPT;
841 new_pinctl |= AC_PINCTL_EPT_HBR;
843 new_pinctl |= AC_PINCTL_EPT_NATIVE;
846 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
848 pinctl == new_pinctl ? "" : "new-",
851 if (pinctl != new_pinctl)
852 snd_hda_codec_write(codec, pin_nid, 0,
853 AC_VERB_SET_PIN_WIDGET_CONTROL,
861 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
862 hda_nid_t pin_nid, u32 stream_tag, int format)
864 struct hdmi_spec *spec = codec->spec;
867 if (is_haswell_plus(codec))
868 haswell_verify_D0(codec, cvt_nid, pin_nid);
870 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
873 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
877 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
881 /* Try to find an available converter
882 * If pin_idx is less then zero, just try to find an available converter.
883 * Otherwise, try to find an available converter and get the cvt mux index
886 static int hdmi_choose_cvt(struct hda_codec *codec,
887 int pin_idx, int *cvt_id, int *mux_id)
889 struct hdmi_spec *spec = codec->spec;
890 struct hdmi_spec_per_pin *per_pin;
891 struct hdmi_spec_per_cvt *per_cvt = NULL;
892 int cvt_idx, mux_idx = 0;
894 /* pin_idx < 0 means no pin will be bound to the converter */
898 per_pin = get_pin(spec, pin_idx);
900 /* Dynamically assign converter to stream */
901 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
902 per_cvt = get_cvt(spec, cvt_idx);
904 /* Must not already be assigned */
905 if (per_cvt->assigned)
909 /* Must be in pin's mux's list of converters */
910 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
911 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
913 /* Not in mux list */
914 if (mux_idx == per_pin->num_mux_nids)
919 /* No free converters */
920 if (cvt_idx == spec->num_cvts)
924 per_pin->mux_idx = mux_idx;
934 /* Assure the pin select the right convetor */
935 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
936 struct hdmi_spec_per_pin *per_pin)
938 hda_nid_t pin_nid = per_pin->pin_nid;
941 mux_idx = per_pin->mux_idx;
942 curr = snd_hda_codec_read(codec, pin_nid, 0,
943 AC_VERB_GET_CONNECT_SEL, 0);
945 snd_hda_codec_write_cache(codec, pin_nid, 0,
946 AC_VERB_SET_CONNECT_SEL,
950 /* get the mux index for the converter of the pins
951 * converter's mux index is the same for all pins on Intel platform
953 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
958 for (i = 0; i < spec->num_cvts; i++)
959 if (spec->cvt_nids[i] == cvt_nid)
964 /* Intel HDMI workaround to fix audio routing issue:
965 * For some Intel display codecs, pins share the same connection list.
966 * So a conveter can be selected by multiple pins and playback on any of these
967 * pins will generate sound on the external display, because audio flows from
968 * the same converter to the display pipeline. Also muting one pin may make
969 * other pins have no sound output.
970 * So this function assures that an assigned converter for a pin is not selected
973 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
974 hda_nid_t pin_nid, int mux_idx)
976 struct hdmi_spec *spec = codec->spec;
979 struct hdmi_spec_per_cvt *per_cvt;
981 /* configure all pins, including "no physical connection" ones */
982 for_each_hda_codec_node(nid, codec) {
983 unsigned int wid_caps = get_wcaps(codec, nid);
984 unsigned int wid_type = get_wcaps_type(wid_caps);
986 if (wid_type != AC_WID_PIN)
992 curr = snd_hda_codec_read(codec, nid, 0,
993 AC_VERB_GET_CONNECT_SEL, 0);
997 /* choose an unassigned converter. The conveters in the
998 * connection list are in the same order as in the codec.
1000 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1001 per_cvt = get_cvt(spec, cvt_idx);
1002 if (!per_cvt->assigned) {
1004 "choose cvt %d for pin nid %d\n",
1006 snd_hda_codec_write_cache(codec, nid, 0,
1007 AC_VERB_SET_CONNECT_SEL,
1015 /* A wrapper of intel_not_share_asigned_cvt() */
1016 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1017 hda_nid_t pin_nid, hda_nid_t cvt_nid)
1020 struct hdmi_spec *spec = codec->spec;
1022 if (!is_haswell_plus(codec) && !is_valleyview_plus(codec))
1025 /* On Intel platform, the mapping of converter nid to
1026 * mux index of the pins are always the same.
1027 * The pin nid may be 0, this means all pins will not
1028 * share the converter.
1030 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1032 intel_not_share_assigned_cvt(codec, pin_nid, mux_idx);
1035 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1036 * in dyn_pcm_assign mode.
1038 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1039 struct hda_codec *codec,
1040 struct snd_pcm_substream *substream)
1042 struct hdmi_spec *spec = codec->spec;
1043 struct snd_pcm_runtime *runtime = substream->runtime;
1044 int cvt_idx, pcm_idx;
1045 struct hdmi_spec_per_cvt *per_cvt = NULL;
1048 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1052 err = hdmi_choose_cvt(codec, -1, &cvt_idx, NULL);
1056 per_cvt = get_cvt(spec, cvt_idx);
1057 per_cvt->assigned = 1;
1058 hinfo->nid = per_cvt->cvt_nid;
1060 intel_not_share_assigned_cvt_nid(codec, 0, per_cvt->cvt_nid);
1062 set_bit(pcm_idx, &spec->pcm_in_use);
1063 /* todo: setup spdif ctls assign */
1065 /* Initially set the converter's capabilities */
1066 hinfo->channels_min = per_cvt->channels_min;
1067 hinfo->channels_max = per_cvt->channels_max;
1068 hinfo->rates = per_cvt->rates;
1069 hinfo->formats = per_cvt->formats;
1070 hinfo->maxbps = per_cvt->maxbps;
1072 /* Store the updated parameters */
1073 runtime->hw.channels_min = hinfo->channels_min;
1074 runtime->hw.channels_max = hinfo->channels_max;
1075 runtime->hw.formats = hinfo->formats;
1076 runtime->hw.rates = hinfo->rates;
1078 snd_pcm_hw_constraint_step(substream->runtime, 0,
1079 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1086 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1087 struct hda_codec *codec,
1088 struct snd_pcm_substream *substream)
1090 struct hdmi_spec *spec = codec->spec;
1091 struct snd_pcm_runtime *runtime = substream->runtime;
1092 int pin_idx, cvt_idx, pcm_idx, mux_idx = 0;
1093 struct hdmi_spec_per_pin *per_pin;
1094 struct hdmi_eld *eld;
1095 struct hdmi_spec_per_cvt *per_cvt = NULL;
1098 /* Validate hinfo */
1099 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1103 mutex_lock(&spec->pcm_lock);
1104 pin_idx = hinfo_to_pin_index(codec, hinfo);
1105 if (!spec->dyn_pcm_assign) {
1106 if (snd_BUG_ON(pin_idx < 0)) {
1107 mutex_unlock(&spec->pcm_lock);
1111 /* no pin is assigned to the PCM
1112 * PA need pcm open successfully when probe
1115 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1116 mutex_unlock(&spec->pcm_lock);
1121 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1123 mutex_unlock(&spec->pcm_lock);
1127 per_cvt = get_cvt(spec, cvt_idx);
1128 /* Claim converter */
1129 per_cvt->assigned = 1;
1131 set_bit(pcm_idx, &spec->pcm_in_use);
1132 per_pin = get_pin(spec, pin_idx);
1133 per_pin->cvt_nid = per_cvt->cvt_nid;
1134 hinfo->nid = per_cvt->cvt_nid;
1136 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1137 AC_VERB_SET_CONNECT_SEL,
1140 /* configure unused pins to choose other converters */
1141 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1142 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1144 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1146 /* Initially set the converter's capabilities */
1147 hinfo->channels_min = per_cvt->channels_min;
1148 hinfo->channels_max = per_cvt->channels_max;
1149 hinfo->rates = per_cvt->rates;
1150 hinfo->formats = per_cvt->formats;
1151 hinfo->maxbps = per_cvt->maxbps;
1153 eld = &per_pin->sink_eld;
1154 /* Restrict capabilities by ELD if this isn't disabled */
1155 if (!static_hdmi_pcm && eld->eld_valid) {
1156 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1157 if (hinfo->channels_min > hinfo->channels_max ||
1158 !hinfo->rates || !hinfo->formats) {
1159 per_cvt->assigned = 0;
1161 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1162 mutex_unlock(&spec->pcm_lock);
1167 mutex_unlock(&spec->pcm_lock);
1168 /* Store the updated parameters */
1169 runtime->hw.channels_min = hinfo->channels_min;
1170 runtime->hw.channels_max = hinfo->channels_max;
1171 runtime->hw.formats = hinfo->formats;
1172 runtime->hw.rates = hinfo->rates;
1174 snd_pcm_hw_constraint_step(substream->runtime, 0,
1175 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1180 * HDA/HDMI auto parsing
1182 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1184 struct hdmi_spec *spec = codec->spec;
1185 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1186 hda_nid_t pin_nid = per_pin->pin_nid;
1188 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1190 "HDMI: pin %d wcaps %#x does not support connection list\n",
1191 pin_nid, get_wcaps(codec, pin_nid));
1195 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1197 HDA_MAX_CONNECTIONS);
1202 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1203 struct hdmi_spec_per_pin *per_pin)
1207 /* try the prefer PCM */
1208 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1209 return per_pin->pin_nid_idx;
1211 /* have a second try; check the "reserved area" over num_pins */
1212 for (i = spec->num_pins; i < spec->pcm_used; i++) {
1213 if (!test_bit(i, &spec->pcm_bitmap))
1217 /* the last try; check the empty slots in pins */
1218 for (i = 0; i < spec->num_pins; i++) {
1219 if (!test_bit(i, &spec->pcm_bitmap))
1225 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1226 struct hdmi_spec_per_pin *per_pin)
1230 /* pcm already be attached to the pin */
1233 idx = hdmi_find_pcm_slot(spec, per_pin);
1236 per_pin->pcm_idx = idx;
1237 per_pin->pcm = get_hdmi_pcm(spec, idx);
1238 set_bit(idx, &spec->pcm_bitmap);
1241 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1242 struct hdmi_spec_per_pin *per_pin)
1246 /* pcm already be detached from the pin */
1249 idx = per_pin->pcm_idx;
1250 per_pin->pcm_idx = -1;
1251 per_pin->pcm = NULL;
1252 if (idx >= 0 && idx < spec->pcm_used)
1253 clear_bit(idx, &spec->pcm_bitmap);
1256 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1257 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1261 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1262 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1267 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1269 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1270 struct hdmi_spec_per_pin *per_pin)
1272 struct hda_codec *codec = per_pin->codec;
1273 struct hda_pcm *pcm;
1274 struct hda_pcm_stream *hinfo;
1275 struct snd_pcm_substream *substream;
1279 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1280 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1283 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1286 /* hdmi audio only uses playback and one substream */
1287 hinfo = pcm->stream;
1288 substream = pcm->pcm->streams[0].substream;
1290 per_pin->cvt_nid = hinfo->nid;
1292 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1293 if (mux_idx < per_pin->num_mux_nids)
1294 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1295 AC_VERB_SET_CONNECT_SEL,
1297 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1299 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1300 if (substream->runtime)
1301 per_pin->channels = substream->runtime->channels;
1302 per_pin->setup = true;
1303 per_pin->mux_idx = mux_idx;
1305 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1308 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1309 struct hdmi_spec_per_pin *per_pin)
1311 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1312 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1314 per_pin->chmap_set = false;
1315 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1317 per_pin->setup = false;
1318 per_pin->channels = 0;
1321 /* update per_pin ELD from the given new ELD;
1322 * setup info frame and notification accordingly
1324 static void update_eld(struct hda_codec *codec,
1325 struct hdmi_spec_per_pin *per_pin,
1326 struct hdmi_eld *eld)
1328 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1329 struct hdmi_spec *spec = codec->spec;
1330 bool old_eld_valid = pin_eld->eld_valid;
1334 /* for monitor disconnection, save pcm_idx firstly */
1335 pcm_idx = per_pin->pcm_idx;
1336 if (spec->dyn_pcm_assign) {
1337 if (eld->eld_valid) {
1338 hdmi_attach_hda_pcm(spec, per_pin);
1339 hdmi_pcm_setup_pin(spec, per_pin);
1341 hdmi_pcm_reset_pin(spec, per_pin);
1342 hdmi_detach_hda_pcm(spec, per_pin);
1345 /* if pcm_idx == -1, it means this is in monitor connection event
1346 * we can get the correct pcm_idx now.
1349 pcm_idx = per_pin->pcm_idx;
1352 snd_hdmi_show_eld(codec, &eld->info);
1354 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1355 if (eld->eld_valid && pin_eld->eld_valid)
1356 if (pin_eld->eld_size != eld->eld_size ||
1357 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1358 eld->eld_size) != 0)
1361 pin_eld->monitor_present = eld->monitor_present;
1362 pin_eld->eld_valid = eld->eld_valid;
1363 pin_eld->eld_size = eld->eld_size;
1365 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1366 pin_eld->info = eld->info;
1369 * Re-setup pin and infoframe. This is needed e.g. when
1370 * - sink is first plugged-in
1371 * - transcoder can change during stream playback on Haswell
1372 * and this can make HW reset converter selection on a pin.
1374 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1375 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1376 intel_verify_pin_cvt_connect(codec, per_pin);
1377 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
1381 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1384 if (eld_changed && pcm_idx >= 0)
1385 snd_ctl_notify(codec->card,
1386 SNDRV_CTL_EVENT_MASK_VALUE |
1387 SNDRV_CTL_EVENT_MASK_INFO,
1388 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1391 /* update ELD and jack state via HD-audio verbs */
1392 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1395 struct hda_jack_tbl *jack;
1396 struct hda_codec *codec = per_pin->codec;
1397 struct hdmi_spec *spec = codec->spec;
1398 struct hdmi_eld *eld = &spec->temp_eld;
1399 hda_nid_t pin_nid = per_pin->pin_nid;
1401 * Always execute a GetPinSense verb here, even when called from
1402 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1403 * response's PD bit is not the real PD value, but indicates that
1404 * the real PD value changed. An older version of the HD-audio
1405 * specification worked this way. Hence, we just ignore the data in
1406 * the unsolicited response to avoid custom WARs.
1410 bool do_repoll = false;
1412 present = snd_hda_pin_sense(codec, pin_nid);
1414 mutex_lock(&per_pin->lock);
1415 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1416 if (eld->monitor_present)
1417 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1419 eld->eld_valid = false;
1422 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1423 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1425 if (eld->eld_valid) {
1426 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1427 &eld->eld_size) < 0)
1428 eld->eld_valid = false;
1430 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1432 eld->eld_valid = false;
1434 if (!eld->eld_valid && repoll)
1439 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1441 update_eld(codec, per_pin, eld);
1443 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1445 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1447 jack->block_report = !ret;
1449 mutex_unlock(&per_pin->lock);
1453 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1454 struct hdmi_spec_per_pin *per_pin)
1456 struct hdmi_spec *spec = codec->spec;
1457 struct snd_jack *jack = NULL;
1458 struct hda_jack_tbl *jack_tbl;
1460 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1461 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1462 * NULL even after snd_hda_jack_tbl_clear() is called to
1463 * free snd_jack. This may cause access invalid memory
1464 * when calling snd_jack_report
1466 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1467 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1468 else if (!spec->dyn_pcm_assign) {
1469 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1471 jack = jack_tbl->jack;
1476 /* update ELD and jack state via audio component */
1477 static void sync_eld_via_acomp(struct hda_codec *codec,
1478 struct hdmi_spec_per_pin *per_pin)
1480 struct hdmi_spec *spec = codec->spec;
1481 struct hdmi_eld *eld = &spec->temp_eld;
1482 struct snd_jack *jack = NULL;
1485 mutex_lock(&per_pin->lock);
1486 eld->monitor_present = false;
1487 size = snd_hdac_acomp_get_eld(&codec->bus->core, per_pin->pin_nid,
1488 &eld->monitor_present, eld->eld_buffer,
1491 size = min(size, ELD_MAX_SIZE);
1492 if (snd_hdmi_parse_eld(codec, &eld->info,
1493 eld->eld_buffer, size) < 0)
1498 eld->eld_valid = true;
1499 eld->eld_size = size;
1501 eld->eld_valid = false;
1505 /* pcm_idx >=0 before update_eld() means it is in monitor
1506 * disconnected event. Jack must be fetched before update_eld()
1508 jack = pin_idx_to_jack(codec, per_pin);
1509 update_eld(codec, per_pin, eld);
1511 jack = pin_idx_to_jack(codec, per_pin);
1514 snd_jack_report(jack,
1515 eld->monitor_present ? SND_JACK_AVOUT : 0);
1517 mutex_unlock(&per_pin->lock);
1520 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1522 struct hda_codec *codec = per_pin->codec;
1523 struct hdmi_spec *spec = codec->spec;
1526 /* no temporary power up/down needed for component notifier */
1527 if (!codec_has_acomp(codec))
1528 snd_hda_power_up_pm(codec);
1530 mutex_lock(&spec->pcm_lock);
1531 if (codec_has_acomp(codec)) {
1532 sync_eld_via_acomp(codec, per_pin);
1533 ret = false; /* don't call snd_hda_jack_report_sync() */
1535 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1537 mutex_unlock(&spec->pcm_lock);
1539 if (!codec_has_acomp(codec))
1540 snd_hda_power_down_pm(codec);
1545 static void hdmi_repoll_eld(struct work_struct *work)
1547 struct hdmi_spec_per_pin *per_pin =
1548 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1550 if (per_pin->repoll_count++ > 6)
1551 per_pin->repoll_count = 0;
1553 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1554 snd_hda_jack_report_sync(per_pin->codec);
1557 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1560 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1562 struct hdmi_spec *spec = codec->spec;
1563 unsigned int caps, config;
1565 struct hdmi_spec_per_pin *per_pin;
1568 caps = snd_hda_query_pin_caps(codec, pin_nid);
1569 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1572 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1573 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1576 if (is_haswell_plus(codec))
1577 intel_haswell_fixup_connect_list(codec, pin_nid);
1579 pin_idx = spec->num_pins;
1580 per_pin = snd_array_new(&spec->pins);
1584 per_pin->pin_nid = pin_nid;
1585 per_pin->non_pcm = false;
1586 if (spec->dyn_pcm_assign)
1587 per_pin->pcm_idx = -1;
1589 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1590 per_pin->pcm_idx = pin_idx;
1592 per_pin->pin_nid_idx = pin_idx;
1594 err = hdmi_read_pin_conn(codec, pin_idx);
1603 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1605 struct hdmi_spec *spec = codec->spec;
1606 struct hdmi_spec_per_cvt *per_cvt;
1610 chans = get_wcaps(codec, cvt_nid);
1611 chans = get_wcaps_channels(chans);
1613 per_cvt = snd_array_new(&spec->cvts);
1617 per_cvt->cvt_nid = cvt_nid;
1618 per_cvt->channels_min = 2;
1620 per_cvt->channels_max = chans;
1621 if (chans > spec->chmap.channels_max)
1622 spec->chmap.channels_max = chans;
1625 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1632 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1633 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1639 static int hdmi_parse_codec(struct hda_codec *codec)
1644 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1645 if (!nid || nodes < 0) {
1646 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1650 for (i = 0; i < nodes; i++, nid++) {
1654 caps = get_wcaps(codec, nid);
1655 type = get_wcaps_type(caps);
1657 if (!(caps & AC_WCAP_DIGITAL))
1661 case AC_WID_AUD_OUT:
1662 hdmi_add_cvt(codec, nid);
1665 hdmi_add_pin(codec, nid);
1675 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1677 struct hda_spdif_out *spdif;
1680 mutex_lock(&codec->spdif_mutex);
1681 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1682 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1683 mutex_unlock(&codec->spdif_mutex);
1691 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1692 struct hda_codec *codec,
1693 unsigned int stream_tag,
1694 unsigned int format,
1695 struct snd_pcm_substream *substream)
1697 hda_nid_t cvt_nid = hinfo->nid;
1698 struct hdmi_spec *spec = codec->spec;
1700 struct hdmi_spec_per_pin *per_pin;
1702 struct snd_pcm_runtime *runtime = substream->runtime;
1707 mutex_lock(&spec->pcm_lock);
1708 pin_idx = hinfo_to_pin_index(codec, hinfo);
1709 if (spec->dyn_pcm_assign && pin_idx < 0) {
1710 /* when dyn_pcm_assign and pcm is not bound to a pin
1711 * skip pin setup and return 0 to make audio playback
1714 intel_not_share_assigned_cvt_nid(codec, 0, cvt_nid);
1715 snd_hda_codec_setup_stream(codec, cvt_nid,
1716 stream_tag, 0, format);
1717 mutex_unlock(&spec->pcm_lock);
1721 if (snd_BUG_ON(pin_idx < 0)) {
1722 mutex_unlock(&spec->pcm_lock);
1725 per_pin = get_pin(spec, pin_idx);
1726 pin_nid = per_pin->pin_nid;
1727 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1728 /* Verify pin:cvt selections to avoid silent audio after S3.
1729 * After S3, the audio driver restores pin:cvt selections
1730 * but this can happen before gfx is ready and such selection
1731 * is overlooked by HW. Thus multiple pins can share a same
1732 * default convertor and mute control will affect each other,
1733 * which can cause a resumed audio playback become silent
1736 intel_verify_pin_cvt_connect(codec, per_pin);
1737 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1740 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1741 /* Todo: add DP1.2 MST audio support later */
1742 if (codec_has_acomp(codec))
1743 snd_hdac_sync_audio_rate(&codec->bus->core, pin_nid, runtime->rate);
1745 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1746 mutex_lock(&per_pin->lock);
1747 per_pin->channels = substream->runtime->channels;
1748 per_pin->setup = true;
1750 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1751 mutex_unlock(&per_pin->lock);
1752 if (spec->dyn_pin_out) {
1753 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1754 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1755 snd_hda_codec_write(codec, pin_nid, 0,
1756 AC_VERB_SET_PIN_WIDGET_CONTROL,
1760 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1761 stream_tag, format);
1762 mutex_unlock(&spec->pcm_lock);
1766 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1767 struct hda_codec *codec,
1768 struct snd_pcm_substream *substream)
1770 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1774 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1775 struct hda_codec *codec,
1776 struct snd_pcm_substream *substream)
1778 struct hdmi_spec *spec = codec->spec;
1779 int cvt_idx, pin_idx, pcm_idx;
1780 struct hdmi_spec_per_cvt *per_cvt;
1781 struct hdmi_spec_per_pin *per_pin;
1785 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1786 if (snd_BUG_ON(pcm_idx < 0))
1788 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1789 if (snd_BUG_ON(cvt_idx < 0))
1791 per_cvt = get_cvt(spec, cvt_idx);
1793 snd_BUG_ON(!per_cvt->assigned);
1794 per_cvt->assigned = 0;
1797 mutex_lock(&spec->pcm_lock);
1798 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1799 clear_bit(pcm_idx, &spec->pcm_in_use);
1800 pin_idx = hinfo_to_pin_index(codec, hinfo);
1801 if (spec->dyn_pcm_assign && pin_idx < 0) {
1802 mutex_unlock(&spec->pcm_lock);
1806 if (snd_BUG_ON(pin_idx < 0)) {
1807 mutex_unlock(&spec->pcm_lock);
1810 per_pin = get_pin(spec, pin_idx);
1812 if (spec->dyn_pin_out) {
1813 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1814 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1815 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1816 AC_VERB_SET_PIN_WIDGET_CONTROL,
1820 mutex_lock(&per_pin->lock);
1821 per_pin->chmap_set = false;
1822 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1824 per_pin->setup = false;
1825 per_pin->channels = 0;
1826 mutex_unlock(&per_pin->lock);
1827 mutex_unlock(&spec->pcm_lock);
1833 static const struct hda_pcm_ops generic_ops = {
1834 .open = hdmi_pcm_open,
1835 .close = hdmi_pcm_close,
1836 .prepare = generic_hdmi_playback_pcm_prepare,
1837 .cleanup = generic_hdmi_playback_pcm_cleanup,
1840 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
1841 unsigned char *chmap)
1843 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1844 struct hdmi_spec *spec = codec->spec;
1845 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1847 /* chmap is already set to 0 in caller */
1851 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
1854 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
1855 unsigned char *chmap, int prepared)
1857 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1858 struct hdmi_spec *spec = codec->spec;
1859 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1863 mutex_lock(&per_pin->lock);
1864 per_pin->chmap_set = true;
1865 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
1867 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1868 mutex_unlock(&per_pin->lock);
1871 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
1873 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1874 struct hdmi_spec *spec = codec->spec;
1875 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1877 return per_pin ? true:false;
1880 static int generic_hdmi_build_pcms(struct hda_codec *codec)
1882 struct hdmi_spec *spec = codec->spec;
1885 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1886 struct hda_pcm *info;
1887 struct hda_pcm_stream *pstr;
1889 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
1893 spec->pcm_rec[pin_idx].pcm = info;
1895 info->pcm_type = HDA_PCM_TYPE_HDMI;
1896 info->own_chmap = true;
1898 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1899 pstr->substreams = 1;
1900 pstr->ops = generic_ops;
1901 /* other pstr fields are set in open */
1907 static void free_hdmi_jack_priv(struct snd_jack *jack)
1909 struct hdmi_pcm *pcm = jack->private_data;
1914 static int add_hdmi_jack_kctl(struct hda_codec *codec,
1915 struct hdmi_spec *spec,
1919 struct snd_jack *jack;
1922 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
1927 spec->pcm_rec[pcm_idx].jack = jack;
1928 jack->private_data = &spec->pcm_rec[pcm_idx];
1929 jack->private_free = free_hdmi_jack_priv;
1933 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
1935 char hdmi_str[32] = "HDMI/DP";
1936 struct hdmi_spec *spec = codec->spec;
1937 struct hdmi_spec_per_pin *per_pin;
1938 struct hda_jack_tbl *jack;
1939 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
1944 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
1946 if (spec->dyn_pcm_assign)
1947 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
1949 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
1950 /* if !dyn_pcm_assign, it must be non-MST mode.
1951 * This means pcms and pins are statically mapped.
1952 * And pcm_idx is pin_idx.
1954 per_pin = get_pin(spec, pcm_idx);
1955 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
1957 strncat(hdmi_str, " Phantom",
1958 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
1959 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
1963 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1966 /* assign jack->jack to pcm_rec[].jack to
1967 * align with dyn_pcm_assign mode
1969 spec->pcm_rec[pcm_idx].jack = jack->jack;
1973 static int generic_hdmi_build_controls(struct hda_codec *codec)
1975 struct hdmi_spec *spec = codec->spec;
1977 int pin_idx, pcm_idx;
1980 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
1981 err = generic_hdmi_build_jack(codec, pcm_idx);
1985 /* create the spdif for each pcm
1986 * pin will be bound when monitor is connected
1988 if (spec->dyn_pcm_assign)
1989 err = snd_hda_create_dig_out_ctls(codec,
1990 0, spec->cvt_nids[0],
1993 struct hdmi_spec_per_pin *per_pin =
1994 get_pin(spec, pcm_idx);
1995 err = snd_hda_create_dig_out_ctls(codec,
1997 per_pin->mux_nids[0],
2002 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2004 /* add control for ELD Bytes */
2005 err = hdmi_create_eld_ctl(codec, pcm_idx,
2006 get_pcm_rec(spec, pcm_idx)->device);
2011 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2012 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2014 hdmi_present_sense(per_pin, 0);
2017 /* add channel maps */
2018 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2019 struct hda_pcm *pcm;
2021 pcm = get_pcm_rec(spec, pcm_idx);
2022 if (!pcm || !pcm->pcm)
2024 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2032 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2034 struct hdmi_spec *spec = codec->spec;
2037 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2038 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2040 per_pin->codec = codec;
2041 mutex_init(&per_pin->lock);
2042 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2043 eld_proc_new(per_pin, pin_idx);
2048 static int generic_hdmi_init(struct hda_codec *codec)
2050 struct hdmi_spec *spec = codec->spec;
2053 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2054 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2055 hda_nid_t pin_nid = per_pin->pin_nid;
2057 hdmi_init_pin(codec, pin_nid);
2058 if (!codec_has_acomp(codec))
2059 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2060 codec->jackpoll_interval > 0 ?
2061 jack_callback : NULL);
2066 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2068 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2069 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2072 static void hdmi_array_free(struct hdmi_spec *spec)
2074 snd_array_free(&spec->pins);
2075 snd_array_free(&spec->cvts);
2078 static void generic_hdmi_free(struct hda_codec *codec)
2080 struct hdmi_spec *spec = codec->spec;
2081 int pin_idx, pcm_idx;
2083 if (codec_has_acomp(codec))
2084 snd_hdac_i915_register_notifier(NULL);
2086 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2087 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2088 cancel_delayed_work_sync(&per_pin->work);
2089 eld_proc_free(per_pin);
2092 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2093 if (spec->pcm_rec[pcm_idx].jack == NULL)
2095 if (spec->dyn_pcm_assign)
2096 snd_device_free(codec->card,
2097 spec->pcm_rec[pcm_idx].jack);
2099 spec->pcm_rec[pcm_idx].jack = NULL;
2102 if (spec->i915_bound)
2103 snd_hdac_i915_exit(&codec->bus->core);
2104 hdmi_array_free(spec);
2109 static int generic_hdmi_resume(struct hda_codec *codec)
2111 struct hdmi_spec *spec = codec->spec;
2114 codec->patch_ops.init(codec);
2115 regcache_sync(codec->core.regmap);
2117 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2118 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2119 hdmi_present_sense(per_pin, 1);
2125 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2126 .init = generic_hdmi_init,
2127 .free = generic_hdmi_free,
2128 .build_pcms = generic_hdmi_build_pcms,
2129 .build_controls = generic_hdmi_build_controls,
2130 .unsol_event = hdmi_unsol_event,
2132 .resume = generic_hdmi_resume,
2136 static const struct hdmi_ops generic_standard_hdmi_ops = {
2137 .pin_get_eld = snd_hdmi_get_eld,
2138 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2139 .pin_hbr_setup = hdmi_pin_hbr_setup,
2140 .setup_stream = hdmi_setup_stream,
2143 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2146 struct hdmi_spec *spec = codec->spec;
2150 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2151 if (nconns == spec->num_cvts &&
2152 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2155 /* override pins connection list */
2156 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2157 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2160 #define INTEL_VENDOR_NID 0x08
2161 #define INTEL_GET_VENDOR_VERB 0xf81
2162 #define INTEL_SET_VENDOR_VERB 0x781
2163 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2164 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2166 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2169 unsigned int vendor_param;
2171 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2172 INTEL_GET_VENDOR_VERB, 0);
2173 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2176 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2177 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2178 INTEL_SET_VENDOR_VERB, vendor_param);
2179 if (vendor_param == -1)
2183 snd_hda_codec_update_widgets(codec);
2186 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2188 unsigned int vendor_param;
2190 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2191 INTEL_GET_VENDOR_VERB, 0);
2192 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2195 /* enable DP1.2 mode */
2196 vendor_param |= INTEL_EN_DP12;
2197 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2198 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2199 INTEL_SET_VENDOR_VERB, vendor_param);
2202 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2203 * Otherwise you may get severe h/w communication errors.
2205 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2206 unsigned int power_state)
2208 if (power_state == AC_PWRST_D0) {
2209 intel_haswell_enable_all_pins(codec, false);
2210 intel_haswell_fixup_enable_dp12(codec);
2213 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2214 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2217 static void intel_pin_eld_notify(void *audio_ptr, int port)
2219 struct hda_codec *codec = audio_ptr;
2220 int pin_nid = port + 0x04;
2222 /* we assume only from port-B to port-D */
2223 if (port < 1 || port > 3)
2226 /* skip notification during system suspend (but not in runtime PM);
2227 * the state will be updated at resume
2229 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2231 /* ditto during suspend/resume process itself */
2232 if (atomic_read(&(codec)->core.in_pm))
2235 snd_hdac_i915_set_bclk(&codec->bus->core);
2236 check_presence_and_report(codec, pin_nid);
2239 static int patch_generic_hdmi(struct hda_codec *codec)
2241 struct hdmi_spec *spec;
2243 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2247 spec->ops = generic_standard_hdmi_ops;
2248 mutex_init(&spec->pcm_lock);
2249 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2251 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2252 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2253 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2256 hdmi_array_init(spec, 4);
2258 #ifdef CONFIG_SND_HDA_I915
2259 /* Try to bind with i915 for Intel HSW+ codecs (if not done yet) */
2260 if ((codec->core.vendor_id >> 16) == 0x8086 &&
2261 is_haswell_plus(codec)) {
2263 /* on-demand binding leads to an unbalanced refcount when
2264 * both i915 and hda drivers are probed concurrently;
2265 * disabled temporarily for now
2267 if (!codec->bus->core.audio_component)
2268 if (!snd_hdac_i915_init(&codec->bus->core))
2269 spec->i915_bound = true;
2271 /* use i915 audio component notifier for hotplug */
2272 if (codec->bus->core.audio_component)
2273 spec->use_acomp_notifier = true;
2277 if (is_haswell_plus(codec)) {
2278 intel_haswell_enable_all_pins(codec, true);
2279 intel_haswell_fixup_enable_dp12(codec);
2282 /* For Valleyview/Cherryview, only the display codec is in the display
2283 * power well and can use link_power ops to request/release the power.
2284 * For Haswell/Broadwell, the controller is also in the power well and
2285 * can cover the codec power request, and so need not set this flag.
2286 * For previous platforms, there is no such power well feature.
2288 if (is_valleyview_plus(codec) || is_skylake(codec) ||
2290 codec->core.link_power_control = 1;
2292 if (hdmi_parse_codec(codec) < 0) {
2293 if (spec->i915_bound)
2294 snd_hdac_i915_exit(&codec->bus->core);
2299 codec->patch_ops = generic_hdmi_patch_ops;
2300 if (is_haswell_plus(codec)) {
2301 codec->patch_ops.set_power_state = haswell_set_power_state;
2302 codec->dp_mst = true;
2305 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2306 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2307 codec->auto_runtime_pm = 1;
2309 generic_hdmi_init_per_pins(codec);
2312 if (codec_has_acomp(codec)) {
2313 codec->depop_delay = 0;
2314 spec->i915_audio_ops.audio_ptr = codec;
2315 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2316 * will call pin_eld_notify with using audio_ptr pointer
2317 * We need make sure audio_ptr is really setup
2320 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2321 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2324 WARN_ON(spec->dyn_pcm_assign && !codec_has_acomp(codec));
2329 * Shared non-generic implementations
2332 static int simple_playback_build_pcms(struct hda_codec *codec)
2334 struct hdmi_spec *spec = codec->spec;
2335 struct hda_pcm *info;
2337 struct hda_pcm_stream *pstr;
2338 struct hdmi_spec_per_cvt *per_cvt;
2340 per_cvt = get_cvt(spec, 0);
2341 chans = get_wcaps(codec, per_cvt->cvt_nid);
2342 chans = get_wcaps_channels(chans);
2344 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2347 spec->pcm_rec[0].pcm = info;
2348 info->pcm_type = HDA_PCM_TYPE_HDMI;
2349 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2350 *pstr = spec->pcm_playback;
2351 pstr->nid = per_cvt->cvt_nid;
2352 if (pstr->channels_max <= 2 && chans && chans <= 16)
2353 pstr->channels_max = chans;
2358 /* unsolicited event for jack sensing */
2359 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2362 snd_hda_jack_set_dirty_all(codec);
2363 snd_hda_jack_report_sync(codec);
2366 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2367 * as long as spec->pins[] is set correctly
2369 #define simple_hdmi_build_jack generic_hdmi_build_jack
2371 static int simple_playback_build_controls(struct hda_codec *codec)
2373 struct hdmi_spec *spec = codec->spec;
2374 struct hdmi_spec_per_cvt *per_cvt;
2377 per_cvt = get_cvt(spec, 0);
2378 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2383 return simple_hdmi_build_jack(codec, 0);
2386 static int simple_playback_init(struct hda_codec *codec)
2388 struct hdmi_spec *spec = codec->spec;
2389 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2390 hda_nid_t pin = per_pin->pin_nid;
2392 snd_hda_codec_write(codec, pin, 0,
2393 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2394 /* some codecs require to unmute the pin */
2395 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2396 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2398 snd_hda_jack_detect_enable(codec, pin);
2402 static void simple_playback_free(struct hda_codec *codec)
2404 struct hdmi_spec *spec = codec->spec;
2406 hdmi_array_free(spec);
2411 * Nvidia specific implementations
2414 #define Nv_VERB_SET_Channel_Allocation 0xF79
2415 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2416 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2417 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2419 #define nvhdmi_master_con_nid_7x 0x04
2420 #define nvhdmi_master_pin_nid_7x 0x05
2422 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2423 /*front, rear, clfe, rear_surr */
2427 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2428 /* set audio protect on */
2429 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2430 /* enable digital output on pin widget */
2431 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2435 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2436 /* set audio protect on */
2437 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2438 /* enable digital output on pin widget */
2439 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2440 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2441 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2442 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2443 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2447 #ifdef LIMITED_RATE_FMT_SUPPORT
2448 /* support only the safe format and rate */
2449 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2450 #define SUPPORTED_MAXBPS 16
2451 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2453 /* support all rates and formats */
2454 #define SUPPORTED_RATES \
2455 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2456 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2457 SNDRV_PCM_RATE_192000)
2458 #define SUPPORTED_MAXBPS 24
2459 #define SUPPORTED_FORMATS \
2460 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2463 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2465 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2469 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2471 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2475 static unsigned int channels_2_6_8[] = {
2479 static unsigned int channels_2_8[] = {
2483 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2484 .count = ARRAY_SIZE(channels_2_6_8),
2485 .list = channels_2_6_8,
2489 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2490 .count = ARRAY_SIZE(channels_2_8),
2491 .list = channels_2_8,
2495 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2496 struct hda_codec *codec,
2497 struct snd_pcm_substream *substream)
2499 struct hdmi_spec *spec = codec->spec;
2500 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2502 switch (codec->preset->vendor_id) {
2507 hw_constraints_channels = &hw_constraints_2_8_channels;
2510 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2516 if (hw_constraints_channels != NULL) {
2517 snd_pcm_hw_constraint_list(substream->runtime, 0,
2518 SNDRV_PCM_HW_PARAM_CHANNELS,
2519 hw_constraints_channels);
2521 snd_pcm_hw_constraint_step(substream->runtime, 0,
2522 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2525 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2528 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2529 struct hda_codec *codec,
2530 struct snd_pcm_substream *substream)
2532 struct hdmi_spec *spec = codec->spec;
2533 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2536 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2537 struct hda_codec *codec,
2538 unsigned int stream_tag,
2539 unsigned int format,
2540 struct snd_pcm_substream *substream)
2542 struct hdmi_spec *spec = codec->spec;
2543 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2544 stream_tag, format, substream);
2547 static const struct hda_pcm_stream simple_pcm_playback = {
2552 .open = simple_playback_pcm_open,
2553 .close = simple_playback_pcm_close,
2554 .prepare = simple_playback_pcm_prepare
2558 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2559 .build_controls = simple_playback_build_controls,
2560 .build_pcms = simple_playback_build_pcms,
2561 .init = simple_playback_init,
2562 .free = simple_playback_free,
2563 .unsol_event = simple_hdmi_unsol_event,
2566 static int patch_simple_hdmi(struct hda_codec *codec,
2567 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2569 struct hdmi_spec *spec;
2570 struct hdmi_spec_per_cvt *per_cvt;
2571 struct hdmi_spec_per_pin *per_pin;
2573 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2578 hdmi_array_init(spec, 1);
2580 spec->multiout.num_dacs = 0; /* no analog */
2581 spec->multiout.max_channels = 2;
2582 spec->multiout.dig_out_nid = cvt_nid;
2585 per_pin = snd_array_new(&spec->pins);
2586 per_cvt = snd_array_new(&spec->cvts);
2587 if (!per_pin || !per_cvt) {
2588 simple_playback_free(codec);
2591 per_cvt->cvt_nid = cvt_nid;
2592 per_pin->pin_nid = pin_nid;
2593 spec->pcm_playback = simple_pcm_playback;
2595 codec->patch_ops = simple_hdmi_patch_ops;
2600 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2603 unsigned int chanmask;
2604 int chan = channels ? (channels - 1) : 1;
2623 /* Set the audio infoframe channel allocation and checksum fields. The
2624 * channel count is computed implicitly by the hardware. */
2625 snd_hda_codec_write(codec, 0x1, 0,
2626 Nv_VERB_SET_Channel_Allocation, chanmask);
2628 snd_hda_codec_write(codec, 0x1, 0,
2629 Nv_VERB_SET_Info_Frame_Checksum,
2630 (0x71 - chan - chanmask));
2633 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2634 struct hda_codec *codec,
2635 struct snd_pcm_substream *substream)
2637 struct hdmi_spec *spec = codec->spec;
2640 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2641 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2642 for (i = 0; i < 4; i++) {
2643 /* set the stream id */
2644 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2645 AC_VERB_SET_CHANNEL_STREAMID, 0);
2646 /* set the stream format */
2647 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2648 AC_VERB_SET_STREAM_FORMAT, 0);
2651 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2652 * streams are disabled. */
2653 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2655 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2658 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2659 struct hda_codec *codec,
2660 unsigned int stream_tag,
2661 unsigned int format,
2662 struct snd_pcm_substream *substream)
2665 unsigned int dataDCC2, channel_id;
2667 struct hdmi_spec *spec = codec->spec;
2668 struct hda_spdif_out *spdif;
2669 struct hdmi_spec_per_cvt *per_cvt;
2671 mutex_lock(&codec->spdif_mutex);
2672 per_cvt = get_cvt(spec, 0);
2673 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2675 chs = substream->runtime->channels;
2679 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2680 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2681 snd_hda_codec_write(codec,
2682 nvhdmi_master_con_nid_7x,
2684 AC_VERB_SET_DIGI_CONVERT_1,
2685 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2687 /* set the stream id */
2688 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2689 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2691 /* set the stream format */
2692 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2693 AC_VERB_SET_STREAM_FORMAT, format);
2695 /* turn on again (if needed) */
2696 /* enable and set the channel status audio/data flag */
2697 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2698 snd_hda_codec_write(codec,
2699 nvhdmi_master_con_nid_7x,
2701 AC_VERB_SET_DIGI_CONVERT_1,
2702 spdif->ctls & 0xff);
2703 snd_hda_codec_write(codec,
2704 nvhdmi_master_con_nid_7x,
2706 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2709 for (i = 0; i < 4; i++) {
2715 /* turn off SPDIF once;
2716 *otherwise the IEC958 bits won't be updated
2718 if (codec->spdif_status_reset &&
2719 (spdif->ctls & AC_DIG1_ENABLE))
2720 snd_hda_codec_write(codec,
2721 nvhdmi_con_nids_7x[i],
2723 AC_VERB_SET_DIGI_CONVERT_1,
2724 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2725 /* set the stream id */
2726 snd_hda_codec_write(codec,
2727 nvhdmi_con_nids_7x[i],
2729 AC_VERB_SET_CHANNEL_STREAMID,
2730 (stream_tag << 4) | channel_id);
2731 /* set the stream format */
2732 snd_hda_codec_write(codec,
2733 nvhdmi_con_nids_7x[i],
2735 AC_VERB_SET_STREAM_FORMAT,
2737 /* turn on again (if needed) */
2738 /* enable and set the channel status audio/data flag */
2739 if (codec->spdif_status_reset &&
2740 (spdif->ctls & AC_DIG1_ENABLE)) {
2741 snd_hda_codec_write(codec,
2742 nvhdmi_con_nids_7x[i],
2744 AC_VERB_SET_DIGI_CONVERT_1,
2745 spdif->ctls & 0xff);
2746 snd_hda_codec_write(codec,
2747 nvhdmi_con_nids_7x[i],
2749 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2753 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2755 mutex_unlock(&codec->spdif_mutex);
2759 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2763 .nid = nvhdmi_master_con_nid_7x,
2764 .rates = SUPPORTED_RATES,
2765 .maxbps = SUPPORTED_MAXBPS,
2766 .formats = SUPPORTED_FORMATS,
2768 .open = simple_playback_pcm_open,
2769 .close = nvhdmi_8ch_7x_pcm_close,
2770 .prepare = nvhdmi_8ch_7x_pcm_prepare
2774 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2776 struct hdmi_spec *spec;
2777 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2778 nvhdmi_master_pin_nid_7x);
2782 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2783 /* override the PCM rates, etc, as the codec doesn't give full list */
2785 spec->pcm_playback.rates = SUPPORTED_RATES;
2786 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2787 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2791 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2793 struct hdmi_spec *spec = codec->spec;
2794 int err = simple_playback_build_pcms(codec);
2796 struct hda_pcm *info = get_pcm_rec(spec, 0);
2797 info->own_chmap = true;
2802 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2804 struct hdmi_spec *spec = codec->spec;
2805 struct hda_pcm *info;
2806 struct snd_pcm_chmap *chmap;
2809 err = simple_playback_build_controls(codec);
2813 /* add channel maps */
2814 info = get_pcm_rec(spec, 0);
2815 err = snd_pcm_add_chmap_ctls(info->pcm,
2816 SNDRV_PCM_STREAM_PLAYBACK,
2817 snd_pcm_alt_chmaps, 8, 0, &chmap);
2820 switch (codec->preset->vendor_id) {
2825 chmap->channel_mask = (1U << 2) | (1U << 8);
2828 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2833 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2835 struct hdmi_spec *spec;
2836 int err = patch_nvhdmi_2ch(codec);
2840 spec->multiout.max_channels = 8;
2841 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2842 codec->patch_ops.init = nvhdmi_7x_init_8ch;
2843 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2844 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2846 /* Initialize the audio infoframe channel mask and checksum to something
2848 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2854 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2858 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
2859 struct hdac_cea_channel_speaker_allocation *cap, int channels)
2861 if (cap->ca_index == 0x00 && channels == 2)
2862 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2864 /* If the speaker allocation matches the channel count, it is OK. */
2865 if (cap->channels != channels)
2868 /* all channels are remappable freely */
2869 return SNDRV_CTL_TLVT_CHMAP_VAR;
2872 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
2873 int ca, int chs, unsigned char *map)
2875 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2881 static int patch_nvhdmi(struct hda_codec *codec)
2883 struct hdmi_spec *spec;
2886 err = patch_generic_hdmi(codec);
2891 spec->dyn_pin_out = true;
2893 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
2894 nvhdmi_chmap_cea_alloc_validate_get_type;
2895 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
2901 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2902 * accessed using vendor-defined verbs. These registers can be used for
2903 * interoperability between the HDA and HDMI drivers.
2906 /* Audio Function Group node */
2907 #define NVIDIA_AFG_NID 0x01
2910 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
2911 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
2912 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
2913 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
2914 * additional bit (at position 30) to signal the validity of the format.
2916 * | 31 | 30 | 29 16 | 15 0 |
2917 * +---------+-------+--------+--------+
2918 * | TRIGGER | VALID | UNUSED | FORMAT |
2919 * +-----------------------------------|
2921 * Note that for the trigger bit to take effect it needs to change value
2922 * (i.e. it needs to be toggled).
2924 #define NVIDIA_GET_SCRATCH0 0xfa6
2925 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
2926 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
2927 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
2928 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
2929 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
2930 #define NVIDIA_SCRATCH_VALID (1 << 6)
2932 #define NVIDIA_GET_SCRATCH1 0xfab
2933 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
2934 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
2935 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
2936 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
2939 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
2940 * the format is invalidated so that the HDMI codec can be disabled.
2942 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
2946 /* bits [31:30] contain the trigger and valid bits */
2947 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
2948 NVIDIA_GET_SCRATCH0, 0);
2949 value = (value >> 24) & 0xff;
2951 /* bits [15:0] are used to store the HDA format */
2952 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2953 NVIDIA_SET_SCRATCH0_BYTE0,
2954 (format >> 0) & 0xff);
2955 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2956 NVIDIA_SET_SCRATCH0_BYTE1,
2957 (format >> 8) & 0xff);
2959 /* bits [16:24] are unused */
2960 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2961 NVIDIA_SET_SCRATCH0_BYTE2, 0);
2964 * Bit 30 signals that the data is valid and hence that HDMI audio can
2968 value &= ~NVIDIA_SCRATCH_VALID;
2970 value |= NVIDIA_SCRATCH_VALID;
2973 * Whenever the trigger bit is toggled, an interrupt is raised in the
2974 * HDMI codec. The HDMI driver will use that as trigger to update its
2977 value ^= NVIDIA_SCRATCH_TRIGGER;
2979 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2980 NVIDIA_SET_SCRATCH0_BYTE3, value);
2983 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
2984 struct hda_codec *codec,
2985 unsigned int stream_tag,
2986 unsigned int format,
2987 struct snd_pcm_substream *substream)
2991 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
2996 /* notify the HDMI codec of the format change */
2997 tegra_hdmi_set_format(codec, format);
3002 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3003 struct hda_codec *codec,
3004 struct snd_pcm_substream *substream)
3006 /* invalidate the format in the HDMI codec */
3007 tegra_hdmi_set_format(codec, 0);
3009 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3012 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3014 struct hdmi_spec *spec = codec->spec;
3017 for (i = 0; i < spec->num_pins; i++) {
3018 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3020 if (pcm->pcm_type == type)
3027 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3029 struct hda_pcm_stream *stream;
3030 struct hda_pcm *pcm;
3033 err = generic_hdmi_build_pcms(codec);
3037 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3042 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3043 * codec about format changes.
3045 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3046 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3047 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3052 static int patch_tegra_hdmi(struct hda_codec *codec)
3056 err = patch_generic_hdmi(codec);
3060 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3066 * ATI/AMD-specific implementations
3069 #define is_amdhdmi_rev3_or_later(codec) \
3070 ((codec)->core.vendor_id == 0x1002aa01 && \
3071 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3072 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3074 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3075 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3076 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3077 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3078 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3079 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3080 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3081 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3082 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3083 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3084 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3085 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3086 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3087 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3088 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3089 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3090 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3091 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3092 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3093 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3094 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3095 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3096 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3097 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3098 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3100 /* AMD specific HDA cvt verbs */
3101 #define ATI_VERB_SET_RAMP_RATE 0x770
3102 #define ATI_VERB_GET_RAMP_RATE 0xf70
3104 #define ATI_OUT_ENABLE 0x1
3106 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3107 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3109 #define ATI_HBR_CAPABLE 0x01
3110 #define ATI_HBR_ENABLE 0x10
3112 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3113 unsigned char *buf, int *eld_size)
3115 /* call hda_eld.c ATI/AMD-specific function */
3116 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3117 is_amdhdmi_rev3_or_later(codec));
3120 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3121 int active_channels, int conn_type)
3123 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3126 static int atihdmi_paired_swap_fc_lfe(int pos)
3129 * ATI/AMD have automatic FC/LFE swap built-in
3130 * when in pairwise mapping mode.
3134 /* see channel_allocations[].speakers[] */
3143 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3144 int ca, int chs, unsigned char *map)
3146 struct hdac_cea_channel_speaker_allocation *cap;
3149 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3151 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3152 for (i = 0; i < chs; ++i) {
3153 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3155 bool companion_ok = false;
3160 for (j = 0 + i % 2; j < 8; j += 2) {
3161 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3162 if (cap->speakers[chan_idx] == mask) {
3163 /* channel is in a supported position */
3166 if (i % 2 == 0 && i + 1 < chs) {
3167 /* even channel, check the odd companion */
3168 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3169 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3170 int comp_mask_act = cap->speakers[comp_chan_idx];
3172 if (comp_mask_req == comp_mask_act)
3173 companion_ok = true;
3185 i++; /* companion channel already checked */
3191 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3192 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3194 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3196 int ati_channel_setup = 0;
3201 if (!has_amd_full_remap_support(codec)) {
3202 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3204 /* In case this is an odd slot but without stream channel, do not
3205 * disable the slot since the corresponding even slot could have a
3206 * channel. In case neither have a channel, the slot pair will be
3207 * disabled when this function is called for the even slot. */
3208 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3211 hdmi_slot -= hdmi_slot % 2;
3213 if (stream_channel != 0xf)
3214 stream_channel -= stream_channel % 2;
3217 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3219 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3221 if (stream_channel != 0xf)
3222 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3224 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3227 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3228 hda_nid_t pin_nid, int asp_slot)
3230 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3231 bool was_odd = false;
3232 int ati_asp_slot = asp_slot;
3234 int ati_channel_setup;
3239 if (!has_amd_full_remap_support(codec)) {
3240 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3241 if (ati_asp_slot % 2 != 0) {
3247 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3249 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3251 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3254 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3257 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3258 struct hdac_chmap *chmap,
3259 struct hdac_cea_channel_speaker_allocation *cap,
3265 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3266 * we need to take that into account (a single channel may take 2
3267 * channel slots if we need to carry a silent channel next to it).
3268 * On Rev3+ AMD codecs this function is not used.
3272 /* We only produce even-numbered channel count TLVs */
3273 if ((channels % 2) != 0)
3276 for (c = 0; c < 7; c += 2) {
3277 if (cap->speakers[c] || cap->speakers[c+1])
3281 if (chanpairs * 2 != channels)
3284 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3287 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3288 struct hdac_cea_channel_speaker_allocation *cap,
3289 unsigned int *chmap, int channels)
3291 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3295 for (c = 7; c >= 0; c--) {
3296 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3297 int spk = cap->speakers[chan];
3299 /* add N/A channel if the companion channel is occupied */
3300 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3301 chmap[count++] = SNDRV_CHMAP_NA;
3306 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3309 WARN_ON(count != channels);
3312 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3315 int hbr_ctl, hbr_ctl_new;
3317 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3318 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3320 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3322 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3325 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3327 hbr_ctl == hbr_ctl_new ? "" : "new-",
3330 if (hbr_ctl != hbr_ctl_new)
3331 snd_hda_codec_write(codec, pin_nid, 0,
3332 ATI_VERB_SET_HBR_CONTROL,
3341 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3342 hda_nid_t pin_nid, u32 stream_tag, int format)
3345 if (is_amdhdmi_rev3_or_later(codec)) {
3346 int ramp_rate = 180; /* default as per AMD spec */
3347 /* disable ramp-up/down for non-pcm as per AMD spec */
3348 if (format & AC_FMT_TYPE_NON_PCM)
3351 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3354 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3358 static int atihdmi_init(struct hda_codec *codec)
3360 struct hdmi_spec *spec = codec->spec;
3363 err = generic_hdmi_init(codec);
3368 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3369 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3371 /* make sure downmix information in infoframe is zero */
3372 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3374 /* enable channel-wise remap mode if supported */
3375 if (has_amd_full_remap_support(codec))
3376 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3377 ATI_VERB_SET_MULTICHANNEL_MODE,
3378 ATI_MULTICHANNEL_MODE_SINGLE);
3384 static int patch_atihdmi(struct hda_codec *codec)
3386 struct hdmi_spec *spec;
3387 struct hdmi_spec_per_cvt *per_cvt;
3390 err = patch_generic_hdmi(codec);
3395 codec->patch_ops.init = atihdmi_init;
3399 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3400 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3401 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3402 spec->ops.setup_stream = atihdmi_setup_stream;
3404 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3405 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3407 if (!has_amd_full_remap_support(codec)) {
3408 /* override to ATI/AMD-specific versions with pairwise mapping */
3409 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3410 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3411 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3412 atihdmi_paired_cea_alloc_to_tlv_chmap;
3413 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3416 /* ATI/AMD converters do not advertise all of their capabilities */
3417 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3418 per_cvt = get_cvt(spec, cvt_idx);
3419 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3420 per_cvt->rates |= SUPPORTED_RATES;
3421 per_cvt->formats |= SUPPORTED_FORMATS;
3422 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3425 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3430 /* VIA HDMI Implementation */
3431 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3432 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3434 static int patch_via_hdmi(struct hda_codec *codec)
3436 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3442 static const struct hda_device_id snd_hda_id_hdmi[] = {
3443 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3444 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3445 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3446 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3447 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3448 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3449 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3450 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3451 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3452 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3453 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3454 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3455 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3456 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3457 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3458 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3459 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3460 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3461 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3462 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3463 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3464 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3465 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3466 /* 17 is known to be absent */
3467 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3468 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3469 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3470 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3471 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3472 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3473 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3474 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3475 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3476 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3477 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3478 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3479 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3480 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3481 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3482 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3483 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3484 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3485 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3486 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3487 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3488 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3489 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3490 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3491 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3492 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3493 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3494 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3495 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
3496 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3497 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3498 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3499 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
3500 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3501 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3502 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
3503 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
3504 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
3505 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
3506 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_generic_hdmi),
3507 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3508 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3509 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
3510 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3511 /* special ID for generic HDMI */
3512 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3515 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3517 MODULE_LICENSE("GPL");
3518 MODULE_DESCRIPTION("HDMI HD-audio codec");
3519 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3520 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3521 MODULE_ALIAS("snd-hda-codec-atihdmi");
3523 static struct hda_codec_driver hdmi_driver = {
3524 .id = snd_hda_id_hdmi,
3527 module_hda_codec_driver(hdmi_driver);