2 * ALSA driver for ICEnsemble ICE1724 (Envy24)
4 * Lowlevel functions for Terratec PHASE 22
6 * Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * Audio controller: VIA Envy24HT-S (slightly trimmed down Envy24HT, 4in/4out)
26 * Analog chip: AK4524 (partially via Philip's 74HCT125)
27 * Digital receiver: CS8414-CS (supported in this release)
28 * PHASE 22 revision 2.0 and Terrasoniq/Musonik TS22PCI have CS8416
29 * (support status unknown, please test and report)
31 * Envy connects to AK4524
32 * - CS directly from GPIO 10
33 * - CCLK via 74HCT125's gate #4 from GPIO 4
34 * - CDTI via 74HCT125's gate #2 from GPIO 5
35 * CDTI may be completely blocked by 74HCT125's gate #1
36 * controlled by GPIO 3
40 * Audio controller: VIA Envy24HT (full untrimmed version, 8in/8out)
41 * Analog chip: WM8770 (8 channel 192k DAC, 2 channel 96k ADC)
42 * Digital receiver: CS8414-CS (supported in this release)
46 #include <linux/delay.h>
47 #include <linux/interrupt.h>
48 #include <linux/init.h>
49 #include <linux/slab.h>
50 #include <linux/mutex.h>
52 #include <sound/core.h>
57 #include <sound/tlv.h>
59 /* AC97 register cache for Phase28 */
61 unsigned short master[2];
62 unsigned short vol[8];
65 /* WM8770 registers */
66 #define WM_DAC_ATTEN 0x00 /* DAC1-8 analog attenuation */
67 #define WM_DAC_MASTER_ATTEN 0x08 /* DAC master analog attenuation */
68 #define WM_DAC_DIG_ATTEN 0x09 /* DAC1-8 digital attenuation */
69 #define WM_DAC_DIG_MASTER_ATTEN 0x11 /* DAC master digital attenuation */
70 #define WM_PHASE_SWAP 0x12 /* DAC phase */
71 #define WM_DAC_CTRL1 0x13 /* DAC control bits */
72 #define WM_MUTE 0x14 /* mute controls */
73 #define WM_DAC_CTRL2 0x15 /* de-emphasis and zefo-flag */
74 #define WM_INT_CTRL 0x16 /* interface control */
75 #define WM_MASTER 0x17 /* master clock and mode */
76 #define WM_POWERDOWN 0x18 /* power-down controls */
77 #define WM_ADC_GAIN 0x19 /* ADC gain L(19)/R(1a) */
78 #define WM_ADC_MUX 0x1b /* input MUX */
79 #define WM_OUT_MUX1 0x1c /* output MUX */
80 #define WM_OUT_MUX2 0x1e /* output MUX */
81 #define WM_RESET 0x1f /* software reset */
85 * Logarithmic volume values for WM8770
86 * Computed as 20 * Log10(255 / x)
88 static const unsigned char wm_vol[256] = {
89 127, 48, 42, 39, 36, 34, 33, 31, 30, 29, 28, 27, 27, 26, 25, 25, 24, 24, 23,
90 23, 22, 22, 21, 21, 21, 20, 20, 20, 19, 19, 19, 18, 18, 18, 18, 17, 17, 17,
91 17, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 13, 13, 13,
92 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11,
93 11, 10, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8,
94 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6,
95 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
96 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3,
97 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
98 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
99 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
103 #define WM_VOL_MAX (sizeof(wm_vol) - 1)
104 #define WM_VOL_MUTE 0x8000
106 static struct snd_akm4xxx akm_phase22 __devinitdata = {
112 static struct snd_ak4xxx_private akm_phase22_priv __devinitdata = {
124 static int __devinit phase22_init(struct snd_ice1712 *ice)
126 struct snd_akm4xxx *ak;
129 // Configure DAC/ADC description for generic part of ice1724
130 switch (ice->eeprom.subvendor) {
131 case VT1724_SUBDEVICE_PHASE22:
132 case VT1724_SUBDEVICE_TS22:
133 ice->num_total_dacs = 2;
134 ice->num_total_adcs = 2;
135 ice->vt1720 = 1; // Envy24HT-S have 16 bit wide GPIO
142 // Initialize analog chips
143 ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
147 switch (ice->eeprom.subvendor) {
148 case VT1724_SUBDEVICE_PHASE22:
149 case VT1724_SUBDEVICE_TS22:
150 if ((err = snd_ice1712_akm4xxx_init(ak, &akm_phase22, &akm_phase22_priv, ice)) < 0)
158 static int __devinit phase22_add_controls(struct snd_ice1712 *ice)
162 switch (ice->eeprom.subvendor) {
163 case VT1724_SUBDEVICE_PHASE22:
164 case VT1724_SUBDEVICE_TS22:
165 err = snd_ice1712_akm4xxx_build_controls(ice);
172 static unsigned char phase22_eeprom[] __devinitdata = {
173 [ICE_EEP2_SYSCONF] = 0x28, /* clock 512, mpu 401,
174 spdif-in/1xADC, 1xDACs */
175 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
176 [ICE_EEP2_I2S] = 0xf0, /* vol, 96k, 24bit */
177 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
178 [ICE_EEP2_GPIO_DIR] = 0xff,
179 [ICE_EEP2_GPIO_DIR1] = 0xff,
180 [ICE_EEP2_GPIO_DIR2] = 0xff,
181 [ICE_EEP2_GPIO_MASK] = 0x00,
182 [ICE_EEP2_GPIO_MASK1] = 0x00,
183 [ICE_EEP2_GPIO_MASK2] = 0x00,
184 [ICE_EEP2_GPIO_STATE] = 0x00,
185 [ICE_EEP2_GPIO_STATE1] = 0x00,
186 [ICE_EEP2_GPIO_STATE2] = 0x00,
189 static unsigned char phase28_eeprom[] __devinitdata = {
190 [ICE_EEP2_SYSCONF] = 0x2b, /* clock 512, mpu401,
191 spdif-in/1xADC, 4xDACs */
192 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
193 [ICE_EEP2_I2S] = 0xfc, /* vol, 96k, 24bit, 192k */
194 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
195 [ICE_EEP2_GPIO_DIR] = 0xff,
196 [ICE_EEP2_GPIO_DIR1] = 0xff,
197 [ICE_EEP2_GPIO_DIR2] = 0x5f,
198 [ICE_EEP2_GPIO_MASK] = 0x00,
199 [ICE_EEP2_GPIO_MASK1] = 0x00,
200 [ICE_EEP2_GPIO_MASK2] = 0x00,
201 [ICE_EEP2_GPIO_STATE] = 0x00,
202 [ICE_EEP2_GPIO_STATE1] = 0x00,
203 [ICE_EEP2_GPIO_STATE2] = 0x00,
207 * write data in the SPI mode
209 static void phase28_spi_write(struct snd_ice1712 *ice, unsigned int cs, unsigned int data, int bits)
214 tmp = snd_ice1712_gpio_read(ice);
216 snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RW|PHASE28_SPI_MOSI|PHASE28_SPI_CLK|
218 tmp |= PHASE28_WM_RW;
220 snd_ice1712_gpio_write(ice, tmp);
223 for (i = bits - 1; i >= 0; i--) {
224 tmp &= ~PHASE28_SPI_CLK;
225 snd_ice1712_gpio_write(ice, tmp);
228 tmp |= PHASE28_SPI_MOSI;
230 tmp &= ~PHASE28_SPI_MOSI;
231 snd_ice1712_gpio_write(ice, tmp);
233 tmp |= PHASE28_SPI_CLK;
234 snd_ice1712_gpio_write(ice, tmp);
238 tmp &= ~PHASE28_SPI_CLK;
240 snd_ice1712_gpio_write(ice, tmp);
242 tmp |= PHASE28_SPI_CLK;
243 snd_ice1712_gpio_write(ice, tmp);
248 * get the current register value of WM codec
250 static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
253 return ((unsigned short)ice->akm[0].images[reg] << 8) |
254 ice->akm[0].images[reg + 1];
258 * set the register value of WM codec
260 static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
262 phase28_spi_write(ice, PHASE28_WM_CS, (reg << 9) | (val & 0x1ff), 16);
266 * set the register value of WM codec and remember it
268 static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
270 wm_put_nocache(ice, reg, val);
272 ice->akm[0].images[reg] = val >> 8;
273 ice->akm[0].images[reg + 1] = val;
276 static void wm_set_vol(struct snd_ice1712 *ice, unsigned int index, unsigned short vol, unsigned short master)
280 if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
283 nvol = 127 - wm_vol[(((vol & ~WM_VOL_MUTE) * (master & ~WM_VOL_MUTE)) / 127) & WM_VOL_MAX];
285 wm_put(ice, index, nvol);
286 wm_put_nocache(ice, index, 0x180 | nvol);
292 #define wm_pcm_mute_info snd_ctl_boolean_mono_info
294 static int wm_pcm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
296 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
298 mutex_lock(&ice->gpio_mutex);
299 ucontrol->value.integer.value[0] = (wm_get(ice, WM_MUTE) & 0x10) ? 0 : 1;
300 mutex_unlock(&ice->gpio_mutex);
304 static int wm_pcm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
306 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
307 unsigned short nval, oval;
310 snd_ice1712_save_gpio_status(ice);
311 oval = wm_get(ice, WM_MUTE);
312 nval = (oval & ~0x10) | (ucontrol->value.integer.value[0] ? 0 : 0x10);
313 if ((change = (nval != oval)))
314 wm_put(ice, WM_MUTE, nval);
315 snd_ice1712_restore_gpio_status(ice);
321 * Master volume attenuation mixer control
323 static int wm_master_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
325 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
327 uinfo->value.integer.min = 0;
328 uinfo->value.integer.max = WM_VOL_MAX;
332 static int wm_master_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
334 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
335 struct phase28_spec *spec = ice->spec;
338 ucontrol->value.integer.value[i] = spec->master[i] & ~WM_VOL_MUTE;
342 static int wm_master_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
344 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
345 struct phase28_spec *spec = ice->spec;
348 snd_ice1712_save_gpio_status(ice);
349 for (ch = 0; ch < 2; ch++) {
350 unsigned int vol = ucontrol->value.integer.value[ch];
351 if (vol > WM_VOL_MAX)
353 vol |= spec->master[ch] & WM_VOL_MUTE;
354 if (vol != spec->master[ch]) {
356 spec->master[ch] = vol;
357 for (dac = 0; dac < ice->num_total_dacs; dac += 2)
358 wm_set_vol(ice, WM_DAC_ATTEN + dac + ch,
364 snd_ice1712_restore_gpio_status(ice);
368 static int __devinit phase28_init(struct snd_ice1712 *ice)
370 static const unsigned short wm_inits_phase28[] = {
371 /* These come first to reduce init pop noise */
372 0x1b, 0x044, /* ADC Mux (AC'97 source) */
373 0x1c, 0x00B, /* Out Mux1 (VOUT1 = DAC+AUX, VOUT2 = DAC) */
374 0x1d, 0x009, /* Out Mux2 (VOUT2 = DAC, VOUT3 = DAC) */
376 0x18, 0x000, /* All power-up */
378 0x16, 0x122, /* I2S, normal polarity, 24bit */
379 0x17, 0x022, /* 256fs, slave mode */
380 0x00, 0, /* DAC1 analog mute */
381 0x01, 0, /* DAC2 analog mute */
382 0x02, 0, /* DAC3 analog mute */
383 0x03, 0, /* DAC4 analog mute */
384 0x04, 0, /* DAC5 analog mute */
385 0x05, 0, /* DAC6 analog mute */
386 0x06, 0, /* DAC7 analog mute */
387 0x07, 0, /* DAC8 analog mute */
388 0x08, 0x100, /* master analog mute */
389 0x09, 0xff, /* DAC1 digital full */
390 0x0a, 0xff, /* DAC2 digital full */
391 0x0b, 0xff, /* DAC3 digital full */
392 0x0c, 0xff, /* DAC4 digital full */
393 0x0d, 0xff, /* DAC5 digital full */
394 0x0e, 0xff, /* DAC6 digital full */
395 0x0f, 0xff, /* DAC7 digital full */
396 0x10, 0xff, /* DAC8 digital full */
397 0x11, 0x1ff, /* master digital full */
398 0x12, 0x000, /* phase normal */
399 0x13, 0x090, /* unmute DAC L/R */
400 0x14, 0x000, /* all unmute */
401 0x15, 0x000, /* no deemphasis, no ZFLG */
402 0x19, 0x000, /* -12dB ADC/L */
403 0x1a, 0x000, /* -12dB ADC/R */
408 struct snd_akm4xxx *ak;
409 struct phase28_spec *spec;
410 const unsigned short *p;
413 ice->num_total_dacs = 8;
414 ice->num_total_adcs = 2;
416 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
421 // Initialize analog chips
422 ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
427 snd_ice1712_gpio_set_dir(ice, 0x5fffff); /* fix this for the time being */
429 /* reset the wm codec as the SPI mode */
430 snd_ice1712_save_gpio_status(ice);
431 snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RESET|PHASE28_WM_CS|PHASE28_HP_SEL));
433 tmp = snd_ice1712_gpio_read(ice);
434 tmp &= ~PHASE28_WM_RESET;
435 snd_ice1712_gpio_write(ice, tmp);
437 tmp |= PHASE28_WM_CS;
438 snd_ice1712_gpio_write(ice, tmp);
440 tmp |= PHASE28_WM_RESET;
441 snd_ice1712_gpio_write(ice, tmp);
444 p = wm_inits_phase28;
445 for (; *p != (unsigned short)-1; p += 2)
446 wm_put(ice, p[0], p[1]);
448 snd_ice1712_restore_gpio_status(ice);
450 spec->master[0] = WM_VOL_MUTE;
451 spec->master[1] = WM_VOL_MUTE;
452 for (i = 0; i < ice->num_total_dacs; i++) {
453 spec->vol[i] = WM_VOL_MUTE;
454 wm_set_vol(ice, i, spec->vol[i], spec->master[i % 2]);
461 * DAC volume attenuation mixer control
463 static int wm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
465 int voices = kcontrol->private_value >> 8;
466 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
467 uinfo->count = voices;
468 uinfo->value.integer.min = 0; /* mute (-101dB) */
469 uinfo->value.integer.max = 0x7F; /* 0dB */
473 static int wm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
475 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
476 struct phase28_spec *spec = ice->spec;
479 voices = kcontrol->private_value >> 8;
480 ofs = kcontrol->private_value & 0xff;
481 for (i = 0; i < voices; i++)
482 ucontrol->value.integer.value[i] =
483 spec->vol[ofs+i] & ~WM_VOL_MUTE;
487 static int wm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
489 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
490 struct phase28_spec *spec = ice->spec;
491 int i, idx, ofs, voices;
494 voices = kcontrol->private_value >> 8;
495 ofs = kcontrol->private_value & 0xff;
496 snd_ice1712_save_gpio_status(ice);
497 for (i = 0; i < voices; i++) {
499 vol = ucontrol->value.integer.value[i];
502 vol |= spec->vol[ofs+i] & WM_VOL_MUTE;
503 if (vol != spec->vol[ofs+i]) {
504 spec->vol[ofs+i] = vol;
505 idx = WM_DAC_ATTEN + ofs + i;
506 wm_set_vol(ice, idx, spec->vol[ofs+i],
511 snd_ice1712_restore_gpio_status(ice);
516 * WM8770 mute control
518 static int wm_mute_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) {
519 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
520 uinfo->count = kcontrol->private_value >> 8;
521 uinfo->value.integer.min = 0;
522 uinfo->value.integer.max = 1;
526 static int wm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
528 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
529 struct phase28_spec *spec = ice->spec;
532 voices = kcontrol->private_value >> 8;
533 ofs = kcontrol->private_value & 0xFF;
535 for (i = 0; i < voices; i++)
536 ucontrol->value.integer.value[i] =
537 (spec->vol[ofs+i] & WM_VOL_MUTE) ? 0 : 1;
541 static int wm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
543 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
544 struct phase28_spec *spec = ice->spec;
545 int change = 0, voices, ofs, i;
547 voices = kcontrol->private_value >> 8;
548 ofs = kcontrol->private_value & 0xFF;
550 snd_ice1712_save_gpio_status(ice);
551 for (i = 0; i < voices; i++) {
552 int val = (spec->vol[ofs + i] & WM_VOL_MUTE) ? 0 : 1;
553 if (ucontrol->value.integer.value[i] != val) {
554 spec->vol[ofs + i] &= ~WM_VOL_MUTE;
555 spec->vol[ofs + i] |=
556 ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
557 wm_set_vol(ice, ofs + i, spec->vol[ofs + i],
562 snd_ice1712_restore_gpio_status(ice);
568 * WM8770 master mute control
570 #define wm_master_mute_info snd_ctl_boolean_stereo_info
572 static int wm_master_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
574 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
575 struct phase28_spec *spec = ice->spec;
577 ucontrol->value.integer.value[0] =
578 (spec->master[0] & WM_VOL_MUTE) ? 0 : 1;
579 ucontrol->value.integer.value[1] =
580 (spec->master[1] & WM_VOL_MUTE) ? 0 : 1;
584 static int wm_master_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
586 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
587 struct phase28_spec *spec = ice->spec;
590 snd_ice1712_save_gpio_status(ice);
591 for (i = 0; i < 2; i++) {
592 int val = (spec->master[i] & WM_VOL_MUTE) ? 0 : 1;
593 if (ucontrol->value.integer.value[i] != val) {
595 spec->master[i] &= ~WM_VOL_MUTE;
597 ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
598 for (dac = 0; dac < ice->num_total_dacs; dac += 2)
599 wm_set_vol(ice, WM_DAC_ATTEN + dac + i,
605 snd_ice1712_restore_gpio_status(ice);
610 /* digital master volume */
612 #define PCM_RES 128 /* -64dB */
613 #define PCM_MIN (PCM_0dB - PCM_RES)
614 static int wm_pcm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
616 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
618 uinfo->value.integer.min = 0; /* mute (-64dB) */
619 uinfo->value.integer.max = PCM_RES; /* 0dB */
623 static int wm_pcm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
625 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
628 mutex_lock(&ice->gpio_mutex);
629 val = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
630 val = val > PCM_MIN ? (val - PCM_MIN) : 0;
631 ucontrol->value.integer.value[0] = val;
632 mutex_unlock(&ice->gpio_mutex);
636 static int wm_pcm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
638 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
639 unsigned short ovol, nvol;
642 nvol = ucontrol->value.integer.value[0];
645 snd_ice1712_save_gpio_status(ice);
646 nvol = (nvol ? (nvol + PCM_MIN) : 0) & 0xff;
647 ovol = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
649 wm_put(ice, WM_DAC_DIG_MASTER_ATTEN, nvol); /* prelatch */
650 wm_put_nocache(ice, WM_DAC_DIG_MASTER_ATTEN, nvol | 0x100); /* update */
653 snd_ice1712_restore_gpio_status(ice);
660 #define phase28_deemp_info snd_ctl_boolean_mono_info
662 static int phase28_deemp_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
664 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
665 ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL2) & 0xf) == 0xf;
669 static int phase28_deemp_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
671 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
673 temp2 = temp = wm_get(ice, WM_DAC_CTRL2);
674 if (ucontrol->value.integer.value[0])
679 wm_put(ice, WM_DAC_CTRL2, temp);
688 static int phase28_oversampling_info(struct snd_kcontrol *k, struct snd_ctl_elem_info *uinfo)
690 static char *texts[2] = { "128x", "64x" };
692 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
694 uinfo->value.enumerated.items = 2;
696 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
697 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
698 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
703 static int phase28_oversampling_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
705 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
706 ucontrol->value.enumerated.item[0] = (wm_get(ice, WM_MASTER) & 0x8) == 0x8;
710 static int phase28_oversampling_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
713 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
715 temp2 = temp = wm_get(ice, WM_MASTER);
717 if (ucontrol->value.enumerated.item[0])
723 wm_put(ice, WM_MASTER, temp);
729 static const DECLARE_TLV_DB_SCALE(db_scale_wm_dac, -12700, 100, 1);
730 static const DECLARE_TLV_DB_SCALE(db_scale_wm_pcm, -6400, 50, 1);
732 static struct snd_kcontrol_new phase28_dac_controls[] __devinitdata = {
734 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
735 .name = "Master Playback Switch",
736 .info = wm_master_mute_info,
737 .get = wm_master_mute_get,
738 .put = wm_master_mute_put
741 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
742 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
743 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
744 .name = "Master Playback Volume",
745 .info = wm_master_vol_info,
746 .get = wm_master_vol_get,
747 .put = wm_master_vol_put,
748 .tlv = { .p = db_scale_wm_dac }
751 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
752 .name = "Front Playback Switch",
753 .info = wm_mute_info,
756 .private_value = (2 << 8) | 0
759 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
760 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
761 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
762 .name = "Front Playback Volume",
766 .private_value = (2 << 8) | 0,
767 .tlv = { .p = db_scale_wm_dac }
770 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
771 .name = "Rear Playback Switch",
772 .info = wm_mute_info,
775 .private_value = (2 << 8) | 2
778 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
779 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
780 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
781 .name = "Rear Playback Volume",
785 .private_value = (2 << 8) | 2,
786 .tlv = { .p = db_scale_wm_dac }
789 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
790 .name = "Center Playback Switch",
791 .info = wm_mute_info,
794 .private_value = (1 << 8) | 4
797 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
798 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
799 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
800 .name = "Center Playback Volume",
804 .private_value = (1 << 8) | 4,
805 .tlv = { .p = db_scale_wm_dac }
808 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
809 .name = "LFE Playback Switch",
810 .info = wm_mute_info,
813 .private_value = (1 << 8) | 5
816 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
817 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
818 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
819 .name = "LFE Playback Volume",
823 .private_value = (1 << 8) | 5,
824 .tlv = { .p = db_scale_wm_dac }
827 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
828 .name = "Side Playback Switch",
829 .info = wm_mute_info,
832 .private_value = (2 << 8) | 6
835 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
836 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
837 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
838 .name = "Side Playback Volume",
842 .private_value = (2 << 8) | 6,
843 .tlv = { .p = db_scale_wm_dac }
847 static struct snd_kcontrol_new wm_controls[] __devinitdata = {
849 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
850 .name = "PCM Playback Switch",
851 .info = wm_pcm_mute_info,
852 .get = wm_pcm_mute_get,
853 .put = wm_pcm_mute_put
856 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
857 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
858 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
859 .name = "PCM Playback Volume",
860 .info = wm_pcm_vol_info,
861 .get = wm_pcm_vol_get,
862 .put = wm_pcm_vol_put,
863 .tlv = { .p = db_scale_wm_pcm }
866 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
867 .name = "DAC Deemphasis Switch",
868 .info = phase28_deemp_info,
869 .get = phase28_deemp_get,
870 .put = phase28_deemp_put
873 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
874 .name = "ADC Oversampling",
875 .info = phase28_oversampling_info,
876 .get = phase28_oversampling_get,
877 .put = phase28_oversampling_put
881 static int __devinit phase28_add_controls(struct snd_ice1712 *ice)
883 unsigned int i, counts;
886 counts = ARRAY_SIZE(phase28_dac_controls);
887 for (i = 0; i < counts; i++) {
888 err = snd_ctl_add(ice->card, snd_ctl_new1(&phase28_dac_controls[i], ice));
893 for (i = 0; i < ARRAY_SIZE(wm_controls); i++) {
894 err = snd_ctl_add(ice->card, snd_ctl_new1(&wm_controls[i], ice));
902 struct snd_ice1712_card_info snd_vt1724_phase_cards[] __devinitdata = {
904 .subvendor = VT1724_SUBDEVICE_PHASE22,
905 .name = "Terratec PHASE 22",
907 .chip_init = phase22_init,
908 .build_controls = phase22_add_controls,
909 .eeprom_size = sizeof(phase22_eeprom),
910 .eeprom_data = phase22_eeprom,
913 .subvendor = VT1724_SUBDEVICE_PHASE28,
914 .name = "Terratec PHASE 28",
916 .chip_init = phase28_init,
917 .build_controls = phase28_add_controls,
918 .eeprom_size = sizeof(phase28_eeprom),
919 .eeprom_data = phase28_eeprom,
922 .subvendor = VT1724_SUBDEVICE_TS22,
923 .name = "Terrasoniq TS22 PCI",
925 .chip_init = phase22_init,
926 .build_controls = phase22_add_controls,
927 .eeprom_size = sizeof(phase22_eeprom),
928 .eeprom_data = phase22_eeprom,