sound/pci/lx6464es/lx_core.c

   1 /* -*- linux-c -*- *
   2  *
   3  * ALSA driver for the digigram lx6464es interface
   4  * low-level interface
   5  *
   6  * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; see the file COPYING.  If not, write to
  20  * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  21  * Boston, MA 02111-1307, USA.
  22  *
  23  */
  24
  25 /* #define RMH_DEBUG 1 */
  26
  27 #include <linux/bitops.h>
  28 #include <linux/module.h>
  29 #include <linux/pci.h>
  30 #include <linux/delay.h>
  31
  32 #include "lx6464es.h"
  33 #include "lx_core.h"
  34
  35 /* low-level register access */
  36
  37 static const unsigned long dsp_port_offsets[] = {
  38         0,
  39         0x400,
  40         0x401,
  41         0x402,
  42         0x403,
  43         0x404,
  44         0x405,
  45         0x406,
  46         0x407,
  47         0x408,
  48         0x409,
  49         0x40a,
  50         0x40b,
  51         0x40c,
  52
  53         0x410,
  54         0x411,
  55         0x412,
  56         0x413,
  57         0x414,
  58         0x415,
  59         0x416,
  60
  61         0x420,
  62         0x430,
  63         0x431,
  64         0x432,
  65         0x433,
  66         0x434,
  67         0x440
  68 };
  69
  70 static void __iomem *lx_dsp_register(struct lx6464es *chip, int port)
  71 {
  72         void __iomem *base_address = chip->port_dsp_bar;
  73         return base_address + dsp_port_offsets[port]*4;
  74 }
  75
  76 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port)
  77 {
  78         void __iomem *address = lx_dsp_register(chip, port);
  79         return ioread32(address);
  80 }
  81
  82 static void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data,
  83                                u32 len)
  84 {
  85         u32 __iomem *address = lx_dsp_register(chip, port);
  86         int i;
  87
  88         /* we cannot use memcpy_fromio */
  89         for (i = 0; i != len; ++i)
  90                 data[i] = ioread32(address + i);
  91 }
  92
  93
  94 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data)
  95 {
  96         void __iomem *address = lx_dsp_register(chip, port);
  97         iowrite32(data, address);
  98 }
  99
 100 static void lx_dsp_reg_writebuf(struct lx6464es *chip, int port,
 101                                 const u32 *data, u32 len)
 102 {
 103         u32 __iomem *address = lx_dsp_register(chip, port);
 104         int i;
 105
 106         /* we cannot use memcpy_to */
 107         for (i = 0; i != len; ++i)
 108                 iowrite32(data[i], address + i);
 109 }
 110
 111
 112 static const unsigned long plx_port_offsets[] = {
 113         0x04,
 114         0x40,
 115         0x44,
 116         0x48,
 117         0x4c,
 118         0x50,
 119         0x54,
 120         0x58,
 121         0x5c,
 122         0x64,
 123         0x68,
 124         0x6C
 125 };
 126
 127 static void __iomem *lx_plx_register(struct lx6464es *chip, int port)
 128 {
 129         void __iomem *base_address = chip->port_plx_remapped;
 130         return base_address + plx_port_offsets[port];
 131 }
 132
 133 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port)
 134 {
 135         void __iomem *address = lx_plx_register(chip, port);
 136         return ioread32(address);
 137 }
 138
 139 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data)
 140 {
 141         void __iomem *address = lx_plx_register(chip, port);
 142         iowrite32(data, address);
 143 }
 144
 145 /* rmh */
 146
 147 #ifdef CONFIG_SND_DEBUG
 148 #define CMD_NAME(a) a
 149 #else
 150 #define CMD_NAME(a) NULL
 151 #endif
 152
 153 #define Reg_CSM_MR                      0x00000002
 154 #define Reg_CSM_MC                      0x00000001
 155
 156 struct dsp_cmd_info {
 157         u32    dcCodeOp;        /* Op Code of the command (usually 1st 24-bits
 158                                  * word).*/
 159         u16    dcCmdLength;     /* Command length in words of 24 bits.*/
 160         u16    dcStatusType;    /* Status type: 0 for fixed length, 1 for
 161                                  * random. */
 162         u16    dcStatusLength;  /* Status length (if fixed).*/
 163         char  *dcOpName;
 164 };
 165
 166 /*
 167   Initialization and control data for the Microblaze interface
 168   - OpCode:
 169     the opcode field of the command set at the proper offset
 170   - CmdLength
 171     the number of command words
 172   - StatusType
 173     offset in the status registers: 0 means that the return value may be
 174     different from 0, and must be read
 175   - StatusLength
 176     the number of status words (in addition to the return value)
 177 */
 178
 179 static struct dsp_cmd_info dsp_commands[] =
 180 {
 181         { (CMD_00_INFO_DEBUG << OPCODE_OFFSET)                  , 1 /*custom*/
 182           , 1   , 0 /**/                    , CMD_NAME("INFO_DEBUG") },
 183         { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET)                 , 1 /**/
 184           , 1      , 2 /**/                 , CMD_NAME("GET_SYS_CFG") },
 185         { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET)             , 1 /**/
 186           , 1      , 0 /**/                 , CMD_NAME("SET_GRANULARITY") },
 187         { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET)               , 1 /**/
 188           , 1      , 0 /**/                 , CMD_NAME("SET_TIMER_IRQ") },
 189         { (CMD_04_GET_EVENT << OPCODE_OFFSET)                   , 1 /**/
 190           , 1      , 0 /*up to 10*/     , CMD_NAME("GET_EVENT") },
 191         { (CMD_05_GET_PIPES << OPCODE_OFFSET)                   , 1 /**/
 192           , 1      , 2 /*up to 4*/      , CMD_NAME("GET_PIPES") },
 193         { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET)               , 1 /**/
 194           , 0      , 0 /**/                 , CMD_NAME("ALLOCATE_PIPE") },
 195         { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET)                , 1 /**/
 196           , 0      , 0 /**/                 , CMD_NAME("RELEASE_PIPE") },
 197         { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET)                 , 1 /**/
 198           , 1      , MAX_STREAM_BUFFER  , CMD_NAME("ASK_BUFFERS") },
 199         { (CMD_09_STOP_PIPE << OPCODE_OFFSET)                   , 1 /**/
 200           , 0      , 0 /*up to 2*/      , CMD_NAME("STOP_PIPE") },
 201         { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET)          , 1 /**/
 202           , 1      , 1 /*up to 2*/      , CMD_NAME("GET_PIPE_SPL_COUNT") },
 203         { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET)           , 1 /*up to 5*/
 204           , 1      , 0 /**/                 , CMD_NAME("TOGGLE_PIPE_STATE") },
 205         { (CMD_0C_DEF_STREAM << OPCODE_OFFSET)                  , 1 /*up to 4*/
 206           , 1      , 0 /**/                 , CMD_NAME("DEF_STREAM") },
 207         { (CMD_0D_SET_MUTE  << OPCODE_OFFSET)                   , 3 /**/
 208           , 1      , 0 /**/                 , CMD_NAME("SET_MUTE") },
 209         { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET)        , 1/**/
 210           , 1      , 2 /**/                 , CMD_NAME("GET_STREAM_SPL_COUNT") },
 211         { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET)               , 3 /*up to 4*/
 212           , 0      , 1 /**/                 , CMD_NAME("UPDATE_BUFFER") },
 213         { (CMD_10_GET_BUFFER << OPCODE_OFFSET)                  , 1 /**/
 214           , 1      , 4 /**/                 , CMD_NAME("GET_BUFFER") },
 215         { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET)               , 1 /**/
 216           , 1      , 1 /*up to 4*/      , CMD_NAME("CANCEL_BUFFER") },
 217         { (CMD_12_GET_PEAK << OPCODE_OFFSET)                    , 1 /**/
 218           , 1      , 1 /**/                 , CMD_NAME("GET_PEAK") },
 219         { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET)            , 1 /**/
 220           , 1      , 0 /**/                 , CMD_NAME("SET_STREAM_STATE") },
 221 };
 222
 223 static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd)
 224 {
 225         snd_BUG_ON(cmd >= CMD_14_INVALID);
 226
 227         rmh->cmd[0] = dsp_commands[cmd].dcCodeOp;
 228         rmh->cmd_len = dsp_commands[cmd].dcCmdLength;
 229         rmh->stat_len = dsp_commands[cmd].dcStatusLength;
 230         rmh->dsp_stat = dsp_commands[cmd].dcStatusType;
 231         rmh->cmd_idx = cmd;
 232         memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32));
 233
 234 #ifdef CONFIG_SND_DEBUG
 235         memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32));
 236 #endif
 237 #ifdef RMH_DEBUG
 238         rmh->cmd_idx = cmd;
 239 #endif
 240 }
 241
 242 #ifdef RMH_DEBUG
 243 #define LXRMH "lx6464es rmh: "
 244 static void lx_message_dump(struct lx_rmh *rmh)
 245 {
 246         u8 idx = rmh->cmd_idx;
 247         int i;
 248
 249         snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName);
 250
 251         for (i = 0; i != rmh->cmd_len; ++i)
 252                 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]);
 253
 254         for (i = 0; i != rmh->stat_len; ++i)
 255                 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]);
 256         snd_printk("\n");
 257 }
 258 #else
 259 static inline void lx_message_dump(struct lx_rmh *rmh)
 260 {}
 261 #endif
 262
 263
 264
 265 /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */
 266 #define XILINX_TIMEOUT_MS       40
 267 #define XILINX_POLL_NO_SLEEP    100
 268 #define XILINX_POLL_ITERATIONS  150
 269
 270
 271 static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh)
 272 {
 273         u32 reg = ED_DSP_TIMED_OUT;
 274         int dwloop;
 275
 276         if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) {
 277                 dev_err(chip->card->dev, "PIOSendMessage eReg_CSM %x\n", reg);
 278                 return -EBUSY;
 279         }
 280
 281         /* write command */
 282         lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len);
 283
 284         /* MicoBlaze gogogo */
 285         lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC);
 286
 287         /* wait for device to answer */
 288         for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) {
 289                 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) {
 290                         if (rmh->dsp_stat == 0)
 291                                 reg = lx_dsp_reg_read(chip, eReg_CRM1);
 292                         else
 293                                 reg = 0;
 294                         goto polling_successful;
 295                 } else
 296                         udelay(1);
 297         }
 298         dev_warn(chip->card->dev, "TIMEOUT lx_message_send_atomic! "
 299                    "polling failed\n");
 300
 301 polling_successful:
 302         if ((reg & ERROR_VALUE) == 0) {
 303                 /* read response */
 304                 if (rmh->stat_len) {
 305                         snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1));
 306                         lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat,
 307                                            rmh->stat_len);
 308                 }
 309         } else
 310                 dev_err(chip->card->dev, "rmh error: %08x\n", reg);
 311
 312         /* clear Reg_CSM_MR */
 313         lx_dsp_reg_write(chip, eReg_CSM, 0);
 314
 315         switch (reg) {
 316         case ED_DSP_TIMED_OUT:
 317                 dev_warn(chip->card->dev, "lx_message_send: dsp timeout\n");
 318                 return -ETIMEDOUT;
 319
 320         case ED_DSP_CRASHED:
 321                 dev_warn(chip->card->dev, "lx_message_send: dsp crashed\n");
 322                 return -EAGAIN;
 323         }
 324
 325         lx_message_dump(rmh);
 326
 327         return reg;
 328 }
 329
 330
 331 /* low-level dsp access */
 332 int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version)
 333 {
 334         u16 ret;
 335         unsigned long flags;
 336
 337         spin_lock_irqsave(&chip->msg_lock, flags);
 338
 339         lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
 340         ret = lx_message_send_atomic(chip, &chip->rmh);
 341
 342         *rdsp_version = chip->rmh.stat[1];
 343         spin_unlock_irqrestore(&chip->msg_lock, flags);
 344         return ret;
 345 }
 346
 347 int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq)
 348 {
 349         u16 ret = 0;
 350         unsigned long flags;
 351         u32 freq_raw = 0;
 352         u32 freq = 0;
 353         u32 frequency = 0;
 354
 355         spin_lock_irqsave(&chip->msg_lock, flags);
 356
 357         lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
 358         ret = lx_message_send_atomic(chip, &chip->rmh);
 359
 360         if (ret == 0) {
 361                 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET;
 362                 freq = freq_raw & XES_FREQ_COUNT8_MASK;
 363
 364                 if ((freq < XES_FREQ_COUNT8_48_MAX) ||
 365                     (freq > XES_FREQ_COUNT8_44_MIN))
 366                         frequency = 0; /* unknown */
 367                 else if (freq >= XES_FREQ_COUNT8_44_MAX)
 368                         frequency = 44100;
 369                 else
 370                         frequency = 48000;
 371         }
 372
 373         spin_unlock_irqrestore(&chip->msg_lock, flags);
 374
 375         *rfreq = frequency * chip->freq_ratio;
 376
 377         return ret;
 378 }
 379
 380 int lx_dsp_get_mac(struct lx6464es *chip)
 381 {
 382         u32 macmsb, maclsb;
 383
 384         macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF;
 385         maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF;
 386
 387         /* todo: endianess handling */
 388         chip->mac_address[5] = ((u8 *)(&maclsb))[0];
 389         chip->mac_address[4] = ((u8 *)(&maclsb))[1];
 390         chip->mac_address[3] = ((u8 *)(&maclsb))[2];
 391         chip->mac_address[2] = ((u8 *)(&macmsb))[0];
 392         chip->mac_address[1] = ((u8 *)(&macmsb))[1];
 393         chip->mac_address[0] = ((u8 *)(&macmsb))[2];
 394
 395         return 0;
 396 }
 397
 398
 399 int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran)
 400 {
 401         unsigned long flags;
 402         int ret;
 403
 404         spin_lock_irqsave(&chip->msg_lock, flags);
 405
 406         lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY);
 407         chip->rmh.cmd[0] |= gran;
 408
 409         ret = lx_message_send_atomic(chip, &chip->rmh);
 410         spin_unlock_irqrestore(&chip->msg_lock, flags);
 411         return ret;
 412 }
 413
 414 int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data)
 415 {
 416         unsigned long flags;
 417         int ret;
 418
 419         spin_lock_irqsave(&chip->msg_lock, flags);
 420
 421         lx_message_init(&chip->rmh, CMD_04_GET_EVENT);
 422         chip->rmh.stat_len = 9; /* we don't necessarily need the full length */
 423
 424         ret = lx_message_send_atomic(chip, &chip->rmh);
 425
 426         if (!ret)
 427                 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32));
 428
 429         spin_unlock_irqrestore(&chip->msg_lock, flags);
 430         return ret;
 431 }
 432
 433 #define PIPE_INFO_TO_CMD(capture, pipe)                                 \
 434         ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET)
 435
 436
 437
 438 /* low-level pipe handling */
 439 int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
 440                      int channels)
 441 {
 442         int err;
 443         unsigned long flags;
 444
 445         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 446
 447         spin_lock_irqsave(&chip->msg_lock, flags);
 448         lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE);
 449
 450         chip->rmh.cmd[0] |= pipe_cmd;
 451         chip->rmh.cmd[0] |= channels;
 452
 453         err = lx_message_send_atomic(chip, &chip->rmh);
 454         spin_unlock_irqrestore(&chip->msg_lock, flags);
 455
 456         if (err != 0)
 457                 dev_err(chip->card->dev, "could not allocate pipe\n");
 458
 459         return err;
 460 }
 461
 462 int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture)
 463 {
 464         int err;
 465         unsigned long flags;
 466
 467         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 468
 469         spin_lock_irqsave(&chip->msg_lock, flags);
 470         lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE);
 471
 472         chip->rmh.cmd[0] |= pipe_cmd;
 473
 474         err = lx_message_send_atomic(chip, &chip->rmh);
 475         spin_unlock_irqrestore(&chip->msg_lock, flags);
 476
 477         return err;
 478 }
 479
 480 int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
 481                   u32 *r_needed, u32 *r_freed, u32 *size_array)
 482 {
 483         int err;
 484         unsigned long flags;
 485
 486         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 487
 488 #ifdef CONFIG_SND_DEBUG
 489         if (size_array)
 490                 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER);
 491 #endif
 492
 493         *r_needed = 0;
 494         *r_freed = 0;
 495
 496         spin_lock_irqsave(&chip->msg_lock, flags);
 497         lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS);
 498
 499         chip->rmh.cmd[0] |= pipe_cmd;
 500
 501         err = lx_message_send_atomic(chip, &chip->rmh);
 502
 503         if (!err) {
 504                 int i;
 505                 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
 506                         u32 stat = chip->rmh.stat[i];
 507                         if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) {
 508                                 /* finished */
 509                                 *r_freed += 1;
 510                                 if (size_array)
 511                                         size_array[i] = stat & MASK_DATA_SIZE;
 512                         } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET))
 513                                    == 0)
 514                                 /* free */
 515                                 *r_needed += 1;
 516                 }
 517
 518 #if 0
 519                 dev_dbg(chip->card->dev,
 520                         "CMD_08_ASK_BUFFERS: needed %d, freed %d\n",
 521                             *r_needed, *r_freed);
 522                 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
 523                         for (i = 0; i != chip->rmh.stat_len; ++i)
 524                                 dev_dbg(chip->card->dev,
 525                                         "  stat[%d]: %x, %x\n", i,
 526                                             chip->rmh.stat[i],
 527                                             chip->rmh.stat[i] & MASK_DATA_SIZE);
 528                 }
 529 #endif
 530         }
 531
 532         spin_unlock_irqrestore(&chip->msg_lock, flags);
 533         return err;
 534 }
 535
 536
 537 int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture)
 538 {
 539         int err;
 540         unsigned long flags;
 541
 542         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 543
 544         spin_lock_irqsave(&chip->msg_lock, flags);
 545         lx_message_init(&chip->rmh, CMD_09_STOP_PIPE);
 546
 547         chip->rmh.cmd[0] |= pipe_cmd;
 548
 549         err = lx_message_send_atomic(chip, &chip->rmh);
 550
 551         spin_unlock_irqrestore(&chip->msg_lock, flags);
 552         return err;
 553 }
 554
 555 static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture)
 556 {
 557         int err;
 558         unsigned long flags;
 559
 560         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 561
 562         spin_lock_irqsave(&chip->msg_lock, flags);
 563         lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE);
 564
 565         chip->rmh.cmd[0] |= pipe_cmd;
 566
 567         err = lx_message_send_atomic(chip, &chip->rmh);
 568
 569         spin_unlock_irqrestore(&chip->msg_lock, flags);
 570         return err;
 571 }
 572
 573
 574 int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture)
 575 {
 576         int err;
 577
 578         err = lx_pipe_wait_for_idle(chip, pipe, is_capture);
 579         if (err < 0)
 580                 return err;
 581
 582         err = lx_pipe_toggle_state(chip, pipe, is_capture);
 583
 584         return err;
 585 }
 586
 587 int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture)
 588 {
 589         int err = 0;
 590
 591         err = lx_pipe_wait_for_start(chip, pipe, is_capture);
 592         if (err < 0)
 593                 return err;
 594
 595         err = lx_pipe_toggle_state(chip, pipe, is_capture);
 596
 597         return err;
 598 }
 599
 600
 601 int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
 602                          u64 *rsample_count)
 603 {
 604         int err;
 605         unsigned long flags;
 606
 607         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 608
 609         spin_lock_irqsave(&chip->msg_lock, flags);
 610         lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
 611
 612         chip->rmh.cmd[0] |= pipe_cmd;
 613         chip->rmh.stat_len = 2; /* need all words here! */
 614
 615         err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */
 616
 617         if (err != 0)
 618                 dev_err(chip->card->dev,
 619                         "could not query pipe's sample count\n");
 620         else {
 621                 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
 622                                   << 24)     /* hi part */
 623                         + chip->rmh.stat[1]; /* lo part */
 624         }
 625
 626         spin_unlock_irqrestore(&chip->msg_lock, flags);
 627         return err;
 628 }
 629
 630 int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate)
 631 {
 632         int err;
 633         unsigned long flags;
 634
 635         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 636
 637         spin_lock_irqsave(&chip->msg_lock, flags);
 638         lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
 639
 640         chip->rmh.cmd[0] |= pipe_cmd;
 641
 642         err = lx_message_send_atomic(chip, &chip->rmh);
 643
 644         if (err != 0)
 645                 dev_err(chip->card->dev, "could not query pipe's state\n");
 646         else
 647                 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F;
 648
 649         spin_unlock_irqrestore(&chip->msg_lock, flags);
 650         return err;
 651 }
 652
 653 static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe,
 654                                   int is_capture, u16 state)
 655 {
 656         int i;
 657
 658         /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms:
 659          * timeout 50 ms */
 660         for (i = 0; i != 50; ++i) {
 661                 u16 current_state;
 662                 int err = lx_pipe_state(chip, pipe, is_capture, &current_state);
 663
 664                 if (err < 0)
 665                         return err;
 666
 667                 if (current_state == state)
 668                         return 0;
 669
 670                 mdelay(1);
 671         }
 672
 673         return -ETIMEDOUT;
 674 }
 675
 676 int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture)
 677 {
 678         return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN);
 679 }
 680
 681 int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture)
 682 {
 683         return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE);
 684 }
 685
 686 /* low-level stream handling */
 687 int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
 688                                int is_capture, enum stream_state_t state)
 689 {
 690         int err;
 691         unsigned long flags;
 692
 693         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 694
 695         spin_lock_irqsave(&chip->msg_lock, flags);
 696         lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE);
 697
 698         chip->rmh.cmd[0] |= pipe_cmd;
 699         chip->rmh.cmd[0] |= state;
 700
 701         err = lx_message_send_atomic(chip, &chip->rmh);
 702         spin_unlock_irqrestore(&chip->msg_lock, flags);
 703
 704         return err;
 705 }
 706
 707 int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
 708                          u32 pipe, int is_capture)
 709 {
 710         int err;
 711         unsigned long flags;
 712
 713         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 714
 715         u32 channels = runtime->channels;
 716
 717         if (runtime->channels != channels)
 718                 dev_err(chip->card->dev, "channel count mismatch: %d vs %d",
 719                            runtime->channels, channels);
 720
 721         spin_lock_irqsave(&chip->msg_lock, flags);
 722         lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM);
 723
 724         chip->rmh.cmd[0] |= pipe_cmd;
 725
 726         if (runtime->sample_bits == 16)
 727                 /* 16 bit format */
 728                 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET);
 729
 730         if (snd_pcm_format_little_endian(runtime->format))
 731                 /* little endian/intel format */
 732                 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET);
 733
 734         chip->rmh.cmd[0] |= channels-1;
 735
 736         err = lx_message_send_atomic(chip, &chip->rmh);
 737         spin_unlock_irqrestore(&chip->msg_lock, flags);
 738
 739         return err;
 740 }
 741
 742 int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
 743                     int *rstate)
 744 {
 745         int err;
 746         unsigned long flags;
 747
 748         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 749
 750         spin_lock_irqsave(&chip->msg_lock, flags);
 751         lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
 752
 753         chip->rmh.cmd[0] |= pipe_cmd;
 754
 755         err = lx_message_send_atomic(chip, &chip->rmh);
 756
 757         *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE;
 758
 759         spin_unlock_irqrestore(&chip->msg_lock, flags);
 760         return err;
 761 }
 762
 763 int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
 764                               u64 *r_bytepos)
 765 {
 766         int err;
 767         unsigned long flags;
 768
 769         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 770
 771         spin_lock_irqsave(&chip->msg_lock, flags);
 772         lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
 773
 774         chip->rmh.cmd[0] |= pipe_cmd;
 775
 776         err = lx_message_send_atomic(chip, &chip->rmh);
 777
 778         *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
 779                       << 32)         /* hi part */
 780                 + chip->rmh.stat[1]; /* lo part */
 781
 782         spin_unlock_irqrestore(&chip->msg_lock, flags);
 783         return err;
 784 }
 785
 786 /* low-level buffer handling */
 787 int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
 788                    u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
 789                    u32 *r_buffer_index)
 790 {
 791         int err;
 792         unsigned long flags;
 793
 794         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 795
 796         spin_lock_irqsave(&chip->msg_lock, flags);
 797         lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER);
 798
 799         chip->rmh.cmd[0] |= pipe_cmd;
 800         chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */
 801
 802         /* todo: pause request, circular buffer */
 803
 804         chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE;
 805         chip->rmh.cmd[2] = buf_address_lo;
 806
 807         if (buf_address_hi) {
 808                 chip->rmh.cmd_len = 4;
 809                 chip->rmh.cmd[3] = buf_address_hi;
 810                 chip->rmh.cmd[0] |= BF_64BITS_ADR;
 811         }
 812
 813         err = lx_message_send_atomic(chip, &chip->rmh);
 814
 815         if (err == 0) {
 816                 *r_buffer_index = chip->rmh.stat[0];
 817                 goto done;
 818         }
 819
 820         if (err == EB_RBUFFERS_TABLE_OVERFLOW)
 821                 dev_err(chip->card->dev,
 822                         "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n");
 823
 824         if (err == EB_INVALID_STREAM)
 825                 dev_err(chip->card->dev,
 826                         "lx_buffer_give EB_INVALID_STREAM\n");
 827
 828         if (err == EB_CMD_REFUSED)
 829                 dev_err(chip->card->dev,
 830                         "lx_buffer_give EB_CMD_REFUSED\n");
 831
 832  done:
 833         spin_unlock_irqrestore(&chip->msg_lock, flags);
 834         return err;
 835 }
 836
 837 int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
 838                    u32 *r_buffer_size)
 839 {
 840         int err;
 841         unsigned long flags;
 842
 843         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 844
 845         spin_lock_irqsave(&chip->msg_lock, flags);
 846         lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
 847
 848         chip->rmh.cmd[0] |= pipe_cmd;
 849         chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the
 850                                              * microblaze will seek for it */
 851
 852         err = lx_message_send_atomic(chip, &chip->rmh);
 853
 854         if (err == 0)
 855                 *r_buffer_size = chip->rmh.stat[0]  & MASK_DATA_SIZE;
 856
 857         spin_unlock_irqrestore(&chip->msg_lock, flags);
 858         return err;
 859 }
 860
 861 int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
 862                      u32 buffer_index)
 863 {
 864         int err;
 865         unsigned long flags;
 866
 867         u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
 868
 869         spin_lock_irqsave(&chip->msg_lock, flags);
 870         lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
 871
 872         chip->rmh.cmd[0] |= pipe_cmd;
 873         chip->rmh.cmd[0] |= buffer_index;
 874
 875         err = lx_message_send_atomic(chip, &chip->rmh);
 876
 877         spin_unlock_irqrestore(&chip->msg_lock, flags);
 878         return err;
 879 }
 880
 881
 882 /* low-level gain/peak handling
 883  *
 884  * \todo: can we unmute capture/playback channels independently?
 885  *
 886  * */
 887 int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute)
 888 {
 889         int err;
 890         unsigned long flags;
 891
 892         /* bit set to 1: channel muted */
 893         u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU;
 894
 895         spin_lock_irqsave(&chip->msg_lock, flags);
 896         lx_message_init(&chip->rmh, CMD_0D_SET_MUTE);
 897
 898         chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0);
 899
 900         chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32);        /* hi part */
 901         chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */
 902
 903         dev_dbg(chip->card->dev,
 904                 "mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1],
 905                    chip->rmh.cmd[2]);
 906
 907         err = lx_message_send_atomic(chip, &chip->rmh);
 908
 909         spin_unlock_irqrestore(&chip->msg_lock, flags);
 910         return err;
 911 }
 912
 913 static u32 peak_map[] = {
 914         0x00000109, /* -90.308dB */
 915         0x0000083B, /* -72.247dB */
 916         0x000020C4, /* -60.205dB */
 917         0x00008273, /* -48.030dB */
 918         0x00020756, /* -36.005dB */
 919         0x00040C37, /* -30.001dB */
 920         0x00081385, /* -24.002dB */
 921         0x00101D3F, /* -18.000dB */
 922         0x0016C310, /* -15.000dB */
 923         0x002026F2, /* -12.001dB */
 924         0x002D6A86, /* -9.000dB */
 925         0x004026E6, /* -6.004dB */
 926         0x005A9DF6, /* -3.000dB */
 927         0x0065AC8B, /* -2.000dB */
 928         0x00721481, /* -1.000dB */
 929         0x007FFFFF, /* FS */
 930 };
 931
 932 int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
 933                    u32 *r_levels)
 934 {
 935         int err = 0;
 936         unsigned long flags;
 937         int i;
 938         spin_lock_irqsave(&chip->msg_lock, flags);
 939
 940         for (i = 0; i < channels; i += 4) {
 941                 u32 s0, s1, s2, s3;
 942
 943                 lx_message_init(&chip->rmh, CMD_12_GET_PEAK);
 944                 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i);
 945
 946                 err = lx_message_send_atomic(chip, &chip->rmh);
 947
 948                 if (err == 0) {
 949                         s0 = peak_map[chip->rmh.stat[0] & 0x0F];
 950                         s1 = peak_map[(chip->rmh.stat[0] >>  4) & 0xf];
 951                         s2 = peak_map[(chip->rmh.stat[0] >>  8) & 0xf];
 952                         s3 = peak_map[(chip->rmh.stat[0] >>  12) & 0xf];
 953                 } else
 954                         s0 = s1 = s2 = s3 = 0;
 955
 956                 r_levels[0] = s0;
 957                 r_levels[1] = s1;
 958                 r_levels[2] = s2;
 959                 r_levels[3] = s3;
 960
 961                 r_levels += 4;
 962         }
 963
 964         spin_unlock_irqrestore(&chip->msg_lock, flags);
 965         return err;
 966 }
 967
 968 /* interrupt handling */
 969 #define PCX_IRQ_NONE 0
 970 #define IRQCS_ACTIVE_PCIDB      BIT(13)
 971 #define IRQCS_ENABLE_PCIIRQ     BIT(8)
 972 #define IRQCS_ENABLE_PCIDB      BIT(9)
 973
 974 static u32 lx_interrupt_test_ack(struct lx6464es *chip)
 975 {
 976         u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS);
 977
 978         /* Test if PCI Doorbell interrupt is active */
 979         if (irqcs & IRQCS_ACTIVE_PCIDB) {
 980                 u32 temp;
 981                 irqcs = PCX_IRQ_NONE;
 982
 983                 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) {
 984                         /* RAZ interrupt */
 985                         irqcs |= temp;
 986                         lx_plx_reg_write(chip, ePLX_L2PCIDB, temp);
 987                 }
 988
 989                 return irqcs;
 990         }
 991         return PCX_IRQ_NONE;
 992 }
 993
 994 static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc,
 995                             int *r_async_pending, int *r_async_escmd)
 996 {
 997         u32 irq_async;
 998         u32 irqsrc = lx_interrupt_test_ack(chip);
 999
1000         if (irqsrc == PCX_IRQ_NONE)
1001                 return 0;
1002
1003         *r_irqsrc = irqsrc;
1004
1005         irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response
1006                                                      * (set by xilinx) + EOB */
1007
1008         if (irq_async & MASK_SYS_STATUS_ESA) {
1009                 irq_async &= ~MASK_SYS_STATUS_ESA;
1010                 *r_async_escmd = 1;
1011         }
1012
1013         if (irq_async) {
1014                 /* dev_dbg(chip->card->dev, "interrupt: async event pending\n"); */
1015                 *r_async_pending = 1;
1016         }
1017
1018         return 1;
1019 }
1020
1021 static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc,
1022                                             int *r_freq_changed,
1023                                             u64 *r_notified_in_pipe_mask,
1024                                             u64 *r_notified_out_pipe_mask)
1025 {
1026         int err;
1027         u32 stat[9];            /* answer from CMD_04_GET_EVENT */
1028
1029         /* On peut optimiser pour ne pas lire les evenements vides
1030          * les mots de rÃ\83Â©ponse sont dans l'ordre suivant :
1031          * Stat[0]      mot de status gÃ\83Â©nÃ\83Â©ral
1032          * Stat[1]      fin de buffer OUT pF
1033          * Stat[2]      fin de buffer OUT pf
1034          * Stat[3]      fin de buffer IN pF
1035          * Stat[4]      fin de buffer IN pf
1036          * Stat[5]      underrun poid fort
1037          * Stat[6]      underrun poid faible
1038          * Stat[7]      overrun poid fort
1039          * Stat[8]      overrun poid faible
1040          * */
1041
1042         u64 orun_mask;
1043         u64 urun_mask;
1044 #if 0
1045         int has_underrun   = (irqsrc & MASK_SYS_STATUS_URUN) ? 1 : 0;
1046         int has_overrun    = (irqsrc & MASK_SYS_STATUS_ORUN) ? 1 : 0;
1047 #endif
1048         int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0;
1049         int eb_pending_in  = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0;
1050
1051         *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0;
1052
1053         err = lx_dsp_read_async_events(chip, stat);
1054         if (err < 0)
1055                 return err;
1056
1057         if (eb_pending_in) {
1058                 *r_notified_in_pipe_mask = ((u64)stat[3] << 32)
1059                         + stat[4];
1060                 dev_dbg(chip->card->dev, "interrupt: EOBI pending %llx\n",
1061                             *r_notified_in_pipe_mask);
1062         }
1063         if (eb_pending_out) {
1064                 *r_notified_out_pipe_mask = ((u64)stat[1] << 32)
1065                         + stat[2];
1066                 dev_dbg(chip->card->dev, "interrupt: EOBO pending %llx\n",
1067                             *r_notified_out_pipe_mask);
1068         }
1069
1070         orun_mask = ((u64)stat[7] << 32) + stat[8];
1071         urun_mask = ((u64)stat[5] << 32) + stat[6];
1072
1073         /* todo: handle xrun notification */
1074
1075         return err;
1076 }
1077
1078 static int lx_interrupt_request_new_buffer(struct lx6464es *chip,
1079                                            struct lx_stream *lx_stream)
1080 {
1081         struct snd_pcm_substream *substream = lx_stream->stream;
1082         const unsigned int is_capture = lx_stream->is_capture;
1083         int err;
1084         unsigned long flags;
1085
1086         const u32 channels = substream->runtime->channels;
1087         const u32 bytes_per_frame = channels * 3;
1088         const u32 period_size = substream->runtime->period_size;
1089         const u32 period_bytes = period_size * bytes_per_frame;
1090         const u32 pos = lx_stream->frame_pos;
1091         const u32 next_pos = ((pos+1) == substream->runtime->periods) ?
1092                 0 : pos + 1;
1093
1094         dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes;
1095         u32 buf_hi = 0;
1096         u32 buf_lo = 0;
1097         u32 buffer_index = 0;
1098
1099         u32 needed, freed;
1100         u32 size_array[MAX_STREAM_BUFFER];
1101
1102         dev_dbg(chip->card->dev, "->lx_interrupt_request_new_buffer\n");
1103
1104         spin_lock_irqsave(&chip->lock, flags);
1105
1106         err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array);
1107         dev_dbg(chip->card->dev,
1108                 "interrupt: needed %d, freed %d\n", needed, freed);
1109
1110         unpack_pointer(buf, &buf_lo, &buf_hi);
1111         err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi,
1112                              &buffer_index);
1113         dev_dbg(chip->card->dev,
1114                 "interrupt: gave buffer index %x on 0x%lx (%d bytes)\n",
1115                     buffer_index, (unsigned long)buf, period_bytes);
1116
1117         lx_stream->frame_pos = next_pos;
1118         spin_unlock_irqrestore(&chip->lock, flags);
1119
1120         return err;
1121 }
1122
1123 void lx_tasklet_playback(unsigned long data)
1124 {
1125         struct lx6464es *chip = (struct lx6464es *)data;
1126         struct lx_stream *lx_stream = &chip->playback_stream;
1127         int err;
1128
1129         dev_dbg(chip->card->dev, "->lx_tasklet_playback\n");
1130
1131         err = lx_interrupt_request_new_buffer(chip, lx_stream);
1132         if (err < 0)
1133                 dev_err(chip->card->dev,
1134                            "cannot request new buffer for playback\n");
1135
1136         snd_pcm_period_elapsed(lx_stream->stream);
1137 }
1138
1139 void lx_tasklet_capture(unsigned long data)
1140 {
1141         struct lx6464es *chip = (struct lx6464es *)data;
1142         struct lx_stream *lx_stream = &chip->capture_stream;
1143         int err;
1144
1145         dev_dbg(chip->card->dev, "->lx_tasklet_capture\n");
1146         err = lx_interrupt_request_new_buffer(chip, lx_stream);
1147         if (err < 0)
1148                 dev_err(chip->card->dev,
1149                            "cannot request new buffer for capture\n");
1150
1151         snd_pcm_period_elapsed(lx_stream->stream);
1152 }
1153
1154
1155
1156 static int lx_interrupt_handle_audio_transfer(struct lx6464es *chip,
1157                                               u64 notified_in_pipe_mask,
1158                                               u64 notified_out_pipe_mask)
1159 {
1160         int err = 0;
1161
1162         if (notified_in_pipe_mask) {
1163                 dev_dbg(chip->card->dev,
1164                         "requesting audio transfer for capture\n");
1165                 tasklet_hi_schedule(&chip->tasklet_capture);
1166         }
1167
1168         if (notified_out_pipe_mask) {
1169                 dev_dbg(chip->card->dev,
1170                         "requesting audio transfer for playback\n");
1171                 tasklet_hi_schedule(&chip->tasklet_playback);
1172         }
1173
1174         return err;
1175 }
1176
1177
1178 irqreturn_t lx_interrupt(int irq, void *dev_id)
1179 {
1180         struct lx6464es *chip = dev_id;
1181         int async_pending, async_escmd;
1182         u32 irqsrc;
1183
1184         spin_lock(&chip->lock);
1185
1186         dev_dbg(chip->card->dev,
1187                 "**************************************************\n");
1188
1189         if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) {
1190                 spin_unlock(&chip->lock);
1191                 dev_dbg(chip->card->dev, "IRQ_NONE\n");
1192                 return IRQ_NONE; /* this device did not cause the interrupt */
1193         }
1194
1195         if (irqsrc & MASK_SYS_STATUS_CMD_DONE)
1196                 goto exit;
1197
1198 #if 0
1199         if (irqsrc & MASK_SYS_STATUS_EOBI)
1200                 dev_dbg(chip->card->dev, "interrupt: EOBI\n");
1201
1202         if (irqsrc & MASK_SYS_STATUS_EOBO)
1203                 dev_dbg(chip->card->dev, "interrupt: EOBO\n");
1204
1205         if (irqsrc & MASK_SYS_STATUS_URUN)
1206                 dev_dbg(chip->card->dev, "interrupt: URUN\n");
1207
1208         if (irqsrc & MASK_SYS_STATUS_ORUN)
1209                 dev_dbg(chip->card->dev, "interrupt: ORUN\n");
1210 #endif
1211
1212         if (async_pending) {
1213                 u64 notified_in_pipe_mask = 0;
1214                 u64 notified_out_pipe_mask = 0;
1215                 int freq_changed;
1216                 int err;
1217
1218                 /* handle async events */
1219                 err = lx_interrupt_handle_async_events(chip, irqsrc,
1220                                                        &freq_changed,
1221                                                        &notified_in_pipe_mask,
1222                                                        &notified_out_pipe_mask);
1223                 if (err)
1224                         dev_err(chip->card->dev,
1225                                    "error handling async events\n");
1226
1227                 err = lx_interrupt_handle_audio_transfer(chip,
1228                                                          notified_in_pipe_mask,
1229                                                          notified_out_pipe_mask
1230                         );
1231                 if (err)
1232                         dev_err(chip->card->dev,
1233                                    "error during audio transfer\n");
1234         }
1235
1236         if (async_escmd) {
1237 #if 0
1238                 /* backdoor for ethersound commands
1239                  *
1240                  * for now, we do not need this
1241                  *
1242                  * */
1243
1244                 dev_dbg(chip->card->dev, "interrupt requests escmd handling\n");
1245 #endif
1246         }
1247
1248 exit:
1249         spin_unlock(&chip->lock);
1250         return IRQ_HANDLED;     /* this device caused the interrupt */
1251 }
1252
1253
1254 static void lx_irq_set(struct lx6464es *chip, int enable)
1255 {
1256         u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS);
1257
1258         /* enable/disable interrupts
1259          *
1260          * Set the Doorbell and PCI interrupt enable bits
1261          *
1262          * */
1263         if (enable)
1264                 reg |=  (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1265         else
1266                 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1267         lx_plx_reg_write(chip, ePLX_IRQCS, reg);
1268 }
1269
1270 void lx_irq_enable(struct lx6464es *chip)
1271 {
1272         dev_dbg(chip->card->dev, "->lx_irq_enable\n");
1273         lx_irq_set(chip, 1);
1274 }
1275
1276 void lx_irq_disable(struct lx6464es *chip)
1277 {
1278         dev_dbg(chip->card->dev, "->lx_irq_disable\n");
1279         lx_irq_set(chip, 0);
1280 }