3 * ALSA driver for the digigram lx6464es interface
6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
21 * Boston, MA 02111-1307, USA.
25 /* #define RMH_DEBUG 1 */
27 #include <linux/bitops.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/delay.h>
35 /* low-level register access */
37 static const unsigned long dsp_port_offsets[] = {
70 static void __iomem *lx_dsp_register(struct lx6464es *chip, int port)
72 void __iomem *base_address = chip->port_dsp_bar;
73 return base_address + dsp_port_offsets[port]*4;
76 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port)
78 void __iomem *address = lx_dsp_register(chip, port);
79 return ioread32(address);
82 static void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data,
85 u32 __iomem *address = lx_dsp_register(chip, port);
88 /* we cannot use memcpy_fromio */
89 for (i = 0; i != len; ++i)
90 data[i] = ioread32(address + i);
94 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data)
96 void __iomem *address = lx_dsp_register(chip, port);
97 iowrite32(data, address);
100 static void lx_dsp_reg_writebuf(struct lx6464es *chip, int port,
101 const u32 *data, u32 len)
103 u32 __iomem *address = lx_dsp_register(chip, port);
106 /* we cannot use memcpy_to */
107 for (i = 0; i != len; ++i)
108 iowrite32(data[i], address + i);
112 static const unsigned long plx_port_offsets[] = {
127 static void __iomem *lx_plx_register(struct lx6464es *chip, int port)
129 void __iomem *base_address = chip->port_plx_remapped;
130 return base_address + plx_port_offsets[port];
133 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port)
135 void __iomem *address = lx_plx_register(chip, port);
136 return ioread32(address);
139 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data)
141 void __iomem *address = lx_plx_register(chip, port);
142 iowrite32(data, address);
147 #ifdef CONFIG_SND_DEBUG
148 #define CMD_NAME(a) a
150 #define CMD_NAME(a) NULL
153 #define Reg_CSM_MR 0x00000002
154 #define Reg_CSM_MC 0x00000001
156 struct dsp_cmd_info {
157 u32 dcCodeOp; /* Op Code of the command (usually 1st 24-bits
159 u16 dcCmdLength; /* Command length in words of 24 bits.*/
160 u16 dcStatusType; /* Status type: 0 for fixed length, 1 for
162 u16 dcStatusLength; /* Status length (if fixed).*/
167 Initialization and control data for the Microblaze interface
169 the opcode field of the command set at the proper offset
171 the number of command words
173 offset in the status registers: 0 means that the return value may be
174 different from 0, and must be read
176 the number of status words (in addition to the return value)
179 static struct dsp_cmd_info dsp_commands[] =
181 { (CMD_00_INFO_DEBUG << OPCODE_OFFSET) , 1 /*custom*/
182 , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") },
183 { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET) , 1 /**/
184 , 1 , 2 /**/ , CMD_NAME("GET_SYS_CFG") },
185 { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET) , 1 /**/
186 , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") },
187 { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET) , 1 /**/
188 , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") },
189 { (CMD_04_GET_EVENT << OPCODE_OFFSET) , 1 /**/
190 , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") },
191 { (CMD_05_GET_PIPES << OPCODE_OFFSET) , 1 /**/
192 , 1 , 2 /*up to 4*/ , CMD_NAME("GET_PIPES") },
193 { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET) , 1 /**/
194 , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") },
195 { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET) , 1 /**/
196 , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") },
197 { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET) , 1 /**/
198 , 1 , MAX_STREAM_BUFFER , CMD_NAME("ASK_BUFFERS") },
199 { (CMD_09_STOP_PIPE << OPCODE_OFFSET) , 1 /**/
200 , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") },
201 { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET) , 1 /**/
202 , 1 , 1 /*up to 2*/ , CMD_NAME("GET_PIPE_SPL_COUNT") },
203 { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET) , 1 /*up to 5*/
204 , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") },
205 { (CMD_0C_DEF_STREAM << OPCODE_OFFSET) , 1 /*up to 4*/
206 , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") },
207 { (CMD_0D_SET_MUTE << OPCODE_OFFSET) , 3 /**/
208 , 1 , 0 /**/ , CMD_NAME("SET_MUTE") },
209 { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET) , 1/**/
210 , 1 , 2 /**/ , CMD_NAME("GET_STREAM_SPL_COUNT") },
211 { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET) , 3 /*up to 4*/
212 , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") },
213 { (CMD_10_GET_BUFFER << OPCODE_OFFSET) , 1 /**/
214 , 1 , 4 /**/ , CMD_NAME("GET_BUFFER") },
215 { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET) , 1 /**/
216 , 1 , 1 /*up to 4*/ , CMD_NAME("CANCEL_BUFFER") },
217 { (CMD_12_GET_PEAK << OPCODE_OFFSET) , 1 /**/
218 , 1 , 1 /**/ , CMD_NAME("GET_PEAK") },
219 { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET) , 1 /**/
220 , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") },
223 static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd)
225 snd_BUG_ON(cmd >= CMD_14_INVALID);
227 rmh->cmd[0] = dsp_commands[cmd].dcCodeOp;
228 rmh->cmd_len = dsp_commands[cmd].dcCmdLength;
229 rmh->stat_len = dsp_commands[cmd].dcStatusLength;
230 rmh->dsp_stat = dsp_commands[cmd].dcStatusType;
232 memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32));
234 #ifdef CONFIG_SND_DEBUG
235 memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32));
243 #define LXRMH "lx6464es rmh: "
244 static void lx_message_dump(struct lx_rmh *rmh)
246 u8 idx = rmh->cmd_idx;
249 snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName);
251 for (i = 0; i != rmh->cmd_len; ++i)
252 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]);
254 for (i = 0; i != rmh->stat_len; ++i)
255 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]);
259 static inline void lx_message_dump(struct lx_rmh *rmh)
265 /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */
266 #define XILINX_TIMEOUT_MS 40
267 #define XILINX_POLL_NO_SLEEP 100
268 #define XILINX_POLL_ITERATIONS 150
271 static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh)
273 u32 reg = ED_DSP_TIMED_OUT;
276 if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) {
277 dev_err(chip->card->dev, "PIOSendMessage eReg_CSM %x\n", reg);
282 lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len);
284 /* MicoBlaze gogogo */
285 lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC);
287 /* wait for device to answer */
288 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) {
289 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) {
290 if (rmh->dsp_stat == 0)
291 reg = lx_dsp_reg_read(chip, eReg_CRM1);
294 goto polling_successful;
298 dev_warn(chip->card->dev, "TIMEOUT lx_message_send_atomic! "
302 if ((reg & ERROR_VALUE) == 0) {
305 snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1));
306 lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat,
310 dev_err(chip->card->dev, "rmh error: %08x\n", reg);
312 /* clear Reg_CSM_MR */
313 lx_dsp_reg_write(chip, eReg_CSM, 0);
316 case ED_DSP_TIMED_OUT:
317 dev_warn(chip->card->dev, "lx_message_send: dsp timeout\n");
321 dev_warn(chip->card->dev, "lx_message_send: dsp crashed\n");
325 lx_message_dump(rmh);
331 /* low-level dsp access */
332 int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version)
337 spin_lock_irqsave(&chip->msg_lock, flags);
339 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
340 ret = lx_message_send_atomic(chip, &chip->rmh);
342 *rdsp_version = chip->rmh.stat[1];
343 spin_unlock_irqrestore(&chip->msg_lock, flags);
347 int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq)
355 spin_lock_irqsave(&chip->msg_lock, flags);
357 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG);
358 ret = lx_message_send_atomic(chip, &chip->rmh);
361 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET;
362 freq = freq_raw & XES_FREQ_COUNT8_MASK;
364 if ((freq < XES_FREQ_COUNT8_48_MAX) ||
365 (freq > XES_FREQ_COUNT8_44_MIN))
366 frequency = 0; /* unknown */
367 else if (freq >= XES_FREQ_COUNT8_44_MAX)
373 spin_unlock_irqrestore(&chip->msg_lock, flags);
375 *rfreq = frequency * chip->freq_ratio;
380 int lx_dsp_get_mac(struct lx6464es *chip)
384 macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF;
385 maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF;
387 /* todo: endianess handling */
388 chip->mac_address[5] = ((u8 *)(&maclsb))[0];
389 chip->mac_address[4] = ((u8 *)(&maclsb))[1];
390 chip->mac_address[3] = ((u8 *)(&maclsb))[2];
391 chip->mac_address[2] = ((u8 *)(&macmsb))[0];
392 chip->mac_address[1] = ((u8 *)(&macmsb))[1];
393 chip->mac_address[0] = ((u8 *)(&macmsb))[2];
399 int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran)
404 spin_lock_irqsave(&chip->msg_lock, flags);
406 lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY);
407 chip->rmh.cmd[0] |= gran;
409 ret = lx_message_send_atomic(chip, &chip->rmh);
410 spin_unlock_irqrestore(&chip->msg_lock, flags);
414 int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data)
419 spin_lock_irqsave(&chip->msg_lock, flags);
421 lx_message_init(&chip->rmh, CMD_04_GET_EVENT);
422 chip->rmh.stat_len = 9; /* we don't necessarily need the full length */
424 ret = lx_message_send_atomic(chip, &chip->rmh);
427 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32));
429 spin_unlock_irqrestore(&chip->msg_lock, flags);
433 #define PIPE_INFO_TO_CMD(capture, pipe) \
434 ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET)
438 /* low-level pipe handling */
439 int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture,
445 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
447 spin_lock_irqsave(&chip->msg_lock, flags);
448 lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE);
450 chip->rmh.cmd[0] |= pipe_cmd;
451 chip->rmh.cmd[0] |= channels;
453 err = lx_message_send_atomic(chip, &chip->rmh);
454 spin_unlock_irqrestore(&chip->msg_lock, flags);
457 dev_err(chip->card->dev, "could not allocate pipe\n");
462 int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture)
467 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
469 spin_lock_irqsave(&chip->msg_lock, flags);
470 lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE);
472 chip->rmh.cmd[0] |= pipe_cmd;
474 err = lx_message_send_atomic(chip, &chip->rmh);
475 spin_unlock_irqrestore(&chip->msg_lock, flags);
480 int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture,
481 u32 *r_needed, u32 *r_freed, u32 *size_array)
486 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
488 #ifdef CONFIG_SND_DEBUG
490 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER);
496 spin_lock_irqsave(&chip->msg_lock, flags);
497 lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS);
499 chip->rmh.cmd[0] |= pipe_cmd;
501 err = lx_message_send_atomic(chip, &chip->rmh);
505 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
506 u32 stat = chip->rmh.stat[i];
507 if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) {
511 size_array[i] = stat & MASK_DATA_SIZE;
512 } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET))
519 dev_dbg(chip->card->dev,
520 "CMD_08_ASK_BUFFERS: needed %d, freed %d\n",
521 *r_needed, *r_freed);
522 for (i = 0; i < MAX_STREAM_BUFFER; ++i) {
523 for (i = 0; i != chip->rmh.stat_len; ++i)
524 dev_dbg(chip->card->dev,
525 " stat[%d]: %x, %x\n", i,
527 chip->rmh.stat[i] & MASK_DATA_SIZE);
532 spin_unlock_irqrestore(&chip->msg_lock, flags);
537 int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture)
542 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
544 spin_lock_irqsave(&chip->msg_lock, flags);
545 lx_message_init(&chip->rmh, CMD_09_STOP_PIPE);
547 chip->rmh.cmd[0] |= pipe_cmd;
549 err = lx_message_send_atomic(chip, &chip->rmh);
551 spin_unlock_irqrestore(&chip->msg_lock, flags);
555 static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture)
560 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
562 spin_lock_irqsave(&chip->msg_lock, flags);
563 lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE);
565 chip->rmh.cmd[0] |= pipe_cmd;
567 err = lx_message_send_atomic(chip, &chip->rmh);
569 spin_unlock_irqrestore(&chip->msg_lock, flags);
574 int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture)
578 err = lx_pipe_wait_for_idle(chip, pipe, is_capture);
582 err = lx_pipe_toggle_state(chip, pipe, is_capture);
587 int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture)
591 err = lx_pipe_wait_for_start(chip, pipe, is_capture);
595 err = lx_pipe_toggle_state(chip, pipe, is_capture);
601 int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture,
607 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
609 spin_lock_irqsave(&chip->msg_lock, flags);
610 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
612 chip->rmh.cmd[0] |= pipe_cmd;
613 chip->rmh.stat_len = 2; /* need all words here! */
615 err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */
618 dev_err(chip->card->dev,
619 "could not query pipe's sample count\n");
621 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
623 + chip->rmh.stat[1]; /* lo part */
626 spin_unlock_irqrestore(&chip->msg_lock, flags);
630 int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate)
635 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
637 spin_lock_irqsave(&chip->msg_lock, flags);
638 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT);
640 chip->rmh.cmd[0] |= pipe_cmd;
642 err = lx_message_send_atomic(chip, &chip->rmh);
645 dev_err(chip->card->dev, "could not query pipe's state\n");
647 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F;
649 spin_unlock_irqrestore(&chip->msg_lock, flags);
653 static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe,
654 int is_capture, u16 state)
658 /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms:
660 for (i = 0; i != 50; ++i) {
662 int err = lx_pipe_state(chip, pipe, is_capture, ¤t_state);
667 if (current_state == state)
676 int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture)
678 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN);
681 int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture)
683 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE);
686 /* low-level stream handling */
687 int lx_stream_set_state(struct lx6464es *chip, u32 pipe,
688 int is_capture, enum stream_state_t state)
693 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
695 spin_lock_irqsave(&chip->msg_lock, flags);
696 lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE);
698 chip->rmh.cmd[0] |= pipe_cmd;
699 chip->rmh.cmd[0] |= state;
701 err = lx_message_send_atomic(chip, &chip->rmh);
702 spin_unlock_irqrestore(&chip->msg_lock, flags);
707 int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime,
708 u32 pipe, int is_capture)
713 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
715 u32 channels = runtime->channels;
717 if (runtime->channels != channels)
718 dev_err(chip->card->dev, "channel count mismatch: %d vs %d",
719 runtime->channels, channels);
721 spin_lock_irqsave(&chip->msg_lock, flags);
722 lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM);
724 chip->rmh.cmd[0] |= pipe_cmd;
726 if (runtime->sample_bits == 16)
728 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET);
730 if (snd_pcm_format_little_endian(runtime->format))
731 /* little endian/intel format */
732 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET);
734 chip->rmh.cmd[0] |= channels-1;
736 err = lx_message_send_atomic(chip, &chip->rmh);
737 spin_unlock_irqrestore(&chip->msg_lock, flags);
742 int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture,
748 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
750 spin_lock_irqsave(&chip->msg_lock, flags);
751 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
753 chip->rmh.cmd[0] |= pipe_cmd;
755 err = lx_message_send_atomic(chip, &chip->rmh);
757 *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE;
759 spin_unlock_irqrestore(&chip->msg_lock, flags);
763 int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture,
769 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
771 spin_lock_irqsave(&chip->msg_lock, flags);
772 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT);
774 chip->rmh.cmd[0] |= pipe_cmd;
776 err = lx_message_send_atomic(chip, &chip->rmh);
778 *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI)
780 + chip->rmh.stat[1]; /* lo part */
782 spin_unlock_irqrestore(&chip->msg_lock, flags);
786 /* low-level buffer handling */
787 int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture,
788 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi,
794 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
796 spin_lock_irqsave(&chip->msg_lock, flags);
797 lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER);
799 chip->rmh.cmd[0] |= pipe_cmd;
800 chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */
802 /* todo: pause request, circular buffer */
804 chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE;
805 chip->rmh.cmd[2] = buf_address_lo;
807 if (buf_address_hi) {
808 chip->rmh.cmd_len = 4;
809 chip->rmh.cmd[3] = buf_address_hi;
810 chip->rmh.cmd[0] |= BF_64BITS_ADR;
813 err = lx_message_send_atomic(chip, &chip->rmh);
816 *r_buffer_index = chip->rmh.stat[0];
820 if (err == EB_RBUFFERS_TABLE_OVERFLOW)
821 dev_err(chip->card->dev,
822 "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n");
824 if (err == EB_INVALID_STREAM)
825 dev_err(chip->card->dev,
826 "lx_buffer_give EB_INVALID_STREAM\n");
828 if (err == EB_CMD_REFUSED)
829 dev_err(chip->card->dev,
830 "lx_buffer_give EB_CMD_REFUSED\n");
833 spin_unlock_irqrestore(&chip->msg_lock, flags);
837 int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture,
843 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
845 spin_lock_irqsave(&chip->msg_lock, flags);
846 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
848 chip->rmh.cmd[0] |= pipe_cmd;
849 chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the
850 * microblaze will seek for it */
852 err = lx_message_send_atomic(chip, &chip->rmh);
855 *r_buffer_size = chip->rmh.stat[0] & MASK_DATA_SIZE;
857 spin_unlock_irqrestore(&chip->msg_lock, flags);
861 int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture,
867 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe);
869 spin_lock_irqsave(&chip->msg_lock, flags);
870 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER);
872 chip->rmh.cmd[0] |= pipe_cmd;
873 chip->rmh.cmd[0] |= buffer_index;
875 err = lx_message_send_atomic(chip, &chip->rmh);
877 spin_unlock_irqrestore(&chip->msg_lock, flags);
882 /* low-level gain/peak handling
884 * \todo: can we unmute capture/playback channels independently?
887 int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute)
892 /* bit set to 1: channel muted */
893 u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU;
895 spin_lock_irqsave(&chip->msg_lock, flags);
896 lx_message_init(&chip->rmh, CMD_0D_SET_MUTE);
898 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0);
900 chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32); /* hi part */
901 chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */
903 dev_dbg(chip->card->dev,
904 "mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1],
907 err = lx_message_send_atomic(chip, &chip->rmh);
909 spin_unlock_irqrestore(&chip->msg_lock, flags);
913 static u32 peak_map[] = {
914 0x00000109, /* -90.308dB */
915 0x0000083B, /* -72.247dB */
916 0x000020C4, /* -60.205dB */
917 0x00008273, /* -48.030dB */
918 0x00020756, /* -36.005dB */
919 0x00040C37, /* -30.001dB */
920 0x00081385, /* -24.002dB */
921 0x00101D3F, /* -18.000dB */
922 0x0016C310, /* -15.000dB */
923 0x002026F2, /* -12.001dB */
924 0x002D6A86, /* -9.000dB */
925 0x004026E6, /* -6.004dB */
926 0x005A9DF6, /* -3.000dB */
927 0x0065AC8B, /* -2.000dB */
928 0x00721481, /* -1.000dB */
932 int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels,
938 spin_lock_irqsave(&chip->msg_lock, flags);
940 for (i = 0; i < channels; i += 4) {
943 lx_message_init(&chip->rmh, CMD_12_GET_PEAK);
944 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i);
946 err = lx_message_send_atomic(chip, &chip->rmh);
949 s0 = peak_map[chip->rmh.stat[0] & 0x0F];
950 s1 = peak_map[(chip->rmh.stat[0] >> 4) & 0xf];
951 s2 = peak_map[(chip->rmh.stat[0] >> 8) & 0xf];
952 s3 = peak_map[(chip->rmh.stat[0] >> 12) & 0xf];
954 s0 = s1 = s2 = s3 = 0;
964 spin_unlock_irqrestore(&chip->msg_lock, flags);
968 /* interrupt handling */
969 #define PCX_IRQ_NONE 0
970 #define IRQCS_ACTIVE_PCIDB BIT(13)
971 #define IRQCS_ENABLE_PCIIRQ BIT(8)
972 #define IRQCS_ENABLE_PCIDB BIT(9)
974 static u32 lx_interrupt_test_ack(struct lx6464es *chip)
976 u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS);
978 /* Test if PCI Doorbell interrupt is active */
979 if (irqcs & IRQCS_ACTIVE_PCIDB) {
981 irqcs = PCX_IRQ_NONE;
983 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) {
986 lx_plx_reg_write(chip, ePLX_L2PCIDB, temp);
994 static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc,
995 int *r_async_pending, int *r_async_escmd)
998 u32 irqsrc = lx_interrupt_test_ack(chip);
1000 if (irqsrc == PCX_IRQ_NONE)
1005 irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response
1006 * (set by xilinx) + EOB */
1008 if (irq_async & MASK_SYS_STATUS_ESA) {
1009 irq_async &= ~MASK_SYS_STATUS_ESA;
1014 /* dev_dbg(chip->card->dev, "interrupt: async event pending\n"); */
1015 *r_async_pending = 1;
1021 static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc,
1022 int *r_freq_changed,
1023 u64 *r_notified_in_pipe_mask,
1024 u64 *r_notified_out_pipe_mask)
1027 u32 stat[9]; /* answer from CMD_04_GET_EVENT */
1029 /* On peut optimiser pour ne pas lire les evenements vides
1030 * les mots de rÃ
\83©ponse sont dans l'ordre suivant :
1031 * Stat[0] mot de status gÃ
\83©nÃ
\83©ral
1032 * Stat[1] fin de buffer OUT pF
1033 * Stat[2] fin de buffer OUT pf
1034 * Stat[3] fin de buffer IN pF
1035 * Stat[4] fin de buffer IN pf
1036 * Stat[5] underrun poid fort
1037 * Stat[6] underrun poid faible
1038 * Stat[7] overrun poid fort
1039 * Stat[8] overrun poid faible
1044 int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0;
1045 int eb_pending_in = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0;
1047 *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0;
1049 err = lx_dsp_read_async_events(chip, stat);
1053 if (eb_pending_in) {
1054 *r_notified_in_pipe_mask = ((u64)stat[3] << 32)
1056 dev_dbg(chip->card->dev, "interrupt: EOBI pending %llx\n",
1057 *r_notified_in_pipe_mask);
1059 if (eb_pending_out) {
1060 *r_notified_out_pipe_mask = ((u64)stat[1] << 32)
1062 dev_dbg(chip->card->dev, "interrupt: EOBO pending %llx\n",
1063 *r_notified_out_pipe_mask);
1066 orun_mask = ((u64)stat[7] << 32) + stat[8];
1067 urun_mask = ((u64)stat[5] << 32) + stat[6];
1069 /* todo: handle xrun notification */
1074 static int lx_interrupt_request_new_buffer(struct lx6464es *chip,
1075 struct lx_stream *lx_stream)
1077 struct snd_pcm_substream *substream = lx_stream->stream;
1078 const unsigned int is_capture = lx_stream->is_capture;
1080 unsigned long flags;
1082 const u32 channels = substream->runtime->channels;
1083 const u32 bytes_per_frame = channels * 3;
1084 const u32 period_size = substream->runtime->period_size;
1085 const u32 period_bytes = period_size * bytes_per_frame;
1086 const u32 pos = lx_stream->frame_pos;
1087 const u32 next_pos = ((pos+1) == substream->runtime->periods) ?
1090 dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes;
1093 u32 buffer_index = 0;
1096 u32 size_array[MAX_STREAM_BUFFER];
1098 dev_dbg(chip->card->dev, "->lx_interrupt_request_new_buffer\n");
1100 spin_lock_irqsave(&chip->lock, flags);
1102 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array);
1103 dev_dbg(chip->card->dev,
1104 "interrupt: needed %d, freed %d\n", needed, freed);
1106 unpack_pointer(buf, &buf_lo, &buf_hi);
1107 err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi,
1109 dev_dbg(chip->card->dev,
1110 "interrupt: gave buffer index %x on 0x%lx (%d bytes)\n",
1111 buffer_index, (unsigned long)buf, period_bytes);
1113 lx_stream->frame_pos = next_pos;
1114 spin_unlock_irqrestore(&chip->lock, flags);
1119 void lx_tasklet_playback(unsigned long data)
1121 struct lx6464es *chip = (struct lx6464es *)data;
1122 struct lx_stream *lx_stream = &chip->playback_stream;
1125 dev_dbg(chip->card->dev, "->lx_tasklet_playback\n");
1127 err = lx_interrupt_request_new_buffer(chip, lx_stream);
1129 dev_err(chip->card->dev,
1130 "cannot request new buffer for playback\n");
1132 snd_pcm_period_elapsed(lx_stream->stream);
1135 void lx_tasklet_capture(unsigned long data)
1137 struct lx6464es *chip = (struct lx6464es *)data;
1138 struct lx_stream *lx_stream = &chip->capture_stream;
1141 dev_dbg(chip->card->dev, "->lx_tasklet_capture\n");
1142 err = lx_interrupt_request_new_buffer(chip, lx_stream);
1144 dev_err(chip->card->dev,
1145 "cannot request new buffer for capture\n");
1147 snd_pcm_period_elapsed(lx_stream->stream);
1152 static int lx_interrupt_handle_audio_transfer(struct lx6464es *chip,
1153 u64 notified_in_pipe_mask,
1154 u64 notified_out_pipe_mask)
1158 if (notified_in_pipe_mask) {
1159 dev_dbg(chip->card->dev,
1160 "requesting audio transfer for capture\n");
1161 tasklet_hi_schedule(&chip->tasklet_capture);
1164 if (notified_out_pipe_mask) {
1165 dev_dbg(chip->card->dev,
1166 "requesting audio transfer for playback\n");
1167 tasklet_hi_schedule(&chip->tasklet_playback);
1174 irqreturn_t lx_interrupt(int irq, void *dev_id)
1176 struct lx6464es *chip = dev_id;
1177 int async_pending, async_escmd;
1180 spin_lock(&chip->lock);
1182 dev_dbg(chip->card->dev,
1183 "**************************************************\n");
1185 if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) {
1186 spin_unlock(&chip->lock);
1187 dev_dbg(chip->card->dev, "IRQ_NONE\n");
1188 return IRQ_NONE; /* this device did not cause the interrupt */
1191 if (irqsrc & MASK_SYS_STATUS_CMD_DONE)
1195 if (irqsrc & MASK_SYS_STATUS_EOBI)
1196 dev_dbg(chip->card->dev, "interrupt: EOBI\n");
1198 if (irqsrc & MASK_SYS_STATUS_EOBO)
1199 dev_dbg(chip->card->dev, "interrupt: EOBO\n");
1201 if (irqsrc & MASK_SYS_STATUS_URUN)
1202 dev_dbg(chip->card->dev, "interrupt: URUN\n");
1204 if (irqsrc & MASK_SYS_STATUS_ORUN)
1205 dev_dbg(chip->card->dev, "interrupt: ORUN\n");
1208 if (async_pending) {
1209 u64 notified_in_pipe_mask = 0;
1210 u64 notified_out_pipe_mask = 0;
1214 /* handle async events */
1215 err = lx_interrupt_handle_async_events(chip, irqsrc,
1217 ¬ified_in_pipe_mask,
1218 ¬ified_out_pipe_mask);
1220 dev_err(chip->card->dev,
1221 "error handling async events\n");
1223 err = lx_interrupt_handle_audio_transfer(chip,
1224 notified_in_pipe_mask,
1225 notified_out_pipe_mask
1228 dev_err(chip->card->dev,
1229 "error during audio transfer\n");
1234 /* backdoor for ethersound commands
1236 * for now, we do not need this
1240 dev_dbg(chip->card->dev, "interrupt requests escmd handling\n");
1245 spin_unlock(&chip->lock);
1246 return IRQ_HANDLED; /* this device caused the interrupt */
1250 static void lx_irq_set(struct lx6464es *chip, int enable)
1252 u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS);
1254 /* enable/disable interrupts
1256 * Set the Doorbell and PCI interrupt enable bits
1260 reg |= (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1262 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB);
1263 lx_plx_reg_write(chip, ePLX_IRQCS, reg);
1266 void lx_irq_enable(struct lx6464es *chip)
1268 dev_dbg(chip->card->dev, "->lx_irq_enable\n");
1269 lx_irq_set(chip, 1);
1272 void lx_irq_disable(struct lx6464es *chip)
1274 dev_dbg(chip->card->dev, "->lx_irq_disable\n");
1275 lx_irq_set(chip, 0);