2 * C-Media CMI8788 driver - main driver module
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
23 #include <linux/pci.h>
24 #include <sound/ac97_codec.h>
25 #include <sound/asoundef.h>
26 #include <sound/core.h>
27 #include <sound/info.h>
28 #include <sound/mpu401.h>
29 #include <sound/pcm.h>
33 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
34 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
35 MODULE_LICENSE("GPL");
38 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
40 struct oxygen *chip = dev_id;
41 unsigned int status, clear, elapsed_streams, i;
43 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
47 spin_lock(&chip->reg_lock);
49 clear = status & (OXYGEN_CHANNEL_A |
52 OXYGEN_CHANNEL_SPDIF |
53 OXYGEN_CHANNEL_MULTICH |
55 OXYGEN_INT_SPDIF_IN_DETECT |
59 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
60 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
61 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
62 chip->interrupt_mask & ~clear);
63 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
64 chip->interrupt_mask);
67 elapsed_streams = status & chip->pcm_running;
69 spin_unlock(&chip->reg_lock);
71 for (i = 0; i < PCM_COUNT; ++i)
72 if ((elapsed_streams & (1 << i)) && chip->streams[i])
73 snd_pcm_period_elapsed(chip->streams[i]);
75 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
76 spin_lock(&chip->reg_lock);
77 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
78 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
79 OXYGEN_SPDIF_RATE_INT)) {
80 /* write the interrupt bit(s) to clear */
81 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
82 schedule_work(&chip->spdif_input_bits_work);
84 spin_unlock(&chip->reg_lock);
87 if (status & OXYGEN_INT_GPIO)
90 if ((status & OXYGEN_INT_MIDI) && chip->midi)
91 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
93 if (status & OXYGEN_INT_AC97)
94 wake_up(&chip->ac97_waitqueue);
99 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
101 struct oxygen *chip = container_of(work, struct oxygen,
102 spdif_input_bits_work);
106 * This function gets called when there is new activity on the SPDIF
107 * input, or when we lose lock on the input signal, or when the rate
111 spin_lock_irq(&chip->reg_lock);
112 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
113 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
114 OXYGEN_SPDIF_LOCK_STATUS))
115 == OXYGEN_SPDIF_SENSE_STATUS) {
117 * If we detect activity on the SPDIF input but cannot lock to
118 * a signal, the clock bit is likely to be wrong.
120 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
121 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
122 spin_unlock_irq(&chip->reg_lock);
124 spin_lock_irq(&chip->reg_lock);
125 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
126 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
127 OXYGEN_SPDIF_LOCK_STATUS))
128 == OXYGEN_SPDIF_SENSE_STATUS) {
129 /* nothing detected with either clock; give up */
130 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
131 == OXYGEN_SPDIF_IN_CLOCK_192) {
133 * Reset clock to <= 96 kHz because this is
134 * more likely to be received next time.
136 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
137 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
138 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
142 spin_unlock_irq(&chip->reg_lock);
144 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
145 spin_lock_irq(&chip->reg_lock);
146 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
147 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
148 chip->interrupt_mask);
149 spin_unlock_irq(&chip->reg_lock);
152 * We don't actually know that any channel status bits have
153 * changed, but let's send a notification just to be sure.
155 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
156 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
160 #ifdef CONFIG_PROC_FS
161 static void oxygen_proc_read(struct snd_info_entry *entry,
162 struct snd_info_buffer *buffer)
164 struct oxygen *chip = entry->private_data;
167 snd_iprintf(buffer, "CMI8788\n\n");
168 for (i = 0; i < 0x100; i += 0x10) {
169 snd_iprintf(buffer, "%02x:", i);
170 for (j = 0; j < 0x10; ++j)
171 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
172 snd_iprintf(buffer, "\n");
174 if (mutex_lock_interruptible(&chip->mutex) < 0)
176 if (chip->has_ac97_0) {
177 snd_iprintf(buffer, "\nAC97\n");
178 for (i = 0; i < 0x80; i += 0x10) {
179 snd_iprintf(buffer, "%02x:", i);
180 for (j = 0; j < 0x10; j += 2)
181 snd_iprintf(buffer, " %04x",
182 oxygen_read_ac97(chip, 0, i + j));
183 snd_iprintf(buffer, "\n");
186 if (chip->has_ac97_1) {
187 snd_iprintf(buffer, "\nAC97 2\n");
188 for (i = 0; i < 0x80; i += 0x10) {
189 snd_iprintf(buffer, "%02x:", i);
190 for (j = 0; j < 0x10; j += 2)
191 snd_iprintf(buffer, " %04x",
192 oxygen_read_ac97(chip, 1, i + j));
193 snd_iprintf(buffer, "\n");
196 mutex_unlock(&chip->mutex);
199 static void __devinit oxygen_proc_init(struct oxygen *chip)
201 struct snd_info_entry *entry;
203 if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
204 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
207 #define oxygen_proc_init(chip)
210 static void __devinit oxygen_init(struct oxygen *chip)
214 chip->dac_routing = 1;
215 for (i = 0; i < 8; ++i)
216 chip->dac_volume[i] = 0xff;
217 chip->spdif_playback_enable = 1;
218 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
219 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
220 chip->spdif_pcm_bits = chip->spdif_bits;
222 if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
227 if (chip->revision == 1)
228 oxygen_set_bits8(chip, OXYGEN_MISC,
229 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
231 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
232 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
233 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
235 oxygen_set_bits8(chip, OXYGEN_FUNCTION,
236 OXYGEN_FUNCTION_RESET_CODEC |
237 chip->model->function_flags);
238 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
240 OXYGEN_FUNCTION_2WIRE_SPI_MASK);
241 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
242 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
243 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
244 OXYGEN_PLAY_CHANNELS_2 |
245 OXYGEN_DMA_A_BURST_8 |
246 OXYGEN_DMA_MULTICH_BURST_8);
247 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
248 oxygen_write8_masked(chip, OXYGEN_MISC, 0,
249 OXYGEN_MISC_WRITE_PCI_SUBID |
250 OXYGEN_MISC_REC_C_FROM_SPDIF |
251 OXYGEN_MISC_REC_B_FROM_AC97 |
252 OXYGEN_MISC_REC_A_FROM_MULTICH);
253 oxygen_write8(chip, OXYGEN_REC_FORMAT,
254 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
255 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
256 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
257 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
258 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
259 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
260 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
261 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
262 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
263 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
264 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
265 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
266 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
267 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
268 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
269 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
270 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
271 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
272 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
273 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
274 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
275 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
276 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
277 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
278 OXYGEN_SPDIF_SENSE_MASK |
279 OXYGEN_SPDIF_LOCK_MASK |
280 OXYGEN_SPDIF_RATE_MASK |
281 OXYGEN_SPDIF_LOCK_PAR |
282 OXYGEN_SPDIF_IN_CLOCK_96,
283 OXYGEN_SPDIF_OUT_ENABLE |
284 OXYGEN_SPDIF_LOOPBACK |
285 OXYGEN_SPDIF_SENSE_MASK |
286 OXYGEN_SPDIF_LOCK_MASK |
287 OXYGEN_SPDIF_RATE_MASK |
288 OXYGEN_SPDIF_SENSE_PAR |
289 OXYGEN_SPDIF_LOCK_PAR |
290 OXYGEN_SPDIF_IN_CLOCK_MASK);
291 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
292 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
293 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
294 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
295 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
296 OXYGEN_PLAY_MULTICH_I2S_DAC |
297 OXYGEN_PLAY_SPDIF_SPDIF |
298 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
299 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
300 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
301 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
302 oxygen_write8(chip, OXYGEN_REC_ROUTING,
303 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
304 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
305 OXYGEN_REC_C_ROUTE_SPDIF);
306 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
307 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
308 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
309 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
310 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
311 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
313 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
314 OXYGEN_AC97_INT_READ_DONE |
315 OXYGEN_AC97_INT_WRITE_DONE);
316 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
317 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
318 if (!(chip->has_ac97_0 | chip->has_ac97_1))
319 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
320 OXYGEN_AC97_CLOCK_DISABLE);
321 if (!chip->has_ac97_0) {
322 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
323 OXYGEN_AC97_NO_CODEC_0);
325 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
327 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
328 CM9780_GPIO0IO | CM9780_GPIO1IO);
329 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
330 CM9780_BSTSEL | CM9780_STRO_MIC |
331 CM9780_MIX2FR | CM9780_PCBSW);
332 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
333 CM9780_RSOE | CM9780_CBOE |
334 CM9780_SSOE | CM9780_FROE |
335 CM9780_MIC2MIC | CM9780_LI2LI);
336 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
337 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
338 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
339 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
340 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
341 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
342 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
343 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
344 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
345 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
346 /* power down unused ADCs and DACs */
347 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
348 AC97_PD_PR0 | AC97_PD_PR1);
349 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
350 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
352 if (chip->has_ac97_1) {
353 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
354 OXYGEN_AC97_CODEC1_SLOT3 |
355 OXYGEN_AC97_CODEC1_SLOT4);
356 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
358 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
359 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
360 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
361 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
362 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
363 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
364 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
365 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
366 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
367 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
368 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x8000);
369 oxygen_ac97_clear_bits(chip, 1, AC97_REC_GAIN, 0x1c00);
370 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
374 static void oxygen_card_free(struct snd_card *card)
376 struct oxygen *chip = card->private_data;
378 spin_lock_irq(&chip->reg_lock);
379 chip->interrupt_mask = 0;
380 chip->pcm_running = 0;
381 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
382 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
383 spin_unlock_irq(&chip->reg_lock);
384 if (chip->irq >= 0) {
385 free_irq(chip->irq, chip);
386 synchronize_irq(chip->irq);
388 flush_scheduled_work();
389 chip->model->cleanup(chip);
390 mutex_destroy(&chip->mutex);
391 pci_release_regions(chip->pci);
392 pci_disable_device(chip->pci);
395 int __devinit oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
396 int midi, const struct oxygen_model *model)
398 struct snd_card *card;
402 card = snd_card_new(index, id, model->owner,
403 sizeof *chip + model->model_data_size);
407 chip = card->private_data;
412 chip->model_data = chip + 1;
413 spin_lock_init(&chip->reg_lock);
414 mutex_init(&chip->mutex);
415 INIT_WORK(&chip->spdif_input_bits_work,
416 oxygen_spdif_input_bits_changed);
417 init_waitqueue_head(&chip->ac97_waitqueue);
419 err = pci_enable_device(pci);
423 err = pci_request_regions(pci, model->chip);
425 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
429 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
430 pci_resource_len(pci, 0) < 0x100) {
431 snd_printk(KERN_ERR "invalid PCI I/O range\n");
433 goto err_pci_regions;
435 chip->addr = pci_resource_start(pci, 0);
438 snd_card_set_dev(card, &pci->dev);
439 card->private_free = oxygen_card_free;
444 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
447 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
450 chip->irq = pci->irq;
452 strcpy(card->driver, model->chip);
453 strcpy(card->shortname, model->shortname);
454 sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
455 model->longname, chip->revision, chip->addr, chip->irq);
456 strcpy(card->mixername, model->chip);
457 snd_component_add(card, model->chip);
459 err = oxygen_pcm_init(chip);
463 err = oxygen_mixer_init(chip);
467 oxygen_write8_masked(chip, OXYGEN_MISC,
468 midi ? OXYGEN_MISC_MIDI : 0, OXYGEN_MISC_MIDI);
470 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
471 chip->addr + OXYGEN_MPU401,
472 MPU401_INFO_INTEGRATED, 0, 0,
478 oxygen_proc_init(chip);
480 spin_lock_irq(&chip->reg_lock);
481 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT | OXYGEN_INT_AC97;
482 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
483 spin_unlock_irq(&chip->reg_lock);
485 err = snd_card_register(card);
489 pci_set_drvdata(pci, card);
493 pci_release_regions(pci);
495 pci_disable_device(pci);
500 EXPORT_SYMBOL(oxygen_pci_probe);
502 void __devexit oxygen_pci_remove(struct pci_dev *pci)
504 snd_card_free(pci_get_drvdata(pci));
505 pci_set_drvdata(pci, NULL);
507 EXPORT_SYMBOL(oxygen_pci_remove);