2 * C-Media CMI8788 driver - main driver module
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
23 #include <linux/pci.h>
24 #include <sound/ac97_codec.h>
25 #include <sound/asoundef.h>
26 #include <sound/core.h>
27 #include <sound/info.h>
28 #include <sound/mpu401.h>
29 #include <sound/pcm.h>
33 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
34 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
35 MODULE_LICENSE("GPL");
38 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
40 struct oxygen *chip = dev_id;
41 unsigned int status, clear, elapsed_streams, i;
43 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
47 spin_lock(&chip->reg_lock);
49 clear = status & (OXYGEN_CHANNEL_A |
52 OXYGEN_CHANNEL_SPDIF |
53 OXYGEN_CHANNEL_MULTICH |
55 OXYGEN_INT_SPDIF_IN_DETECT |
58 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
59 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
60 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
61 chip->interrupt_mask & ~clear);
62 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
63 chip->interrupt_mask);
66 elapsed_streams = status & chip->pcm_running;
68 spin_unlock(&chip->reg_lock);
70 for (i = 0; i < PCM_COUNT; ++i)
71 if ((elapsed_streams & (1 << i)) && chip->streams[i])
72 snd_pcm_period_elapsed(chip->streams[i]);
74 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
75 spin_lock(&chip->reg_lock);
76 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
77 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
78 OXYGEN_SPDIF_RATE_INT)) {
79 /* write the interrupt bit(s) to clear */
80 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
81 schedule_work(&chip->spdif_input_bits_work);
83 spin_unlock(&chip->reg_lock);
86 if (status & OXYGEN_INT_GPIO)
89 if ((status & OXYGEN_INT_MIDI) && chip->midi)
90 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
95 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
97 struct oxygen *chip = container_of(work, struct oxygen,
98 spdif_input_bits_work);
102 * This function gets called when there is new activity on the SPDIF
103 * input, or when we lose lock on the input signal, or when the rate
107 spin_lock_irq(&chip->reg_lock);
108 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
109 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
110 OXYGEN_SPDIF_LOCK_STATUS))
111 == OXYGEN_SPDIF_SENSE_STATUS) {
113 * If we detect activity on the SPDIF input but cannot lock to
114 * a signal, the clock bit is likely to be wrong.
116 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
117 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
118 spin_unlock_irq(&chip->reg_lock);
120 spin_lock_irq(&chip->reg_lock);
121 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
122 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
123 OXYGEN_SPDIF_LOCK_STATUS))
124 == OXYGEN_SPDIF_SENSE_STATUS) {
125 /* nothing detected with either clock; give up */
126 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
127 == OXYGEN_SPDIF_IN_CLOCK_192) {
129 * Reset clock to <= 96 kHz because this is
130 * more likely to be received next time.
132 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
133 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
134 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
138 spin_unlock_irq(&chip->reg_lock);
140 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
141 spin_lock_irq(&chip->reg_lock);
142 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
143 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
144 chip->interrupt_mask);
145 spin_unlock_irq(&chip->reg_lock);
148 * We don't actually know that any channel status bits have
149 * changed, but let's send a notification just to be sure.
151 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
152 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
156 #ifdef CONFIG_PROC_FS
157 static void oxygen_proc_read(struct snd_info_entry *entry,
158 struct snd_info_buffer *buffer)
160 struct oxygen *chip = entry->private_data;
163 snd_iprintf(buffer, "CMI8788\n\n");
164 for (i = 0; i < 0x100; i += 0x10) {
165 snd_iprintf(buffer, "%02x:", i);
166 for (j = 0; j < 0x10; ++j)
167 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
168 snd_iprintf(buffer, "\n");
170 if (mutex_lock_interruptible(&chip->mutex) < 0)
172 if (chip->has_ac97_0) {
173 snd_iprintf(buffer, "\nAC97\n");
174 for (i = 0; i < 0x80; i += 0x10) {
175 snd_iprintf(buffer, "%02x:", i);
176 for (j = 0; j < 0x10; j += 2)
177 snd_iprintf(buffer, " %04x",
178 oxygen_read_ac97(chip, 0, i + j));
179 snd_iprintf(buffer, "\n");
182 if (chip->has_ac97_1) {
183 snd_iprintf(buffer, "\nAC97 2\n");
184 for (i = 0; i < 0x80; i += 0x10) {
185 snd_iprintf(buffer, "%02x:", i);
186 for (j = 0; j < 0x10; j += 2)
187 snd_iprintf(buffer, " %04x",
188 oxygen_read_ac97(chip, 1, i + j));
189 snd_iprintf(buffer, "\n");
192 mutex_unlock(&chip->mutex);
195 static void __devinit oxygen_proc_init(struct oxygen *chip)
197 struct snd_info_entry *entry;
199 if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
200 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
203 #define oxygen_proc_init(chip)
206 static void __devinit oxygen_init(struct oxygen *chip)
210 chip->dac_routing = 1;
211 for (i = 0; i < 8; ++i)
212 chip->dac_volume[i] = 0xff;
213 chip->spdif_playback_enable = 1;
214 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
215 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
216 chip->spdif_pcm_bits = chip->spdif_bits;
218 if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
223 if (chip->revision == 1)
224 oxygen_set_bits8(chip, OXYGEN_MISC,
225 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
227 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
228 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
229 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
231 oxygen_set_bits8(chip, OXYGEN_FUNCTION,
232 OXYGEN_FUNCTION_RESET_CODEC |
233 chip->model->function_flags);
234 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
236 OXYGEN_FUNCTION_2WIRE_SPI_MASK);
237 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
238 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
239 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
240 OXYGEN_PLAY_CHANNELS_2 |
241 OXYGEN_DMA_A_BURST_8 |
242 OXYGEN_DMA_MULTICH_BURST_8);
243 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
244 oxygen_write8_masked(chip, OXYGEN_MISC, 0,
245 OXYGEN_MISC_WRITE_PCI_SUBID |
246 OXYGEN_MISC_REC_C_FROM_SPDIF |
247 OXYGEN_MISC_REC_B_FROM_AC97 |
248 OXYGEN_MISC_REC_A_FROM_MULTICH);
249 oxygen_write8(chip, OXYGEN_REC_FORMAT,
250 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
251 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
252 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
253 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
254 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
255 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
256 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
257 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
258 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
259 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
260 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
261 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
262 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
263 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
264 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
265 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
266 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
267 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
268 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
269 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
270 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
271 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
272 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
273 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
274 OXYGEN_SPDIF_SENSE_MASK |
275 OXYGEN_SPDIF_LOCK_MASK |
276 OXYGEN_SPDIF_RATE_MASK |
277 OXYGEN_SPDIF_LOCK_PAR |
278 OXYGEN_SPDIF_IN_CLOCK_96,
279 OXYGEN_SPDIF_OUT_ENABLE |
280 OXYGEN_SPDIF_LOOPBACK |
281 OXYGEN_SPDIF_SENSE_MASK |
282 OXYGEN_SPDIF_LOCK_MASK |
283 OXYGEN_SPDIF_RATE_MASK |
284 OXYGEN_SPDIF_SENSE_PAR |
285 OXYGEN_SPDIF_LOCK_PAR |
286 OXYGEN_SPDIF_IN_CLOCK_MASK);
287 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
288 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
289 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
290 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
291 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
292 OXYGEN_PLAY_MULTICH_I2S_DAC |
293 OXYGEN_PLAY_SPDIF_SPDIF |
294 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
295 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
296 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
297 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
298 oxygen_write8(chip, OXYGEN_REC_ROUTING,
299 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
300 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
301 OXYGEN_REC_C_ROUTE_SPDIF);
302 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
303 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
304 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
305 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
306 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
307 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
309 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
310 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
311 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
312 if (!(chip->has_ac97_0 | chip->has_ac97_1))
313 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
314 OXYGEN_AC97_CLOCK_DISABLE);
315 if (!chip->has_ac97_0) {
316 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
317 OXYGEN_AC97_NO_CODEC_0);
319 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
321 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
322 CM9780_GPIO0IO | CM9780_GPIO1IO);
323 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
324 CM9780_BSTSEL | CM9780_STRO_MIC |
325 CM9780_MIX2FR | CM9780_PCBSW);
326 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
327 CM9780_RSOE | CM9780_CBOE |
328 CM9780_SSOE | CM9780_FROE |
329 CM9780_MIC2MIC | CM9780_LI2LI);
330 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
331 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
332 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
333 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
334 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
335 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
336 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
337 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
338 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
339 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
340 /* power down unused ADCs and DACs */
341 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
342 AC97_PD_PR0 | AC97_PD_PR1);
343 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
344 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
346 if (chip->has_ac97_1) {
347 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
348 OXYGEN_AC97_CODEC1_SLOT3 |
349 OXYGEN_AC97_CODEC1_SLOT4);
350 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
352 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
353 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
354 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
355 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
356 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
357 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
358 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
359 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
360 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
361 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
362 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x8000);
363 oxygen_ac97_clear_bits(chip, 1, AC97_REC_GAIN, 0x1c00);
364 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
368 static void oxygen_card_free(struct snd_card *card)
370 struct oxygen *chip = card->private_data;
372 spin_lock_irq(&chip->reg_lock);
373 chip->interrupt_mask = 0;
374 chip->pcm_running = 0;
375 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
376 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
377 spin_unlock_irq(&chip->reg_lock);
378 if (chip->irq >= 0) {
379 free_irq(chip->irq, chip);
380 synchronize_irq(chip->irq);
382 flush_scheduled_work();
383 chip->model->cleanup(chip);
384 mutex_destroy(&chip->mutex);
385 pci_release_regions(chip->pci);
386 pci_disable_device(chip->pci);
389 int __devinit oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
390 int midi, const struct oxygen_model *model)
392 struct snd_card *card;
396 card = snd_card_new(index, id, model->owner,
397 sizeof *chip + model->model_data_size);
401 chip = card->private_data;
406 chip->model_data = chip + 1;
407 spin_lock_init(&chip->reg_lock);
408 mutex_init(&chip->mutex);
409 INIT_WORK(&chip->spdif_input_bits_work,
410 oxygen_spdif_input_bits_changed);
412 err = pci_enable_device(pci);
416 err = pci_request_regions(pci, model->chip);
418 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
422 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
423 pci_resource_len(pci, 0) < 0x100) {
424 snd_printk(KERN_ERR "invalid PCI I/O range\n");
426 goto err_pci_regions;
428 chip->addr = pci_resource_start(pci, 0);
431 snd_card_set_dev(card, &pci->dev);
432 card->private_free = oxygen_card_free;
437 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
440 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
443 chip->irq = pci->irq;
445 strcpy(card->driver, model->chip);
446 strcpy(card->shortname, model->shortname);
447 sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
448 model->longname, chip->revision, chip->addr, chip->irq);
449 strcpy(card->mixername, model->chip);
450 snd_component_add(card, model->chip);
452 err = oxygen_pcm_init(chip);
456 err = oxygen_mixer_init(chip);
460 oxygen_write8_masked(chip, OXYGEN_MISC,
461 midi ? OXYGEN_MISC_MIDI : 0, OXYGEN_MISC_MIDI);
463 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
464 chip->addr + OXYGEN_MPU401,
465 MPU401_INFO_INTEGRATED, 0, 0,
471 oxygen_proc_init(chip);
473 spin_lock_irq(&chip->reg_lock);
474 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
475 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
476 spin_unlock_irq(&chip->reg_lock);
478 err = snd_card_register(card);
482 pci_set_drvdata(pci, card);
486 pci_release_regions(pci);
488 pci_disable_device(pci);
493 EXPORT_SYMBOL(oxygen_pci_probe);
495 void __devexit oxygen_pci_remove(struct pci_dev *pci)
497 snd_card_free(pci_get_drvdata(pci));
498 pci_set_drvdata(pci, NULL);
500 EXPORT_SYMBOL(oxygen_pci_remove);