2 * ALSA driver for RME Hammerfall DSP audio interface(s)
4 * Copyright (c) 2002 Paul Davis
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <sound/driver.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
28 #include <linux/slab.h>
29 #include <linux/pci.h>
30 #include <linux/firmware.h>
31 #include <linux/moduleparam.h>
33 #include <sound/core.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/info.h>
37 #include <sound/asoundef.h>
38 #include <sound/rawmidi.h>
39 #include <sound/hwdep.h>
40 #include <sound/initval.h>
41 #include <sound/hdsp.h>
43 #include <asm/byteorder.h>
44 #include <asm/current.h>
47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
49 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
51 module_param_array(index, int, NULL, 0444);
52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
53 module_param_array(id, charp, NULL, 0444);
54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
55 module_param_array(enable, bool, NULL, 0444);
56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
58 MODULE_DESCRIPTION("RME Hammerfall DSP");
59 MODULE_LICENSE("GPL");
60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
64 MODULE_FIRMWARE("multiface_firmware.bin");
65 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
66 MODULE_FIRMWARE("digiface_firmware.bin");
67 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
70 #define HDSP_MAX_CHANNELS 26
71 #define HDSP_MAX_DS_CHANNELS 14
72 #define HDSP_MAX_QS_CHANNELS 8
73 #define DIGIFACE_SS_CHANNELS 26
74 #define DIGIFACE_DS_CHANNELS 14
75 #define MULTIFACE_SS_CHANNELS 18
76 #define MULTIFACE_DS_CHANNELS 14
77 #define H9652_SS_CHANNELS 26
78 #define H9652_DS_CHANNELS 14
79 /* This does not include possible Analog Extension Boards
80 AEBs are detected at card initialization
82 #define H9632_SS_CHANNELS 12
83 #define H9632_DS_CHANNELS 8
84 #define H9632_QS_CHANNELS 4
86 /* Write registers. These are defined as byte-offsets from the iobase value.
88 #define HDSP_resetPointer 0
89 #define HDSP_freqReg 0
90 #define HDSP_outputBufferAddress 32
91 #define HDSP_inputBufferAddress 36
92 #define HDSP_controlRegister 64
93 #define HDSP_interruptConfirmation 96
94 #define HDSP_outputEnable 128
95 #define HDSP_control2Reg 256
96 #define HDSP_midiDataOut0 352
97 #define HDSP_midiDataOut1 356
98 #define HDSP_fifoData 368
99 #define HDSP_inputEnable 384
101 /* Read registers. These are defined as byte-offsets from the iobase value
104 #define HDSP_statusRegister 0
105 #define HDSP_timecode 128
106 #define HDSP_status2Register 192
107 #define HDSP_midiDataIn0 360
108 #define HDSP_midiDataIn1 364
109 #define HDSP_midiStatusOut0 384
110 #define HDSP_midiStatusOut1 388
111 #define HDSP_midiStatusIn0 392
112 #define HDSP_midiStatusIn1 396
113 #define HDSP_fifoStatus 400
115 /* the meters are regular i/o-mapped registers, but offset
116 considerably from the rest. the peak registers are reset
117 when read; the least-significant 4 bits are full-scale counters;
118 the actual peak value is in the most-significant 24 bits.
121 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
122 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
123 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
124 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
125 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
128 /* This is for H9652 cards
129 Peak values are read downward from the base
130 Rms values are read upward
131 There are rms values for the outputs too
132 26*3 values are read in ss mode
133 14*3 in ds mode, with no gap between values
135 #define HDSP_9652_peakBase 7164
136 #define HDSP_9652_rmsBase 4096
138 /* c.f. the hdsp_9632_meters_t struct */
139 #define HDSP_9632_metersBase 4096
141 #define HDSP_IO_EXTENT 7168
143 /* control2 register bits */
145 #define HDSP_TMS 0x01
146 #define HDSP_TCK 0x02
147 #define HDSP_TDI 0x04
148 #define HDSP_JTAG 0x08
149 #define HDSP_PWDN 0x10
150 #define HDSP_PROGRAM 0x020
151 #define HDSP_CONFIG_MODE_0 0x040
152 #define HDSP_CONFIG_MODE_1 0x080
153 #define HDSP_VERSION_BIT 0x100
154 #define HDSP_BIGENDIAN_MODE 0x200
155 #define HDSP_RD_MULTIPLE 0x400
156 #define HDSP_9652_ENABLE_MIXER 0x800
157 #define HDSP_TDO 0x10000000
159 #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
160 #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
162 /* Control Register bits */
164 #define HDSP_Start (1<<0) /* start engine */
165 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
166 #define HDSP_Latency1 (1<<2) /* [ see above ] */
167 #define HDSP_Latency2 (1<<3) /* [ see above ] */
168 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
169 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
170 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
171 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
172 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
173 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
174 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
175 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
176 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
177 #define HDSP_SyncRef2 (1<<13)
178 #define HDSP_SPDIFInputSelect0 (1<<14)
179 #define HDSP_SPDIFInputSelect1 (1<<15)
180 #define HDSP_SyncRef0 (1<<16)
181 #define HDSP_SyncRef1 (1<<17)
182 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
183 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
184 #define HDSP_Midi0InterruptEnable (1<<22)
185 #define HDSP_Midi1InterruptEnable (1<<23)
186 #define HDSP_LineOut (1<<24)
187 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
188 #define HDSP_ADGain1 (1<<26)
189 #define HDSP_DAGain0 (1<<27)
190 #define HDSP_DAGain1 (1<<28)
191 #define HDSP_PhoneGain0 (1<<29)
192 #define HDSP_PhoneGain1 (1<<30)
193 #define HDSP_QuadSpeed (1<<31)
195 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
196 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
197 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
198 #define HDSP_ADGainLowGain 0
200 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
201 #define HDSP_DAGainHighGain HDSP_DAGainMask
202 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
203 #define HDSP_DAGainMinus10dBV 0
205 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
206 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
207 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
208 #define HDSP_PhoneGainMinus12dB 0
210 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
211 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
213 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
214 #define HDSP_SPDIFInputADAT1 0
215 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
216 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
217 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
219 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
220 #define HDSP_SyncRef_ADAT1 0
221 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
222 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
223 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
224 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
225 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
227 /* Sample Clock Sources */
229 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
230 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
231 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
232 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
233 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
234 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
235 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
236 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
237 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
238 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
240 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
242 #define HDSP_SYNC_FROM_WORD 0
243 #define HDSP_SYNC_FROM_SPDIF 1
244 #define HDSP_SYNC_FROM_ADAT1 2
245 #define HDSP_SYNC_FROM_ADAT_SYNC 3
246 #define HDSP_SYNC_FROM_ADAT2 4
247 #define HDSP_SYNC_FROM_ADAT3 5
249 /* SyncCheck status */
251 #define HDSP_SYNC_CHECK_NO_LOCK 0
252 #define HDSP_SYNC_CHECK_LOCK 1
253 #define HDSP_SYNC_CHECK_SYNC 2
255 /* AutoSync references - used by "autosync_ref" control switch */
257 #define HDSP_AUTOSYNC_FROM_WORD 0
258 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
259 #define HDSP_AUTOSYNC_FROM_SPDIF 2
260 #define HDSP_AUTOSYNC_FROM_NONE 3
261 #define HDSP_AUTOSYNC_FROM_ADAT1 4
262 #define HDSP_AUTOSYNC_FROM_ADAT2 5
263 #define HDSP_AUTOSYNC_FROM_ADAT3 6
265 /* Possible sources of S/PDIF input */
267 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
268 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
269 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
270 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
272 #define HDSP_Frequency32KHz HDSP_Frequency0
273 #define HDSP_Frequency44_1KHz HDSP_Frequency1
274 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
275 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
276 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
277 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
278 /* For H9632 cards */
279 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
280 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
281 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
282 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
283 return 104857600000000 / rate; // 100 MHz
284 return 110100480000000 / rate; // 105 MHz
286 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
288 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
289 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
291 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
292 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
294 /* Status Register bits */
296 #define HDSP_audioIRQPending (1<<0)
297 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
298 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
299 #define HDSP_Lock1 (1<<2)
300 #define HDSP_Lock0 (1<<3)
301 #define HDSP_SPDIFSync (1<<4)
302 #define HDSP_TimecodeLock (1<<5)
303 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
304 #define HDSP_Sync2 (1<<16)
305 #define HDSP_Sync1 (1<<17)
306 #define HDSP_Sync0 (1<<18)
307 #define HDSP_DoubleSpeedStatus (1<<19)
308 #define HDSP_ConfigError (1<<20)
309 #define HDSP_DllError (1<<21)
310 #define HDSP_spdifFrequency0 (1<<22)
311 #define HDSP_spdifFrequency1 (1<<23)
312 #define HDSP_spdifFrequency2 (1<<24)
313 #define HDSP_SPDIFErrorFlag (1<<25)
314 #define HDSP_BufferID (1<<26)
315 #define HDSP_TimecodeSync (1<<27)
316 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
317 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
318 #define HDSP_midi0IRQPending (1<<30)
319 #define HDSP_midi1IRQPending (1<<31)
321 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
323 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
324 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
325 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
327 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
328 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
329 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
331 /* This is for H9632 cards */
332 #define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask
333 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
334 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
336 /* Status2 Register bits */
338 #define HDSP_version0 (1<<0)
339 #define HDSP_version1 (1<<1)
340 #define HDSP_version2 (1<<2)
341 #define HDSP_wc_lock (1<<3)
342 #define HDSP_wc_sync (1<<4)
343 #define HDSP_inp_freq0 (1<<5)
344 #define HDSP_inp_freq1 (1<<6)
345 #define HDSP_inp_freq2 (1<<7)
346 #define HDSP_SelSyncRef0 (1<<8)
347 #define HDSP_SelSyncRef1 (1<<9)
348 #define HDSP_SelSyncRef2 (1<<10)
350 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
352 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
353 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
354 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
355 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
356 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
357 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
358 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
359 /* FIXME : more values for 9632 cards ? */
361 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
362 #define HDSP_SelSyncRef_ADAT1 0
363 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
364 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
365 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
366 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
367 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
369 /* Card state flags */
371 #define HDSP_InitializationComplete (1<<0)
372 #define HDSP_FirmwareLoaded (1<<1)
373 #define HDSP_FirmwareCached (1<<2)
375 /* FIFO wait times, defined in terms of 1/10ths of msecs */
377 #define HDSP_LONG_WAIT 5000
378 #define HDSP_SHORT_WAIT 30
380 #define UNITY_GAIN 32768
381 #define MINUS_INFINITY_GAIN 0
383 /* the size of a substream (1 mono data stream) */
385 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
386 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
388 /* the size of the area we need to allocate for DMA transfers. the
389 size is the same regardless of the number of channels - the
390 Multiface still uses the same memory area.
392 Note that we allocate 1 more channel than is apparently needed
393 because the h/w seems to write 1 byte beyond the end of the last
397 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
398 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
400 /* use hotplug firmeare loader? */
401 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
402 #if !defined(HDSP_USE_HWDEP_LOADER) && !defined(CONFIG_SND_HDSP)
403 #define HDSP_FW_LOADER
407 struct hdsp_9632_meters {
409 u32 playback_peak[16];
413 u32 input_rms_low[16];
414 u32 playback_rms_low[16];
415 u32 output_rms_low[16];
417 u32 input_rms_high[16];
418 u32 playback_rms_high[16];
419 u32 output_rms_high[16];
420 u32 xxx_rms_high[16];
426 struct snd_rawmidi *rmidi;
427 struct snd_rawmidi_substream *input;
428 struct snd_rawmidi_substream *output;
429 char istimer; /* timer in use */
430 struct timer_list timer;
437 struct snd_pcm_substream *capture_substream;
438 struct snd_pcm_substream *playback_substream;
439 struct hdsp_midi midi[2];
440 struct tasklet_struct midi_tasklet;
441 int use_midi_tasklet;
443 u32 control_register; /* cached value */
444 u32 control2_register; /* cached value */
446 u32 creg_spdif_stream;
447 int clock_source_locked;
448 char *card_name; /* digiface/multiface */
449 enum HDSP_IO_Type io_type; /* ditto, but for code use */
450 unsigned short firmware_rev;
451 unsigned short state; /* stores state bits */
452 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
453 size_t period_bytes; /* guess what this is */
454 unsigned char max_channels;
455 unsigned char qs_in_channels; /* quad speed mode for H9632 */
456 unsigned char ds_in_channels;
457 unsigned char ss_in_channels; /* different for multiface/digiface */
458 unsigned char qs_out_channels;
459 unsigned char ds_out_channels;
460 unsigned char ss_out_channels;
462 struct snd_dma_buffer capture_dma_buf;
463 struct snd_dma_buffer playback_dma_buf;
464 unsigned char *capture_buffer; /* suitably aligned address */
465 unsigned char *playback_buffer; /* suitably aligned address */
470 int system_sample_rate;
475 void __iomem *iobase;
476 struct snd_card *card;
478 struct snd_hwdep *hwdep;
480 struct snd_kcontrol *spdif_ctl;
481 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
482 unsigned int dds_value; /* last value written to freq register */
485 /* These tables map the ALSA channels 1..N to the channels that we
486 need to use in order to find the relevant channel buffer. RME
487 refer to this kind of mapping as between "the ADAT channel and
488 the DMA channel." We index it using the logical audio channel,
489 and the value is the DMA channel (i.e. channel buffer number)
490 where the data for that channel can be read/written from/to.
493 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
494 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
495 18, 19, 20, 21, 22, 23, 24, 25
498 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
500 0, 1, 2, 3, 4, 5, 6, 7,
502 16, 17, 18, 19, 20, 21, 22, 23,
505 -1, -1, -1, -1, -1, -1, -1, -1
508 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
509 /* ADAT channels are remapped */
510 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
511 /* channels 12 and 13 are S/PDIF */
513 /* others don't exist */
514 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
517 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
519 0, 1, 2, 3, 4, 5, 6, 7,
524 /* AO4S-192 and AI4S-192 extension boards */
526 /* others don't exist */
527 -1, -1, -1, -1, -1, -1, -1, -1,
531 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
538 /* AO4S-192 and AI4S-192 extension boards */
540 /* others don't exist */
541 -1, -1, -1, -1, -1, -1, -1, -1,
542 -1, -1, -1, -1, -1, -1
545 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
546 /* ADAT is disabled in this mode */
551 /* AO4S-192 and AI4S-192 extension boards */
553 /* others don't exist */
554 -1, -1, -1, -1, -1, -1, -1, -1,
555 -1, -1, -1, -1, -1, -1, -1, -1,
559 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
561 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
562 dmab->dev.dev = snd_dma_pci_data(pci);
563 if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
564 if (dmab->bytes >= size)
567 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
573 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
576 dmab->dev.dev = NULL; /* make it anonymous */
577 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
582 static struct pci_device_id snd_hdsp_ids[] = {
584 .vendor = PCI_VENDOR_ID_XILINX,
585 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
586 .subvendor = PCI_ANY_ID,
587 .subdevice = PCI_ANY_ID,
588 }, /* RME Hammerfall-DSP */
592 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
595 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
596 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
597 static int snd_hdsp_enable_io (struct hdsp *hdsp);
598 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
599 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
600 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
601 static int hdsp_autosync_ref(struct hdsp *hdsp);
602 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
603 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
605 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
607 switch (hdsp->io_type) {
611 return (64 * out) + (32 + (in));
613 return (32 * out) + (16 + (in));
615 return (52 * out) + (26 + (in));
619 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
621 switch (hdsp->io_type) {
625 return (64 * out) + in;
627 return (32 * out) + in;
629 return (52 * out) + in;
633 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
635 writel(val, hdsp->iobase + reg);
638 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
640 return readl (hdsp->iobase + reg);
643 static int hdsp_check_for_iobox (struct hdsp *hdsp)
646 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
647 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
648 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
649 hdsp->state &= ~HDSP_FirmwareLoaded;
656 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
661 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
663 snd_printk ("Hammerfall-DSP: loading firmware\n");
665 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
666 hdsp_write (hdsp, HDSP_fifoData, 0);
668 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
669 snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n");
673 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
675 for (i = 0; i < 24413; ++i) {
676 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
677 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
678 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n");
685 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
686 snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n");
690 #ifdef SNDRV_BIG_ENDIAN
691 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
693 hdsp->control2_register = 0;
695 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
696 snd_printk ("Hammerfall-DSP: finished firmware loading\n");
699 if (hdsp->state & HDSP_InitializationComplete) {
700 snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n");
701 spin_lock_irqsave(&hdsp->lock, flags);
702 snd_hdsp_set_defaults(hdsp);
703 spin_unlock_irqrestore(&hdsp->lock, flags);
706 hdsp->state |= HDSP_FirmwareLoaded;
711 static int hdsp_get_iobox_version (struct hdsp *hdsp)
713 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
715 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
716 hdsp_write (hdsp, HDSP_fifoData, 0);
717 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0)
720 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
721 hdsp_write (hdsp, HDSP_fifoData, 0);
723 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
724 hdsp->io_type = Multiface;
725 hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
726 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
727 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
729 hdsp->io_type = Digiface;
732 /* firmware was already loaded, get iobox type */
733 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
734 hdsp->io_type = Multiface;
736 hdsp->io_type = Digiface;
742 #ifdef HDSP_FW_LOADER
743 static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp);
746 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
748 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
750 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
751 hdsp->state &= ~HDSP_FirmwareLoaded;
752 if (! load_on_demand)
754 snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n");
755 /* try to load firmware */
756 if (! (hdsp->state & HDSP_FirmwareCached)) {
757 #ifdef HDSP_FW_LOADER
758 if (! hdsp_request_fw_loader(hdsp))
762 "Hammerfall-DSP: No firmware loaded nor "
763 "cached, please upload firmware.\n");
766 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
768 "Hammerfall-DSP: Firmware loading from "
769 "cache failed, please upload manually.\n");
777 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
781 /* the fifoStatus registers reports on how many words
782 are available in the command FIFO.
785 for (i = 0; i < timeout; i++) {
787 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
790 /* not very friendly, but we only do this during a firmware
791 load and changing the mixer, so we just put up with it.
797 snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n",
802 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
804 if (addr >= HDSP_MATRIX_MIXER_SIZE)
807 return hdsp->mixer_matrix[addr];
810 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
814 if (addr >= HDSP_MATRIX_MIXER_SIZE)
817 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
819 /* from martin bjornsen:
821 "You can only write dwords to the
822 mixer memory which contain two
823 mixer values in the low and high
824 word. So if you want to change
825 value 0 you have to read value 1
826 from the cache and write both to
827 the first dword in the mixer
831 if (hdsp->io_type == H9632 && addr >= 512)
834 if (hdsp->io_type == H9652 && addr >= 1352)
837 hdsp->mixer_matrix[addr] = data;
840 /* `addr' addresses a 16-bit wide address, but
841 the address space accessed via hdsp_write
842 uses byte offsets. put another way, addr
843 varies from 0 to 1351, but to access the
844 corresponding memory location, we need
845 to access 0 to 2703 ...
849 hdsp_write (hdsp, 4096 + (ad*4),
850 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
851 hdsp->mixer_matrix[addr&0x7fe]);
857 ad = (addr << 16) + data;
859 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
862 hdsp_write (hdsp, HDSP_fifoData, ad);
863 hdsp->mixer_matrix[addr] = data;
870 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
875 spin_lock_irqsave(&hdsp->lock, flags);
876 if ((hdsp->playback_pid != hdsp->capture_pid) &&
877 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
879 spin_unlock_irqrestore(&hdsp->lock, flags);
883 static int hdsp_external_sample_rate (struct hdsp *hdsp)
885 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
886 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
889 case HDSP_systemFrequency32: return 32000;
890 case HDSP_systemFrequency44_1: return 44100;
891 case HDSP_systemFrequency48: return 48000;
892 case HDSP_systemFrequency64: return 64000;
893 case HDSP_systemFrequency88_2: return 88200;
894 case HDSP_systemFrequency96: return 96000;
900 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
902 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
903 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
905 if (status & HDSP_SPDIFErrorFlag)
909 case HDSP_spdifFrequency32KHz: return 32000;
910 case HDSP_spdifFrequency44_1KHz: return 44100;
911 case HDSP_spdifFrequency48KHz: return 48000;
912 case HDSP_spdifFrequency64KHz: return 64000;
913 case HDSP_spdifFrequency88_2KHz: return 88200;
914 case HDSP_spdifFrequency96KHz: return 96000;
915 case HDSP_spdifFrequency128KHz:
916 if (hdsp->io_type == H9632) return 128000;
918 case HDSP_spdifFrequency176_4KHz:
919 if (hdsp->io_type == H9632) return 176400;
921 case HDSP_spdifFrequency192KHz:
922 if (hdsp->io_type == H9632) return 192000;
927 snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
931 static void hdsp_compute_period_size(struct hdsp *hdsp)
933 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
936 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
940 position = hdsp_read(hdsp, HDSP_statusRegister);
942 if (!hdsp->precise_ptr)
943 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
945 position &= HDSP_BufferPositionMask;
947 position &= (hdsp->period_bytes/2) - 1;
951 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
953 hdsp_write (hdsp, HDSP_resetPointer, 0);
954 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
955 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
956 * requires (?) to write again DDS value after a reset pointer
957 * (at least, it works like this) */
958 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
961 static void hdsp_start_audio(struct hdsp *s)
963 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
964 hdsp_write(s, HDSP_controlRegister, s->control_register);
967 static void hdsp_stop_audio(struct hdsp *s)
969 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
970 hdsp_write(s, HDSP_controlRegister, s->control_register);
973 static void hdsp_silence_playback(struct hdsp *hdsp)
975 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
978 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
982 spin_lock_irq(&s->lock);
991 s->control_register &= ~HDSP_LatencyMask;
992 s->control_register |= hdsp_encode_latency(n);
994 hdsp_write(s, HDSP_controlRegister, s->control_register);
996 hdsp_compute_period_size(s);
998 spin_unlock_irq(&s->lock);
1003 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1010 else if (rate >= 56000)
1014 div64_32(&n, rate, &r);
1015 /* n should be less than 2^32 for being written to FREQ register */
1016 snd_assert((n >> 32) == 0);
1017 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1018 value to write it after a reset */
1019 hdsp->dds_value = n;
1020 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1023 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1025 int reject_if_open = 0;
1029 /* ASSUMPTION: hdsp->lock is either held, or
1030 there is no need for it (e.g. during module
1034 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1035 if (called_internally) {
1036 /* request from ctl or card initialization */
1037 snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n");
1040 /* hw_param request while in AutoSync mode */
1041 int external_freq = hdsp_external_sample_rate(hdsp);
1042 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1044 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1045 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n");
1046 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1047 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n");
1048 else if (rate != external_freq) {
1049 snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n");
1055 current_rate = hdsp->system_sample_rate;
1057 /* Changing from a "single speed" to a "double speed" rate is
1058 not allowed if any substreams are open. This is because
1059 such a change causes a shift in the location of
1060 the DMA buffers and a reduction in the number of available
1063 Note that a similar but essentially insoluble problem
1064 exists for externally-driven rate changes. All we can do
1065 is to flag rate changes in the read/write routines. */
1067 if (rate > 96000 && hdsp->io_type != H9632)
1072 if (current_rate > 48000)
1074 rate_bits = HDSP_Frequency32KHz;
1077 if (current_rate > 48000)
1079 rate_bits = HDSP_Frequency44_1KHz;
1082 if (current_rate > 48000)
1084 rate_bits = HDSP_Frequency48KHz;
1087 if (current_rate <= 48000 || current_rate > 96000)
1089 rate_bits = HDSP_Frequency64KHz;
1092 if (current_rate <= 48000 || current_rate > 96000)
1094 rate_bits = HDSP_Frequency88_2KHz;
1097 if (current_rate <= 48000 || current_rate > 96000)
1099 rate_bits = HDSP_Frequency96KHz;
1102 if (current_rate < 128000)
1104 rate_bits = HDSP_Frequency128KHz;
1107 if (current_rate < 128000)
1109 rate_bits = HDSP_Frequency176_4KHz;
1112 if (current_rate < 128000)
1114 rate_bits = HDSP_Frequency192KHz;
1120 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1121 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1123 hdsp->playback_pid);
1127 hdsp->control_register &= ~HDSP_FrequencyMask;
1128 hdsp->control_register |= rate_bits;
1129 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1131 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1132 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1133 hdsp_set_dds_value(hdsp, rate);
1135 if (rate >= 128000) {
1136 hdsp->channel_map = channel_map_H9632_qs;
1137 } else if (rate > 48000) {
1138 if (hdsp->io_type == H9632)
1139 hdsp->channel_map = channel_map_H9632_ds;
1141 hdsp->channel_map = channel_map_ds;
1143 switch (hdsp->io_type) {
1145 hdsp->channel_map = channel_map_mf_ss;
1149 hdsp->channel_map = channel_map_df_ss;
1152 hdsp->channel_map = channel_map_H9632_ss;
1155 /* should never happen */
1160 hdsp->system_sample_rate = rate;
1165 /*----------------------------------------------------------------------------
1167 ----------------------------------------------------------------------------*/
1169 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1171 /* the hardware already does the relevant bit-mask with 0xff */
1173 return hdsp_read(hdsp, HDSP_midiDataIn1);
1175 return hdsp_read(hdsp, HDSP_midiDataIn0);
1178 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1180 /* the hardware already does the relevant bit-mask with 0xff */
1182 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1184 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1187 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1190 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1192 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1195 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1197 int fifo_bytes_used;
1200 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1202 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1204 if (fifo_bytes_used < 128)
1205 return 128 - fifo_bytes_used;
1210 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1212 while (snd_hdsp_midi_input_available (hdsp, id))
1213 snd_hdsp_midi_read_byte (hdsp, id);
1216 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1218 unsigned long flags;
1222 unsigned char buf[128];
1224 /* Output is not interrupt driven */
1226 spin_lock_irqsave (&hmidi->lock, flags);
1227 if (hmidi->output) {
1228 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1229 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1230 if (n_pending > (int)sizeof (buf))
1231 n_pending = sizeof (buf);
1233 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1234 for (i = 0; i < to_write; ++i)
1235 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1240 spin_unlock_irqrestore (&hmidi->lock, flags);
1244 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1246 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1247 unsigned long flags;
1251 spin_lock_irqsave (&hmidi->lock, flags);
1252 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1254 if (n_pending > (int)sizeof (buf))
1255 n_pending = sizeof (buf);
1256 for (i = 0; i < n_pending; ++i)
1257 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1259 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1261 /* flush the MIDI input FIFO */
1263 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1268 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1270 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1271 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1272 spin_unlock_irqrestore (&hmidi->lock, flags);
1273 return snd_hdsp_midi_output_write (hmidi);
1276 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1279 struct hdsp_midi *hmidi;
1280 unsigned long flags;
1283 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1285 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1286 spin_lock_irqsave (&hdsp->lock, flags);
1288 if (!(hdsp->control_register & ie)) {
1289 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1290 hdsp->control_register |= ie;
1293 hdsp->control_register &= ~ie;
1294 tasklet_kill(&hdsp->midi_tasklet);
1297 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1298 spin_unlock_irqrestore (&hdsp->lock, flags);
1301 static void snd_hdsp_midi_output_timer(unsigned long data)
1303 struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1304 unsigned long flags;
1306 snd_hdsp_midi_output_write(hmidi);
1307 spin_lock_irqsave (&hmidi->lock, flags);
1309 /* this does not bump hmidi->istimer, because the
1310 kernel automatically removed the timer when it
1311 expired, and we are now adding it back, thus
1312 leaving istimer wherever it was set before.
1315 if (hmidi->istimer) {
1316 hmidi->timer.expires = 1 + jiffies;
1317 add_timer(&hmidi->timer);
1320 spin_unlock_irqrestore (&hmidi->lock, flags);
1323 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1325 struct hdsp_midi *hmidi;
1326 unsigned long flags;
1328 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1329 spin_lock_irqsave (&hmidi->lock, flags);
1331 if (!hmidi->istimer) {
1332 init_timer(&hmidi->timer);
1333 hmidi->timer.function = snd_hdsp_midi_output_timer;
1334 hmidi->timer.data = (unsigned long) hmidi;
1335 hmidi->timer.expires = 1 + jiffies;
1336 add_timer(&hmidi->timer);
1340 if (hmidi->istimer && --hmidi->istimer <= 0)
1341 del_timer (&hmidi->timer);
1343 spin_unlock_irqrestore (&hmidi->lock, flags);
1345 snd_hdsp_midi_output_write(hmidi);
1348 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1350 struct hdsp_midi *hmidi;
1352 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1353 spin_lock_irq (&hmidi->lock);
1354 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1355 hmidi->input = substream;
1356 spin_unlock_irq (&hmidi->lock);
1361 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1363 struct hdsp_midi *hmidi;
1365 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1366 spin_lock_irq (&hmidi->lock);
1367 hmidi->output = substream;
1368 spin_unlock_irq (&hmidi->lock);
1373 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1375 struct hdsp_midi *hmidi;
1377 snd_hdsp_midi_input_trigger (substream, 0);
1379 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1380 spin_lock_irq (&hmidi->lock);
1381 hmidi->input = NULL;
1382 spin_unlock_irq (&hmidi->lock);
1387 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1389 struct hdsp_midi *hmidi;
1391 snd_hdsp_midi_output_trigger (substream, 0);
1393 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1394 spin_lock_irq (&hmidi->lock);
1395 hmidi->output = NULL;
1396 spin_unlock_irq (&hmidi->lock);
1401 static struct snd_rawmidi_ops snd_hdsp_midi_output =
1403 .open = snd_hdsp_midi_output_open,
1404 .close = snd_hdsp_midi_output_close,
1405 .trigger = snd_hdsp_midi_output_trigger,
1408 static struct snd_rawmidi_ops snd_hdsp_midi_input =
1410 .open = snd_hdsp_midi_input_open,
1411 .close = snd_hdsp_midi_input_close,
1412 .trigger = snd_hdsp_midi_input_trigger,
1415 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1419 hdsp->midi[id].id = id;
1420 hdsp->midi[id].rmidi = NULL;
1421 hdsp->midi[id].input = NULL;
1422 hdsp->midi[id].output = NULL;
1423 hdsp->midi[id].hdsp = hdsp;
1424 hdsp->midi[id].istimer = 0;
1425 hdsp->midi[id].pending = 0;
1426 spin_lock_init (&hdsp->midi[id].lock);
1428 sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1429 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1432 sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1433 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1435 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1436 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1438 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1439 SNDRV_RAWMIDI_INFO_INPUT |
1440 SNDRV_RAWMIDI_INFO_DUPLEX;
1445 /*-----------------------------------------------------------------------------
1447 ----------------------------------------------------------------------------*/
1449 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1452 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1453 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1454 if (val & HDSP_SPDIFProfessional)
1455 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1457 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1461 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1463 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1464 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1465 if (val & HDSP_SPDIFProfessional)
1466 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1468 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1471 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1473 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1478 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1480 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1482 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1486 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1488 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1492 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1493 spin_lock_irq(&hdsp->lock);
1494 change = val != hdsp->creg_spdif;
1495 hdsp->creg_spdif = val;
1496 spin_unlock_irq(&hdsp->lock);
1500 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1502 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1507 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1509 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1511 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1515 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1517 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1521 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1522 spin_lock_irq(&hdsp->lock);
1523 change = val != hdsp->creg_spdif_stream;
1524 hdsp->creg_spdif_stream = val;
1525 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1526 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1527 spin_unlock_irq(&hdsp->lock);
1531 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1533 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1538 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1540 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1544 #define HDSP_SPDIF_IN(xname, xindex) \
1545 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1548 .info = snd_hdsp_info_spdif_in, \
1549 .get = snd_hdsp_get_spdif_in, \
1550 .put = snd_hdsp_put_spdif_in }
1552 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1554 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1557 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1559 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1560 hdsp->control_register |= hdsp_encode_spdif_in(in);
1561 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1565 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1567 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1568 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1570 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1572 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1573 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1574 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1575 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1579 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1581 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1583 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1587 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1589 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1593 if (!snd_hdsp_use_is_exclusive(hdsp))
1595 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1596 spin_lock_irq(&hdsp->lock);
1597 change = val != hdsp_spdif_in(hdsp);
1599 hdsp_set_spdif_input(hdsp, val);
1600 spin_unlock_irq(&hdsp->lock);
1604 #define HDSP_SPDIF_OUT(xname, xindex) \
1605 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1606 .info = snd_hdsp_info_spdif_bits, \
1607 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1609 static int hdsp_spdif_out(struct hdsp *hdsp)
1611 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1614 static int hdsp_set_spdif_output(struct hdsp *hdsp, int out)
1617 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1619 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1620 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1624 #define snd_hdsp_info_spdif_bits snd_ctl_boolean_mono_info
1626 static int snd_hdsp_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1628 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1630 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1634 static int snd_hdsp_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1636 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1640 if (!snd_hdsp_use_is_exclusive(hdsp))
1642 val = ucontrol->value.integer.value[0] & 1;
1643 spin_lock_irq(&hdsp->lock);
1644 change = (int)val != hdsp_spdif_out(hdsp);
1645 hdsp_set_spdif_output(hdsp, val);
1646 spin_unlock_irq(&hdsp->lock);
1650 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1651 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1652 .info = snd_hdsp_info_spdif_bits, \
1653 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1655 static int hdsp_spdif_professional(struct hdsp *hdsp)
1657 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1660 static int hdsp_set_spdif_professional(struct hdsp *hdsp, int val)
1663 hdsp->control_register |= HDSP_SPDIFProfessional;
1665 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1666 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1670 static int snd_hdsp_get_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1672 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1674 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1678 static int snd_hdsp_put_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1680 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1684 if (!snd_hdsp_use_is_exclusive(hdsp))
1686 val = ucontrol->value.integer.value[0] & 1;
1687 spin_lock_irq(&hdsp->lock);
1688 change = (int)val != hdsp_spdif_professional(hdsp);
1689 hdsp_set_spdif_professional(hdsp, val);
1690 spin_unlock_irq(&hdsp->lock);
1694 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1695 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1696 .info = snd_hdsp_info_spdif_bits, \
1697 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1699 static int hdsp_spdif_emphasis(struct hdsp *hdsp)
1701 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1704 static int hdsp_set_spdif_emphasis(struct hdsp *hdsp, int val)
1707 hdsp->control_register |= HDSP_SPDIFEmphasis;
1709 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1710 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1714 static int snd_hdsp_get_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1716 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1718 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1722 static int snd_hdsp_put_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1724 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1728 if (!snd_hdsp_use_is_exclusive(hdsp))
1730 val = ucontrol->value.integer.value[0] & 1;
1731 spin_lock_irq(&hdsp->lock);
1732 change = (int)val != hdsp_spdif_emphasis(hdsp);
1733 hdsp_set_spdif_emphasis(hdsp, val);
1734 spin_unlock_irq(&hdsp->lock);
1738 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1739 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1740 .info = snd_hdsp_info_spdif_bits, \
1741 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1743 static int hdsp_spdif_nonaudio(struct hdsp *hdsp)
1745 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1748 static int hdsp_set_spdif_nonaudio(struct hdsp *hdsp, int val)
1751 hdsp->control_register |= HDSP_SPDIFNonAudio;
1753 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1754 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1758 static int snd_hdsp_get_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1760 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1762 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1766 static int snd_hdsp_put_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1768 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1772 if (!snd_hdsp_use_is_exclusive(hdsp))
1774 val = ucontrol->value.integer.value[0] & 1;
1775 spin_lock_irq(&hdsp->lock);
1776 change = (int)val != hdsp_spdif_nonaudio(hdsp);
1777 hdsp_set_spdif_nonaudio(hdsp, val);
1778 spin_unlock_irq(&hdsp->lock);
1782 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1783 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1786 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1787 .info = snd_hdsp_info_spdif_sample_rate, \
1788 .get = snd_hdsp_get_spdif_sample_rate \
1791 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1793 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1794 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1796 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1798 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1799 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1800 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1801 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1805 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1807 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1809 switch (hdsp_spdif_sample_rate(hdsp)) {
1811 ucontrol->value.enumerated.item[0] = 0;
1814 ucontrol->value.enumerated.item[0] = 1;
1817 ucontrol->value.enumerated.item[0] = 2;
1820 ucontrol->value.enumerated.item[0] = 3;
1823 ucontrol->value.enumerated.item[0] = 4;
1826 ucontrol->value.enumerated.item[0] = 5;
1829 ucontrol->value.enumerated.item[0] = 7;
1832 ucontrol->value.enumerated.item[0] = 8;
1835 ucontrol->value.enumerated.item[0] = 9;
1838 ucontrol->value.enumerated.item[0] = 6;
1843 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1844 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1847 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1848 .info = snd_hdsp_info_system_sample_rate, \
1849 .get = snd_hdsp_get_system_sample_rate \
1852 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1854 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1859 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1861 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1863 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1867 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1868 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1871 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1872 .info = snd_hdsp_info_autosync_sample_rate, \
1873 .get = snd_hdsp_get_autosync_sample_rate \
1876 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1878 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1879 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1880 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1882 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1883 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1884 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1885 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1889 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1891 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1893 switch (hdsp_external_sample_rate(hdsp)) {
1895 ucontrol->value.enumerated.item[0] = 0;
1898 ucontrol->value.enumerated.item[0] = 1;
1901 ucontrol->value.enumerated.item[0] = 2;
1904 ucontrol->value.enumerated.item[0] = 3;
1907 ucontrol->value.enumerated.item[0] = 4;
1910 ucontrol->value.enumerated.item[0] = 5;
1913 ucontrol->value.enumerated.item[0] = 7;
1916 ucontrol->value.enumerated.item[0] = 8;
1919 ucontrol->value.enumerated.item[0] = 9;
1922 ucontrol->value.enumerated.item[0] = 6;
1927 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1928 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1931 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1932 .info = snd_hdsp_info_system_clock_mode, \
1933 .get = snd_hdsp_get_system_clock_mode \
1936 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1938 if (hdsp->control_register & HDSP_ClockModeMaster)
1940 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1945 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1947 static char *texts[] = {"Master", "Slave" };
1949 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1951 uinfo->value.enumerated.items = 2;
1952 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1953 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1954 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1958 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1960 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1962 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1966 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1967 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1970 .info = snd_hdsp_info_clock_source, \
1971 .get = snd_hdsp_get_clock_source, \
1972 .put = snd_hdsp_put_clock_source \
1975 static int hdsp_clock_source(struct hdsp *hdsp)
1977 if (hdsp->control_register & HDSP_ClockModeMaster) {
1978 switch (hdsp->system_sample_rate) {
2005 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
2009 case HDSP_CLOCK_SOURCE_AUTOSYNC:
2010 if (hdsp_external_sample_rate(hdsp) != 0) {
2011 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2012 hdsp->control_register &= ~HDSP_ClockModeMaster;
2013 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2018 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2021 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2024 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2027 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2030 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2033 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2036 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2039 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2042 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2048 hdsp->control_register |= HDSP_ClockModeMaster;
2049 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2050 hdsp_set_rate(hdsp, rate, 1);
2054 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2056 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2057 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2059 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2061 if (hdsp->io_type == H9632)
2062 uinfo->value.enumerated.items = 10;
2064 uinfo->value.enumerated.items = 7;
2065 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2066 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2067 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2071 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2073 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2075 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2079 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2081 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2085 if (!snd_hdsp_use_is_exclusive(hdsp))
2087 val = ucontrol->value.enumerated.item[0];
2088 if (val < 0) val = 0;
2089 if (hdsp->io_type == H9632) {
2096 spin_lock_irq(&hdsp->lock);
2097 if (val != hdsp_clock_source(hdsp))
2098 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2101 spin_unlock_irq(&hdsp->lock);
2105 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2107 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2109 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2111 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2115 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2117 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2120 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2122 hdsp->clock_source_locked = ucontrol->value.integer.value[0];
2126 #define HDSP_DA_GAIN(xname, xindex) \
2127 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2130 .info = snd_hdsp_info_da_gain, \
2131 .get = snd_hdsp_get_da_gain, \
2132 .put = snd_hdsp_put_da_gain \
2135 static int hdsp_da_gain(struct hdsp *hdsp)
2137 switch (hdsp->control_register & HDSP_DAGainMask) {
2138 case HDSP_DAGainHighGain:
2140 case HDSP_DAGainPlus4dBu:
2142 case HDSP_DAGainMinus10dBV:
2149 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2151 hdsp->control_register &= ~HDSP_DAGainMask;
2154 hdsp->control_register |= HDSP_DAGainHighGain;
2157 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2160 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2166 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2170 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2172 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2174 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2176 uinfo->value.enumerated.items = 3;
2177 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2178 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2179 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2183 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2185 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2187 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2191 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2193 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2197 if (!snd_hdsp_use_is_exclusive(hdsp))
2199 val = ucontrol->value.enumerated.item[0];
2200 if (val < 0) val = 0;
2201 if (val > 2) val = 2;
2202 spin_lock_irq(&hdsp->lock);
2203 if (val != hdsp_da_gain(hdsp))
2204 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2207 spin_unlock_irq(&hdsp->lock);
2211 #define HDSP_AD_GAIN(xname, xindex) \
2212 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2215 .info = snd_hdsp_info_ad_gain, \
2216 .get = snd_hdsp_get_ad_gain, \
2217 .put = snd_hdsp_put_ad_gain \
2220 static int hdsp_ad_gain(struct hdsp *hdsp)
2222 switch (hdsp->control_register & HDSP_ADGainMask) {
2223 case HDSP_ADGainMinus10dBV:
2225 case HDSP_ADGainPlus4dBu:
2227 case HDSP_ADGainLowGain:
2234 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2236 hdsp->control_register &= ~HDSP_ADGainMask;
2239 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2242 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2245 hdsp->control_register |= HDSP_ADGainLowGain;
2251 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2255 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2257 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2259 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2261 uinfo->value.enumerated.items = 3;
2262 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2263 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2264 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2268 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2270 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2272 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2276 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2278 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2282 if (!snd_hdsp_use_is_exclusive(hdsp))
2284 val = ucontrol->value.enumerated.item[0];
2285 if (val < 0) val = 0;
2286 if (val > 2) val = 2;
2287 spin_lock_irq(&hdsp->lock);
2288 if (val != hdsp_ad_gain(hdsp))
2289 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2292 spin_unlock_irq(&hdsp->lock);
2296 #define HDSP_PHONE_GAIN(xname, xindex) \
2297 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2300 .info = snd_hdsp_info_phone_gain, \
2301 .get = snd_hdsp_get_phone_gain, \
2302 .put = snd_hdsp_put_phone_gain \
2305 static int hdsp_phone_gain(struct hdsp *hdsp)
2307 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2308 case HDSP_PhoneGain0dB:
2310 case HDSP_PhoneGainMinus6dB:
2312 case HDSP_PhoneGainMinus12dB:
2319 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2321 hdsp->control_register &= ~HDSP_PhoneGainMask;
2324 hdsp->control_register |= HDSP_PhoneGain0dB;
2327 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2330 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2336 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2340 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2342 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2344 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2346 uinfo->value.enumerated.items = 3;
2347 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2348 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2349 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2353 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2355 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2357 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2361 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2363 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2367 if (!snd_hdsp_use_is_exclusive(hdsp))
2369 val = ucontrol->value.enumerated.item[0];
2370 if (val < 0) val = 0;
2371 if (val > 2) val = 2;
2372 spin_lock_irq(&hdsp->lock);
2373 if (val != hdsp_phone_gain(hdsp))
2374 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2377 spin_unlock_irq(&hdsp->lock);
2381 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2382 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2385 .info = snd_hdsp_info_xlr_breakout_cable, \
2386 .get = snd_hdsp_get_xlr_breakout_cable, \
2387 .put = snd_hdsp_put_xlr_breakout_cable \
2390 static int hdsp_xlr_breakout_cable(struct hdsp *hdsp)
2392 if (hdsp->control_register & HDSP_XLRBreakoutCable)
2397 static int hdsp_set_xlr_breakout_cable(struct hdsp *hdsp, int mode)
2400 hdsp->control_register |= HDSP_XLRBreakoutCable;
2402 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2403 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2407 #define snd_hdsp_info_xlr_breakout_cable snd_ctl_boolean_mono_info
2409 static int snd_hdsp_get_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2411 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2413 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2417 static int snd_hdsp_put_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2419 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2423 if (!snd_hdsp_use_is_exclusive(hdsp))
2425 val = ucontrol->value.integer.value[0] & 1;
2426 spin_lock_irq(&hdsp->lock);
2427 change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2428 hdsp_set_xlr_breakout_cable(hdsp, val);
2429 spin_unlock_irq(&hdsp->lock);
2433 /* (De)activates old RME Analog Extension Board
2434 These are connected to the internal ADAT connector
2435 Switching this on desactivates external ADAT
2437 #define HDSP_AEB(xname, xindex) \
2438 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2441 .info = snd_hdsp_info_aeb, \
2442 .get = snd_hdsp_get_aeb, \
2443 .put = snd_hdsp_put_aeb \
2446 static int hdsp_aeb(struct hdsp *hdsp)
2448 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
2453 static int hdsp_set_aeb(struct hdsp *hdsp, int mode)
2456 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2458 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2459 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2463 #define snd_hdsp_info_aeb snd_ctl_boolean_mono_info
2465 static int snd_hdsp_get_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2467 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2469 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2473 static int snd_hdsp_put_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2475 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2479 if (!snd_hdsp_use_is_exclusive(hdsp))
2481 val = ucontrol->value.integer.value[0] & 1;
2482 spin_lock_irq(&hdsp->lock);
2483 change = (int)val != hdsp_aeb(hdsp);
2484 hdsp_set_aeb(hdsp, val);
2485 spin_unlock_irq(&hdsp->lock);
2489 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2490 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2493 .info = snd_hdsp_info_pref_sync_ref, \
2494 .get = snd_hdsp_get_pref_sync_ref, \
2495 .put = snd_hdsp_put_pref_sync_ref \
2498 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2500 /* Notice that this looks at the requested sync source,
2501 not the one actually in use.
2504 switch (hdsp->control_register & HDSP_SyncRefMask) {
2505 case HDSP_SyncRef_ADAT1:
2506 return HDSP_SYNC_FROM_ADAT1;
2507 case HDSP_SyncRef_ADAT2:
2508 return HDSP_SYNC_FROM_ADAT2;
2509 case HDSP_SyncRef_ADAT3:
2510 return HDSP_SYNC_FROM_ADAT3;
2511 case HDSP_SyncRef_SPDIF:
2512 return HDSP_SYNC_FROM_SPDIF;
2513 case HDSP_SyncRef_WORD:
2514 return HDSP_SYNC_FROM_WORD;
2515 case HDSP_SyncRef_ADAT_SYNC:
2516 return HDSP_SYNC_FROM_ADAT_SYNC;
2518 return HDSP_SYNC_FROM_WORD;
2523 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2525 hdsp->control_register &= ~HDSP_SyncRefMask;
2527 case HDSP_SYNC_FROM_ADAT1:
2528 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2530 case HDSP_SYNC_FROM_ADAT2:
2531 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2533 case HDSP_SYNC_FROM_ADAT3:
2534 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2536 case HDSP_SYNC_FROM_SPDIF:
2537 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2539 case HDSP_SYNC_FROM_WORD:
2540 hdsp->control_register |= HDSP_SyncRef_WORD;
2542 case HDSP_SYNC_FROM_ADAT_SYNC:
2543 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2548 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2552 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2554 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2555 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2557 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2560 switch (hdsp->io_type) {
2563 uinfo->value.enumerated.items = 6;
2566 uinfo->value.enumerated.items = 4;
2569 uinfo->value.enumerated.items = 3;
2572 uinfo->value.enumerated.items = 0;
2576 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2577 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2578 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2582 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2584 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2586 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2590 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2592 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2596 if (!snd_hdsp_use_is_exclusive(hdsp))
2599 switch (hdsp->io_type) {
2614 val = ucontrol->value.enumerated.item[0] % max;
2615 spin_lock_irq(&hdsp->lock);
2616 change = (int)val != hdsp_pref_sync_ref(hdsp);
2617 hdsp_set_pref_sync_ref(hdsp, val);
2618 spin_unlock_irq(&hdsp->lock);
2622 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2623 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2626 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2627 .info = snd_hdsp_info_autosync_ref, \
2628 .get = snd_hdsp_get_autosync_ref, \
2631 static int hdsp_autosync_ref(struct hdsp *hdsp)
2633 /* This looks at the autosync selected sync reference */
2634 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2636 switch (status2 & HDSP_SelSyncRefMask) {
2637 case HDSP_SelSyncRef_WORD:
2638 return HDSP_AUTOSYNC_FROM_WORD;
2639 case HDSP_SelSyncRef_ADAT_SYNC:
2640 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2641 case HDSP_SelSyncRef_SPDIF:
2642 return HDSP_AUTOSYNC_FROM_SPDIF;
2643 case HDSP_SelSyncRefMask:
2644 return HDSP_AUTOSYNC_FROM_NONE;
2645 case HDSP_SelSyncRef_ADAT1:
2646 return HDSP_AUTOSYNC_FROM_ADAT1;
2647 case HDSP_SelSyncRef_ADAT2:
2648 return HDSP_AUTOSYNC_FROM_ADAT2;
2649 case HDSP_SelSyncRef_ADAT3:
2650 return HDSP_AUTOSYNC_FROM_ADAT3;
2652 return HDSP_AUTOSYNC_FROM_WORD;
2657 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2659 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2661 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2663 uinfo->value.enumerated.items = 7;
2664 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2665 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2666 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2670 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2672 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2674 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2678 #define HDSP_LINE_OUT(xname, xindex) \
2679 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2682 .info = snd_hdsp_info_line_out, \
2683 .get = snd_hdsp_get_line_out, \
2684 .put = snd_hdsp_put_line_out \
2687 static int hdsp_line_out(struct hdsp *hdsp)
2689 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2692 static int hdsp_set_line_output(struct hdsp *hdsp, int out)
2695 hdsp->control_register |= HDSP_LineOut;
2697 hdsp->control_register &= ~HDSP_LineOut;
2698 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2702 #define snd_hdsp_info_line_out snd_ctl_boolean_mono_info
2704 static int snd_hdsp_get_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2706 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2708 spin_lock_irq(&hdsp->lock);
2709 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2710 spin_unlock_irq(&hdsp->lock);
2714 static int snd_hdsp_put_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2716 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2720 if (!snd_hdsp_use_is_exclusive(hdsp))
2722 val = ucontrol->value.integer.value[0] & 1;
2723 spin_lock_irq(&hdsp->lock);
2724 change = (int)val != hdsp_line_out(hdsp);
2725 hdsp_set_line_output(hdsp, val);
2726 spin_unlock_irq(&hdsp->lock);
2730 #define HDSP_PRECISE_POINTER(xname, xindex) \
2731 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2734 .info = snd_hdsp_info_precise_pointer, \
2735 .get = snd_hdsp_get_precise_pointer, \
2736 .put = snd_hdsp_put_precise_pointer \
2739 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2742 hdsp->precise_ptr = 1;
2744 hdsp->precise_ptr = 0;
2748 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2750 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2752 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2754 spin_lock_irq(&hdsp->lock);
2755 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2756 spin_unlock_irq(&hdsp->lock);
2760 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2762 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2766 if (!snd_hdsp_use_is_exclusive(hdsp))
2768 val = ucontrol->value.integer.value[0] & 1;
2769 spin_lock_irq(&hdsp->lock);
2770 change = (int)val != hdsp->precise_ptr;
2771 hdsp_set_precise_pointer(hdsp, val);
2772 spin_unlock_irq(&hdsp->lock);
2776 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2777 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2780 .info = snd_hdsp_info_use_midi_tasklet, \
2781 .get = snd_hdsp_get_use_midi_tasklet, \
2782 .put = snd_hdsp_put_use_midi_tasklet \
2785 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2788 hdsp->use_midi_tasklet = 1;
2790 hdsp->use_midi_tasklet = 0;
2794 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
2796 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2798 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2800 spin_lock_irq(&hdsp->lock);
2801 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2802 spin_unlock_irq(&hdsp->lock);
2806 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2808 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2812 if (!snd_hdsp_use_is_exclusive(hdsp))
2814 val = ucontrol->value.integer.value[0] & 1;
2815 spin_lock_irq(&hdsp->lock);
2816 change = (int)val != hdsp->use_midi_tasklet;
2817 hdsp_set_use_midi_tasklet(hdsp, val);
2818 spin_unlock_irq(&hdsp->lock);
2822 #define HDSP_MIXER(xname, xindex) \
2823 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2827 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2828 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2829 .info = snd_hdsp_info_mixer, \
2830 .get = snd_hdsp_get_mixer, \
2831 .put = snd_hdsp_put_mixer \
2834 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2836 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2838 uinfo->value.integer.min = 0;
2839 uinfo->value.integer.max = 65536;
2840 uinfo->value.integer.step = 1;
2844 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2846 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2851 source = ucontrol->value.integer.value[0];
2852 destination = ucontrol->value.integer.value[1];
2854 if (source >= hdsp->max_channels)
2855 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2857 addr = hdsp_input_to_output_key(hdsp,source, destination);
2859 spin_lock_irq(&hdsp->lock);
2860 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2861 spin_unlock_irq(&hdsp->lock);
2865 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2867 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2874 if (!snd_hdsp_use_is_exclusive(hdsp))
2877 source = ucontrol->value.integer.value[0];
2878 destination = ucontrol->value.integer.value[1];
2880 if (source >= hdsp->max_channels)
2881 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2883 addr = hdsp_input_to_output_key(hdsp,source, destination);
2885 gain = ucontrol->value.integer.value[2];
2887 spin_lock_irq(&hdsp->lock);
2888 change = gain != hdsp_read_gain(hdsp, addr);
2890 hdsp_write_gain(hdsp, addr, gain);
2891 spin_unlock_irq(&hdsp->lock);
2895 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2896 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2899 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2900 .info = snd_hdsp_info_sync_check, \
2901 .get = snd_hdsp_get_wc_sync_check \
2904 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2906 static char *texts[] = {"No Lock", "Lock", "Sync" };
2907 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2909 uinfo->value.enumerated.items = 3;
2910 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2911 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2912 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2916 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2918 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2919 if (status2 & HDSP_wc_lock) {
2920 if (status2 & HDSP_wc_sync)
2929 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2931 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2933 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2937 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2938 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2941 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2942 .info = snd_hdsp_info_sync_check, \
2943 .get = snd_hdsp_get_spdif_sync_check \
2946 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2948 int status = hdsp_read(hdsp, HDSP_statusRegister);
2949 if (status & HDSP_SPDIFErrorFlag)
2952 if (status & HDSP_SPDIFSync)
2960 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2962 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2964 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2968 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2969 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2972 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2973 .info = snd_hdsp_info_sync_check, \
2974 .get = snd_hdsp_get_adatsync_sync_check \
2977 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2979 int status = hdsp_read(hdsp, HDSP_statusRegister);
2980 if (status & HDSP_TimecodeLock) {
2981 if (status & HDSP_TimecodeSync)
2989 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2991 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2993 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2997 #define HDSP_ADAT_SYNC_CHECK \
2998 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2999 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3000 .info = snd_hdsp_info_sync_check, \
3001 .get = snd_hdsp_get_adat_sync_check \
3004 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
3006 int status = hdsp_read(hdsp, HDSP_statusRegister);
3008 if (status & (HDSP_Lock0>>idx)) {
3009 if (status & (HDSP_Sync0>>idx))
3017 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3020 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3022 offset = ucontrol->id.index - 1;
3023 snd_assert(offset >= 0);
3025 switch (hdsp->io_type) {
3040 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3044 #define HDSP_DDS_OFFSET(xname, xindex) \
3045 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3048 .info = snd_hdsp_info_dds_offset, \
3049 .get = snd_hdsp_get_dds_offset, \
3050 .put = snd_hdsp_put_dds_offset \
3053 static int hdsp_dds_offset(struct hdsp *hdsp)
3057 unsigned int dds_value = hdsp->dds_value;
3058 int system_sample_rate = hdsp->system_sample_rate;
3065 * dds_value = n / rate
3066 * rate = n / dds_value
3068 div64_32(&n, dds_value, &r);
3069 if (system_sample_rate >= 112000)
3071 else if (system_sample_rate >= 56000)
3073 return ((int)n) - system_sample_rate;
3076 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
3078 int rate = hdsp->system_sample_rate + offset_hz;
3079 hdsp_set_dds_value(hdsp, rate);
3083 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3085 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3087 uinfo->value.integer.min = -5000;
3088 uinfo->value.integer.max = 5000;
3092 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3094 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3096 ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp);
3100 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3102 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3106 if (!snd_hdsp_use_is_exclusive(hdsp))
3108 val = ucontrol->value.enumerated.item[0];
3109 spin_lock_irq(&hdsp->lock);
3110 if (val != hdsp_dds_offset(hdsp))
3111 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
3114 spin_unlock_irq(&hdsp->lock);
3118 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
3119 HDSP_DA_GAIN("DA Gain", 0),
3120 HDSP_AD_GAIN("AD Gain", 0),
3121 HDSP_PHONE_GAIN("Phones Gain", 0),
3122 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0),
3123 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
3126 static struct snd_kcontrol_new snd_hdsp_controls[] = {
3128 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3129 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3130 .info = snd_hdsp_control_spdif_info,
3131 .get = snd_hdsp_control_spdif_get,
3132 .put = snd_hdsp_control_spdif_put,
3135 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3136 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3137 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3138 .info = snd_hdsp_control_spdif_stream_info,
3139 .get = snd_hdsp_control_spdif_stream_get,
3140 .put = snd_hdsp_control_spdif_stream_put,
3143 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3144 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3145 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3146 .info = snd_hdsp_control_spdif_mask_info,
3147 .get = snd_hdsp_control_spdif_mask_get,
3148 .private_value = IEC958_AES0_NONAUDIO |
3149 IEC958_AES0_PROFESSIONAL |
3150 IEC958_AES0_CON_EMPHASIS,
3153 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3154 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3155 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3156 .info = snd_hdsp_control_spdif_mask_info,
3157 .get = snd_hdsp_control_spdif_mask_get,
3158 .private_value = IEC958_AES0_NONAUDIO |
3159 IEC958_AES0_PROFESSIONAL |
3160 IEC958_AES0_PRO_EMPHASIS,
3162 HDSP_MIXER("Mixer", 0),
3163 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3164 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3165 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3166 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3167 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3168 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3169 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3171 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3172 .name = "Sample Clock Source Locking",
3173 .info = snd_hdsp_info_clock_source_lock,
3174 .get = snd_hdsp_get_clock_source_lock,
3175 .put = snd_hdsp_put_clock_source_lock,
3177 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3178 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3179 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3180 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3181 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3182 /* 'External Rate' complies with the alsa control naming scheme */
3183 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3184 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3185 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3186 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3187 HDSP_LINE_OUT("Line Out", 0),
3188 HDSP_PRECISE_POINTER("Precise Pointer", 0),
3189 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
3192 static struct snd_kcontrol_new snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3193 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3195 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3199 struct snd_kcontrol *kctl;
3201 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3202 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3204 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3205 hdsp->spdif_ctl = kctl;
3208 /* ADAT SyncCheck status */
3209 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3210 snd_hdsp_adat_sync_check.index = 1;
3211 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3213 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3214 for (idx = 1; idx < 3; ++idx) {
3215 snd_hdsp_adat_sync_check.index = idx+1;
3216 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3221 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3222 if (hdsp->io_type == H9632) {
3223 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3224 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3229 /* AEB control for H96xx card */
3230 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3231 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3238 /*------------------------------------------------------------
3240 ------------------------------------------------------------*/
3243 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3245 struct hdsp *hdsp = (struct hdsp *) entry->private_data;
3246 unsigned int status;
3247 unsigned int status2;
3248 char *pref_sync_ref;
3250 char *system_clock_mode;
3254 if (hdsp_check_for_iobox (hdsp)) {
3255 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3259 if (hdsp_check_for_firmware(hdsp, 0)) {
3260 if (hdsp->state & HDSP_FirmwareCached) {
3261 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3262 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3267 #ifdef HDSP_FW_LOADER
3268 err = hdsp_request_fw_loader(hdsp);
3272 "No firmware loaded nor cached, "
3273 "please upload firmware.\n");
3279 status = hdsp_read(hdsp, HDSP_statusRegister);
3280 status2 = hdsp_read(hdsp, HDSP_status2Register);
3282 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3283 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3284 hdsp->capture_buffer, hdsp->playback_buffer);
3285 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3286 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3287 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3288 snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3289 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3290 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3291 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3292 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3293 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3294 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3295 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3296 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3298 snd_iprintf(buffer, "\n");
3300 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3302 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3303 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3304 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3305 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3307 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3309 snd_iprintf(buffer, "\n");
3312 switch (hdsp_clock_source(hdsp)) {
3313 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3314 clock_source = "AutoSync";
3316 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3317 clock_source = "Internal 32 kHz";
3319 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3320 clock_source = "Internal 44.1 kHz";
3322 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3323 clock_source = "Internal 48 kHz";
3325 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3326 clock_source = "Internal 64 kHz";
3328 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3329 clock_source = "Internal 88.2 kHz";
3331 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3332 clock_source = "Internal 96 kHz";
3334 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3335 clock_source = "Internal 128 kHz";
3337 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3338 clock_source = "Internal 176.4 kHz";
3340 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3341 clock_source = "Internal 192 kHz";
3344 clock_source = "Error";
3346 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3348 if (hdsp_system_clock_mode(hdsp))
3349 system_clock_mode = "Slave";
3351 system_clock_mode = "Master";
3353 switch (hdsp_pref_sync_ref (hdsp)) {
3354 case HDSP_SYNC_FROM_WORD:
3355 pref_sync_ref = "Word Clock";
3357 case HDSP_SYNC_FROM_ADAT_SYNC:
3358 pref_sync_ref = "ADAT Sync";
3360 case HDSP_SYNC_FROM_SPDIF:
3361 pref_sync_ref = "SPDIF";
3363 case HDSP_SYNC_FROM_ADAT1:
3364 pref_sync_ref = "ADAT1";
3366 case HDSP_SYNC_FROM_ADAT2:
3367 pref_sync_ref = "ADAT2";
3369 case HDSP_SYNC_FROM_ADAT3:
3370 pref_sync_ref = "ADAT3";
3373 pref_sync_ref = "Word Clock";
3376 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3378 switch (hdsp_autosync_ref (hdsp)) {
3379 case HDSP_AUTOSYNC_FROM_WORD:
3380 autosync_ref = "Word Clock";
3382 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3383 autosync_ref = "ADAT Sync";
3385 case HDSP_AUTOSYNC_FROM_SPDIF:
3386 autosync_ref = "SPDIF";
3388 case HDSP_AUTOSYNC_FROM_NONE:
3389 autosync_ref = "None";
3391 case HDSP_AUTOSYNC_FROM_ADAT1:
3392 autosync_ref = "ADAT1";
3394 case HDSP_AUTOSYNC_FROM_ADAT2:
3395 autosync_ref = "ADAT2";
3397 case HDSP_AUTOSYNC_FROM_ADAT3:
3398 autosync_ref = "ADAT3";
3401 autosync_ref = "---";
3404 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3406 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3408 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3410 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3411 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3413 snd_iprintf(buffer, "\n");
3415 switch (hdsp_spdif_in(hdsp)) {
3416 case HDSP_SPDIFIN_OPTICAL:
3417 snd_iprintf(buffer, "IEC958 input: Optical\n");
3419 case HDSP_SPDIFIN_COAXIAL:
3420 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3422 case HDSP_SPDIFIN_INTERNAL:
3423 snd_iprintf(buffer, "IEC958 input: Internal\n");
3425 case HDSP_SPDIFIN_AES:
3426 snd_iprintf(buffer, "IEC958 input: AES\n");
3429 snd_iprintf(buffer, "IEC958 input: ???\n");
3433 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3434 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3436 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3438 if (hdsp->control_register & HDSP_SPDIFProfessional)
3439 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3441 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3443 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3444 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3446 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3448 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3449 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3451 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3452 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0)
3453 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3455 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3457 snd_iprintf(buffer, "\n");
3460 x = status & HDSP_Sync0;
3461 if (status & HDSP_Lock0)
3462 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3464 snd_iprintf(buffer, "ADAT1: No Lock\n");
3466 switch (hdsp->io_type) {
3469 x = status & HDSP_Sync1;
3470 if (status & HDSP_Lock1)
3471 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3473 snd_iprintf(buffer, "ADAT2: No Lock\n");
3474 x = status & HDSP_Sync2;
3475 if (status & HDSP_Lock2)
3476 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3478 snd_iprintf(buffer, "ADAT3: No Lock\n");
3485 x = status & HDSP_SPDIFSync;
3486 if (status & HDSP_SPDIFErrorFlag)
3487 snd_iprintf (buffer, "SPDIF: No Lock\n");
3489 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3491 x = status2 & HDSP_wc_sync;
3492 if (status2 & HDSP_wc_lock)
3493 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3495 snd_iprintf (buffer, "Word Clock: No Lock\n");
3497 x = status & HDSP_TimecodeSync;
3498 if (status & HDSP_TimecodeLock)
3499 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3501 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3503 snd_iprintf(buffer, "\n");
3505 /* Informations about H9632 specific controls */
3506 if (hdsp->io_type == H9632) {
3509 switch (hdsp_ad_gain(hdsp)) {
3520 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3522 switch (hdsp_da_gain(hdsp)) {
3533 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3535 switch (hdsp_phone_gain(hdsp)) {
3546 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3548 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3550 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3551 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3553 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3554 snd_iprintf(buffer, "\n");
3559 static void __devinit snd_hdsp_proc_init(struct hdsp *hdsp)
3561 struct snd_info_entry *entry;
3563 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3564 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3567 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3569 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3570 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3573 static int __devinit snd_hdsp_initialize_memory(struct hdsp *hdsp)
3575 unsigned long pb_bus, cb_bus;
3577 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3578 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3579 if (hdsp->capture_dma_buf.area)
3580 snd_dma_free_pages(&hdsp->capture_dma_buf);
3581 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3585 /* Align to bus-space 64K boundary */
3587 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3588 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3590 /* Tell the card where it is */
3592 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3593 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3595 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3596 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3601 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3605 /* ASSUMPTION: hdsp->lock is either held, or
3606 there is no need to hold it (e.g. during module
3612 SPDIF Input via Coax
3614 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3615 which implies 2 4096 sample, 32Kbyte periods).
3619 hdsp->control_register = HDSP_ClockModeMaster |
3620 HDSP_SPDIFInputCoaxial |
3621 hdsp_encode_latency(7) |
3625 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3627 #ifdef SNDRV_BIG_ENDIAN
3628 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3630 hdsp->control2_register = 0;
3632 if (hdsp->io_type == H9652)
3633 snd_hdsp_9652_enable_mixer (hdsp);
3635 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3637 hdsp_reset_hw_pointer(hdsp);
3638 hdsp_compute_period_size(hdsp);
3640 /* silence everything */
3642 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3643 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3645 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3646 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3650 /* H9632 specific defaults */
3651 if (hdsp->io_type == H9632) {
3652 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3653 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3656 /* set a default rate so that the channel map is set up.
3659 hdsp_set_rate(hdsp, 48000, 1);
3664 static void hdsp_midi_tasklet(unsigned long arg)
3666 struct hdsp *hdsp = (struct hdsp *)arg;
3668 if (hdsp->midi[0].pending)
3669 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3670 if (hdsp->midi[1].pending)
3671 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3674 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3676 struct hdsp *hdsp = (struct hdsp *) dev_id;
3677 unsigned int status;
3681 unsigned int midi0status;
3682 unsigned int midi1status;
3685 status = hdsp_read(hdsp, HDSP_statusRegister);
3687 audio = status & HDSP_audioIRQPending;
3688 midi0 = status & HDSP_midi0IRQPending;
3689 midi1 = status & HDSP_midi1IRQPending;
3691 if (!audio && !midi0 && !midi1)
3694 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3696 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3697 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3700 if (hdsp->capture_substream)
3701 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3703 if (hdsp->playback_substream)
3704 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3707 if (midi0 && midi0status) {
3708 if (hdsp->use_midi_tasklet) {
3709 /* we disable interrupts for this input until processing is done */
3710 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3711 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3712 hdsp->midi[0].pending = 1;
3715 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3718 if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) {
3719 if (hdsp->use_midi_tasklet) {
3720 /* we disable interrupts for this input until processing is done */
3721 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3722 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3723 hdsp->midi[1].pending = 1;
3726 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3729 if (hdsp->use_midi_tasklet && schedule)
3730 tasklet_hi_schedule(&hdsp->midi_tasklet);
3734 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3736 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3737 return hdsp_hw_pointer(hdsp);
3740 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3747 snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3749 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3752 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3753 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3755 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3758 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
3759 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3761 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3764 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3766 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3767 snd_assert(channel_buf != NULL, return -EIO);
3768 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3773 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
3774 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3776 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3779 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3781 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3782 snd_assert(channel_buf != NULL, return -EIO);
3783 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3788 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
3789 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3791 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3794 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3795 snd_assert(channel_buf != NULL, return -EIO);
3796 memset(channel_buf + pos * 4, 0, count * 4);
3800 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3802 struct snd_pcm_runtime *runtime = substream->runtime;
3803 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3804 struct snd_pcm_substream *other;
3805 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3806 other = hdsp->capture_substream;
3808 other = hdsp->playback_substream;
3810 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3812 runtime->status->hw_ptr = 0;
3814 struct snd_pcm_substream *s;
3815 struct snd_pcm_runtime *oruntime = other->runtime;
3816 snd_pcm_group_for_each_entry(s, substream) {
3818 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3826 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3827 struct snd_pcm_hw_params *params)
3829 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3834 if (hdsp_check_for_iobox (hdsp))
3837 if (hdsp_check_for_firmware(hdsp, 1))
3840 spin_lock_irq(&hdsp->lock);
3842 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3843 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3844 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3845 this_pid = hdsp->playback_pid;
3846 other_pid = hdsp->capture_pid;
3848 this_pid = hdsp->capture_pid;
3849 other_pid = hdsp->playback_pid;
3852 if ((other_pid > 0) && (this_pid != other_pid)) {
3854 /* The other stream is open, and not by the same
3855 task as this one. Make sure that the parameters
3856 that matter are the same.
3859 if (params_rate(params) != hdsp->system_sample_rate) {
3860 spin_unlock_irq(&hdsp->lock);
3861 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3865 if (params_period_size(params) != hdsp->period_bytes / 4) {
3866 spin_unlock_irq(&hdsp->lock);
3867 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3873 spin_unlock_irq(&hdsp->lock);
3877 spin_unlock_irq(&hdsp->lock);
3880 /* how to make sure that the rate matches an externally-set one ?
3883 spin_lock_irq(&hdsp->lock);
3884 if (! hdsp->clock_source_locked) {
3885 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3886 spin_unlock_irq(&hdsp->lock);
3887 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3891 spin_unlock_irq(&hdsp->lock);
3893 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3894 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3901 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
3902 struct snd_pcm_channel_info *info)
3904 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3907 snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3909 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0)
3912 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3918 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
3919 unsigned int cmd, void *arg)
3922 case SNDRV_PCM_IOCTL1_RESET:
3923 return snd_hdsp_reset(substream);
3924 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3925 return snd_hdsp_channel_info(substream, arg);
3930 return snd_pcm_lib_ioctl(substream, cmd, arg);
3933 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
3935 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3936 struct snd_pcm_substream *other;
3939 if (hdsp_check_for_iobox (hdsp))
3942 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
3945 spin_lock(&hdsp->lock);
3946 running = hdsp->running;
3948 case SNDRV_PCM_TRIGGER_START:
3949 running |= 1 << substream->stream;
3951 case SNDRV_PCM_TRIGGER_STOP:
3952 running &= ~(1 << substream->stream);
3956 spin_unlock(&hdsp->lock);
3959 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3960 other = hdsp->capture_substream;
3962 other = hdsp->playback_substream;
3965 struct snd_pcm_substream *s;
3966 snd_pcm_group_for_each_entry(s, substream) {
3968 snd_pcm_trigger_done(s, substream);
3969 if (cmd == SNDRV_PCM_TRIGGER_START)
3970 running |= 1 << s->stream;
3972 running &= ~(1 << s->stream);
3976 if (cmd == SNDRV_PCM_TRIGGER_START) {
3977 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
3978 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3979 hdsp_silence_playback(hdsp);
3982 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3983 hdsp_silence_playback(hdsp);
3986 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3987 hdsp_silence_playback(hdsp);
3990 snd_pcm_trigger_done(substream, substream);
3991 if (!hdsp->running && running)
3992 hdsp_start_audio(hdsp);
3993 else if (hdsp->running && !running)
3994 hdsp_stop_audio(hdsp);
3995 hdsp->running = running;
3996 spin_unlock(&hdsp->lock);
4001 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4003 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4006 if (hdsp_check_for_iobox (hdsp))
4009 if (hdsp_check_for_firmware(hdsp, 1))
4012 spin_lock_irq(&hdsp->lock);
4014 hdsp_reset_hw_pointer(hdsp);
4015 spin_unlock_irq(&hdsp->lock);
4019 static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4021 .info = (SNDRV_PCM_INFO_MMAP |
4022 SNDRV_PCM_INFO_MMAP_VALID |
4023 SNDRV_PCM_INFO_NONINTERLEAVED |
4024 SNDRV_PCM_INFO_SYNC_START |
4025 SNDRV_PCM_INFO_DOUBLE),
4026 #ifdef SNDRV_BIG_ENDIAN
4027 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4029 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4031 .rates = (SNDRV_PCM_RATE_32000 |
4032 SNDRV_PCM_RATE_44100 |
4033 SNDRV_PCM_RATE_48000 |
4034 SNDRV_PCM_RATE_64000 |
4035 SNDRV_PCM_RATE_88200 |
4036 SNDRV_PCM_RATE_96000),
4040 .channels_max = HDSP_MAX_CHANNELS,
4041 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4042 .period_bytes_min = (64 * 4) * 10,
4043 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4049 static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4051 .info = (SNDRV_PCM_INFO_MMAP |
4052 SNDRV_PCM_INFO_MMAP_VALID |
4053 SNDRV_PCM_INFO_NONINTERLEAVED |
4054 SNDRV_PCM_INFO_SYNC_START),
4055 #ifdef SNDRV_BIG_ENDIAN
4056 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4058 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4060 .rates = (SNDRV_PCM_RATE_32000 |
4061 SNDRV_PCM_RATE_44100 |
4062 SNDRV_PCM_RATE_48000 |
4063 SNDRV_PCM_RATE_64000 |
4064 SNDRV_PCM_RATE_88200 |
4065 SNDRV_PCM_RATE_96000),
4069 .channels_max = HDSP_MAX_CHANNELS,
4070 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4071 .period_bytes_min = (64 * 4) * 10,
4072 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4078 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4080 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4081 .count = ARRAY_SIZE(hdsp_period_sizes),
4082 .list = hdsp_period_sizes,
4086 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4088 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4089 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4090 .list = hdsp_9632_sample_rates,
4094 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4095 struct snd_pcm_hw_rule *rule)
4097 struct hdsp *hdsp = rule->private;
4098 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4099 if (hdsp->io_type == H9632) {
4100 unsigned int list[3];
4101 list[0] = hdsp->qs_in_channels;
4102 list[1] = hdsp->ds_in_channels;
4103 list[2] = hdsp->ss_in_channels;
4104 return snd_interval_list(c, 3, list, 0);
4106 unsigned int list[2];
4107 list[0] = hdsp->ds_in_channels;
4108 list[1] = hdsp->ss_in_channels;
4109 return snd_interval_list(c, 2, list, 0);
4113 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4114 struct snd_pcm_hw_rule *rule)
4116 unsigned int list[3];
4117 struct hdsp *hdsp = rule->private;
4118 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4119 if (hdsp->io_type == H9632) {
4120 list[0] = hdsp->qs_out_channels;
4121 list[1] = hdsp->ds_out_channels;
4122 list[2] = hdsp->ss_out_channels;
4123 return snd_interval_list(c, 3, list, 0);
4125 list[0] = hdsp->ds_out_channels;
4126 list[1] = hdsp->ss_out_channels;
4128 return snd_interval_list(c, 2, list, 0);
4131 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4132 struct snd_pcm_hw_rule *rule)
4134 struct hdsp *hdsp = rule->private;
4135 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4136 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4137 if (r->min > 96000 && hdsp->io_type == H9632) {
4138 struct snd_interval t = {
4139 .min = hdsp->qs_in_channels,
4140 .max = hdsp->qs_in_channels,
4143 return snd_interval_refine(c, &t);
4144 } else if (r->min > 48000 && r->max <= 96000) {
4145 struct snd_interval t = {
4146 .min = hdsp->ds_in_channels,
4147 .max = hdsp->ds_in_channels,
4150 return snd_interval_refine(c, &t);
4151 } else if (r->max < 64000) {
4152 struct snd_interval t = {
4153 .min = hdsp->ss_in_channels,
4154 .max = hdsp->ss_in_channels,
4157 return snd_interval_refine(c, &t);
4162 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4163 struct snd_pcm_hw_rule *rule)
4165 struct hdsp *hdsp = rule->private;
4166 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4167 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4168 if (r->min > 96000 && hdsp->io_type == H9632) {
4169 struct snd_interval t = {
4170 .min = hdsp->qs_out_channels,
4171 .max = hdsp->qs_out_channels,
4174 return snd_interval_refine(c, &t);
4175 } else if (r->min > 48000 && r->max <= 96000) {
4176 struct snd_interval t = {
4177 .min = hdsp->ds_out_channels,
4178 .max = hdsp->ds_out_channels,
4181 return snd_interval_refine(c, &t);
4182 } else if (r->max < 64000) {
4183 struct snd_interval t = {
4184 .min = hdsp->ss_out_channels,
4185 .max = hdsp->ss_out_channels,
4188 return snd_interval_refine(c, &t);
4193 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4194 struct snd_pcm_hw_rule *rule)
4196 struct hdsp *hdsp = rule->private;
4197 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4198 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4199 if (c->min >= hdsp->ss_out_channels) {
4200 struct snd_interval t = {
4205 return snd_interval_refine(r, &t);
4206 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4207 struct snd_interval t = {
4212 return snd_interval_refine(r, &t);
4213 } else if (c->max <= hdsp->ds_out_channels) {
4214 struct snd_interval t = {
4219 return snd_interval_refine(r, &t);
4224 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4225 struct snd_pcm_hw_rule *rule)
4227 struct hdsp *hdsp = rule->private;
4228 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4229 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4230 if (c->min >= hdsp->ss_in_channels) {
4231 struct snd_interval t = {
4236 return snd_interval_refine(r, &t);
4237 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4238 struct snd_interval t = {
4243 return snd_interval_refine(r, &t);
4244 } else if (c->max <= hdsp->ds_in_channels) {
4245 struct snd_interval t = {
4250 return snd_interval_refine(r, &t);
4255 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4257 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4258 struct snd_pcm_runtime *runtime = substream->runtime;
4260 if (hdsp_check_for_iobox (hdsp))
4263 if (hdsp_check_for_firmware(hdsp, 1))
4266 spin_lock_irq(&hdsp->lock);
4268 snd_pcm_set_sync(substream);
4270 runtime->hw = snd_hdsp_playback_subinfo;
4271 runtime->dma_area = hdsp->playback_buffer;
4272 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4274 hdsp->playback_pid = current->pid;
4275 hdsp->playback_substream = substream;
4277 spin_unlock_irq(&hdsp->lock);
4279 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4280 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4281 if (hdsp->clock_source_locked) {
4282 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4283 } else if (hdsp->io_type == H9632) {
4284 runtime->hw.rate_max = 192000;
4285 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4286 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4288 if (hdsp->io_type == H9632) {
4289 runtime->hw.channels_min = hdsp->qs_out_channels;
4290 runtime->hw.channels_max = hdsp->ss_out_channels;
4293 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4294 snd_hdsp_hw_rule_out_channels, hdsp,
4295 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4296 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4297 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4298 SNDRV_PCM_HW_PARAM_RATE, -1);
4299 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4300 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4301 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4303 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4304 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4305 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4306 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4310 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4312 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4314 spin_lock_irq(&hdsp->lock);
4316 hdsp->playback_pid = -1;
4317 hdsp->playback_substream = NULL;
4319 spin_unlock_irq(&hdsp->lock);
4321 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4322 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4323 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4328 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4330 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4331 struct snd_pcm_runtime *runtime = substream->runtime;
4333 if (hdsp_check_for_iobox (hdsp))
4336 if (hdsp_check_for_firmware(hdsp, 1))
4339 spin_lock_irq(&hdsp->lock);
4341 snd_pcm_set_sync(substream);
4343 runtime->hw = snd_hdsp_capture_subinfo;
4344 runtime->dma_area = hdsp->capture_buffer;
4345 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4347 hdsp->capture_pid = current->pid;
4348 hdsp->capture_substream = substream;
4350 spin_unlock_irq(&hdsp->lock);
4352 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4353 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4354 if (hdsp->io_type == H9632) {
4355 runtime->hw.channels_min = hdsp->qs_in_channels;
4356 runtime->hw.channels_max = hdsp->ss_in_channels;
4357 runtime->hw.rate_max = 192000;
4358 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4359 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4361 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4362 snd_hdsp_hw_rule_in_channels, hdsp,
4363 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4364 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4365 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4366 SNDRV_PCM_HW_PARAM_RATE, -1);
4367 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4368 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4369 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4373 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4375 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4377 spin_lock_irq(&hdsp->lock);
4379 hdsp->capture_pid = -1;
4380 hdsp->capture_substream = NULL;
4382 spin_unlock_irq(&hdsp->lock);
4386 static int snd_hdsp_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
4388 /* we have nothing to initialize but the call is required */
4393 /* helper functions for copying meter values */
4394 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4396 u32 val = readl(src);
4397 return copy_to_user(dest, &val, 4);
4400 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4402 u32 rms_low, rms_high;
4404 rms_low = readl(src_low);
4405 rms_high = readl(src_high);
4406 rms = ((u64)rms_high << 32) | rms_low;
4407 return copy_to_user(dest, &rms, 8);
4410 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4412 u32 rms_low, rms_high;
4414 rms_low = readl(src_low) & 0xffffff00;
4415 rms_high = readl(src_high) & 0xffffff00;
4416 rms = ((u64)rms_high << 32) | rms_low;
4417 return copy_to_user(dest, &rms, 8);
4420 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4422 int doublespeed = 0;
4423 int i, j, channels, ofs;
4425 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4427 channels = doublespeed ? 14 : 26;
4428 for (i = 0, j = 0; i < 26; ++i) {
4429 if (doublespeed && (i & 4))
4431 ofs = HDSP_9652_peakBase - j * 4;
4432 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4434 ofs -= channels * 4;
4435 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4437 ofs -= channels * 4;
4438 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4440 ofs = HDSP_9652_rmsBase + j * 8;
4441 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4442 hdsp->iobase + ofs + 4))
4444 ofs += channels * 8;
4445 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4446 hdsp->iobase + ofs + 4))
4448 ofs += channels * 8;
4449 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4450 hdsp->iobase + ofs + 4))
4457 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4460 struct hdsp_9632_meters __iomem *m;
4461 int doublespeed = 0;
4463 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4465 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4466 for (i = 0, j = 0; i < 16; ++i, ++j) {
4467 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4469 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4471 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4473 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4474 &m->input_rms_high[j]))
4476 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4477 &m->playback_rms_high[j]))
4479 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4480 &m->output_rms_high[j]))
4482 if (doublespeed && i == 3) i += 4;
4487 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4491 for (i = 0; i < 26; i++) {
4492 if (copy_u32_le(&peak_rms->playback_peaks[i],
4493 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4495 if (copy_u32_le(&peak_rms->input_peaks[i],
4496 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4499 for (i = 0; i < 28; i++) {
4500 if (copy_u32_le(&peak_rms->output_peaks[i],
4501 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4504 for (i = 0; i < 26; ++i) {
4505 if (copy_u64_le(&peak_rms->playback_rms[i],
4506 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4507 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4509 if (copy_u64_le(&peak_rms->input_rms[i],
4510 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4511 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4517 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4519 struct hdsp *hdsp = (struct hdsp *)hw->private_data;
4520 void __user *argp = (void __user *)arg;
4523 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4524 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4526 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4527 snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n");
4531 switch (hdsp->io_type) {
4533 return hdsp_9652_get_peak(hdsp, peak_rms);
4535 return hdsp_9632_get_peak(hdsp, peak_rms);
4537 return hdsp_get_peak(hdsp, peak_rms);
4540 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4541 struct hdsp_config_info info;
4542 unsigned long flags;
4545 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4546 snd_printk(KERN_ERR "Hammerfall-DSP: Firmware needs to be uploaded to the card.\n");
4549 spin_lock_irqsave(&hdsp->lock, flags);
4550 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4551 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4552 if (hdsp->io_type != H9632)
4553 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4554 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4555 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i)
4556 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4557 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4558 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4559 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4560 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4561 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4562 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4563 info.system_sample_rate = hdsp->system_sample_rate;
4564 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4565 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4566 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4567 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4568 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4569 if (hdsp->io_type == H9632) {
4570 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4571 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4572 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4573 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4576 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4577 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4578 spin_unlock_irqrestore(&hdsp->lock, flags);
4579 if (copy_to_user(argp, &info, sizeof(info)))
4583 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4584 struct hdsp_9632_aeb h9632_aeb;
4586 if (hdsp->io_type != H9632) return -EINVAL;
4587 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4588 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4589 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4593 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4594 struct hdsp_version hdsp_version;
4597 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4598 if (hdsp->io_type == Undefined) {
4599 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4602 hdsp_version.io_type = hdsp->io_type;
4603 hdsp_version.firmware_rev = hdsp->firmware_rev;
4604 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4608 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4609 struct hdsp_firmware __user *firmware;
4610 u32 __user *firmware_data;
4613 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4614 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4615 if (hdsp->io_type == Undefined) return -EINVAL;
4617 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4620 snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n");
4621 firmware = (struct hdsp_firmware __user *)argp;
4623 if (get_user(firmware_data, &firmware->firmware_data))
4626 if (hdsp_check_for_iobox (hdsp))
4629 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0)
4632 hdsp->state |= HDSP_FirmwareCached;
4634 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4637 if (!(hdsp->state & HDSP_InitializationComplete)) {
4638 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4641 snd_hdsp_initialize_channels(hdsp);
4642 snd_hdsp_initialize_midi_flush(hdsp);
4644 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4645 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
4651 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4652 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4653 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4663 static struct snd_pcm_ops snd_hdsp_playback_ops = {
4664 .open = snd_hdsp_playback_open,
4665 .close = snd_hdsp_playback_release,
4666 .ioctl = snd_hdsp_ioctl,
4667 .hw_params = snd_hdsp_hw_params,
4668 .prepare = snd_hdsp_prepare,
4669 .trigger = snd_hdsp_trigger,
4670 .pointer = snd_hdsp_hw_pointer,
4671 .copy = snd_hdsp_playback_copy,
4672 .silence = snd_hdsp_hw_silence,
4675 static struct snd_pcm_ops snd_hdsp_capture_ops = {
4676 .open = snd_hdsp_capture_open,
4677 .close = snd_hdsp_capture_release,
4678 .ioctl = snd_hdsp_ioctl,
4679 .hw_params = snd_hdsp_hw_params,
4680 .prepare = snd_hdsp_prepare,
4681 .trigger = snd_hdsp_trigger,
4682 .pointer = snd_hdsp_hw_pointer,
4683 .copy = snd_hdsp_capture_copy,
4686 static int __devinit snd_hdsp_create_hwdep(struct snd_card *card,
4689 struct snd_hwdep *hw;
4692 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4696 hw->private_data = hdsp;
4697 strcpy(hw->name, "HDSP hwdep interface");
4699 hw->ops.open = snd_hdsp_hwdep_dummy_op;
4700 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4701 hw->ops.release = snd_hdsp_hwdep_dummy_op;
4706 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4708 struct snd_pcm *pcm;
4711 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4715 pcm->private_data = hdsp;
4716 strcpy(pcm->name, hdsp->card_name);
4718 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4719 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4721 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4726 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4728 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4729 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4732 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4736 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4737 snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n");
4741 for (i = 0; i < hdsp->max_channels; ++i) {
4742 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4743 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4749 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4751 int status, aebi_channels, aebo_channels;
4753 switch (hdsp->io_type) {
4755 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4756 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4757 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4761 hdsp->card_name = "RME Hammerfall HDSP 9652";
4762 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4763 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4767 status = hdsp_read(hdsp, HDSP_statusRegister);
4768 /* HDSP_AEBx bits are low when AEB are connected */
4769 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4770 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4771 hdsp->card_name = "RME Hammerfall HDSP 9632";
4772 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4773 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4774 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4775 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4776 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4777 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4781 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4782 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4783 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4787 /* should never get here */
4792 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
4794 snd_hdsp_flush_midi_input (hdsp, 0);
4795 snd_hdsp_flush_midi_input (hdsp, 1);
4798 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
4802 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4803 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n");
4808 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4809 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n");
4813 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
4814 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4815 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n");
4820 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4821 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n");
4825 snd_hdsp_proc_init(hdsp);
4827 hdsp->system_sample_rate = -1;
4828 hdsp->playback_pid = -1;
4829 hdsp->capture_pid = -1;
4830 hdsp->capture_substream = NULL;
4831 hdsp->playback_substream = NULL;
4833 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4834 snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n");
4838 if (!(hdsp->state & HDSP_InitializationComplete)) {
4839 strcpy(card->shortname, "Hammerfall DSP");
4840 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4841 hdsp->port, hdsp->irq);
4843 if ((err = snd_card_register(card)) < 0) {
4844 snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n");
4847 hdsp->state |= HDSP_InitializationComplete;
4853 #ifdef HDSP_FW_LOADER
4854 /* load firmware via hotplug fw loader */
4855 static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp)
4858 const struct firmware *fw;
4861 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4863 if (hdsp->io_type == Undefined) {
4864 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4866 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4870 /* caution: max length of firmware filename is 30! */
4871 switch (hdsp->io_type) {
4873 if (hdsp->firmware_rev == 0xa)
4874 fwfile = "multiface_firmware.bin";
4876 fwfile = "multiface_firmware_rev11.bin";
4879 if (hdsp->firmware_rev == 0xa)
4880 fwfile = "digiface_firmware.bin";
4882 fwfile = "digiface_firmware_rev11.bin";
4885 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type);
4889 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
4890 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile);
4893 if (fw->size < sizeof(hdsp->firmware_cache)) {
4894 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n",
4895 (int)fw->size, (int)sizeof(hdsp->firmware_cache));
4896 release_firmware(fw);
4900 memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache));
4902 release_firmware(fw);
4904 hdsp->state |= HDSP_FirmwareCached;
4906 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4909 if (!(hdsp->state & HDSP_InitializationComplete)) {
4910 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4913 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
4914 snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n");
4917 snd_hdsp_initialize_channels(hdsp);
4918 snd_hdsp_initialize_midi_flush(hdsp);
4919 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4920 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
4928 static int __devinit snd_hdsp_create(struct snd_card *card,
4931 struct pci_dev *pci = hdsp->pci;
4938 hdsp->midi[0].rmidi = NULL;
4939 hdsp->midi[1].rmidi = NULL;
4940 hdsp->midi[0].input = NULL;
4941 hdsp->midi[1].input = NULL;
4942 hdsp->midi[0].output = NULL;
4943 hdsp->midi[1].output = NULL;
4944 hdsp->midi[0].pending = 0;
4945 hdsp->midi[1].pending = 0;
4946 spin_lock_init(&hdsp->midi[0].lock);
4947 spin_lock_init(&hdsp->midi[1].lock);
4948 hdsp->iobase = NULL;
4949 hdsp->control_register = 0;
4950 hdsp->control2_register = 0;
4951 hdsp->io_type = Undefined;
4952 hdsp->max_channels = 26;
4956 spin_lock_init(&hdsp->lock);
4958 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
4960 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
4961 hdsp->firmware_rev &= 0xff;
4963 /* From Martin Bjoernsen :
4964 "It is important that the card's latency timer register in
4965 the PCI configuration space is set to a value much larger
4966 than 0 by the computer's BIOS or the driver.
4967 The windows driver always sets this 8 bit register [...]
4968 to its maximum 255 to avoid problems with some computers."
4970 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
4972 strcpy(card->driver, "H-DSP");
4973 strcpy(card->mixername, "Xilinx FPGA");
4975 if (hdsp->firmware_rev < 0xa)
4977 else if (hdsp->firmware_rev < 0x64)
4978 hdsp->card_name = "RME Hammerfall DSP";
4979 else if (hdsp->firmware_rev < 0x96) {
4980 hdsp->card_name = "RME HDSP 9652";
4983 hdsp->card_name = "RME HDSP 9632";
4984 hdsp->max_channels = 16;
4988 if ((err = pci_enable_device(pci)) < 0)
4991 pci_set_master(hdsp->pci);
4993 if ((err = pci_request_regions(pci, "hdsp")) < 0)
4995 hdsp->port = pci_resource_start(pci, 0);
4996 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
4997 snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5001 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5003 snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq);
5007 hdsp->irq = pci->irq;
5008 hdsp->precise_ptr = 0;
5009 hdsp->use_midi_tasklet = 1;
5010 hdsp->dds_value = 0;
5012 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5015 if (!is_9652 && !is_9632) {
5016 /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */
5019 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5020 #ifdef HDSP_FW_LOADER
5021 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5022 /* we don't fail as this can happen
5023 if userspace is not ready for
5026 snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n");
5028 /* init is complete, we return */
5031 /* no iobox connected, we defer initialization */
5032 snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n");
5033 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5037 snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n");
5038 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5039 hdsp->io_type = Multiface;
5041 hdsp->io_type = Digiface;
5045 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5049 hdsp->io_type = H9652;
5052 hdsp->io_type = H9632;
5054 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5057 snd_hdsp_initialize_channels(hdsp);
5058 snd_hdsp_initialize_midi_flush(hdsp);
5060 hdsp->state |= HDSP_FirmwareLoaded;
5062 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5068 static int snd_hdsp_free(struct hdsp *hdsp)
5071 /* stop the audio, and cancel all interrupts */
5072 tasklet_kill(&hdsp->midi_tasklet);
5073 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5074 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5078 free_irq(hdsp->irq, (void *)hdsp);
5080 snd_hdsp_free_buffers(hdsp);
5083 iounmap(hdsp->iobase);
5086 pci_release_regions(hdsp->pci);
5088 pci_disable_device(hdsp->pci);
5092 static void snd_hdsp_card_free(struct snd_card *card)
5094 struct hdsp *hdsp = (struct hdsp *) card->private_data;
5097 snd_hdsp_free(hdsp);
5100 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5101 const struct pci_device_id *pci_id)
5105 struct snd_card *card;
5108 if (dev >= SNDRV_CARDS)
5115 if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(struct hdsp))))
5118 hdsp = (struct hdsp *) card->private_data;
5119 card->private_free = snd_hdsp_card_free;
5122 snd_card_set_dev(card, &pci->dev);
5124 if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5125 snd_card_free(card);
5129 strcpy(card->shortname, "Hammerfall DSP");
5130 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5131 hdsp->port, hdsp->irq);
5133 if ((err = snd_card_register(card)) < 0) {
5134 snd_card_free(card);
5137 pci_set_drvdata(pci, card);
5142 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5144 snd_card_free(pci_get_drvdata(pci));
5145 pci_set_drvdata(pci, NULL);
5148 static struct pci_driver driver = {
5149 .name = "RME Hammerfall DSP",
5150 .id_table = snd_hdsp_ids,
5151 .probe = snd_hdsp_probe,
5152 .remove = __devexit_p(snd_hdsp_remove),
5155 static int __init alsa_card_hdsp_init(void)
5157 return pci_register_driver(&driver);
5160 static void __exit alsa_card_hdsp_exit(void)
5162 pci_unregister_driver(&driver);
5165 module_init(alsa_card_hdsp_init)
5166 module_exit(alsa_card_hdsp_exit)