sound/pci/rme9652/hdspm.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
   3  *
   4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
   5  *      code based on hdsp.c   Paul Davis
   6  *                             Marcus Andersson
   7  *                             Thomas Charbonnel
   8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
   9  *                                               <remy.bruno@trinnov.com>
  10  *
  11  *      Modified 2009-04-13 for proper metering by Florian Faber
  12  *                                               <faber@faberman.de>
  13  *
  14  *      Modified 2009-04-14 for native float support by Florian Faber
  15  *                                               <faber@faberman.de>
  16  *
  17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
  18  *                                               <faber@faberman.de>
  19  *
  20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
  21  *
  22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
  23  *
  24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
  25  *
  26  *   This program is free software; you can redistribute it and/or modify
  27  *   it under the terms of the GNU General Public License as published by
  28  *   the Free Software Foundation; either version 2 of the License, or
  29  *   (at your option) any later version.
  30  *
  31  *   This program is distributed in the hope that it will be useful,
  32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  34  *   GNU General Public License for more details.
  35  *
  36  *   You should have received a copy of the GNU General Public License
  37  *   along with this program; if not, write to the Free Software
  38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  39  *
  40  */
  41
  42 /* *************    Register Documentation   *******************************************************
  43  *
  44  * Work in progress! Documentation is based on the code in this file.
  45  *
  46  * --------- HDSPM_controlRegister ---------
  47  * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
  48  * :||||.||||:||||.||||:||||.||||:||||.||||:
  49  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
  50  * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
  51  * :||||.||||:||||.||||:||||.||||:||||.||||:
  52  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
  53  * :    .    :    .    :    .    :  x .    :  HDSPM_AudioInterruptEnable \_ setting both bits
  54  * :    .    :    .    :    .    :    .   x:  HDSPM_Start                /  enables audio IO
  55  * :    .    :    .    :    .    :   x.    :  HDSPM_ClockModeMaster - 1: Master, 0: Slave
  56  * :    .    :    .    :    .    :    .210 :  HDSPM_LatencyMask - 3 Bit value for latency
  57  * :    .    :    .    :    .    :    .    :      0:64, 1:128, 2:256, 3:512,
  58  * :    .    :    .    :    .    :    .    :      4:1024, 5:2048, 6:4096, 7:8192
  59  * :x   .    :    .    :    .   x:xx  .    :  HDSPM_FrequencyMask
  60  * :    .    :    .    :    .    :10  .    :  HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=??
  61  * :    .    :    .    :    .   x:    .    :  <MADI> HDSPM_DoubleSpeed
  62  * :x   .    :    .    :    .    :    .    :  <MADI> HDSPM_QuadSpeed
  63  * :    .  3 :    .  10:  2 .    :    .    :  HDSPM_SyncRefMask :
  64  * :    .    :    .   x:    .    :    .    :  HDSPM_SyncRef0
  65  * :    .    :    .  x :    .    :    .    :  HDSPM_SyncRef1
  66  * :    .    :    .    :  x .    :    .    :  <AES32> HDSPM_SyncRef2
  67  * :    .  x :    .    :    .    :    .    :  <AES32> HDSPM_SyncRef3
  68  * :    .    :    .  10:    .    :    .    :  <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn
  69  * :    .  3 :    .  10:  2 .    :    .    :  <AES32>  0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn?
  70  * :    .  x :    .    :    .    :    .    :  <MADIe> HDSPe_FLOAT_FORMAT
  71  * :    .    :    .    : x  .    :    .    :  <MADI> HDSPM_InputSelect0 : 0=optical,1=coax
  72  * :    .    :    .    :x   .    :    .    :  <MADI> HDSPM_InputSelect1
  73  * :    .    :    .x   :    .    :    .    :  <MADI> HDSPM_clr_tms
  74  * :    .    :    .    :    . x  :    .    :  <MADI> HDSPM_TX_64ch
  75  * :    .    :    .    :    . x  :    .    :  <AES32> HDSPM_Emphasis
  76  * :    .    :    .    :    .x   :    .    :  <MADI> HDSPM_AutoInp
  77  * :    .    :    . x  :    .    :    .    :  <MADI> HDSPM_SMUX
  78  * :    .    :    .x   :    .    :    .    :  <MADI> HDSPM_clr_tms
  79  * :    .    :   x.    :    .    :    .    :  <MADI> HDSPM_taxi_reset
  80  * :    .   x:    .    :    .    :    .    :  <MADI> HDSPM_LineOut
  81  * :    .   x:    .    :    .    :    .    :  <AES32> ??????????????????
  82  * :    .    :   x.    :    .    :    .    :  <AES32> HDSPM_WCK48
  83  * :    .    :    .    :    .x   :    .    :  <AES32> HDSPM_Dolby
  84  * :    .    : x  .    :    .    :    .    :  HDSPM_Midi0InterruptEnable
  85  * :    .    :x   .    :    .    :    .    :  HDSPM_Midi1InterruptEnable
  86  * :    .    :  x .    :    .    :    .    :  HDSPM_Midi2InterruptEnable
  87  * :    . x  :    .    :    .    :    .    :  <MADI> HDSPM_Midi3InterruptEnable
  88  * :    . x  :    .    :    .    :    .    :  <AES32> HDSPM_DS_DoubleWire
  89  * :    .x   :    .    :    .    :    .    :  <AES32> HDSPM_QS_DoubleWire
  90  * :   x.    :    .    :    .    :    .    :  <AES32> HDSPM_QS_QuadWire
  91  * :    .    :    .    :    .  x :    .    :  <AES32> HDSPM_Professional
  92  * : x  .    :    .    :    .    :    .    :  HDSPM_wclk_sel
  93  * :    .    :    .    :    .    :    .    :
  94  * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
  95  * :||||.||||:||||.||||:||||.||||:||||.||||:
  96  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
  97  * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
  98  * :||||.||||:||||.||||:||||.||||:||||.||||:
  99  * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit
 100  *
 101  *
 102  *
 103  * AIO / RayDAT only
 104  *
 105  * ------------ HDSPM_WR_SETTINGS ----------
 106  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
 107  * :1098.7654:3210.9876:5432.1098:7654.3210:
 108  * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
 109  * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
 110  * :||||.||||:||||.||||:||||.||||:||||.||||:
 111  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
 112  * :    .    :    .    :    .    :    .   x: HDSPM_c0Master 1: Master, 0: Slave
 113  * :    .    :    .    :    .    :    .  x : HDSPM_c0_SyncRef0
 114  * :    .    :    .    :    .    :    . x  : HDSPM_c0_SyncRef1
 115  * :    .    :    .    :    .    :    .x   : HDSPM_c0_SyncRef2
 116  * :    .    :    .    :    .    :   x.    : HDSPM_c0_SyncRef3
 117  * :    .    :    .    :    .    :   3.210 : HDSPM_c0_SyncRefMask:
 118  * :    .    :    .    :    .    :    .    :  RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4,
 119  * :    .    :    .    :    .    :    .    :          9:TCO, 10:SyncIn
 120  * :    .    :    .    :    .    :    .    :  AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT,
 121  * :    .    :    .    :    .    :    .    :          9:TCO, 10:SyncIn
 122  * :    .    :    .    :    .    :    .    :
 123  * :    .    :    .    :    .    :    .    :
 124  * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
 125  * :1098.7654:3210.9876:5432.1098:7654.3210:
 126  * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
 127  * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
 128  * :||||.||||:||||.||||:||||.||||:||||.||||:
 129  * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
 130  *
 131  */
 132 #include <linux/init.h>
 133 #include <linux/delay.h>
 134 #include <linux/interrupt.h>
 135 #include <linux/module.h>
 136 #include <linux/slab.h>
 137 #include <linux/pci.h>
 138 #include <linux/math64.h>
 139 #include <linux/io.h>
 140
 141 #include <sound/core.h>
 142 #include <sound/control.h>
 143 #include <sound/pcm.h>
 144 #include <sound/pcm_params.h>
 145 #include <sound/info.h>
 146 #include <sound/asoundef.h>
 147 #include <sound/rawmidi.h>
 148 #include <sound/hwdep.h>
 149 #include <sound/initval.h>
 150
 151 #include <sound/hdspm.h>
 152
 153 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
 154 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
 155 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
 156
 157 module_param_array(index, int, NULL, 0444);
 158 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
 159
 160 module_param_array(id, charp, NULL, 0444);
 161 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
 162
 163 module_param_array(enable, bool, NULL, 0444);
 164 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
 165
 166
 167 MODULE_AUTHOR
 168 (
 169         "Winfried Ritsch <ritsch_AT_iem.at>, "
 170         "Paul Davis <paul@linuxaudiosystems.com>, "
 171         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
 172         "Remy Bruno <remy.bruno@trinnov.com>, "
 173         "Florian Faber <faberman@linuxproaudio.org>, "
 174         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
 175 );
 176 MODULE_DESCRIPTION("RME HDSPM");
 177 MODULE_LICENSE("GPL");
 178 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
 179
 180 /* --- Write registers. ---
 181   These are defined as byte-offsets from the iobase value.  */
 182
 183 #define HDSPM_WR_SETTINGS             0
 184 #define HDSPM_outputBufferAddress    32
 185 #define HDSPM_inputBufferAddress     36
 186 #define HDSPM_controlRegister        64
 187 #define HDSPM_interruptConfirmation  96
 188 #define HDSPM_control2Reg            256  /* not in specs ???????? */
 189 #define HDSPM_freqReg                256  /* for setting arbitrary clock values (DDS feature) */
 190 #define HDSPM_midiDataOut0           352  /* just believe in old code */
 191 #define HDSPM_midiDataOut1           356
 192 #define HDSPM_eeprom_wr              384  /* for AES32 */
 193
 194 /* DMA enable for 64 channels, only Bit 0 is relevant */
 195 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
 196 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
 197
 198 /* 16 page addresses for each of the 64 channels DMA buffer in and out
 199    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
 200 #define HDSPM_pageAddressBufferOut       8192
 201 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
 202
 203 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
 204
 205 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
 206
 207 /* --- Read registers. ---
 208    These are defined as byte-offsets from the iobase value */
 209 #define HDSPM_statusRegister    0
 210 /*#define HDSPM_statusRegister2  96 */
 211 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
 212  * offset 192, for AES32 *and* MADI
 213  * => need to check that offset 192 is working on MADI */
 214 #define HDSPM_statusRegister2  192
 215 #define HDSPM_timecodeRegister 128
 216
 217 /* AIO, RayDAT */
 218 #define HDSPM_RD_STATUS_0 0
 219 #define HDSPM_RD_STATUS_1 64
 220 #define HDSPM_RD_STATUS_2 128
 221 #define HDSPM_RD_STATUS_3 192
 222
 223 #define HDSPM_RD_TCO           256
 224 #define HDSPM_RD_PLL_FREQ      512
 225 #define HDSPM_WR_TCO           128
 226
 227 #define HDSPM_TCO1_TCO_lock                     0x00000001
 228 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
 229 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
 230 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
 231 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
 232 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
 233 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
 234
 235 #define HDSPM_TCO1_set_TC                       0x00000100
 236 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
 237 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
 238 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
 239
 240 #define HDSPM_TCO2_TC_run                       0x00010000
 241 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
 242 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
 243 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
 244 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
 245 #define HDSPM_TCO2_set_jam_sync                 0x00200000
 246 #define HDSPM_TCO2_set_flywheel                 0x00400000
 247
 248 #define HDSPM_TCO2_set_01_4                     0x01000000
 249 #define HDSPM_TCO2_set_pull_down                0x02000000
 250 #define HDSPM_TCO2_set_pull_up                  0x04000000
 251 #define HDSPM_TCO2_set_freq                     0x08000000
 252 #define HDSPM_TCO2_set_term_75R                 0x10000000
 253 #define HDSPM_TCO2_set_input_LSB                0x20000000
 254 #define HDSPM_TCO2_set_input_MSB                0x40000000
 255 #define HDSPM_TCO2_set_freq_from_app            0x80000000
 256
 257
 258 #define HDSPM_midiDataOut0    352
 259 #define HDSPM_midiDataOut1    356
 260 #define HDSPM_midiDataOut2    368
 261
 262 #define HDSPM_midiDataIn0     360
 263 #define HDSPM_midiDataIn1     364
 264 #define HDSPM_midiDataIn2     372
 265 #define HDSPM_midiDataIn3     376
 266
 267 /* status is data bytes in MIDI-FIFO (0-128) */
 268 #define HDSPM_midiStatusOut0  384
 269 #define HDSPM_midiStatusOut1  388
 270 #define HDSPM_midiStatusOut2  400
 271
 272 #define HDSPM_midiStatusIn0   392
 273 #define HDSPM_midiStatusIn1   396
 274 #define HDSPM_midiStatusIn2   404
 275 #define HDSPM_midiStatusIn3   408
 276
 277
 278 /* the meters are regular i/o-mapped registers, but offset
 279    considerably from the rest. the peak registers are reset
 280    when read; the least-significant 4 bits are full-scale counters;
 281    the actual peak value is in the most-significant 24 bits.
 282 */
 283
 284 #define HDSPM_MADI_INPUT_PEAK           4096
 285 #define HDSPM_MADI_PLAYBACK_PEAK        4352
 286 #define HDSPM_MADI_OUTPUT_PEAK          4608
 287
 288 #define HDSPM_MADI_INPUT_RMS_L          6144
 289 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
 290 #define HDSPM_MADI_OUTPUT_RMS_L         6656
 291
 292 #define HDSPM_MADI_INPUT_RMS_H          7168
 293 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
 294 #define HDSPM_MADI_OUTPUT_RMS_H         7680
 295
 296 /* --- Control Register bits --------- */
 297 #define HDSPM_Start                (1<<0) /* start engine */
 298
 299 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
 300 #define HDSPM_Latency1             (1<<2) /* where n is defined */
 301 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
 302
 303 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
 304 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
 305                                           register [RayDAT, AIO] */
 306
 307 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
 308
 309 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
 310 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
 311 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
 312 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
 313
 314 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
 315 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
 316                                      56channelMODE=0 */ /* MADI ONLY*/
 317 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
 318
 319 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
 320                                      0=off, 1=on  */ /* MADI ONLY */
 321 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
 322
 323 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
 324                                     * -- MADI ONLY
 325                                     */
 326 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
 327
 328 #define HDSPM_SyncRef2     (1<<13)
 329 #define HDSPM_SyncRef3     (1<<25)
 330
 331 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
 332 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
 333                                       AES additional bits in
 334                                       lower 5 Audiodatabits ??? */
 335 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
 336 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
 337
 338 #define HDSPM_Midi0InterruptEnable 0x0400000
 339 #define HDSPM_Midi1InterruptEnable 0x0800000
 340 #define HDSPM_Midi2InterruptEnable 0x0200000
 341 #define HDSPM_Midi3InterruptEnable 0x4000000
 342
 343 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
 344 #define HDSPe_FLOAT_FORMAT         0x2000000
 345
 346 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
 347 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
 348 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
 349
 350 #define HDSPM_wclk_sel (1<<30)
 351
 352 /* additional control register bits for AIO*/
 353 #define HDSPM_c0_Wck48                          0x20 /* also RayDAT */
 354 #define HDSPM_c0_Input0                         0x1000
 355 #define HDSPM_c0_Input1                         0x2000
 356 #define HDSPM_c0_Spdif_Opt                      0x4000
 357 #define HDSPM_c0_Pro                            0x8000
 358 #define HDSPM_c0_clr_tms                        0x10000
 359 #define HDSPM_c0_AEB1                           0x20000
 360 #define HDSPM_c0_AEB2                           0x40000
 361 #define HDSPM_c0_LineOut                        0x80000
 362 #define HDSPM_c0_AD_GAIN0                       0x100000
 363 #define HDSPM_c0_AD_GAIN1                       0x200000
 364 #define HDSPM_c0_DA_GAIN0                       0x400000
 365 #define HDSPM_c0_DA_GAIN1                       0x800000
 366 #define HDSPM_c0_PH_GAIN0                       0x1000000
 367 #define HDSPM_c0_PH_GAIN1                       0x2000000
 368 #define HDSPM_c0_Sym6db                         0x4000000
 369
 370
 371 /* --- bit helper defines */
 372 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
 373 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
 374                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
 375 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
 376 #define HDSPM_InputOptical   0
 377 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
 378 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
 379                               HDSPM_SyncRef2|HDSPM_SyncRef3)
 380
 381 #define HDSPM_c0_SyncRef0      0x2
 382 #define HDSPM_c0_SyncRef1      0x4
 383 #define HDSPM_c0_SyncRef2      0x8
 384 #define HDSPM_c0_SyncRef3      0x10
 385 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
 386                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
 387
 388 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
 389 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
 390 #define HDSPM_SYNC_FROM_TCO     2
 391 #define HDSPM_SYNC_FROM_SYNC_IN 3
 392
 393 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
 394 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
 395 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
 396 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
 397 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
 398 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
 399                                 HDSPM_Frequency0)
 400 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
 401 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
 402 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
 403                                  HDSPM_Frequency0)
 404
 405
 406 /* Synccheck Status */
 407 #define HDSPM_SYNC_CHECK_NO_LOCK 0
 408 #define HDSPM_SYNC_CHECK_LOCK    1
 409 #define HDSPM_SYNC_CHECK_SYNC    2
 410
 411 /* AutoSync References - used by "autosync_ref" control switch */
 412 #define HDSPM_AUTOSYNC_FROM_WORD      0
 413 #define HDSPM_AUTOSYNC_FROM_MADI      1
 414 #define HDSPM_AUTOSYNC_FROM_TCO       2
 415 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
 416 #define HDSPM_AUTOSYNC_FROM_NONE      4
 417
 418 /* Possible sources of MADI input */
 419 #define HDSPM_OPTICAL 0         /* optical   */
 420 #define HDSPM_COAXIAL 1         /* BNC */
 421
 422 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
 423 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
 424
 425 #define hdspm_encode_in(x) (((x)&0x3)<<14)
 426 #define hdspm_decode_in(x) (((x)>>14)&0x3)
 427
 428 /* --- control2 register bits --- */
 429 #define HDSPM_TMS             (1<<0)
 430 #define HDSPM_TCK             (1<<1)
 431 #define HDSPM_TDI             (1<<2)
 432 #define HDSPM_JTAG            (1<<3)
 433 #define HDSPM_PWDN            (1<<4)
 434 #define HDSPM_PROGRAM         (1<<5)
 435 #define HDSPM_CONFIG_MODE_0   (1<<6)
 436 #define HDSPM_CONFIG_MODE_1   (1<<7)
 437 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
 438 #define HDSPM_BIGENDIAN_MODE  (1<<9)
 439 #define HDSPM_RD_MULTIPLE     (1<<10)
 440
 441 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
 442      that do not conflict with specific bits for AES32 seem to be valid also
 443      for the AES32
 444  */
 445 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
 446 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
 447 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
 448                                          * (like inp0)
 449                                          */
 450
 451 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
 452 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
 453
 454 #define HDSPM_tcoLockMadi    0x00000020 /* Optional TCO locked status for HDSPe MADI*/
 455 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
 456
 457 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
 458 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
 459
 460 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 461                         /* since 64byte accurate, last 6 bits are not used */
 462
 463
 464
 465 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
 466
 467 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
 468 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
 469 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
 470 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
 471
 472 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
 473                                          * Interrupt
 474                                          */
 475 #define HDSPM_tco_detect         0x08000000
 476 #define HDSPM_tcoLockAes         0x20000000 /* Optional TCO locked status for HDSPe AES */
 477
 478 #define HDSPM_s2_tco_detect      0x00000040
 479 #define HDSPM_s2_AEBO_D          0x00000080
 480 #define HDSPM_s2_AEBI_D          0x00000100
 481
 482
 483 #define HDSPM_midi0IRQPending    0x40000000
 484 #define HDSPM_midi1IRQPending    0x80000000
 485 #define HDSPM_midi2IRQPending    0x20000000
 486 #define HDSPM_midi2IRQPendingAES 0x00000020
 487 #define HDSPM_midi3IRQPending    0x00200000
 488
 489 /* --- status bit helpers */
 490 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
 491                              HDSPM_madiFreq2|HDSPM_madiFreq3)
 492 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
 493 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
 494 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
 495 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
 496 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
 497 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
 498 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
 499 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
 500 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
 501
 502 /* Status2 Register bits */ /* MADI ONLY */
 503
 504 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
 505 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
 506 #define HDSPM_version2 (1<<2)
 507
 508 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
 509 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
 510
 511 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
 512 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
 513 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, 111=128 */
 514 #define HDSPM_wc_freq3 0x800    /* 1000=176.4, 1001=192 */
 515
 516 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
 517 #define HDSPM_SyncRef1 0x20000
 518
 519 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
 520 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
 521 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
 522
 523 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
 524
 525 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
 526                             HDSPM_wc_freq3)
 527 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
 528 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
 529 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
 530 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
 531 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
 532 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
 533 #define HDSPM_wcFreq128   (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
 534 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
 535 #define HDSPM_wcFreq192   (HDSPM_wc_freq0|HDSPM_wc_freq3)
 536
 537 #define HDSPM_status1_F_0 0x0400000
 538 #define HDSPM_status1_F_1 0x0800000
 539 #define HDSPM_status1_F_2 0x1000000
 540 #define HDSPM_status1_F_3 0x2000000
 541 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
 542
 543
 544 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 545                                     HDSPM_SelSyncRef2)
 546 #define HDSPM_SelSyncRef_WORD      0
 547 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
 548 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
 549 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
 550 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 551                                     HDSPM_SelSyncRef2)
 552
 553 /*
 554    For AES32, bits for status, status2 and timecode are different
 555 */
 556 /* status */
 557 #define HDSPM_AES32_wcLock      0x0200000
 558 #define HDSPM_AES32_wcSync      0x0100000
 559 #define HDSPM_AES32_wcFreq_bit  22
 560 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
 561   HDSPM_bit2freq */
 562 #define HDSPM_AES32_syncref_bit  16
 563 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
 564
 565 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
 566 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
 567 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
 568 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
 569 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
 570 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
 571 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
 572 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
 573 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
 574 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9
 575 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10
 576 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11
 577
 578 /*  status2 */
 579 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
 580 #define HDSPM_LockAES   0x80
 581 #define HDSPM_LockAES1  0x80
 582 #define HDSPM_LockAES2  0x40
 583 #define HDSPM_LockAES3  0x20
 584 #define HDSPM_LockAES4  0x10
 585 #define HDSPM_LockAES5  0x8
 586 #define HDSPM_LockAES6  0x4
 587 #define HDSPM_LockAES7  0x2
 588 #define HDSPM_LockAES8  0x1
 589 /*
 590    Timecode
 591    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
 592    AES i+1
 593  bits 3210
 594       0001  32kHz
 595       0010  44.1kHz
 596       0011  48kHz
 597       0100  64kHz
 598       0101  88.2kHz
 599       0110  96kHz
 600       0111  128kHz
 601       1000  176.4kHz
 602       1001  192kHz
 603   NB: Timecode register doesn't seem to work on AES32 card revision 230
 604 */
 605
 606 /* Mixer Values */
 607 #define UNITY_GAIN          32768       /* = 65536/2 */
 608 #define MINUS_INFINITY_GAIN 0
 609
 610 /* Number of channels for different Speed Modes */
 611 #define MADI_SS_CHANNELS       64
 612 #define MADI_DS_CHANNELS       32
 613 #define MADI_QS_CHANNELS       16
 614
 615 #define RAYDAT_SS_CHANNELS     36
 616 #define RAYDAT_DS_CHANNELS     20
 617 #define RAYDAT_QS_CHANNELS     12
 618
 619 #define AIO_IN_SS_CHANNELS        14
 620 #define AIO_IN_DS_CHANNELS        10
 621 #define AIO_IN_QS_CHANNELS        8
 622 #define AIO_OUT_SS_CHANNELS        16
 623 #define AIO_OUT_DS_CHANNELS        12
 624 #define AIO_OUT_QS_CHANNELS        10
 625
 626 #define AES32_CHANNELS          16
 627
 628 /* the size of a substream (1 mono data stream) */
 629 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
 630 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
 631
 632 /* the size of the area we need to allocate for DMA transfers. the
 633    size is the same regardless of the number of channels, and
 634    also the latency to use.
 635    for one direction !!!
 636 */
 637 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
 638 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
 639
 640 #define HDSPM_RAYDAT_REV        211
 641 #define HDSPM_AIO_REV           212
 642 #define HDSPM_MADIFACE_REV      213
 643
 644 /* speed factor modes */
 645 #define HDSPM_SPEED_SINGLE 0
 646 #define HDSPM_SPEED_DOUBLE 1
 647 #define HDSPM_SPEED_QUAD   2
 648
 649 /* names for speed modes */
 650 static char *hdspm_speed_names[] = { "single", "double", "quad" };
 651
 652 static const char *const texts_autosync_aes_tco[] = { "Word Clock",
 653                                           "AES1", "AES2", "AES3", "AES4",
 654                                           "AES5", "AES6", "AES7", "AES8",
 655                                           "TCO", "Sync In"
 656 };
 657 static const char *const texts_autosync_aes[] = { "Word Clock",
 658                                       "AES1", "AES2", "AES3", "AES4",
 659                                       "AES5", "AES6", "AES7", "AES8",
 660                                       "Sync In"
 661 };
 662 static const char *const texts_autosync_madi_tco[] = { "Word Clock",
 663                                            "MADI", "TCO", "Sync In" };
 664 static const char *const texts_autosync_madi[] = { "Word Clock",
 665                                        "MADI", "Sync In" };
 666
 667 static const char *const texts_autosync_raydat_tco[] = {
 668         "Word Clock",
 669         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 670         "AES", "SPDIF", "TCO", "Sync In"
 671 };
 672 static const char *const texts_autosync_raydat[] = {
 673         "Word Clock",
 674         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 675         "AES", "SPDIF", "Sync In"
 676 };
 677 static const char *const texts_autosync_aio_tco[] = {
 678         "Word Clock",
 679         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
 680 };
 681 static const char *const texts_autosync_aio[] = { "Word Clock",
 682                                       "ADAT", "AES", "SPDIF", "Sync In" };
 683
 684 static const char *const texts_freq[] = {
 685         "No Lock",
 686         "32 kHz",
 687         "44.1 kHz",
 688         "48 kHz",
 689         "64 kHz",
 690         "88.2 kHz",
 691         "96 kHz",
 692         "128 kHz",
 693         "176.4 kHz",
 694         "192 kHz"
 695 };
 696
 697 static char *texts_ports_madi[] = {
 698         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
 699         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
 700         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
 701         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
 702         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
 703         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
 704         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
 705         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
 706         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
 707         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
 708         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
 709 };
 710
 711
 712 static char *texts_ports_raydat_ss[] = {
 713         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
 714         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 715         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
 716         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
 717         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
 718         "ADAT4.7", "ADAT4.8",
 719         "AES.L", "AES.R",
 720         "SPDIF.L", "SPDIF.R"
 721 };
 722
 723 static char *texts_ports_raydat_ds[] = {
 724         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
 725         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 726         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
 727         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
 728         "AES.L", "AES.R",
 729         "SPDIF.L", "SPDIF.R"
 730 };
 731
 732 static char *texts_ports_raydat_qs[] = {
 733         "ADAT1.1", "ADAT1.2",
 734         "ADAT2.1", "ADAT2.2",
 735         "ADAT3.1", "ADAT3.2",
 736         "ADAT4.1", "ADAT4.2",
 737         "AES.L", "AES.R",
 738         "SPDIF.L", "SPDIF.R"
 739 };
 740
 741
 742 static char *texts_ports_aio_in_ss[] = {
 743         "Analogue.L", "Analogue.R",
 744         "AES.L", "AES.R",
 745         "SPDIF.L", "SPDIF.R",
 746         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 747         "ADAT.7", "ADAT.8",
 748         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 749 };
 750
 751 static char *texts_ports_aio_out_ss[] = {
 752         "Analogue.L", "Analogue.R",
 753         "AES.L", "AES.R",
 754         "SPDIF.L", "SPDIF.R",
 755         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 756         "ADAT.7", "ADAT.8",
 757         "Phone.L", "Phone.R",
 758         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 759 };
 760
 761 static char *texts_ports_aio_in_ds[] = {
 762         "Analogue.L", "Analogue.R",
 763         "AES.L", "AES.R",
 764         "SPDIF.L", "SPDIF.R",
 765         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 766         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 767 };
 768
 769 static char *texts_ports_aio_out_ds[] = {
 770         "Analogue.L", "Analogue.R",
 771         "AES.L", "AES.R",
 772         "SPDIF.L", "SPDIF.R",
 773         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 774         "Phone.L", "Phone.R",
 775         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 776 };
 777
 778 static char *texts_ports_aio_in_qs[] = {
 779         "Analogue.L", "Analogue.R",
 780         "AES.L", "AES.R",
 781         "SPDIF.L", "SPDIF.R",
 782         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 783         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 784 };
 785
 786 static char *texts_ports_aio_out_qs[] = {
 787         "Analogue.L", "Analogue.R",
 788         "AES.L", "AES.R",
 789         "SPDIF.L", "SPDIF.R",
 790         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 791         "Phone.L", "Phone.R",
 792         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 793 };
 794
 795 static char *texts_ports_aes32[] = {
 796         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
 797         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
 798         "AES.15", "AES.16"
 799 };
 800
 801 /* These tables map the ALSA channels 1..N to the channels that we
 802    need to use in order to find the relevant channel buffer. RME
 803    refers to this kind of mapping as between "the ADAT channel and
 804    the DMA channel." We index it using the logical audio channel,
 805    and the value is the DMA channel (i.e. channel buffer number)
 806    where the data for that channel can be read/written from/to.
 807 */
 808
 809 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
 810         0, 1, 2, 3, 4, 5, 6, 7,
 811         8, 9, 10, 11, 12, 13, 14, 15,
 812         16, 17, 18, 19, 20, 21, 22, 23,
 813         24, 25, 26, 27, 28, 29, 30, 31,
 814         32, 33, 34, 35, 36, 37, 38, 39,
 815         40, 41, 42, 43, 44, 45, 46, 47,
 816         48, 49, 50, 51, 52, 53, 54, 55,
 817         56, 57, 58, 59, 60, 61, 62, 63
 818 };
 819
 820 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
 821         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
 822         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
 823         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
 824         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
 825         0, 1,                   /* AES */
 826         2, 3,                   /* SPDIF */
 827         -1, -1, -1, -1,
 828         -1, -1, -1, -1, -1, -1, -1, -1,
 829         -1, -1, -1, -1, -1, -1, -1, -1,
 830         -1, -1, -1, -1, -1, -1, -1, -1,
 831 };
 832
 833 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
 834         4, 5, 6, 7,             /* ADAT 1 */
 835         8, 9, 10, 11,           /* ADAT 2 */
 836         12, 13, 14, 15,         /* ADAT 3 */
 837         16, 17, 18, 19,         /* ADAT 4 */
 838         0, 1,                   /* AES */
 839         2, 3,                   /* SPDIF */
 840         -1, -1, -1, -1,
 841         -1, -1, -1, -1, -1, -1, -1, -1,
 842         -1, -1, -1, -1, -1, -1, -1, -1,
 843         -1, -1, -1, -1, -1, -1, -1, -1,
 844         -1, -1, -1, -1, -1, -1, -1, -1,
 845         -1, -1, -1, -1, -1, -1, -1, -1,
 846 };
 847
 848 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
 849         4, 5,                   /* ADAT 1 */
 850         6, 7,                   /* ADAT 2 */
 851         8, 9,                   /* ADAT 3 */
 852         10, 11,                 /* ADAT 4 */
 853         0, 1,                   /* AES */
 854         2, 3,                   /* SPDIF */
 855         -1, -1, -1, -1,
 856         -1, -1, -1, -1, -1, -1, -1, -1,
 857         -1, -1, -1, -1, -1, -1, -1, -1,
 858         -1, -1, -1, -1, -1, -1, -1, -1,
 859         -1, -1, -1, -1, -1, -1, -1, -1,
 860         -1, -1, -1, -1, -1, -1, -1, -1,
 861         -1, -1, -1, -1, -1, -1, -1, -1,
 862 };
 863
 864 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
 865         0, 1,                   /* line in */
 866         8, 9,                   /* aes in, */
 867         10, 11,                 /* spdif in */
 868         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
 869         2, 3, 4, 5,             /* AEB */
 870         -1, -1, -1, -1, -1, -1,
 871         -1, -1, -1, -1, -1, -1, -1, -1,
 872         -1, -1, -1, -1, -1, -1, -1, -1,
 873         -1, -1, -1, -1, -1, -1, -1, -1,
 874         -1, -1, -1, -1, -1, -1, -1, -1,
 875         -1, -1, -1, -1, -1, -1, -1, -1,
 876 };
 877
 878 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
 879         0, 1,                   /* line out */
 880         8, 9,                   /* aes out */
 881         10, 11,                 /* spdif out */
 882         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
 883         6, 7,                   /* phone out */
 884         2, 3, 4, 5,             /* AEB */
 885         -1, -1, -1, -1,
 886         -1, -1, -1, -1, -1, -1, -1, -1,
 887         -1, -1, -1, -1, -1, -1, -1, -1,
 888         -1, -1, -1, -1, -1, -1, -1, -1,
 889         -1, -1, -1, -1, -1, -1, -1, -1,
 890         -1, -1, -1, -1, -1, -1, -1, -1,
 891 };
 892
 893 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
 894         0, 1,                   /* line in */
 895         8, 9,                   /* aes in */
 896         10, 11,                 /* spdif in */
 897         12, 14, 16, 18,         /* adat in */
 898         2, 3, 4, 5,             /* AEB */
 899         -1, -1,
 900         -1, -1, -1, -1, -1, -1, -1, -1,
 901         -1, -1, -1, -1, -1, -1, -1, -1,
 902         -1, -1, -1, -1, -1, -1, -1, -1,
 903         -1, -1, -1, -1, -1, -1, -1, -1,
 904         -1, -1, -1, -1, -1, -1, -1, -1,
 905         -1, -1, -1, -1, -1, -1, -1, -1
 906 };
 907
 908 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
 909         0, 1,                   /* line out */
 910         8, 9,                   /* aes out */
 911         10, 11,                 /* spdif out */
 912         12, 14, 16, 18,         /* adat out */
 913         6, 7,                   /* phone out */
 914         2, 3, 4, 5,             /* AEB */
 915         -1, -1, -1, -1, -1, -1, -1, -1,
 916         -1, -1, -1, -1, -1, -1, -1, -1,
 917         -1, -1, -1, -1, -1, -1, -1, -1,
 918         -1, -1, -1, -1, -1, -1, -1, -1,
 919         -1, -1, -1, -1, -1, -1, -1, -1,
 920         -1, -1, -1, -1, -1, -1, -1, -1
 921 };
 922
 923 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
 924         0, 1,                   /* line in */
 925         8, 9,                   /* aes in */
 926         10, 11,                 /* spdif in */
 927         12, 16,                 /* adat in */
 928         2, 3, 4, 5,             /* AEB */
 929         -1, -1, -1, -1,
 930         -1, -1, -1, -1, -1, -1, -1, -1,
 931         -1, -1, -1, -1, -1, -1, -1, -1,
 932         -1, -1, -1, -1, -1, -1, -1, -1,
 933         -1, -1, -1, -1, -1, -1, -1, -1,
 934         -1, -1, -1, -1, -1, -1, -1, -1,
 935         -1, -1, -1, -1, -1, -1, -1, -1
 936 };
 937
 938 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
 939         0, 1,                   /* line out */
 940         8, 9,                   /* aes out */
 941         10, 11,                 /* spdif out */
 942         12, 16,                 /* adat out */
 943         6, 7,                   /* phone out */
 944         2, 3, 4, 5,             /* AEB */
 945         -1, -1,
 946         -1, -1, -1, -1, -1, -1, -1, -1,
 947         -1, -1, -1, -1, -1, -1, -1, -1,
 948         -1, -1, -1, -1, -1, -1, -1, -1,
 949         -1, -1, -1, -1, -1, -1, -1, -1,
 950         -1, -1, -1, -1, -1, -1, -1, -1,
 951         -1, -1, -1, -1, -1, -1, -1, -1
 952 };
 953
 954 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
 955         0, 1, 2, 3, 4, 5, 6, 7,
 956         8, 9, 10, 11, 12, 13, 14, 15,
 957         -1, -1, -1, -1, -1, -1, -1, -1,
 958         -1, -1, -1, -1, -1, -1, -1, -1,
 959         -1, -1, -1, -1, -1, -1, -1, -1,
 960         -1, -1, -1, -1, -1, -1, -1, -1,
 961         -1, -1, -1, -1, -1, -1, -1, -1,
 962         -1, -1, -1, -1, -1, -1, -1, -1
 963 };
 964
 965 struct hdspm_midi {
 966         struct hdspm *hdspm;
 967         int id;
 968         struct snd_rawmidi *rmidi;
 969         struct snd_rawmidi_substream *input;
 970         struct snd_rawmidi_substream *output;
 971         char istimer;           /* timer in use */
 972         struct timer_list timer;
 973         spinlock_t lock;
 974         int pending;
 975         int dataIn;
 976         int statusIn;
 977         int dataOut;
 978         int statusOut;
 979         int ie;
 980         int irq;
 981 };
 982
 983 struct hdspm_tco {
 984         int input; /* 0: LTC, 1:Video, 2: WC*/
 985         int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */
 986         int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */
 987         int samplerate; /* 0=44.1, 1=48, 2= freq from app */
 988         int pull; /*   0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/
 989         int term; /* 0 = off, 1 = on */
 990 };
 991
 992 struct hdspm {
 993         spinlock_t lock;
 994         /* only one playback and/or capture stream */
 995         struct snd_pcm_substream *capture_substream;
 996         struct snd_pcm_substream *playback_substream;
 997
 998         char *card_name;             /* for procinfo */
 999         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
1000
1001         uint8_t io_type;
1002
1003         int monitor_outs;       /* set up monitoring outs init flag */
1004
1005         u32 control_register;   /* cached value */
1006         u32 control2_register;  /* cached value */
1007         u32 settings_register;  /* cached value for AIO / RayDat (sync reference, master/slave) */
1008
1009         struct hdspm_midi midi[4];
1010         struct tasklet_struct midi_tasklet;
1011
1012         size_t period_bytes;
1013         unsigned char ss_in_channels;
1014         unsigned char ds_in_channels;
1015         unsigned char qs_in_channels;
1016         unsigned char ss_out_channels;
1017         unsigned char ds_out_channels;
1018         unsigned char qs_out_channels;
1019
1020         unsigned char max_channels_in;
1021         unsigned char max_channels_out;
1022
1023         signed char *channel_map_in;
1024         signed char *channel_map_out;
1025
1026         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
1027         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
1028
1029         char **port_names_in;
1030         char **port_names_out;
1031
1032         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
1033         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
1034
1035         unsigned char *playback_buffer; /* suitably aligned address */
1036         unsigned char *capture_buffer;  /* suitably aligned address */
1037
1038         pid_t capture_pid;      /* process id which uses capture */
1039         pid_t playback_pid;     /* process id which uses capture */
1040         int running;            /* running status */
1041
1042         int last_external_sample_rate;  /* samplerate mystic ... */
1043         int last_internal_sample_rate;
1044         int system_sample_rate;
1045
1046         int dev;                /* Hardware vars... */
1047         int irq;
1048         unsigned long port;
1049         void __iomem *iobase;
1050
1051         int irq_count;          /* for debug */
1052         int midiPorts;
1053
1054         struct snd_card *card;  /* one card */
1055         struct snd_pcm *pcm;            /* has one pcm */
1056         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
1057         struct pci_dev *pci;    /* and an pci info */
1058
1059         /* Mixer vars */
1060         /* fast alsa mixer */
1061         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
1062         /* but input to much, so not used */
1063         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
1064         /* full mixer accessible over mixer ioctl or hwdep-device */
1065         struct hdspm_mixer *mixer;
1066
1067         struct hdspm_tco *tco;  /* NULL if no TCO detected */
1068
1069         const char *const *texts_autosync;
1070         int texts_autosync_items;
1071
1072         cycles_t last_interrupt;
1073
1074         unsigned int serial;
1075
1076         struct hdspm_peak_rms peak_rms;
1077 };
1078
1079
1080 static const struct pci_device_id snd_hdspm_ids[] = {
1081         {
1082          .vendor = PCI_VENDOR_ID_XILINX,
1083          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
1084          .subvendor = PCI_ANY_ID,
1085          .subdevice = PCI_ANY_ID,
1086          .class = 0,
1087          .class_mask = 0,
1088          .driver_data = 0},
1089         {0,}
1090 };
1091
1092 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
1093
1094 /* prototypes */
1095 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1096                                          struct hdspm *hdspm);
1097 static int snd_hdspm_create_pcm(struct snd_card *card,
1098                                 struct hdspm *hdspm);
1099
1100 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1101 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1102 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1103 static int hdspm_autosync_ref(struct hdspm *hdspm);
1104 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1105 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1106 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1107 static void hdspm_set_sgbuf(struct hdspm *hdspm,
1108                             struct snd_pcm_substream *substream,
1109                              unsigned int reg, int channels);
1110
1111 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1112 static int hdspm_wc_sync_check(struct hdspm *hdspm);
1113 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1114 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1115
1116 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1117 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1118 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1119
1120
1121
1122 static inline int HDSPM_bit2freq(int n)
1123 {
1124         static const int bit2freq_tab[] = {
1125                 0, 32000, 44100, 48000, 64000, 88200,
1126                 96000, 128000, 176400, 192000 };
1127         if (n < 1 || n > 9)
1128                 return 0;
1129         return bit2freq_tab[n];
1130 }
1131
1132 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1133 {
1134         return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1135 }
1136
1137
1138 /* Write/read to/from HDSPM with Adresses in Bytes
1139    not words but only 32Bit writes are allowed */
1140
1141 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1142                                unsigned int val)
1143 {
1144         writel(val, hdspm->iobase + reg);
1145 }
1146
1147 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1148 {
1149         return readl(hdspm->iobase + reg);
1150 }
1151
1152 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1153    mixer is write only on hardware so we have to cache him for read
1154    each fader is a u32, but uses only the first 16 bit */
1155
1156 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1157                                      unsigned int in)
1158 {
1159         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1160                 return 0;
1161
1162         return hdspm->mixer->ch[chan].in[in];
1163 }
1164
1165 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1166                                      unsigned int pb)
1167 {
1168         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1169                 return 0;
1170         return hdspm->mixer->ch[chan].pb[pb];
1171 }
1172
1173 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1174                                       unsigned int in, unsigned short data)
1175 {
1176         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1177                 return -1;
1178
1179         hdspm_write(hdspm,
1180                     HDSPM_MADI_mixerBase +
1181                     ((in + 128 * chan) * sizeof(u32)),
1182                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1183         return 0;
1184 }
1185
1186 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1187                                       unsigned int pb, unsigned short data)
1188 {
1189         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1190                 return -1;
1191
1192         hdspm_write(hdspm,
1193                     HDSPM_MADI_mixerBase +
1194                     ((64 + pb + 128 * chan) * sizeof(u32)),
1195                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1196         return 0;
1197 }
1198
1199
1200 /* enable DMA for specific channels, now available for DSP-MADI */
1201 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1202 {
1203         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1204 }
1205
1206 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1207 {
1208         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1209 }
1210
1211 /* check if same process is writing and reading */
1212 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1213 {
1214         unsigned long flags;
1215         int ret = 1;
1216
1217         spin_lock_irqsave(&hdspm->lock, flags);
1218         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1219             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1220                 ret = 0;
1221         }
1222         spin_unlock_irqrestore(&hdspm->lock, flags);
1223         return ret;
1224 }
1225
1226 /* round arbitary sample rates to commonly known rates */
1227 static int hdspm_round_frequency(int rate)
1228 {
1229         if (rate < 38050)
1230                 return 32000;
1231         if (rate < 46008)
1232                 return 44100;
1233         else
1234                 return 48000;
1235 }
1236
1237 /* QS and DS rates normally can not be detected
1238  * automatically by the card. Only exception is MADI
1239  * in 96k frame mode.
1240  *
1241  * So if we read SS values (32 .. 48k), check for
1242  * user-provided DS/QS bits in the control register
1243  * and multiply the base frequency accordingly.
1244  */
1245 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1246 {
1247         if (rate <= 48000) {
1248                 if (hdspm->control_register & HDSPM_QuadSpeed)
1249                         return rate * 4;
1250                 else if (hdspm->control_register &
1251                                 HDSPM_DoubleSpeed)
1252                         return rate * 2;
1253         }
1254         return rate;
1255 }
1256
1257 /* check for external sample rate, returns the sample rate in Hz*/
1258 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1259 {
1260         unsigned int status, status2;
1261         int syncref, rate = 0, rate_bits;
1262
1263         switch (hdspm->io_type) {
1264         case AES32:
1265                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1266                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1267
1268                 syncref = hdspm_autosync_ref(hdspm);
1269                 switch (syncref) {
1270                 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
1271                 /* Check WC sync and get sample rate */
1272                         if (hdspm_wc_sync_check(hdspm))
1273                                 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm));
1274                         break;
1275
1276                 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
1277                 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
1278                 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
1279                 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
1280                 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
1281                 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
1282                 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
1283                 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
1284                 /* Check AES sync and get sample rate */
1285                         if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1286                                 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm,
1287                                                         syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1));
1288                         break;
1289
1290
1291                 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
1292                 /* Check TCO sync and get sample rate */
1293                         if (hdspm_tco_sync_check(hdspm))
1294                                 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm));
1295                         break;
1296                 default:
1297                         return 0;
1298                 } /* end switch(syncref) */
1299                 break;
1300
1301         case MADIface:
1302                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1303
1304                 if (!(status & HDSPM_madiLock)) {
1305                         rate = 0;  /* no lock */
1306                 } else {
1307                         switch (status & (HDSPM_status1_freqMask)) {
1308                         case HDSPM_status1_F_0*1:
1309                                 rate = 32000; break;
1310                         case HDSPM_status1_F_0*2:
1311                                 rate = 44100; break;
1312                         case HDSPM_status1_F_0*3:
1313                                 rate = 48000; break;
1314                         case HDSPM_status1_F_0*4:
1315                                 rate = 64000; break;
1316                         case HDSPM_status1_F_0*5:
1317                                 rate = 88200; break;
1318                         case HDSPM_status1_F_0*6:
1319                                 rate = 96000; break;
1320                         case HDSPM_status1_F_0*7:
1321                                 rate = 128000; break;
1322                         case HDSPM_status1_F_0*8:
1323                                 rate = 176400; break;
1324                         case HDSPM_status1_F_0*9:
1325                                 rate = 192000; break;
1326                         default:
1327                                 rate = 0; break;
1328                         }
1329                 }
1330
1331                 break;
1332
1333         case MADI:
1334         case AIO:
1335         case RayDAT:
1336                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1337                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1338                 rate = 0;
1339
1340                 /* if wordclock has synced freq and wordclock is valid */
1341                 if ((status2 & HDSPM_wcLock) != 0 &&
1342                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1343
1344                         rate_bits = status2 & HDSPM_wcFreqMask;
1345
1346
1347                         switch (rate_bits) {
1348                         case HDSPM_wcFreq32:
1349                                 rate = 32000;
1350                                 break;
1351                         case HDSPM_wcFreq44_1:
1352                                 rate = 44100;
1353                                 break;
1354                         case HDSPM_wcFreq48:
1355                                 rate = 48000;
1356                                 break;
1357                         case HDSPM_wcFreq64:
1358                                 rate = 64000;
1359                                 break;
1360                         case HDSPM_wcFreq88_2:
1361                                 rate = 88200;
1362                                 break;
1363                         case HDSPM_wcFreq96:
1364                                 rate = 96000;
1365                                 break;
1366                         case HDSPM_wcFreq128:
1367                                 rate = 128000;
1368                                 break;
1369                         case HDSPM_wcFreq176_4:
1370                                 rate = 176400;
1371                                 break;
1372                         case HDSPM_wcFreq192:
1373                                 rate = 192000;
1374                                 break;
1375                         default:
1376                                 rate = 0;
1377                                 break;
1378                         }
1379                 }
1380
1381                 /* if rate detected and Syncref is Word than have it,
1382                  * word has priority to MADI
1383                  */
1384                 if (rate != 0 &&
1385                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1386                         return hdspm_rate_multiplier(hdspm, rate);
1387
1388                 /* maybe a madi input (which is taken if sel sync is madi) */
1389                 if (status & HDSPM_madiLock) {
1390                         rate_bits = status & HDSPM_madiFreqMask;
1391
1392                         switch (rate_bits) {
1393                         case HDSPM_madiFreq32:
1394                                 rate = 32000;
1395                                 break;
1396                         case HDSPM_madiFreq44_1:
1397                                 rate = 44100;
1398                                 break;
1399                         case HDSPM_madiFreq48:
1400                                 rate = 48000;
1401                                 break;
1402                         case HDSPM_madiFreq64:
1403                                 rate = 64000;
1404                                 break;
1405                         case HDSPM_madiFreq88_2:
1406                                 rate = 88200;
1407                                 break;
1408                         case HDSPM_madiFreq96:
1409                                 rate = 96000;
1410                                 break;
1411                         case HDSPM_madiFreq128:
1412                                 rate = 128000;
1413                                 break;
1414                         case HDSPM_madiFreq176_4:
1415                                 rate = 176400;
1416                                 break;
1417                         case HDSPM_madiFreq192:
1418                                 rate = 192000;
1419                                 break;
1420                         default:
1421                                 rate = 0;
1422                                 break;
1423                         }
1424
1425                 } /* endif HDSPM_madiLock */
1426
1427                 /* check sample rate from TCO or SYNC_IN */
1428                 {
1429                         bool is_valid_input = 0;
1430                         bool has_sync = 0;
1431
1432                         syncref = hdspm_autosync_ref(hdspm);
1433                         if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1434                                 is_valid_input = 1;
1435                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1436                                         hdspm_tco_sync_check(hdspm));
1437                         } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1438                                 is_valid_input = 1;
1439                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1440                                         hdspm_sync_in_sync_check(hdspm));
1441                         }
1442
1443                         if (is_valid_input && has_sync) {
1444                                 rate = hdspm_round_frequency(
1445                                         hdspm_get_pll_freq(hdspm));
1446                         }
1447                 }
1448
1449                 rate = hdspm_rate_multiplier(hdspm, rate);
1450
1451                 break;
1452         }
1453
1454         return rate;
1455 }
1456
1457 /* return latency in samples per period */
1458 static int hdspm_get_latency(struct hdspm *hdspm)
1459 {
1460         int n;
1461
1462         n = hdspm_decode_latency(hdspm->control_register);
1463
1464         /* Special case for new RME cards with 32 samples period size.
1465          * The three latency bits in the control register
1466          * (HDSP_LatencyMask) encode latency values of 64 samples as
1467          * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1468          * denotes 8192 samples, but on new cards like RayDAT or AIO,
1469          * it corresponds to 32 samples.
1470          */
1471         if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1472                 n = -1;
1473
1474         return 1 << (n + 6);
1475 }
1476
1477 /* Latency function */
1478 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1479 {
1480         hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1481 }
1482
1483
1484 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1485 {
1486         int position;
1487
1488         position = hdspm_read(hdspm, HDSPM_statusRegister);
1489
1490         switch (hdspm->io_type) {
1491         case RayDAT:
1492         case AIO:
1493                 position &= HDSPM_BufferPositionMask;
1494                 position /= 4; /* Bytes per sample */
1495                 break;
1496         default:
1497                 position = (position & HDSPM_BufferID) ?
1498                         (hdspm->period_bytes / 4) : 0;
1499         }
1500
1501         return position;
1502 }
1503
1504
1505 static inline void hdspm_start_audio(struct hdspm * s)
1506 {
1507         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1508         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1509 }
1510
1511 static inline void hdspm_stop_audio(struct hdspm * s)
1512 {
1513         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1514         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1515 }
1516
1517 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1518 static void hdspm_silence_playback(struct hdspm *hdspm)
1519 {
1520         int i;
1521         int n = hdspm->period_bytes;
1522         void *buf = hdspm->playback_buffer;
1523
1524         if (buf == NULL)
1525                 return;
1526
1527         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1528                 memset(buf, 0, n);
1529                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1530         }
1531 }
1532
1533 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1534 {
1535         int n;
1536
1537         spin_lock_irq(&s->lock);
1538
1539         if (32 == frames) {
1540                 /* Special case for new RME cards like RayDAT/AIO which
1541                  * support period sizes of 32 samples. Since latency is
1542                  * encoded in the three bits of HDSP_LatencyMask, we can only
1543                  * have values from 0 .. 7. While 0 still means 64 samples and
1544                  * 6 represents 4096 samples on all cards, 7 represents 8192
1545                  * on older cards and 32 samples on new cards.
1546                  *
1547                  * In other words, period size in samples is calculated by
1548                  * 2^(n+6) with n ranging from 0 .. 7.
1549                  */
1550                 n = 7;
1551         } else {
1552                 frames >>= 7;
1553                 n = 0;
1554                 while (frames) {
1555                         n++;
1556                         frames >>= 1;
1557                 }
1558         }
1559
1560         s->control_register &= ~HDSPM_LatencyMask;
1561         s->control_register |= hdspm_encode_latency(n);
1562
1563         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1564
1565         hdspm_compute_period_size(s);
1566
1567         spin_unlock_irq(&s->lock);
1568
1569         return 0;
1570 }
1571
1572 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1573 {
1574         u64 freq_const;
1575
1576         if (period == 0)
1577                 return 0;
1578
1579         switch (hdspm->io_type) {
1580         case MADI:
1581         case AES32:
1582                 freq_const = 110069313433624ULL;
1583                 break;
1584         case RayDAT:
1585         case AIO:
1586                 freq_const = 104857600000000ULL;
1587                 break;
1588         case MADIface:
1589                 freq_const = 131072000000000ULL;
1590                 break;
1591         default:
1592                 snd_BUG();
1593                 return 0;
1594         }
1595
1596         return div_u64(freq_const, period);
1597 }
1598
1599
1600 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1601 {
1602         u64 n;
1603
1604         if (rate >= 112000)
1605                 rate /= 4;
1606         else if (rate >= 56000)
1607                 rate /= 2;
1608
1609         switch (hdspm->io_type) {
1610         case MADIface:
1611                 n = 131072000000000ULL;  /* 125 MHz */
1612                 break;
1613         case MADI:
1614         case AES32:
1615                 n = 110069313433624ULL;  /* 105 MHz */
1616                 break;
1617         case RayDAT:
1618         case AIO:
1619                 n = 104857600000000ULL;  /* 100 MHz */
1620                 break;
1621         default:
1622                 snd_BUG();
1623                 return;
1624         }
1625
1626         n = div_u64(n, rate);
1627         /* n should be less than 2^32 for being written to FREQ register */
1628         snd_BUG_ON(n >> 32);
1629         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1630 }
1631
1632 /* dummy set rate lets see what happens */
1633 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1634 {
1635         int current_rate;
1636         int rate_bits;
1637         int not_set = 0;
1638         int current_speed, target_speed;
1639
1640         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1641            it (e.g. during module initialization).
1642          */
1643
1644         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1645
1646                 /* SLAVE --- */
1647                 if (called_internally) {
1648
1649                         /* request from ctl or card initialization
1650                            just make a warning an remember setting
1651                            for future master mode switching */
1652
1653                         dev_warn(hdspm->card->dev,
1654                                  "Warning: device is not running as a clock master.\n");
1655                         not_set = 1;
1656                 } else {
1657
1658                         /* hw_param request while in AutoSync mode */
1659                         int external_freq =
1660                             hdspm_external_sample_rate(hdspm);
1661
1662                         if (hdspm_autosync_ref(hdspm) ==
1663                             HDSPM_AUTOSYNC_FROM_NONE) {
1664
1665                                 dev_warn(hdspm->card->dev,
1666                                          "Detected no Externel Sync\n");
1667                                 not_set = 1;
1668
1669                         } else if (rate != external_freq) {
1670
1671                                 dev_warn(hdspm->card->dev,
1672                                          "Warning: No AutoSync source for requested rate\n");
1673                                 not_set = 1;
1674                         }
1675                 }
1676         }
1677
1678         current_rate = hdspm->system_sample_rate;
1679
1680         /* Changing between Singe, Double and Quad speed is not
1681            allowed if any substreams are open. This is because such a change
1682            causes a shift in the location of the DMA buffers and a reduction
1683            in the number of available buffers.
1684
1685            Note that a similar but essentially insoluble problem exists for
1686            externally-driven rate changes. All we can do is to flag rate
1687            changes in the read/write routines.
1688          */
1689
1690         if (current_rate <= 48000)
1691                 current_speed = HDSPM_SPEED_SINGLE;
1692         else if (current_rate <= 96000)
1693                 current_speed = HDSPM_SPEED_DOUBLE;
1694         else
1695                 current_speed = HDSPM_SPEED_QUAD;
1696
1697         if (rate <= 48000)
1698                 target_speed = HDSPM_SPEED_SINGLE;
1699         else if (rate <= 96000)
1700                 target_speed = HDSPM_SPEED_DOUBLE;
1701         else
1702                 target_speed = HDSPM_SPEED_QUAD;
1703
1704         switch (rate) {
1705         case 32000:
1706                 rate_bits = HDSPM_Frequency32KHz;
1707                 break;
1708         case 44100:
1709                 rate_bits = HDSPM_Frequency44_1KHz;
1710                 break;
1711         case 48000:
1712                 rate_bits = HDSPM_Frequency48KHz;
1713                 break;
1714         case 64000:
1715                 rate_bits = HDSPM_Frequency64KHz;
1716                 break;
1717         case 88200:
1718                 rate_bits = HDSPM_Frequency88_2KHz;
1719                 break;
1720         case 96000:
1721                 rate_bits = HDSPM_Frequency96KHz;
1722                 break;
1723         case 128000:
1724                 rate_bits = HDSPM_Frequency128KHz;
1725                 break;
1726         case 176400:
1727                 rate_bits = HDSPM_Frequency176_4KHz;
1728                 break;
1729         case 192000:
1730                 rate_bits = HDSPM_Frequency192KHz;
1731                 break;
1732         default:
1733                 return -EINVAL;
1734         }
1735
1736         if (current_speed != target_speed
1737             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1738                 dev_err(hdspm->card->dev,
1739                         "cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n",
1740                         hdspm_speed_names[current_speed],
1741                         hdspm_speed_names[target_speed],
1742                         hdspm->capture_pid, hdspm->playback_pid);
1743                 return -EBUSY;
1744         }
1745
1746         hdspm->control_register &= ~HDSPM_FrequencyMask;
1747         hdspm->control_register |= rate_bits;
1748         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1749
1750         /* For AES32, need to set DDS value in FREQ register
1751            For MADI, also apparently */
1752         hdspm_set_dds_value(hdspm, rate);
1753
1754         if (AES32 == hdspm->io_type && rate != current_rate)
1755                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1756
1757         hdspm->system_sample_rate = rate;
1758
1759         if (rate <= 48000) {
1760                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1761                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1762                 hdspm->max_channels_in = hdspm->ss_in_channels;
1763                 hdspm->max_channels_out = hdspm->ss_out_channels;
1764                 hdspm->port_names_in = hdspm->port_names_in_ss;
1765                 hdspm->port_names_out = hdspm->port_names_out_ss;
1766         } else if (rate <= 96000) {
1767                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1768                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1769                 hdspm->max_channels_in = hdspm->ds_in_channels;
1770                 hdspm->max_channels_out = hdspm->ds_out_channels;
1771                 hdspm->port_names_in = hdspm->port_names_in_ds;
1772                 hdspm->port_names_out = hdspm->port_names_out_ds;
1773         } else {
1774                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1775                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1776                 hdspm->max_channels_in = hdspm->qs_in_channels;
1777                 hdspm->max_channels_out = hdspm->qs_out_channels;
1778                 hdspm->port_names_in = hdspm->port_names_in_qs;
1779                 hdspm->port_names_out = hdspm->port_names_out_qs;
1780         }
1781
1782         if (not_set != 0)
1783                 return -1;
1784
1785         return 0;
1786 }
1787
1788 /* mainly for init to 0 on load */
1789 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1790 {
1791         int i, j;
1792         unsigned int gain;
1793
1794         if (sgain > UNITY_GAIN)
1795                 gain = UNITY_GAIN;
1796         else if (sgain < 0)
1797                 gain = 0;
1798         else
1799                 gain = sgain;
1800
1801         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1802                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1803                         hdspm_write_in_gain(hdspm, i, j, gain);
1804                         hdspm_write_pb_gain(hdspm, i, j, gain);
1805                 }
1806 }
1807
1808 /*----------------------------------------------------------------------------
1809    MIDI
1810   ----------------------------------------------------------------------------*/
1811
1812 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1813                                                       int id)
1814 {
1815         /* the hardware already does the relevant bit-mask with 0xff */
1816         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1817 }
1818
1819 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1820                                               int val)
1821 {
1822         /* the hardware already does the relevant bit-mask with 0xff */
1823         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1824 }
1825
1826 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1827 {
1828         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1829 }
1830
1831 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1832 {
1833         int fifo_bytes_used;
1834
1835         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1836
1837         if (fifo_bytes_used < 128)
1838                 return  128 - fifo_bytes_used;
1839         else
1840                 return 0;
1841 }
1842
1843 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1844 {
1845         while (snd_hdspm_midi_input_available (hdspm, id))
1846                 snd_hdspm_midi_read_byte (hdspm, id);
1847 }
1848
1849 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1850 {
1851         unsigned long flags;
1852         int n_pending;
1853         int to_write;
1854         int i;
1855         unsigned char buf[128];
1856
1857         /* Output is not interrupt driven */
1858
1859         spin_lock_irqsave (&hmidi->lock, flags);
1860         if (hmidi->output &&
1861             !snd_rawmidi_transmit_empty (hmidi->output)) {
1862                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1863                                                             hmidi->id);
1864                 if (n_pending > 0) {
1865                         if (n_pending > (int)sizeof (buf))
1866                                 n_pending = sizeof (buf);
1867
1868                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1869                                                          n_pending);
1870                         if (to_write > 0) {
1871                                 for (i = 0; i < to_write; ++i)
1872                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1873                                                                    hmidi->id,
1874                                                                    buf[i]);
1875                         }
1876                 }
1877         }
1878         spin_unlock_irqrestore (&hmidi->lock, flags);
1879         return 0;
1880 }
1881
1882 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1883 {
1884         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1885                                  * input FIFO size
1886                                  */
1887         unsigned long flags;
1888         int n_pending;
1889         int i;
1890
1891         spin_lock_irqsave (&hmidi->lock, flags);
1892         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1893         if (n_pending > 0) {
1894                 if (hmidi->input) {
1895                         if (n_pending > (int)sizeof (buf))
1896                                 n_pending = sizeof (buf);
1897                         for (i = 0; i < n_pending; ++i)
1898                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1899                                                                    hmidi->id);
1900                         if (n_pending)
1901                                 snd_rawmidi_receive (hmidi->input, buf,
1902                                                      n_pending);
1903                 } else {
1904                         /* flush the MIDI input FIFO */
1905                         while (n_pending--)
1906                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1907                                                           hmidi->id);
1908                 }
1909         }
1910         hmidi->pending = 0;
1911         spin_unlock_irqrestore(&hmidi->lock, flags);
1912
1913         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1914         hmidi->hdspm->control_register |= hmidi->ie;
1915         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1916                     hmidi->hdspm->control_register);
1917         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1918
1919         return snd_hdspm_midi_output_write (hmidi);
1920 }
1921
1922 static void
1923 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1924 {
1925         struct hdspm *hdspm;
1926         struct hdspm_midi *hmidi;
1927         unsigned long flags;
1928
1929         hmidi = substream->rmidi->private_data;
1930         hdspm = hmidi->hdspm;
1931
1932         spin_lock_irqsave (&hdspm->lock, flags);
1933         if (up) {
1934                 if (!(hdspm->control_register & hmidi->ie)) {
1935                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1936                         hdspm->control_register |= hmidi->ie;
1937                 }
1938         } else {
1939                 hdspm->control_register &= ~hmidi->ie;
1940         }
1941
1942         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1943         spin_unlock_irqrestore (&hdspm->lock, flags);
1944 }
1945
1946 static void snd_hdspm_midi_output_timer(unsigned long data)
1947 {
1948         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1949         unsigned long flags;
1950
1951         snd_hdspm_midi_output_write(hmidi);
1952         spin_lock_irqsave (&hmidi->lock, flags);
1953
1954         /* this does not bump hmidi->istimer, because the
1955            kernel automatically removed the timer when it
1956            expired, and we are now adding it back, thus
1957            leaving istimer wherever it was set before.
1958         */
1959
1960         if (hmidi->istimer)
1961                 mod_timer(&hmidi->timer, 1 + jiffies);
1962
1963         spin_unlock_irqrestore (&hmidi->lock, flags);
1964 }
1965
1966 static void
1967 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1968 {
1969         struct hdspm_midi *hmidi;
1970         unsigned long flags;
1971
1972         hmidi = substream->rmidi->private_data;
1973         spin_lock_irqsave (&hmidi->lock, flags);
1974         if (up) {
1975                 if (!hmidi->istimer) {
1976                         setup_timer(&hmidi->timer, snd_hdspm_midi_output_timer,
1977                                     (unsigned long) hmidi);
1978                         mod_timer(&hmidi->timer, 1 + jiffies);
1979                         hmidi->istimer++;
1980                 }
1981         } else {
1982                 if (hmidi->istimer && --hmidi->istimer <= 0)
1983                         del_timer (&hmidi->timer);
1984         }
1985         spin_unlock_irqrestore (&hmidi->lock, flags);
1986         if (up)
1987                 snd_hdspm_midi_output_write(hmidi);
1988 }
1989
1990 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1991 {
1992         struct hdspm_midi *hmidi;
1993
1994         hmidi = substream->rmidi->private_data;
1995         spin_lock_irq (&hmidi->lock);
1996         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1997         hmidi->input = substream;
1998         spin_unlock_irq (&hmidi->lock);
1999
2000         return 0;
2001 }
2002
2003 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
2004 {
2005         struct hdspm_midi *hmidi;
2006
2007         hmidi = substream->rmidi->private_data;
2008         spin_lock_irq (&hmidi->lock);
2009         hmidi->output = substream;
2010         spin_unlock_irq (&hmidi->lock);
2011
2012         return 0;
2013 }
2014
2015 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
2016 {
2017         struct hdspm_midi *hmidi;
2018
2019         snd_hdspm_midi_input_trigger (substream, 0);
2020
2021         hmidi = substream->rmidi->private_data;
2022         spin_lock_irq (&hmidi->lock);
2023         hmidi->input = NULL;
2024         spin_unlock_irq (&hmidi->lock);
2025
2026         return 0;
2027 }
2028
2029 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
2030 {
2031         struct hdspm_midi *hmidi;
2032
2033         snd_hdspm_midi_output_trigger (substream, 0);
2034
2035         hmidi = substream->rmidi->private_data;
2036         spin_lock_irq (&hmidi->lock);
2037         hmidi->output = NULL;
2038         spin_unlock_irq (&hmidi->lock);
2039
2040         return 0;
2041 }
2042
2043 static struct snd_rawmidi_ops snd_hdspm_midi_output =
2044 {
2045         .open =         snd_hdspm_midi_output_open,
2046         .close =        snd_hdspm_midi_output_close,
2047         .trigger =      snd_hdspm_midi_output_trigger,
2048 };
2049
2050 static struct snd_rawmidi_ops snd_hdspm_midi_input =
2051 {
2052         .open =         snd_hdspm_midi_input_open,
2053         .close =        snd_hdspm_midi_input_close,
2054         .trigger =      snd_hdspm_midi_input_trigger,
2055 };
2056
2057 static int snd_hdspm_create_midi(struct snd_card *card,
2058                                  struct hdspm *hdspm, int id)
2059 {
2060         int err;
2061         char buf[32];
2062
2063         hdspm->midi[id].id = id;
2064         hdspm->midi[id].hdspm = hdspm;
2065         spin_lock_init (&hdspm->midi[id].lock);
2066
2067         if (0 == id) {
2068                 if (MADIface == hdspm->io_type) {
2069                         /* MIDI-over-MADI on HDSPe MADIface */
2070                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
2071                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
2072                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
2073                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
2074                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
2075                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
2076                 } else {
2077                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
2078                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
2079                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
2080                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
2081                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2082                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2083                 }
2084         } else if (1 == id) {
2085                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2086                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2087                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2088                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2089                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2090                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2091         } else if ((2 == id) && (MADI == hdspm->io_type)) {
2092                 /* MIDI-over-MADI on HDSPe MADI */
2093                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2094                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2095                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2096                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2097                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2098                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2099         } else if (2 == id) {
2100                 /* TCO MTC, read only */
2101                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2102                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2103                 hdspm->midi[2].dataOut = -1;
2104                 hdspm->midi[2].statusOut = -1;
2105                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2106                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2107         } else if (3 == id) {
2108                 /* TCO MTC on HDSPe MADI */
2109                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2110                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2111                 hdspm->midi[3].dataOut = -1;
2112                 hdspm->midi[3].statusOut = -1;
2113                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2114                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2115         }
2116
2117         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2118                                         (MADIface == hdspm->io_type)))) {
2119                 if ((id == 0) && (MADIface == hdspm->io_type)) {
2120                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
2121                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
2122                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
2123                 } else {
2124                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
2125                 }
2126                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2127                                 &hdspm->midi[id].rmidi);
2128                 if (err < 0)
2129                         return err;
2130
2131                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
2132                                 card->id, id+1);
2133                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2134
2135                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2136                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
2137                                 &snd_hdspm_midi_output);
2138                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2139                                 SNDRV_RAWMIDI_STREAM_INPUT,
2140                                 &snd_hdspm_midi_input);
2141
2142                 hdspm->midi[id].rmidi->info_flags |=
2143                         SNDRV_RAWMIDI_INFO_OUTPUT |
2144                         SNDRV_RAWMIDI_INFO_INPUT |
2145                         SNDRV_RAWMIDI_INFO_DUPLEX;
2146         } else {
2147                 /* TCO MTC, read only */
2148                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
2149                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2150                                 &hdspm->midi[id].rmidi);
2151                 if (err < 0)
2152                         return err;
2153
2154                 sprintf(hdspm->midi[id].rmidi->name,
2155                                 "%s MTC %d", card->id, id+1);
2156                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2157
2158                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2159                                 SNDRV_RAWMIDI_STREAM_INPUT,
2160                                 &snd_hdspm_midi_input);
2161
2162                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2163         }
2164
2165         return 0;
2166 }
2167
2168
2169 static void hdspm_midi_tasklet(unsigned long arg)
2170 {
2171         struct hdspm *hdspm = (struct hdspm *)arg;
2172         int i = 0;
2173
2174         while (i < hdspm->midiPorts) {
2175                 if (hdspm->midi[i].pending)
2176                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
2177
2178                 i++;
2179         }
2180 }
2181
2182
2183 /*-----------------------------------------------------------------------------
2184   Status Interface
2185   ----------------------------------------------------------------------------*/
2186
2187 /* get the system sample rate which is set */
2188
2189
2190 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2191 {
2192         unsigned int period, rate;
2193
2194         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2195         rate = hdspm_calc_dds_value(hdspm, period);
2196
2197         return rate;
2198 }
2199
2200 /*
2201  * Calculate the real sample rate from the
2202  * current DDS value.
2203  */
2204 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2205 {
2206         unsigned int rate;
2207
2208         rate = hdspm_get_pll_freq(hdspm);
2209
2210         if (rate > 207000) {
2211                 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2212                 if (0 == hdspm_system_clock_mode(hdspm)) {
2213                         /* master mode, return internal sample rate */
2214                         rate = hdspm->system_sample_rate;
2215                 } else {
2216                         /* slave mode, return external sample rate */
2217                         rate = hdspm_external_sample_rate(hdspm);
2218                 }
2219         }
2220
2221         return rate;
2222 }
2223
2224
2225 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2226 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2227         .name = xname, \
2228         .index = xindex, \
2229         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2230                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2231         .info = snd_hdspm_info_system_sample_rate, \
2232         .put = snd_hdspm_put_system_sample_rate, \
2233         .get = snd_hdspm_get_system_sample_rate \
2234 }
2235
2236 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2237                                              struct snd_ctl_elem_info *uinfo)
2238 {
2239         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2240         uinfo->count = 1;
2241         uinfo->value.integer.min = 27000;
2242         uinfo->value.integer.max = 207000;
2243         uinfo->value.integer.step = 1;
2244         return 0;
2245 }
2246
2247
2248 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2249                                             struct snd_ctl_elem_value *
2250                                             ucontrol)
2251 {
2252         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2253
2254         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2255         return 0;
2256 }
2257
2258 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2259                                             struct snd_ctl_elem_value *
2260                                             ucontrol)
2261 {
2262         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2263
2264         hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2265         return 0;
2266 }
2267
2268
2269 /*
2270  * Returns the WordClock sample rate class for the given card.
2271  */
2272 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2273 {
2274         int status;
2275
2276         switch (hdspm->io_type) {
2277         case RayDAT:
2278         case AIO:
2279                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2280                 return (status >> 16) & 0xF;
2281                 break;
2282         case AES32:
2283                 status = hdspm_read(hdspm, HDSPM_statusRegister);
2284                 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF;
2285         default:
2286                 break;
2287         }
2288
2289
2290         return 0;
2291 }
2292
2293
2294 /*
2295  * Returns the TCO sample rate class for the given card.
2296  */
2297 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2298 {
2299         int status;
2300
2301         if (hdspm->tco) {
2302                 switch (hdspm->io_type) {
2303                 case RayDAT:
2304                 case AIO:
2305                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2306                         return (status >> 20) & 0xF;
2307                         break;
2308                 case AES32:
2309                         status = hdspm_read(hdspm, HDSPM_statusRegister);
2310                         return (status >> 1) & 0xF;
2311                 default:
2312                         break;
2313                 }
2314         }
2315
2316         return 0;
2317 }
2318
2319
2320 /*
2321  * Returns the SYNC_IN sample rate class for the given card.
2322  */
2323 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2324 {
2325         int status;
2326
2327         if (hdspm->tco) {
2328                 switch (hdspm->io_type) {
2329                 case RayDAT:
2330                 case AIO:
2331                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2332                         return (status >> 12) & 0xF;
2333                         break;
2334                 default:
2335                         break;
2336                 }
2337         }
2338
2339         return 0;
2340 }
2341
2342 /*
2343  * Returns the AES sample rate class for the given card.
2344  */
2345 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2346 {
2347         int timecode;
2348
2349         switch (hdspm->io_type) {
2350         case AES32:
2351                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2352                 return (timecode >> (4*index)) & 0xF;
2353                 break;
2354         default:
2355                 break;
2356         }
2357         return 0;
2358 }
2359
2360 /*
2361  * Returns the sample rate class for input source <idx> for
2362  * 'new style' cards like the AIO and RayDAT.
2363  */
2364 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2365 {
2366         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2367
2368         return (status >> (idx*4)) & 0xF;
2369 }
2370
2371 #define ENUMERATED_CTL_INFO(info, texts) \
2372         snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts)
2373
2374
2375 /* Helper function to query the external sample rate and return the
2376  * corresponding enum to be returned to userspace.
2377  */
2378 static int hdspm_external_rate_to_enum(struct hdspm *hdspm)
2379 {
2380         int rate = hdspm_external_sample_rate(hdspm);
2381         int i, selected_rate = 0;
2382         for (i = 1; i < 10; i++)
2383                 if (HDSPM_bit2freq(i) == rate) {
2384                         selected_rate = i;
2385                         break;
2386                 }
2387         return selected_rate;
2388 }
2389
2390
2391 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2392 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2393         .name = xname, \
2394         .private_value = xindex, \
2395         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2396         .info = snd_hdspm_info_autosync_sample_rate, \
2397         .get = snd_hdspm_get_autosync_sample_rate \
2398 }
2399
2400
2401 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2402                                                struct snd_ctl_elem_info *uinfo)
2403 {
2404         ENUMERATED_CTL_INFO(uinfo, texts_freq);
2405         return 0;
2406 }
2407
2408
2409 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2410                                               struct snd_ctl_elem_value *
2411                                               ucontrol)
2412 {
2413         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2414
2415         switch (hdspm->io_type) {
2416         case RayDAT:
2417                 switch (kcontrol->private_value) {
2418                 case 0:
2419                         ucontrol->value.enumerated.item[0] =
2420                                 hdspm_get_wc_sample_rate(hdspm);
2421                         break;
2422                 case 7:
2423                         ucontrol->value.enumerated.item[0] =
2424                                 hdspm_get_tco_sample_rate(hdspm);
2425                         break;
2426                 case 8:
2427                         ucontrol->value.enumerated.item[0] =
2428                                 hdspm_get_sync_in_sample_rate(hdspm);
2429                         break;
2430                 default:
2431                         ucontrol->value.enumerated.item[0] =
2432                                 hdspm_get_s1_sample_rate(hdspm,
2433                                                 kcontrol->private_value-1);
2434                 }
2435                 break;
2436
2437         case AIO:
2438                 switch (kcontrol->private_value) {
2439                 case 0: /* WC */
2440                         ucontrol->value.enumerated.item[0] =
2441                                 hdspm_get_wc_sample_rate(hdspm);
2442                         break;
2443                 case 4: /* TCO */
2444                         ucontrol->value.enumerated.item[0] =
2445                                 hdspm_get_tco_sample_rate(hdspm);
2446                         break;
2447                 case 5: /* SYNC_IN */
2448                         ucontrol->value.enumerated.item[0] =
2449                                 hdspm_get_sync_in_sample_rate(hdspm);
2450                         break;
2451                 default:
2452                         ucontrol->value.enumerated.item[0] =
2453                                 hdspm_get_s1_sample_rate(hdspm,
2454                                                 kcontrol->private_value-1);
2455                 }
2456                 break;
2457
2458         case AES32:
2459
2460                 switch (kcontrol->private_value) {
2461                 case 0: /* WC */
2462                         ucontrol->value.enumerated.item[0] =
2463                                 hdspm_get_wc_sample_rate(hdspm);
2464                         break;
2465                 case 9: /* TCO */
2466                         ucontrol->value.enumerated.item[0] =
2467                                 hdspm_get_tco_sample_rate(hdspm);
2468                         break;
2469                 case 10: /* SYNC_IN */
2470                         ucontrol->value.enumerated.item[0] =
2471                                 hdspm_get_sync_in_sample_rate(hdspm);
2472                         break;
2473                 case 11: /* External Rate */
2474                         ucontrol->value.enumerated.item[0] =
2475                                 hdspm_external_rate_to_enum(hdspm);
2476                         break;
2477                 default: /* AES1 to AES8 */
2478                         ucontrol->value.enumerated.item[0] =
2479                                 hdspm_get_aes_sample_rate(hdspm,
2480                                                 kcontrol->private_value -
2481                                                 HDSPM_AES32_AUTOSYNC_FROM_AES1);
2482                         break;
2483                 }
2484                 break;
2485
2486         case MADI:
2487         case MADIface:
2488                 ucontrol->value.enumerated.item[0] =
2489                         hdspm_external_rate_to_enum(hdspm);
2490                 break;
2491         default:
2492                 break;
2493         }
2494
2495         return 0;
2496 }
2497
2498
2499 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2500 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2501         .name = xname, \
2502         .index = xindex, \
2503         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2504                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2505         .info = snd_hdspm_info_system_clock_mode, \
2506         .get = snd_hdspm_get_system_clock_mode, \
2507         .put = snd_hdspm_put_system_clock_mode, \
2508 }
2509
2510
2511 /*
2512  * Returns the system clock mode for the given card.
2513  * @returns 0 - master, 1 - slave
2514  */
2515 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2516 {
2517         switch (hdspm->io_type) {
2518         case AIO:
2519         case RayDAT:
2520                 if (hdspm->settings_register & HDSPM_c0Master)
2521                         return 0;
2522                 break;
2523
2524         default:
2525                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2526                         return 0;
2527         }
2528
2529         return 1;
2530 }
2531
2532
2533 /*
2534  * Sets the system clock mode.
2535  * @param mode 0 - master, 1 - slave
2536  */
2537 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2538 {
2539         hdspm_set_toggle_setting(hdspm,
2540                         (hdspm_is_raydat_or_aio(hdspm)) ?
2541                         HDSPM_c0Master : HDSPM_ClockModeMaster,
2542                         (0 == mode));
2543 }
2544
2545
2546 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2547                                             struct snd_ctl_elem_info *uinfo)
2548 {
2549         static const char *const texts[] = { "Master", "AutoSync" };
2550         ENUMERATED_CTL_INFO(uinfo, texts);
2551         return 0;
2552 }
2553
2554 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2555                                            struct snd_ctl_elem_value *ucontrol)
2556 {
2557         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2558
2559         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2560         return 0;
2561 }
2562
2563 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2564                                            struct snd_ctl_elem_value *ucontrol)
2565 {
2566         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2567         int val;
2568
2569         if (!snd_hdspm_use_is_exclusive(hdspm))
2570                 return -EBUSY;
2571
2572         val = ucontrol->value.enumerated.item[0];
2573         if (val < 0)
2574                 val = 0;
2575         else if (val > 1)
2576                 val = 1;
2577
2578         hdspm_set_system_clock_mode(hdspm, val);
2579
2580         return 0;
2581 }
2582
2583
2584 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2585 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2586         .name = xname, \
2587         .index = xindex, \
2588         .info = snd_hdspm_info_clock_source, \
2589         .get = snd_hdspm_get_clock_source, \
2590         .put = snd_hdspm_put_clock_source \
2591 }
2592
2593
2594 static int hdspm_clock_source(struct hdspm * hdspm)
2595 {
2596         switch (hdspm->system_sample_rate) {
2597         case 32000: return 0;
2598         case 44100: return 1;
2599         case 48000: return 2;
2600         case 64000: return 3;
2601         case 88200: return 4;
2602         case 96000: return 5;
2603         case 128000: return 6;
2604         case 176400: return 7;
2605         case 192000: return 8;
2606         }
2607
2608         return -1;
2609 }
2610
2611 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2612 {
2613         int rate;
2614         switch (mode) {
2615         case 0:
2616                 rate = 32000; break;
2617         case 1:
2618                 rate = 44100; break;
2619         case 2:
2620                 rate = 48000; break;
2621         case 3:
2622                 rate = 64000; break;
2623         case 4:
2624                 rate = 88200; break;
2625         case 5:
2626                 rate = 96000; break;
2627         case 6:
2628                 rate = 128000; break;
2629         case 7:
2630                 rate = 176400; break;
2631         case 8:
2632                 rate = 192000; break;
2633         default:
2634                 rate = 48000;
2635         }
2636         hdspm_set_rate(hdspm, rate, 1);
2637         return 0;
2638 }
2639
2640 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2641                                        struct snd_ctl_elem_info *uinfo)
2642 {
2643         return snd_ctl_enum_info(uinfo, 1, 9, texts_freq + 1);
2644 }
2645
2646 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2647                                       struct snd_ctl_elem_value *ucontrol)
2648 {
2649         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2650
2651         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2652         return 0;
2653 }
2654
2655 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2656                                       struct snd_ctl_elem_value *ucontrol)
2657 {
2658         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2659         int change;
2660         int val;
2661
2662         if (!snd_hdspm_use_is_exclusive(hdspm))
2663                 return -EBUSY;
2664         val = ucontrol->value.enumerated.item[0];
2665         if (val < 0)
2666                 val = 0;
2667         if (val > 9)
2668                 val = 9;
2669         spin_lock_irq(&hdspm->lock);
2670         if (val != hdspm_clock_source(hdspm))
2671                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2672         else
2673                 change = 0;
2674         spin_unlock_irq(&hdspm->lock);
2675         return change;
2676 }
2677
2678
2679 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2680 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2681         .name = xname, \
2682         .index = xindex, \
2683         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2684                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2685         .info = snd_hdspm_info_pref_sync_ref, \
2686         .get = snd_hdspm_get_pref_sync_ref, \
2687         .put = snd_hdspm_put_pref_sync_ref \
2688 }
2689
2690
2691 /*
2692  * Returns the current preferred sync reference setting.
2693  * The semantics of the return value are depending on the
2694  * card, please see the comments for clarification.
2695  */
2696 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2697 {
2698         switch (hdspm->io_type) {
2699         case AES32:
2700                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2701                 case 0: return 0;  /* WC */
2702                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2703                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2704                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2705                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2706                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2707                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2708                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2709                                                     return 7; /* AES 7 */
2710                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2711                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2712                 }
2713                 break;
2714
2715         case MADI:
2716         case MADIface:
2717                 if (hdspm->tco) {
2718                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2719                         case 0: return 0;  /* WC */
2720                         case HDSPM_SyncRef0: return 1;  /* MADI */
2721                         case HDSPM_SyncRef1: return 2;  /* TCO */
2722                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2723                                              return 3;  /* SYNC_IN */
2724                         }
2725                 } else {
2726                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2727                         case 0: return 0;  /* WC */
2728                         case HDSPM_SyncRef0: return 1;  /* MADI */
2729                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2730                                              return 2;  /* SYNC_IN */
2731                         }
2732                 }
2733                 break;
2734
2735         case RayDAT:
2736                 if (hdspm->tco) {
2737                         switch ((hdspm->settings_register &
2738                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2739                         case 0: return 0;  /* WC */
2740                         case 3: return 1;  /* ADAT 1 */
2741                         case 4: return 2;  /* ADAT 2 */
2742                         case 5: return 3;  /* ADAT 3 */
2743                         case 6: return 4;  /* ADAT 4 */
2744                         case 1: return 5;  /* AES */
2745                         case 2: return 6;  /* SPDIF */
2746                         case 9: return 7;  /* TCO */
2747                         case 10: return 8; /* SYNC_IN */
2748                         }
2749                 } else {
2750                         switch ((hdspm->settings_register &
2751                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2752                         case 0: return 0;  /* WC */
2753                         case 3: return 1;  /* ADAT 1 */
2754                         case 4: return 2;  /* ADAT 2 */
2755                         case 5: return 3;  /* ADAT 3 */
2756                         case 6: return 4;  /* ADAT 4 */
2757                         case 1: return 5;  /* AES */
2758                         case 2: return 6;  /* SPDIF */
2759                         case 10: return 7; /* SYNC_IN */
2760                         }
2761                 }
2762
2763                 break;
2764
2765         case AIO:
2766                 if (hdspm->tco) {
2767                         switch ((hdspm->settings_register &
2768                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2769                         case 0: return 0;  /* WC */
2770                         case 3: return 1;  /* ADAT */
2771                         case 1: return 2;  /* AES */
2772                         case 2: return 3;  /* SPDIF */
2773                         case 9: return 4;  /* TCO */
2774                         case 10: return 5; /* SYNC_IN */
2775                         }
2776                 } else {
2777                         switch ((hdspm->settings_register &
2778                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2779                         case 0: return 0;  /* WC */
2780                         case 3: return 1;  /* ADAT */
2781                         case 1: return 2;  /* AES */
2782                         case 2: return 3;  /* SPDIF */
2783                         case 10: return 4; /* SYNC_IN */
2784                         }
2785                 }
2786
2787                 break;
2788         }
2789
2790         return -1;
2791 }
2792
2793
2794 /*
2795  * Set the preferred sync reference to <pref>. The semantics
2796  * of <pref> are depending on the card type, see the comments
2797  * for clarification.
2798  */
2799 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2800 {
2801         int p = 0;
2802
2803         switch (hdspm->io_type) {
2804         case AES32:
2805                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2806                 switch (pref) {
2807                 case 0: /* WC  */
2808                         break;
2809                 case 1: /* AES 1 */
2810                         hdspm->control_register |= HDSPM_SyncRef0;
2811                         break;
2812                 case 2: /* AES 2 */
2813                         hdspm->control_register |= HDSPM_SyncRef1;
2814                         break;
2815                 case 3: /* AES 3 */
2816                         hdspm->control_register |=
2817                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2818                         break;
2819                 case 4: /* AES 4 */
2820                         hdspm->control_register |= HDSPM_SyncRef2;
2821                         break;
2822                 case 5: /* AES 5 */
2823                         hdspm->control_register |=
2824                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2825                         break;
2826                 case 6: /* AES 6 */
2827                         hdspm->control_register |=
2828                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2829                         break;
2830                 case 7: /* AES 7 */
2831                         hdspm->control_register |=
2832                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2833                         break;
2834                 case 8: /* AES 8 */
2835                         hdspm->control_register |= HDSPM_SyncRef3;
2836                         break;
2837                 case 9: /* TCO */
2838                         hdspm->control_register |=
2839                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2840                         break;
2841                 default:
2842                         return -1;
2843                 }
2844
2845                 break;
2846
2847         case MADI:
2848         case MADIface:
2849                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2850                 if (hdspm->tco) {
2851                         switch (pref) {
2852                         case 0: /* WC */
2853                                 break;
2854                         case 1: /* MADI */
2855                                 hdspm->control_register |= HDSPM_SyncRef0;
2856                                 break;
2857                         case 2: /* TCO */
2858                                 hdspm->control_register |= HDSPM_SyncRef1;
2859                                 break;
2860                         case 3: /* SYNC_IN */
2861                                 hdspm->control_register |=
2862                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2863                                 break;
2864                         default:
2865                                 return -1;
2866                         }
2867                 } else {
2868                         switch (pref) {
2869                         case 0: /* WC */
2870                                 break;
2871                         case 1: /* MADI */
2872                                 hdspm->control_register |= HDSPM_SyncRef0;
2873                                 break;
2874                         case 2: /* SYNC_IN */
2875                                 hdspm->control_register |=
2876                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2877                                 break;
2878                         default:
2879                                 return -1;
2880                         }
2881                 }
2882
2883                 break;
2884
2885         case RayDAT:
2886                 if (hdspm->tco) {
2887                         switch (pref) {
2888                         case 0: p = 0; break;  /* WC */
2889                         case 1: p = 3; break;  /* ADAT 1 */
2890                         case 2: p = 4; break;  /* ADAT 2 */
2891                         case 3: p = 5; break;  /* ADAT 3 */
2892                         case 4: p = 6; break;  /* ADAT 4 */
2893                         case 5: p = 1; break;  /* AES */
2894                         case 6: p = 2; break;  /* SPDIF */
2895                         case 7: p = 9; break;  /* TCO */
2896                         case 8: p = 10; break; /* SYNC_IN */
2897                         default: return -1;
2898                         }
2899                 } else {
2900                         switch (pref) {
2901                         case 0: p = 0; break;  /* WC */
2902                         case 1: p = 3; break;  /* ADAT 1 */
2903                         case 2: p = 4; break;  /* ADAT 2 */
2904                         case 3: p = 5; break;  /* ADAT 3 */
2905                         case 4: p = 6; break;  /* ADAT 4 */
2906                         case 5: p = 1; break;  /* AES */
2907                         case 6: p = 2; break;  /* SPDIF */
2908                         case 7: p = 10; break; /* SYNC_IN */
2909                         default: return -1;
2910                         }
2911                 }
2912                 break;
2913
2914         case AIO:
2915                 if (hdspm->tco) {
2916                         switch (pref) {
2917                         case 0: p = 0; break;  /* WC */
2918                         case 1: p = 3; break;  /* ADAT */
2919                         case 2: p = 1; break;  /* AES */
2920                         case 3: p = 2; break;  /* SPDIF */
2921                         case 4: p = 9; break;  /* TCO */
2922                         case 5: p = 10; break; /* SYNC_IN */
2923                         default: return -1;
2924                         }
2925                 } else {
2926                         switch (pref) {
2927                         case 0: p = 0; break;  /* WC */
2928                         case 1: p = 3; break;  /* ADAT */
2929                         case 2: p = 1; break;  /* AES */
2930                         case 3: p = 2; break;  /* SPDIF */
2931                         case 4: p = 10; break; /* SYNC_IN */
2932                         default: return -1;
2933                         }
2934                 }
2935                 break;
2936         }
2937
2938         switch (hdspm->io_type) {
2939         case RayDAT:
2940         case AIO:
2941                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2942                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2943                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2944                 break;
2945
2946         case MADI:
2947         case MADIface:
2948         case AES32:
2949                 hdspm_write(hdspm, HDSPM_controlRegister,
2950                                 hdspm->control_register);
2951         }
2952
2953         return 0;
2954 }
2955
2956
2957 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2958                                         struct snd_ctl_elem_info *uinfo)
2959 {
2960         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2961
2962         snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync);
2963
2964         return 0;
2965 }
2966
2967 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2968                                        struct snd_ctl_elem_value *ucontrol)
2969 {
2970         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2971         int psf = hdspm_pref_sync_ref(hdspm);
2972
2973         if (psf >= 0) {
2974                 ucontrol->value.enumerated.item[0] = psf;
2975                 return 0;
2976         }
2977
2978         return -1;
2979 }
2980
2981 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2982                                        struct snd_ctl_elem_value *ucontrol)
2983 {
2984         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2985         int val, change = 0;
2986
2987         if (!snd_hdspm_use_is_exclusive(hdspm))
2988                 return -EBUSY;
2989
2990         val = ucontrol->value.enumerated.item[0];
2991
2992         if (val < 0)
2993                 val = 0;
2994         else if (val >= hdspm->texts_autosync_items)
2995                 val = hdspm->texts_autosync_items-1;
2996
2997         spin_lock_irq(&hdspm->lock);
2998         if (val != hdspm_pref_sync_ref(hdspm))
2999                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
3000
3001         spin_unlock_irq(&hdspm->lock);
3002         return change;
3003 }
3004
3005
3006 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
3007 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3008         .name = xname, \
3009         .index = xindex, \
3010         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
3011         .info = snd_hdspm_info_autosync_ref, \
3012         .get = snd_hdspm_get_autosync_ref, \
3013 }
3014
3015 static int hdspm_autosync_ref(struct hdspm *hdspm)
3016 {
3017         /* This looks at the autosync selected sync reference */
3018         if (AES32 == hdspm->io_type) {
3019
3020                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
3021                 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
3022                 if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) &&
3023                                 (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) {
3024                         return syncref;
3025                 }
3026                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
3027
3028         } else if (MADI == hdspm->io_type) {
3029
3030                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3031                 switch (status2 & HDSPM_SelSyncRefMask) {
3032                 case HDSPM_SelSyncRef_WORD:
3033                         return HDSPM_AUTOSYNC_FROM_WORD;
3034                 case HDSPM_SelSyncRef_MADI:
3035                         return HDSPM_AUTOSYNC_FROM_MADI;
3036                 case HDSPM_SelSyncRef_TCO:
3037                         return HDSPM_AUTOSYNC_FROM_TCO;
3038                 case HDSPM_SelSyncRef_SyncIn:
3039                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
3040                 case HDSPM_SelSyncRef_NVALID:
3041                         return HDSPM_AUTOSYNC_FROM_NONE;
3042                 default:
3043                         return HDSPM_AUTOSYNC_FROM_NONE;
3044                 }
3045
3046         }
3047         return 0;
3048 }
3049
3050
3051 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
3052                                        struct snd_ctl_elem_info *uinfo)
3053 {
3054         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3055
3056         if (AES32 == hdspm->io_type) {
3057                 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3",
3058                         "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
3059
3060                 ENUMERATED_CTL_INFO(uinfo, texts);
3061         } else if (MADI == hdspm->io_type) {
3062                 static const char *const texts[] = {"Word Clock", "MADI", "TCO",
3063                         "Sync In", "None" };
3064
3065                 ENUMERATED_CTL_INFO(uinfo, texts);
3066         }
3067         return 0;
3068 }
3069
3070 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
3071                                       struct snd_ctl_elem_value *ucontrol)
3072 {
3073         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3074
3075         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3076         return 0;
3077 }
3078
3079
3080
3081 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
3082 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3083         .name = xname, \
3084         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3085                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3086         .info = snd_hdspm_info_tco_video_input_format, \
3087         .get = snd_hdspm_get_tco_video_input_format, \
3088 }
3089
3090 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
3091                                        struct snd_ctl_elem_info *uinfo)
3092 {
3093         static const char *const texts[] = {"No video", "NTSC", "PAL"};
3094         ENUMERATED_CTL_INFO(uinfo, texts);
3095         return 0;
3096 }
3097
3098 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
3099                                       struct snd_ctl_elem_value *ucontrol)
3100 {
3101         u32 status;
3102         int ret = 0;
3103
3104         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3105         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3106         switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3107                         HDSPM_TCO1_Video_Input_Format_PAL)) {
3108         case HDSPM_TCO1_Video_Input_Format_NTSC:
3109                 /* ntsc */
3110                 ret = 1;
3111                 break;
3112         case HDSPM_TCO1_Video_Input_Format_PAL:
3113                 /* pal */
3114                 ret = 2;
3115                 break;
3116         default:
3117                 /* no video */
3118                 ret = 0;
3119                 break;
3120         }
3121         ucontrol->value.enumerated.item[0] = ret;
3122         return 0;
3123 }
3124
3125
3126
3127 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3128 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3129         .name = xname, \
3130         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3131                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3132         .info = snd_hdspm_info_tco_ltc_frames, \
3133         .get = snd_hdspm_get_tco_ltc_frames, \
3134 }
3135
3136 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3137                                        struct snd_ctl_elem_info *uinfo)
3138 {
3139         static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3140                                 "30 fps"};
3141         ENUMERATED_CTL_INFO(uinfo, texts);
3142         return 0;
3143 }
3144
3145 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3146 {
3147         u32 status;
3148         int ret = 0;
3149
3150         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3151         if (status & HDSPM_TCO1_LTC_Input_valid) {
3152                 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3153                                         HDSPM_TCO1_LTC_Format_MSB)) {
3154                 case 0:
3155                         /* 24 fps */
3156                         ret = fps_24;
3157                         break;
3158                 case HDSPM_TCO1_LTC_Format_LSB:
3159                         /* 25 fps */
3160                         ret = fps_25;
3161                         break;
3162                 case HDSPM_TCO1_LTC_Format_MSB:
3163                         /* 29.97 fps */
3164                         ret = fps_2997;
3165                         break;
3166                 default:
3167                         /* 30 fps */
3168                         ret = fps_30;
3169                         break;
3170                 }
3171         }
3172
3173         return ret;
3174 }
3175
3176 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3177                                       struct snd_ctl_elem_value *ucontrol)
3178 {
3179         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3180
3181         ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3182         return 0;
3183 }
3184
3185 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3186 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3187         .name = xname, \
3188         .private_value = xindex, \
3189         .info = snd_hdspm_info_toggle_setting, \
3190         .get = snd_hdspm_get_toggle_setting, \
3191         .put = snd_hdspm_put_toggle_setting \
3192 }
3193
3194 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3195 {
3196         u32 reg;
3197
3198         if (hdspm_is_raydat_or_aio(hdspm))
3199                 reg = hdspm->settings_register;
3200         else
3201                 reg = hdspm->control_register;
3202
3203         return (reg & regmask) ? 1 : 0;
3204 }
3205
3206 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3207 {
3208         u32 *reg;
3209         u32 target_reg;
3210
3211         if (hdspm_is_raydat_or_aio(hdspm)) {
3212                 reg = &(hdspm->settings_register);
3213                 target_reg = HDSPM_WR_SETTINGS;
3214         } else {
3215                 reg = &(hdspm->control_register);
3216                 target_reg = HDSPM_controlRegister;
3217         }
3218
3219         if (out)
3220                 *reg |= regmask;
3221         else
3222                 *reg &= ~regmask;
3223
3224         hdspm_write(hdspm, target_reg, *reg);
3225
3226         return 0;
3227 }
3228
3229 #define snd_hdspm_info_toggle_setting           snd_ctl_boolean_mono_info
3230
3231 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3232                                struct snd_ctl_elem_value *ucontrol)
3233 {
3234         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3235         u32 regmask = kcontrol->private_value;
3236
3237         spin_lock_irq(&hdspm->lock);
3238         ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3239         spin_unlock_irq(&hdspm->lock);
3240         return 0;
3241 }
3242
3243 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3244                                struct snd_ctl_elem_value *ucontrol)
3245 {
3246         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3247         u32 regmask = kcontrol->private_value;
3248         int change;
3249         unsigned int val;
3250
3251         if (!snd_hdspm_use_is_exclusive(hdspm))
3252                 return -EBUSY;
3253         val = ucontrol->value.integer.value[0] & 1;
3254         spin_lock_irq(&hdspm->lock);
3255         change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3256         hdspm_set_toggle_setting(hdspm, regmask, val);
3257         spin_unlock_irq(&hdspm->lock);
3258         return change;
3259 }
3260
3261 #define HDSPM_INPUT_SELECT(xname, xindex) \
3262 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3263         .name = xname, \
3264         .index = xindex, \
3265         .info = snd_hdspm_info_input_select, \
3266         .get = snd_hdspm_get_input_select, \
3267         .put = snd_hdspm_put_input_select \
3268 }
3269
3270 static int hdspm_input_select(struct hdspm * hdspm)
3271 {
3272         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3273 }
3274
3275 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3276 {
3277         if (out)
3278                 hdspm->control_register |= HDSPM_InputSelect0;
3279         else
3280                 hdspm->control_register &= ~HDSPM_InputSelect0;
3281         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3282
3283         return 0;
3284 }
3285
3286 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3287                                        struct snd_ctl_elem_info *uinfo)
3288 {
3289         static const char *const texts[] = { "optical", "coaxial" };
3290         ENUMERATED_CTL_INFO(uinfo, texts);
3291         return 0;
3292 }
3293
3294 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3295                                       struct snd_ctl_elem_value *ucontrol)
3296 {
3297         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3298
3299         spin_lock_irq(&hdspm->lock);
3300         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3301         spin_unlock_irq(&hdspm->lock);
3302         return 0;
3303 }
3304
3305 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3306                                       struct snd_ctl_elem_value *ucontrol)
3307 {
3308         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3309         int change;
3310         unsigned int val;
3311
3312         if (!snd_hdspm_use_is_exclusive(hdspm))
3313                 return -EBUSY;
3314         val = ucontrol->value.integer.value[0] & 1;
3315         spin_lock_irq(&hdspm->lock);
3316         change = (int) val != hdspm_input_select(hdspm);
3317         hdspm_set_input_select(hdspm, val);
3318         spin_unlock_irq(&hdspm->lock);
3319         return change;
3320 }
3321
3322
3323 #define HDSPM_DS_WIRE(xname, xindex) \
3324 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3325         .name = xname, \
3326         .index = xindex, \
3327         .info = snd_hdspm_info_ds_wire, \
3328         .get = snd_hdspm_get_ds_wire, \
3329         .put = snd_hdspm_put_ds_wire \
3330 }
3331
3332 static int hdspm_ds_wire(struct hdspm * hdspm)
3333 {
3334         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3335 }
3336
3337 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3338 {
3339         if (ds)
3340                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3341         else
3342                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3343         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3344
3345         return 0;
3346 }
3347
3348 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3349                                   struct snd_ctl_elem_info *uinfo)
3350 {
3351         static const char *const texts[] = { "Single", "Double" };
3352         ENUMERATED_CTL_INFO(uinfo, texts);
3353         return 0;
3354 }
3355
3356 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3357                                  struct snd_ctl_elem_value *ucontrol)
3358 {
3359         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3360
3361         spin_lock_irq(&hdspm->lock);
3362         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3363         spin_unlock_irq(&hdspm->lock);
3364         return 0;
3365 }
3366
3367 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3368                                  struct snd_ctl_elem_value *ucontrol)
3369 {
3370         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3371         int change;
3372         unsigned int val;
3373
3374         if (!snd_hdspm_use_is_exclusive(hdspm))
3375                 return -EBUSY;
3376         val = ucontrol->value.integer.value[0] & 1;
3377         spin_lock_irq(&hdspm->lock);
3378         change = (int) val != hdspm_ds_wire(hdspm);
3379         hdspm_set_ds_wire(hdspm, val);
3380         spin_unlock_irq(&hdspm->lock);
3381         return change;
3382 }
3383
3384
3385 #define HDSPM_QS_WIRE(xname, xindex) \
3386 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3387         .name = xname, \
3388         .index = xindex, \
3389         .info = snd_hdspm_info_qs_wire, \
3390         .get = snd_hdspm_get_qs_wire, \
3391         .put = snd_hdspm_put_qs_wire \
3392 }
3393
3394 static int hdspm_qs_wire(struct hdspm * hdspm)
3395 {
3396         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3397                 return 1;
3398         if (hdspm->control_register & HDSPM_QS_QuadWire)
3399                 return 2;
3400         return 0;
3401 }
3402
3403 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3404 {
3405         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3406         switch (mode) {
3407         case 0:
3408                 break;
3409         case 1:
3410                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3411                 break;
3412         case 2:
3413                 hdspm->control_register |= HDSPM_QS_QuadWire;
3414                 break;
3415         }
3416         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3417
3418         return 0;
3419 }
3420
3421 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3422                                        struct snd_ctl_elem_info *uinfo)
3423 {
3424         static const char *const texts[] = { "Single", "Double", "Quad" };
3425         ENUMERATED_CTL_INFO(uinfo, texts);
3426         return 0;
3427 }
3428
3429 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3430                                       struct snd_ctl_elem_value *ucontrol)
3431 {
3432         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3433
3434         spin_lock_irq(&hdspm->lock);
3435         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3436         spin_unlock_irq(&hdspm->lock);
3437         return 0;
3438 }
3439
3440 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3441                                       struct snd_ctl_elem_value *ucontrol)
3442 {
3443         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3444         int change;
3445         int val;
3446
3447         if (!snd_hdspm_use_is_exclusive(hdspm))
3448                 return -EBUSY;
3449         val = ucontrol->value.integer.value[0];
3450         if (val < 0)
3451                 val = 0;
3452         if (val > 2)
3453                 val = 2;
3454         spin_lock_irq(&hdspm->lock);
3455         change = val != hdspm_qs_wire(hdspm);
3456         hdspm_set_qs_wire(hdspm, val);
3457         spin_unlock_irq(&hdspm->lock);
3458         return change;
3459 }
3460
3461 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3462 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3463         .name = xname, \
3464         .private_value = xindex, \
3465         .info = snd_hdspm_info_tristate, \
3466         .get = snd_hdspm_get_tristate, \
3467         .put = snd_hdspm_put_tristate \
3468 }
3469
3470 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3471 {
3472         u32 reg = hdspm->settings_register & (regmask * 3);
3473         return reg / regmask;
3474 }
3475
3476 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3477 {
3478         hdspm->settings_register &= ~(regmask * 3);
3479         hdspm->settings_register |= (regmask * mode);
3480         hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3481
3482         return 0;
3483 }
3484
3485 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3486                                        struct snd_ctl_elem_info *uinfo)
3487 {
3488         u32 regmask = kcontrol->private_value;
3489
3490         static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3491         static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3492
3493         switch (regmask) {
3494         case HDSPM_c0_Input0:
3495                 ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3496                 break;
3497         default:
3498                 ENUMERATED_CTL_INFO(uinfo, texts_levels);
3499                 break;
3500         }
3501         return 0;
3502 }
3503
3504 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3505                                       struct snd_ctl_elem_value *ucontrol)
3506 {
3507         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3508         u32 regmask = kcontrol->private_value;
3509
3510         spin_lock_irq(&hdspm->lock);
3511         ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3512         spin_unlock_irq(&hdspm->lock);
3513         return 0;
3514 }
3515
3516 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3517                                       struct snd_ctl_elem_value *ucontrol)
3518 {
3519         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3520         u32 regmask = kcontrol->private_value;
3521         int change;
3522         int val;
3523
3524         if (!snd_hdspm_use_is_exclusive(hdspm))
3525                 return -EBUSY;
3526         val = ucontrol->value.integer.value[0];
3527         if (val < 0)
3528                 val = 0;
3529         if (val > 2)
3530                 val = 2;
3531
3532         spin_lock_irq(&hdspm->lock);
3533         change = val != hdspm_tristate(hdspm, regmask);
3534         hdspm_set_tristate(hdspm, val, regmask);
3535         spin_unlock_irq(&hdspm->lock);
3536         return change;
3537 }
3538
3539 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3540 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3541         .name = xname, \
3542         .index = xindex, \
3543         .info = snd_hdspm_info_madi_speedmode, \
3544         .get = snd_hdspm_get_madi_speedmode, \
3545         .put = snd_hdspm_put_madi_speedmode \
3546 }
3547
3548 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3549 {
3550         if (hdspm->control_register & HDSPM_QuadSpeed)
3551                 return 2;
3552         if (hdspm->control_register & HDSPM_DoubleSpeed)
3553                 return 1;
3554         return 0;
3555 }
3556
3557 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3558 {
3559         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3560         switch (mode) {
3561         case 0:
3562                 break;
3563         case 1:
3564                 hdspm->control_register |= HDSPM_DoubleSpeed;
3565                 break;
3566         case 2:
3567                 hdspm->control_register |= HDSPM_QuadSpeed;
3568                 break;
3569         }
3570         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3571
3572         return 0;
3573 }
3574
3575 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3576                                        struct snd_ctl_elem_info *uinfo)
3577 {
3578         static const char *const texts[] = { "Single", "Double", "Quad" };
3579         ENUMERATED_CTL_INFO(uinfo, texts);
3580         return 0;
3581 }
3582
3583 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3584                                       struct snd_ctl_elem_value *ucontrol)
3585 {
3586         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3587
3588         spin_lock_irq(&hdspm->lock);
3589         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3590         spin_unlock_irq(&hdspm->lock);
3591         return 0;
3592 }
3593
3594 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3595                                       struct snd_ctl_elem_value *ucontrol)
3596 {
3597         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3598         int change;
3599         int val;
3600
3601         if (!snd_hdspm_use_is_exclusive(hdspm))
3602                 return -EBUSY;
3603         val = ucontrol->value.integer.value[0];
3604         if (val < 0)
3605                 val = 0;
3606         if (val > 2)
3607                 val = 2;
3608         spin_lock_irq(&hdspm->lock);
3609         change = val != hdspm_madi_speedmode(hdspm);
3610         hdspm_set_madi_speedmode(hdspm, val);
3611         spin_unlock_irq(&hdspm->lock);
3612         return change;
3613 }
3614
3615 #define HDSPM_MIXER(xname, xindex) \
3616 {       .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3617         .name = xname, \
3618         .index = xindex, \
3619         .device = 0, \
3620         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3621                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3622         .info = snd_hdspm_info_mixer, \
3623         .get = snd_hdspm_get_mixer, \
3624         .put = snd_hdspm_put_mixer \
3625 }
3626
3627 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3628                                 struct snd_ctl_elem_info *uinfo)
3629 {
3630         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3631         uinfo->count = 3;
3632         uinfo->value.integer.min = 0;
3633         uinfo->value.integer.max = 65535;
3634         uinfo->value.integer.step = 1;
3635         return 0;
3636 }
3637
3638 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3639                                struct snd_ctl_elem_value *ucontrol)
3640 {
3641         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3642         int source;
3643         int destination;
3644
3645         source = ucontrol->value.integer.value[0];
3646         if (source < 0)
3647                 source = 0;
3648         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3649                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3650
3651         destination = ucontrol->value.integer.value[1];
3652         if (destination < 0)
3653                 destination = 0;
3654         else if (destination >= HDSPM_MAX_CHANNELS)
3655                 destination = HDSPM_MAX_CHANNELS - 1;
3656
3657         spin_lock_irq(&hdspm->lock);
3658         if (source >= HDSPM_MAX_CHANNELS)
3659                 ucontrol->value.integer.value[2] =
3660                     hdspm_read_pb_gain(hdspm, destination,
3661                                        source - HDSPM_MAX_CHANNELS);
3662         else
3663                 ucontrol->value.integer.value[2] =
3664                     hdspm_read_in_gain(hdspm, destination, source);
3665
3666         spin_unlock_irq(&hdspm->lock);
3667
3668         return 0;
3669 }
3670
3671 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3672                                struct snd_ctl_elem_value *ucontrol)
3673 {
3674         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3675         int change;
3676         int source;
3677         int destination;
3678         int gain;
3679
3680         if (!snd_hdspm_use_is_exclusive(hdspm))
3681                 return -EBUSY;
3682
3683         source = ucontrol->value.integer.value[0];
3684         destination = ucontrol->value.integer.value[1];
3685
3686         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3687                 return -1;
3688         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3689                 return -1;
3690
3691         gain = ucontrol->value.integer.value[2];
3692
3693         spin_lock_irq(&hdspm->lock);
3694
3695         if (source >= HDSPM_MAX_CHANNELS)
3696                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3697                                                     source -
3698                                                     HDSPM_MAX_CHANNELS);
3699         else
3700                 change = gain != hdspm_read_in_gain(hdspm, destination,
3701                                                     source);
3702
3703         if (change) {
3704                 if (source >= HDSPM_MAX_CHANNELS)
3705                         hdspm_write_pb_gain(hdspm, destination,
3706                                             source - HDSPM_MAX_CHANNELS,
3707                                             gain);
3708                 else
3709                         hdspm_write_in_gain(hdspm, destination, source,
3710                                             gain);
3711         }
3712         spin_unlock_irq(&hdspm->lock);
3713
3714         return change;
3715 }
3716
3717 /* The simple mixer control(s) provide gain control for the
3718    basic 1:1 mappings of playback streams to output
3719    streams.
3720 */
3721
3722 #define HDSPM_PLAYBACK_MIXER \
3723 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3724         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3725                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3726         .info = snd_hdspm_info_playback_mixer, \
3727         .get = snd_hdspm_get_playback_mixer, \
3728         .put = snd_hdspm_put_playback_mixer \
3729 }
3730
3731 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3732                                          struct snd_ctl_elem_info *uinfo)
3733 {
3734         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3735         uinfo->count = 1;
3736         uinfo->value.integer.min = 0;
3737         uinfo->value.integer.max = 64;
3738         uinfo->value.integer.step = 1;
3739         return 0;
3740 }
3741
3742 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3743                                         struct snd_ctl_elem_value *ucontrol)
3744 {
3745         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3746         int channel;
3747
3748         channel = ucontrol->id.index - 1;
3749
3750         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3751                 return -EINVAL;
3752
3753         spin_lock_irq(&hdspm->lock);
3754         ucontrol->value.integer.value[0] =
3755           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3756         spin_unlock_irq(&hdspm->lock);
3757
3758         return 0;
3759 }
3760
3761 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3762                                         struct snd_ctl_elem_value *ucontrol)
3763 {
3764         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3765         int change;
3766         int channel;
3767         int gain;
3768
3769         if (!snd_hdspm_use_is_exclusive(hdspm))
3770                 return -EBUSY;
3771
3772         channel = ucontrol->id.index - 1;
3773
3774         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3775                 return -EINVAL;
3776
3777         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3778
3779         spin_lock_irq(&hdspm->lock);
3780         change =
3781             gain != hdspm_read_pb_gain(hdspm, channel,
3782                                        channel);
3783         if (change)
3784                 hdspm_write_pb_gain(hdspm, channel, channel,
3785                                     gain);
3786         spin_unlock_irq(&hdspm->lock);
3787         return change;
3788 }
3789
3790 #define HDSPM_SYNC_CHECK(xname, xindex) \
3791 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3792         .name = xname, \
3793         .private_value = xindex, \
3794         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3795         .info = snd_hdspm_info_sync_check, \
3796         .get = snd_hdspm_get_sync_check \
3797 }
3798
3799 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3800 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3801         .name = xname, \
3802         .private_value = xindex, \
3803         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3804         .info = snd_hdspm_tco_info_lock_check, \
3805         .get = snd_hdspm_get_sync_check \
3806 }
3807
3808
3809
3810 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3811                                      struct snd_ctl_elem_info *uinfo)
3812 {
3813         static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3814         ENUMERATED_CTL_INFO(uinfo, texts);
3815         return 0;
3816 }
3817
3818 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3819                                      struct snd_ctl_elem_info *uinfo)
3820 {
3821         static const char *const texts[] = { "No Lock", "Lock" };
3822         ENUMERATED_CTL_INFO(uinfo, texts);
3823         return 0;
3824 }
3825
3826 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3827 {
3828         int status, status2;
3829
3830         switch (hdspm->io_type) {
3831         case AES32:
3832                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3833                 if (status & HDSPM_AES32_wcLock) {
3834                         if (status & HDSPM_AES32_wcSync)
3835                                 return 2;
3836                         else
3837                                 return 1;
3838                 }
3839                 return 0;
3840                 break;
3841
3842         case MADI:
3843                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3844                 if (status2 & HDSPM_wcLock) {
3845                         if (status2 & HDSPM_wcSync)
3846                                 return 2;
3847                         else
3848                                 return 1;
3849                 }
3850                 return 0;
3851                 break;
3852
3853         case RayDAT:
3854         case AIO:
3855                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3856
3857                 if (status & 0x2000000)
3858                         return 2;
3859                 else if (status & 0x1000000)
3860                         return 1;
3861                 return 0;
3862
3863                 break;
3864
3865         case MADIface:
3866                 break;
3867         }
3868
3869
3870         return 3;
3871 }
3872
3873
3874 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3875 {
3876         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3877         if (status & HDSPM_madiLock) {
3878                 if (status & HDSPM_madiSync)
3879                         return 2;
3880                 else
3881                         return 1;
3882         }
3883         return 0;
3884 }
3885
3886
3887 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3888 {
3889         int status, lock, sync;
3890
3891         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3892
3893         lock = (status & (0x1<<idx)) ? 1 : 0;
3894         sync = (status & (0x100<<idx)) ? 1 : 0;
3895
3896         if (lock && sync)
3897                 return 2;
3898         else if (lock)
3899                 return 1;
3900         return 0;
3901 }
3902
3903
3904 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3905 {
3906         int status, lock = 0, sync = 0;
3907
3908         switch (hdspm->io_type) {
3909         case RayDAT:
3910         case AIO:
3911                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3912                 lock = (status & 0x400) ? 1 : 0;
3913                 sync = (status & 0x800) ? 1 : 0;
3914                 break;
3915
3916         case MADI:
3917                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3918                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3919                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3920                 break;
3921
3922         case AES32:
3923                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3924                 lock = (status & 0x100000) ? 1 : 0;
3925                 sync = (status & 0x200000) ? 1 : 0;
3926                 break;
3927
3928         case MADIface:
3929                 break;
3930         }
3931
3932         if (lock && sync)
3933                 return 2;
3934         else if (lock)
3935                 return 1;
3936
3937         return 0;
3938 }
3939
3940 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3941 {
3942         int status2, lock, sync;
3943         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3944
3945         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3946         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3947
3948         if (sync)
3949                 return 2;
3950         else if (lock)
3951                 return 1;
3952         return 0;
3953 }
3954
3955 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3956 {
3957         u32 status;
3958         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3959
3960         return (status & mask) ? 1 : 0;
3961 }
3962
3963
3964 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3965 {
3966         int status;
3967
3968         if (hdspm->tco) {
3969                 switch (hdspm->io_type) {
3970                 case MADI:
3971                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3972                         if (status & HDSPM_tcoLockMadi) {
3973                                 if (status & HDSPM_tcoSync)
3974                                         return 2;
3975                                 else
3976                                         return 1;
3977                         }
3978                         return 0;
3979                 case AES32:
3980                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3981                         if (status & HDSPM_tcoLockAes) {
3982                                 if (status & HDSPM_tcoSync)
3983                                         return 2;
3984                                 else
3985                                         return 1;
3986                         }
3987                         return 0;
3988                 case RayDAT:
3989                 case AIO:
3990                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3991
3992                         if (status & 0x8000000)
3993                                 return 2; /* Sync */
3994                         if (status & 0x4000000)
3995                                 return 1; /* Lock */
3996                         return 0; /* No signal */
3997
3998                 default:
3999                         break;
4000                 }
4001         }
4002
4003         return 3; /* N/A */
4004 }
4005
4006
4007 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
4008                                     struct snd_ctl_elem_value *ucontrol)
4009 {
4010         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4011         int val = -1;
4012
4013         switch (hdspm->io_type) {
4014         case RayDAT:
4015                 switch (kcontrol->private_value) {
4016                 case 0: /* WC */
4017                         val = hdspm_wc_sync_check(hdspm); break;
4018                 case 7: /* TCO */
4019                         val = hdspm_tco_sync_check(hdspm); break;
4020                 case 8: /* SYNC IN */
4021                         val = hdspm_sync_in_sync_check(hdspm); break;
4022                 default:
4023                         val = hdspm_s1_sync_check(hdspm,
4024                                         kcontrol->private_value-1);
4025                 }
4026                 break;
4027
4028         case AIO:
4029                 switch (kcontrol->private_value) {
4030                 case 0: /* WC */
4031                         val = hdspm_wc_sync_check(hdspm); break;
4032                 case 4: /* TCO */
4033                         val = hdspm_tco_sync_check(hdspm); break;
4034                 case 5: /* SYNC IN */
4035                         val = hdspm_sync_in_sync_check(hdspm); break;
4036                 default:
4037                         val = hdspm_s1_sync_check(hdspm,
4038                                         kcontrol->private_value-1);
4039                 }
4040                 break;
4041
4042         case MADI:
4043                 switch (kcontrol->private_value) {
4044                 case 0: /* WC */
4045                         val = hdspm_wc_sync_check(hdspm); break;
4046                 case 1: /* MADI */
4047                         val = hdspm_madi_sync_check(hdspm); break;
4048                 case 2: /* TCO */
4049                         val = hdspm_tco_sync_check(hdspm); break;
4050                 case 3: /* SYNC_IN */
4051                         val = hdspm_sync_in_sync_check(hdspm); break;
4052                 }
4053                 break;
4054
4055         case MADIface:
4056                 val = hdspm_madi_sync_check(hdspm); /* MADI */
4057                 break;
4058
4059         case AES32:
4060                 switch (kcontrol->private_value) {
4061                 case 0: /* WC */
4062                         val = hdspm_wc_sync_check(hdspm); break;
4063                 case 9: /* TCO */
4064                         val = hdspm_tco_sync_check(hdspm); break;
4065                 case 10 /* SYNC IN */:
4066                         val = hdspm_sync_in_sync_check(hdspm); break;
4067                 default: /* AES1 to AES8 */
4068                          val = hdspm_aes_sync_check(hdspm,
4069                                          kcontrol->private_value-1);
4070                 }
4071                 break;
4072
4073         }
4074
4075         if (hdspm->tco) {
4076                 switch (kcontrol->private_value) {
4077                 case 11:
4078                         /* Check TCO for lock state of its current input */
4079                         val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4080                         break;
4081                 case 12:
4082                         /* Check TCO for valid time code on LTC input. */
4083                         val = hdspm_tco_input_check(hdspm,
4084                                 HDSPM_TCO1_LTC_Input_valid);
4085                         break;
4086                 default:
4087                         break;
4088                 }
4089         }
4090
4091         if (-1 == val)
4092                 val = 3;
4093
4094         ucontrol->value.enumerated.item[0] = val;
4095         return 0;
4096 }
4097
4098
4099
4100 /*
4101  * TCO controls
4102  */
4103 static void hdspm_tco_write(struct hdspm *hdspm)
4104 {
4105         unsigned int tc[4] = { 0, 0, 0, 0};
4106
4107         switch (hdspm->tco->input) {
4108         case 0:
4109                 tc[2] |= HDSPM_TCO2_set_input_MSB;
4110                 break;
4111         case 1:
4112                 tc[2] |= HDSPM_TCO2_set_input_LSB;
4113                 break;
4114         default:
4115                 break;
4116         }
4117
4118         switch (hdspm->tco->framerate) {
4119         case 1:
4120                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4121                 break;
4122         case 2:
4123                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4124                 break;
4125         case 3:
4126                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4127                         HDSPM_TCO1_set_drop_frame_flag;
4128                 break;
4129         case 4:
4130                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4131                         HDSPM_TCO1_LTC_Format_MSB;
4132                 break;
4133         case 5:
4134                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4135                         HDSPM_TCO1_LTC_Format_MSB +
4136                         HDSPM_TCO1_set_drop_frame_flag;
4137                 break;
4138         default:
4139                 break;
4140         }
4141
4142         switch (hdspm->tco->wordclock) {
4143         case 1:
4144                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4145                 break;
4146         case 2:
4147                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4148                 break;
4149         default:
4150                 break;
4151         }
4152
4153         switch (hdspm->tco->samplerate) {
4154         case 1:
4155                 tc[2] |= HDSPM_TCO2_set_freq;
4156                 break;
4157         case 2:
4158                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4159                 break;
4160         default:
4161                 break;
4162         }
4163
4164         switch (hdspm->tco->pull) {
4165         case 1:
4166                 tc[2] |= HDSPM_TCO2_set_pull_up;
4167                 break;
4168         case 2:
4169                 tc[2] |= HDSPM_TCO2_set_pull_down;
4170                 break;
4171         case 3:
4172                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4173                 break;
4174         case 4:
4175                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4176                 break;
4177         default:
4178                 break;
4179         }
4180
4181         if (1 == hdspm->tco->term) {
4182                 tc[2] |= HDSPM_TCO2_set_term_75R;
4183         }
4184
4185         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4186         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4187         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4188         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4189 }
4190
4191
4192 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4193 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4194         .name = xname, \
4195         .index = xindex, \
4196         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4197                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4198         .info = snd_hdspm_info_tco_sample_rate, \
4199         .get = snd_hdspm_get_tco_sample_rate, \
4200         .put = snd_hdspm_put_tco_sample_rate \
4201 }
4202
4203 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4204                                           struct snd_ctl_elem_info *uinfo)
4205 {
4206         /* TODO freq from app could be supported here, see tco->samplerate */
4207         static const char *const texts[] = { "44.1 kHz", "48 kHz" };
4208         ENUMERATED_CTL_INFO(uinfo, texts);
4209         return 0;
4210 }
4211
4212 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4213                                       struct snd_ctl_elem_value *ucontrol)
4214 {
4215         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4216
4217         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4218
4219         return 0;
4220 }
4221
4222 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4223                                          struct snd_ctl_elem_value *ucontrol)
4224 {
4225         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4226
4227         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4228                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4229
4230                 hdspm_tco_write(hdspm);
4231
4232                 return 1;
4233         }
4234
4235         return 0;
4236 }
4237
4238
4239 #define HDSPM_TCO_PULL(xname, xindex) \
4240 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4241         .name = xname, \
4242         .index = xindex, \
4243         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4244                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4245         .info = snd_hdspm_info_tco_pull, \
4246         .get = snd_hdspm_get_tco_pull, \
4247         .put = snd_hdspm_put_tco_pull \
4248 }
4249
4250 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4251                                    struct snd_ctl_elem_info *uinfo)
4252 {
4253         static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %",
4254                 "+ 4 %", "- 4 %" };
4255         ENUMERATED_CTL_INFO(uinfo, texts);
4256         return 0;
4257 }
4258
4259 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4260                                   struct snd_ctl_elem_value *ucontrol)
4261 {
4262         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4263
4264         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4265
4266         return 0;
4267 }
4268
4269 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4270                                   struct snd_ctl_elem_value *ucontrol)
4271 {
4272         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4273
4274         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4275                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4276
4277                 hdspm_tco_write(hdspm);
4278
4279                 return 1;
4280         }
4281
4282         return 0;
4283 }
4284
4285 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4286 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4287         .name = xname, \
4288         .index = xindex, \
4289         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4290                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4291         .info = snd_hdspm_info_tco_wck_conversion, \
4292         .get = snd_hdspm_get_tco_wck_conversion, \
4293         .put = snd_hdspm_put_tco_wck_conversion \
4294 }
4295
4296 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4297                                              struct snd_ctl_elem_info *uinfo)
4298 {
4299         static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4300         ENUMERATED_CTL_INFO(uinfo, texts);
4301         return 0;
4302 }
4303
4304 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4305                                             struct snd_ctl_elem_value *ucontrol)
4306 {
4307         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4308
4309         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4310
4311         return 0;
4312 }
4313
4314 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4315                                             struct snd_ctl_elem_value *ucontrol)
4316 {
4317         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4318
4319         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4320                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4321
4322                 hdspm_tco_write(hdspm);
4323
4324                 return 1;
4325         }
4326
4327         return 0;
4328 }
4329
4330
4331 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4332 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4333         .name = xname, \
4334         .index = xindex, \
4335         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4336                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4337         .info = snd_hdspm_info_tco_frame_rate, \
4338         .get = snd_hdspm_get_tco_frame_rate, \
4339         .put = snd_hdspm_put_tco_frame_rate \
4340 }
4341
4342 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4343                                           struct snd_ctl_elem_info *uinfo)
4344 {
4345         static const char *const texts[] = { "24 fps", "25 fps", "29.97fps",
4346                 "29.97 dfps", "30 fps", "30 dfps" };
4347         ENUMERATED_CTL_INFO(uinfo, texts);
4348         return 0;
4349 }
4350
4351 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4352                                         struct snd_ctl_elem_value *ucontrol)
4353 {
4354         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4355
4356         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4357
4358         return 0;
4359 }
4360
4361 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4362                                         struct snd_ctl_elem_value *ucontrol)
4363 {
4364         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4365
4366         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4367                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4368
4369                 hdspm_tco_write(hdspm);
4370
4371                 return 1;
4372         }
4373
4374         return 0;
4375 }
4376
4377
4378 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4379 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4380         .name = xname, \
4381         .index = xindex, \
4382         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4383                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4384         .info = snd_hdspm_info_tco_sync_source, \
4385         .get = snd_hdspm_get_tco_sync_source, \
4386         .put = snd_hdspm_put_tco_sync_source \
4387 }
4388
4389 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4390                                           struct snd_ctl_elem_info *uinfo)
4391 {
4392         static const char *const texts[] = { "LTC", "Video", "WCK" };
4393         ENUMERATED_CTL_INFO(uinfo, texts);
4394         return 0;
4395 }
4396
4397 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4398                                          struct snd_ctl_elem_value *ucontrol)
4399 {
4400         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4401
4402         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4403
4404         return 0;
4405 }
4406
4407 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4408                                          struct snd_ctl_elem_value *ucontrol)
4409 {
4410         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4411
4412         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4413                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4414
4415                 hdspm_tco_write(hdspm);
4416
4417                 return 1;
4418         }
4419
4420         return 0;
4421 }
4422
4423
4424 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4425 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4426         .name = xname, \
4427         .index = xindex, \
4428         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4429                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4430         .info = snd_hdspm_info_tco_word_term, \
4431         .get = snd_hdspm_get_tco_word_term, \
4432         .put = snd_hdspm_put_tco_word_term \
4433 }
4434
4435 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4436                                         struct snd_ctl_elem_info *uinfo)
4437 {
4438         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4439         uinfo->count = 1;
4440         uinfo->value.integer.min = 0;
4441         uinfo->value.integer.max = 1;
4442
4443         return 0;
4444 }
4445
4446
4447 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4448                                        struct snd_ctl_elem_value *ucontrol)
4449 {
4450         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4451
4452         ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4453
4454         return 0;
4455 }
4456
4457
4458 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4459                                        struct snd_ctl_elem_value *ucontrol)
4460 {
4461         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4462
4463         if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4464                 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4465
4466                 hdspm_tco_write(hdspm);
4467
4468                 return 1;
4469         }
4470
4471         return 0;
4472 }
4473
4474
4475
4476
4477 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4478         HDSPM_MIXER("Mixer", 0),
4479         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4480         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4481         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4482         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4483         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4484         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4485         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4486         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4487         HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4488         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4489         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4490         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4491         HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4492         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4493         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4494         HDSPM_INPUT_SELECT("Input Select", 0),
4495         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4496 };
4497
4498
4499 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4500         HDSPM_MIXER("Mixer", 0),
4501         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4502         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4503         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4504         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4505         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4506         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4507         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4508         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4509         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4510 };
4511
4512 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4513         HDSPM_MIXER("Mixer", 0),
4514         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4515         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4516         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4517         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4518         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4519         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4520         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4521         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4522         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4523         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4524         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4525         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4526         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4527         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4528         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4529         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4530         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4531         HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
4532         HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4533         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4534         HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4535         HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4536         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4537         HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4538         HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4539         HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
4540
4541                 /*
4542                    HDSPM_INPUT_SELECT("Input Select", 0),
4543                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4544                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4545                    HDSPM_SPDIF_IN("SPDIF In", 0);
4546                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4547                    HDSPM_INPUT_LEVEL("Input Level", 0);
4548                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4549                    HDSPM_PHONES("Phones", 0);
4550                    */
4551 };
4552
4553 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4554         HDSPM_MIXER("Mixer", 0),
4555         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4556         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4557         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4558         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4559         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4560         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4561         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4562         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4563         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4564         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4565         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4566         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4567         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4568         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4569         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4570         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4571         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4572         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4573         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4574         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4575         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4576         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4577         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4578         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4579 };
4580
4581 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4582         HDSPM_MIXER("Mixer", 0),
4583         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4584         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4585         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4586         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4587         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4588         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11),
4589         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4590         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4591         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4592         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4593         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4594         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4595         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4596         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4597         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4598         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4599         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4600         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4601         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4602         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4603         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4604         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4605         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4606         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4607         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4608         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4609         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4610         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4611         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4612         HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4613         HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4614         HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4615         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4616         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4617         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4618 };
4619
4620
4621
4622 /* Control elements for the optional TCO module */
4623 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4624         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4625         HDSPM_TCO_PULL("TCO Pull", 0),
4626         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4627         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4628         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4629         HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4630         HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4631         HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4632         HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4633         HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4634 };
4635
4636
4637 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4638
4639
4640 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4641 {
4642         int i;
4643
4644         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4645                 if (hdspm->system_sample_rate > 48000) {
4646                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4647                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4648                                 SNDRV_CTL_ELEM_ACCESS_READ |
4649                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4650                 } else {
4651                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4652                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4653                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4654                 }
4655                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4656                                 SNDRV_CTL_EVENT_MASK_INFO,
4657                                 &hdspm->playback_mixer_ctls[i]->id);
4658         }
4659
4660         return 0;
4661 }
4662
4663
4664 static int snd_hdspm_create_controls(struct snd_card *card,
4665                                         struct hdspm *hdspm)
4666 {
4667         unsigned int idx, limit;
4668         int err;
4669         struct snd_kcontrol *kctl;
4670         struct snd_kcontrol_new *list = NULL;
4671
4672         switch (hdspm->io_type) {
4673         case MADI:
4674                 list = snd_hdspm_controls_madi;
4675                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4676                 break;
4677         case MADIface:
4678                 list = snd_hdspm_controls_madiface;
4679                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4680                 break;
4681         case AIO:
4682                 list = snd_hdspm_controls_aio;
4683                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4684                 break;
4685         case RayDAT:
4686                 list = snd_hdspm_controls_raydat;
4687                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4688                 break;
4689         case AES32:
4690                 list = snd_hdspm_controls_aes32;
4691                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4692                 break;
4693         }
4694
4695         if (NULL != list) {
4696                 for (idx = 0; idx < limit; idx++) {
4697                         err = snd_ctl_add(card,
4698                                         snd_ctl_new1(&list[idx], hdspm));
4699                         if (err < 0)
4700                                 return err;
4701                 }
4702         }
4703
4704
4705         /* create simple 1:1 playback mixer controls */
4706         snd_hdspm_playback_mixer.name = "Chn";
4707         if (hdspm->system_sample_rate >= 128000) {
4708                 limit = hdspm->qs_out_channels;
4709         } else if (hdspm->system_sample_rate >= 64000) {
4710                 limit = hdspm->ds_out_channels;
4711         } else {
4712                 limit = hdspm->ss_out_channels;
4713         }
4714         for (idx = 0; idx < limit; ++idx) {
4715                 snd_hdspm_playback_mixer.index = idx + 1;
4716                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4717                 err = snd_ctl_add(card, kctl);
4718                 if (err < 0)
4719                         return err;
4720                 hdspm->playback_mixer_ctls[idx] = kctl;
4721         }
4722
4723
4724         if (hdspm->tco) {
4725                 /* add tco control elements */
4726                 list = snd_hdspm_controls_tco;
4727                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4728                 for (idx = 0; idx < limit; idx++) {
4729                         err = snd_ctl_add(card,
4730                                         snd_ctl_new1(&list[idx], hdspm));
4731                         if (err < 0)
4732                                 return err;
4733                 }
4734         }
4735
4736         return 0;
4737 }
4738
4739 /*------------------------------------------------------------
4740    /proc interface
4741  ------------------------------------------------------------*/
4742
4743 static void
4744 snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4745                                         struct snd_info_buffer *buffer)
4746 {
4747         struct hdspm *hdspm = entry->private_data;
4748         unsigned int status, control;
4749         int a, ltc, frames, seconds, minutes, hours;
4750         unsigned int period;
4751         u64 freq_const = 0;
4752         u32 rate;
4753
4754         snd_iprintf(buffer, "--- TCO ---\n");
4755
4756         status = hdspm_read(hdspm, HDSPM_statusRegister);
4757         control = hdspm->control_register;
4758
4759
4760         if (status & HDSPM_tco_detect) {
4761                 snd_iprintf(buffer, "TCO module detected.\n");
4762                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4763                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4764                         snd_iprintf(buffer, "  LTC valid, ");
4765                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4766                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4767                         case 0:
4768                                 snd_iprintf(buffer, "24 fps, ");
4769                                 break;
4770                         case HDSPM_TCO1_LTC_Format_LSB:
4771                                 snd_iprintf(buffer, "25 fps, ");
4772                                 break;
4773                         case HDSPM_TCO1_LTC_Format_MSB:
4774                                 snd_iprintf(buffer, "29.97 fps, ");
4775                                 break;
4776                         default:
4777                                 snd_iprintf(buffer, "30 fps, ");
4778                                 break;
4779                         }
4780                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4781                                 snd_iprintf(buffer, "drop frame\n");
4782                         } else {
4783                                 snd_iprintf(buffer, "full frame\n");
4784                         }
4785                 } else {
4786                         snd_iprintf(buffer, "  no LTC\n");
4787                 }
4788                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4789                         snd_iprintf(buffer, "  Video: NTSC\n");
4790                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4791                         snd_iprintf(buffer, "  Video: PAL\n");
4792                 } else {
4793                         snd_iprintf(buffer, "  No video\n");
4794                 }
4795                 if (a & HDSPM_TCO1_TCO_lock) {
4796                         snd_iprintf(buffer, "  Sync: lock\n");
4797                 } else {
4798                         snd_iprintf(buffer, "  Sync: no lock\n");
4799                 }
4800
4801                 switch (hdspm->io_type) {
4802                 case MADI:
4803                 case AES32:
4804                         freq_const = 110069313433624ULL;
4805                         break;
4806                 case RayDAT:
4807                 case AIO:
4808                         freq_const = 104857600000000ULL;
4809                         break;
4810                 case MADIface:
4811                         break; /* no TCO possible */
4812                 }
4813
4814                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4815                 snd_iprintf(buffer, "    period: %u\n", period);
4816
4817
4818                 /* rate = freq_const/period; */
4819                 rate = div_u64(freq_const, period);
4820
4821                 if (control & HDSPM_QuadSpeed) {
4822                         rate *= 4;
4823                 } else if (control & HDSPM_DoubleSpeed) {
4824                         rate *= 2;
4825                 }
4826
4827                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4828                                 (unsigned int) rate);
4829
4830                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4831                 frames = ltc & 0xF;
4832                 ltc >>= 4;
4833                 frames += (ltc & 0x3) * 10;
4834                 ltc >>= 4;
4835                 seconds = ltc & 0xF;
4836                 ltc >>= 4;
4837                 seconds += (ltc & 0x7) * 10;
4838                 ltc >>= 4;
4839                 minutes = ltc & 0xF;
4840                 ltc >>= 4;
4841                 minutes += (ltc & 0x7) * 10;
4842                 ltc >>= 4;
4843                 hours = ltc & 0xF;
4844                 ltc >>= 4;
4845                 hours += (ltc & 0x3) * 10;
4846                 snd_iprintf(buffer,
4847                         "  LTC In: %02d:%02d:%02d:%02d\n",
4848                         hours, minutes, seconds, frames);
4849
4850         } else {
4851                 snd_iprintf(buffer, "No TCO module detected.\n");
4852         }
4853 }
4854
4855 static void
4856 snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4857                          struct snd_info_buffer *buffer)
4858 {
4859         struct hdspm *hdspm = entry->private_data;
4860         unsigned int status, status2;
4861
4862         char *pref_sync_ref;
4863         char *autosync_ref;
4864         char *system_clock_mode;
4865         int x, x2;
4866
4867         status = hdspm_read(hdspm, HDSPM_statusRegister);
4868         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4869
4870         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4871                         hdspm->card_name, hdspm->card->number + 1,
4872                         hdspm->firmware_rev,
4873                         (status2 & HDSPM_version0) |
4874                         (status2 & HDSPM_version1) | (status2 &
4875                                 HDSPM_version2));
4876
4877         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4878                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4879                         hdspm->serial);
4880
4881         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4882                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4883
4884         snd_iprintf(buffer, "--- System ---\n");
4885
4886         snd_iprintf(buffer,
4887                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4888                 status & HDSPM_audioIRQPending,
4889                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4890                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4891                 hdspm->irq_count);
4892         snd_iprintf(buffer,
4893                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4894                 "estimated= %ld (bytes)\n",
4895                 ((status & HDSPM_BufferID) ? 1 : 0),
4896                 (status & HDSPM_BufferPositionMask),
4897                 (status & HDSPM_BufferPositionMask) %
4898                 (2 * (int)hdspm->period_bytes),
4899                 ((status & HDSPM_BufferPositionMask) - 64) %
4900                 (2 * (int)hdspm->period_bytes),
4901                 (long) hdspm_hw_pointer(hdspm) * 4);
4902
4903         snd_iprintf(buffer,
4904                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4905                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4906                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4907                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4908                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4909         snd_iprintf(buffer,
4910                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4911                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4912                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4913         snd_iprintf(buffer,
4914                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4915                 "status2=0x%x\n",
4916                 hdspm->control_register, hdspm->control2_register,
4917                 status, status2);
4918
4919
4920         snd_iprintf(buffer, "--- Settings ---\n");
4921
4922         x = hdspm_get_latency(hdspm);
4923
4924         snd_iprintf(buffer,
4925                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4926                 x, (unsigned long) hdspm->period_bytes);
4927
4928         snd_iprintf(buffer, "Line out: %s\n",
4929                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4930
4931         snd_iprintf(buffer,
4932                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4933                 "Auto Input %s\n",
4934                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4935                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4936                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4937
4938
4939         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4940                 system_clock_mode = "AutoSync";
4941         else
4942                 system_clock_mode = "Master";
4943         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4944
4945         switch (hdspm_pref_sync_ref(hdspm)) {
4946         case HDSPM_SYNC_FROM_WORD:
4947                 pref_sync_ref = "Word Clock";
4948                 break;
4949         case HDSPM_SYNC_FROM_MADI:
4950                 pref_sync_ref = "MADI Sync";
4951                 break;
4952         case HDSPM_SYNC_FROM_TCO:
4953                 pref_sync_ref = "TCO";
4954                 break;
4955         case HDSPM_SYNC_FROM_SYNC_IN:
4956                 pref_sync_ref = "Sync In";
4957                 break;
4958         default:
4959                 pref_sync_ref = "XXXX Clock";
4960                 break;
4961         }
4962         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4963                         pref_sync_ref);
4964
4965         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4966                         hdspm->system_sample_rate);
4967
4968
4969         snd_iprintf(buffer, "--- Status:\n");
4970
4971         x = status & HDSPM_madiSync;
4972         x2 = status2 & HDSPM_wcSync;
4973
4974         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4975                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4976                         "NoLock",
4977                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4978                         "NoLock");
4979
4980         switch (hdspm_autosync_ref(hdspm)) {
4981         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4982                 autosync_ref = "Sync In";
4983                 break;
4984         case HDSPM_AUTOSYNC_FROM_TCO:
4985                 autosync_ref = "TCO";
4986                 break;
4987         case HDSPM_AUTOSYNC_FROM_WORD:
4988                 autosync_ref = "Word Clock";
4989                 break;
4990         case HDSPM_AUTOSYNC_FROM_MADI:
4991                 autosync_ref = "MADI Sync";
4992                 break;
4993         case HDSPM_AUTOSYNC_FROM_NONE:
4994                 autosync_ref = "Input not valid";
4995                 break;
4996         default:
4997                 autosync_ref = "---";
4998                 break;
4999         }
5000         snd_iprintf(buffer,
5001                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
5002                 autosync_ref, hdspm_external_sample_rate(hdspm),
5003                 (status & HDSPM_madiFreqMask) >> 22,
5004                 (status2 & HDSPM_wcFreqMask) >> 5);
5005
5006         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
5007                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
5008                 (status & HDSPM_RX_64ch) ? "64 channels" :
5009                 "56 channels");
5010
5011         /* call readout function for TCO specific status */
5012         snd_hdspm_proc_read_tco(entry, buffer);
5013
5014         snd_iprintf(buffer, "\n");
5015 }
5016
5017 static void
5018 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
5019                           struct snd_info_buffer *buffer)
5020 {
5021         struct hdspm *hdspm = entry->private_data;
5022         unsigned int status;
5023         unsigned int status2;
5024         unsigned int timecode;
5025         unsigned int wcLock, wcSync;
5026         int pref_syncref;
5027         char *autosync_ref;
5028         int x;
5029
5030         status = hdspm_read(hdspm, HDSPM_statusRegister);
5031         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5032         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
5033
5034         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
5035                     hdspm->card_name, hdspm->card->number + 1,
5036                     hdspm->firmware_rev);
5037
5038         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
5039                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5040
5041         snd_iprintf(buffer, "--- System ---\n");
5042
5043         snd_iprintf(buffer,
5044                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
5045                     status & HDSPM_audioIRQPending,
5046                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
5047                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
5048                     hdspm->irq_count);
5049         snd_iprintf(buffer,
5050                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
5051                     "estimated= %ld (bytes)\n",
5052                     ((status & HDSPM_BufferID) ? 1 : 0),
5053                     (status & HDSPM_BufferPositionMask),
5054                     (status & HDSPM_BufferPositionMask) %
5055                     (2 * (int)hdspm->period_bytes),
5056                     ((status & HDSPM_BufferPositionMask) - 64) %
5057                     (2 * (int)hdspm->period_bytes),
5058                     (long) hdspm_hw_pointer(hdspm) * 4);
5059
5060         snd_iprintf(buffer,
5061                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5062                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5063                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5064                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5065                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5066         snd_iprintf(buffer,
5067                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5068                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5069                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5070         snd_iprintf(buffer,
5071                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5072                     "status2=0x%x\n",
5073                     hdspm->control_register, hdspm->control2_register,
5074                     status, status2);
5075
5076         snd_iprintf(buffer, "--- Settings ---\n");
5077
5078         x = hdspm_get_latency(hdspm);
5079
5080         snd_iprintf(buffer,
5081                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5082                     x, (unsigned long) hdspm->period_bytes);
5083
5084         snd_iprintf(buffer, "Line out: %s\n",
5085                     (hdspm->
5086                      control_register & HDSPM_LineOut) ? "on " : "off");
5087
5088         snd_iprintf(buffer,
5089                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5090                     (hdspm->
5091                      control_register & HDSPM_clr_tms) ? "on" : "off",
5092                     (hdspm->
5093                      control_register & HDSPM_Emphasis) ? "on" : "off",
5094                     (hdspm->
5095                      control_register & HDSPM_Dolby) ? "on" : "off");
5096
5097
5098         pref_syncref = hdspm_pref_sync_ref(hdspm);
5099         if (pref_syncref == 0)
5100                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5101         else
5102                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5103                                 pref_syncref);
5104
5105         snd_iprintf(buffer, "System Clock Frequency: %d\n",
5106                     hdspm->system_sample_rate);
5107
5108         snd_iprintf(buffer, "Double speed: %s\n",
5109                         hdspm->control_register & HDSPM_DS_DoubleWire?
5110                         "Double wire" : "Single wire");
5111         snd_iprintf(buffer, "Quad speed: %s\n",
5112                         hdspm->control_register & HDSPM_QS_DoubleWire?
5113                         "Double wire" :
5114                         hdspm->control_register & HDSPM_QS_QuadWire?
5115                         "Quad wire" : "Single wire");
5116
5117         snd_iprintf(buffer, "--- Status:\n");
5118
5119         wcLock = status & HDSPM_AES32_wcLock;
5120         wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5121
5122         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5123                     (wcLock) ? (wcSync ? "Sync   " : "Lock   ") : "No Lock",
5124                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5125
5126         for (x = 0; x < 8; x++) {
5127                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5128                             x+1,
5129                             (status2 & (HDSPM_LockAES >> x)) ?
5130                             "Sync   " : "No Lock",
5131                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5132         }
5133
5134         switch (hdspm_autosync_ref(hdspm)) {
5135         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5136                 autosync_ref = "None"; break;
5137         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5138                 autosync_ref = "Word Clock"; break;
5139         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5140                 autosync_ref = "AES1"; break;
5141         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5142                 autosync_ref = "AES2"; break;
5143         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5144                 autosync_ref = "AES3"; break;
5145         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5146                 autosync_ref = "AES4"; break;
5147         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5148                 autosync_ref = "AES5"; break;
5149         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5150                 autosync_ref = "AES6"; break;
5151         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5152                 autosync_ref = "AES7"; break;
5153         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5154                 autosync_ref = "AES8"; break;
5155         case HDSPM_AES32_AUTOSYNC_FROM_TCO:
5156                 autosync_ref = "TCO"; break;
5157         case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN:
5158                 autosync_ref = "Sync In"; break;
5159         default:
5160                 autosync_ref = "---"; break;
5161         }
5162         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5163
5164         /* call readout function for TCO specific status */
5165         snd_hdspm_proc_read_tco(entry, buffer);
5166
5167         snd_iprintf(buffer, "\n");
5168 }
5169
5170 static void
5171 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5172                          struct snd_info_buffer *buffer)
5173 {
5174         struct hdspm *hdspm = entry->private_data;
5175         unsigned int status1, status2, status3, i;
5176         unsigned int lock, sync;
5177
5178         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5179         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5180         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5181
5182         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5183         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5184         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5185
5186
5187         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5188
5189         snd_iprintf(buffer, "Clock mode      : %s\n",
5190                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5191         snd_iprintf(buffer, "System frequency: %d Hz\n",
5192                 hdspm_get_system_sample_rate(hdspm));
5193
5194         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5195
5196         lock = 0x1;
5197         sync = 0x100;
5198
5199         for (i = 0; i < 8; i++) {
5200                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5201                                 i,
5202                                 (status1 & lock) ? 1 : 0,
5203                                 (status1 & sync) ? 1 : 0,
5204                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
5205
5206                 lock = lock<<1;
5207                 sync = sync<<1;
5208         }
5209
5210         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5211                         (status1 & 0x1000000) ? 1 : 0,
5212                         (status1 & 0x2000000) ? 1 : 0,
5213                         texts_freq[(status1 >> 16) & 0xF]);
5214
5215         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5216                         (status1 & 0x4000000) ? 1 : 0,
5217                         (status1 & 0x8000000) ? 1 : 0,
5218                         texts_freq[(status1 >> 20) & 0xF]);
5219
5220         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5221                         (status3 & 0x400) ? 1 : 0,
5222                         (status3 & 0x800) ? 1 : 0,
5223                         texts_freq[(status2 >> 12) & 0xF]);
5224
5225 }
5226
5227 #ifdef CONFIG_SND_DEBUG
5228 static void
5229 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5230                           struct snd_info_buffer *buffer)
5231 {
5232         struct hdspm *hdspm = entry->private_data;
5233
5234         int j,i;
5235
5236         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5237                 snd_iprintf(buffer, "0x%08X: ", i);
5238                 for (j = 0; j < 16; j += 4)
5239                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5240                 snd_iprintf(buffer, "\n");
5241         }
5242 }
5243 #endif
5244
5245
5246 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5247                           struct snd_info_buffer *buffer)
5248 {
5249         struct hdspm *hdspm = entry->private_data;
5250         int i;
5251
5252         snd_iprintf(buffer, "# generated by hdspm\n");
5253
5254         for (i = 0; i < hdspm->max_channels_in; i++) {
5255                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5256         }
5257 }
5258
5259 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5260                           struct snd_info_buffer *buffer)
5261 {
5262         struct hdspm *hdspm = entry->private_data;
5263         int i;
5264
5265         snd_iprintf(buffer, "# generated by hdspm\n");
5266
5267         for (i = 0; i < hdspm->max_channels_out; i++) {
5268                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5269         }
5270 }
5271
5272
5273 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5274 {
5275         struct snd_info_entry *entry;
5276
5277         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5278                 switch (hdspm->io_type) {
5279                 case AES32:
5280                         snd_info_set_text_ops(entry, hdspm,
5281                                         snd_hdspm_proc_read_aes32);
5282                         break;
5283                 case MADI:
5284                         snd_info_set_text_ops(entry, hdspm,
5285                                         snd_hdspm_proc_read_madi);
5286                         break;
5287                 case MADIface:
5288                         /* snd_info_set_text_ops(entry, hdspm,
5289                          snd_hdspm_proc_read_madiface); */
5290                         break;
5291                 case RayDAT:
5292                         snd_info_set_text_ops(entry, hdspm,
5293                                         snd_hdspm_proc_read_raydat);
5294                         break;
5295                 case AIO:
5296                         break;
5297                 }
5298         }
5299
5300         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5301                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5302         }
5303
5304         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5305                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5306         }
5307
5308 #ifdef CONFIG_SND_DEBUG
5309         /* debug file to read all hdspm registers */
5310         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5311                 snd_info_set_text_ops(entry, hdspm,
5312                                 snd_hdspm_proc_read_debug);
5313 #endif
5314 }
5315
5316 /*------------------------------------------------------------
5317    hdspm intitialize
5318  ------------------------------------------------------------*/
5319
5320 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5321 {
5322         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5323            hold it (e.g. during module initialization).
5324            */
5325
5326         /* set defaults:       */
5327
5328         hdspm->settings_register = 0;
5329
5330         switch (hdspm->io_type) {
5331         case MADI:
5332         case MADIface:
5333                 hdspm->control_register =
5334                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5335                 break;
5336
5337         case RayDAT:
5338         case AIO:
5339                 hdspm->settings_register = 0x1 + 0x1000;
5340                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5341                  * line_out */
5342                 hdspm->control_register =
5343                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5344                 break;
5345
5346         case AES32:
5347                 hdspm->control_register =
5348                         HDSPM_ClockModeMaster | /* Master Clock Mode on */
5349                         hdspm_encode_latency(7) | /* latency max=8192samples */
5350                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5351                         HDSPM_LineOut | /* Analog output in */
5352                         HDSPM_Professional;  /* Professional mode */
5353                 break;
5354         }
5355
5356         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5357
5358         if (AES32 == hdspm->io_type) {
5359                 /* No control2 register for AES32 */
5360 #ifdef SNDRV_BIG_ENDIAN
5361                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5362 #else
5363                 hdspm->control2_register = 0;
5364 #endif
5365
5366                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5367         }
5368         hdspm_compute_period_size(hdspm);
5369
5370         /* silence everything */
5371
5372         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5373
5374         if (hdspm_is_raydat_or_aio(hdspm))
5375                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5376
5377         /* set a default rate so that the channel map is set up. */
5378         hdspm_set_rate(hdspm, 48000, 1);
5379
5380         return 0;
5381 }
5382
5383
5384 /*------------------------------------------------------------
5385    interrupt
5386  ------------------------------------------------------------*/
5387
5388 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5389 {
5390         struct hdspm *hdspm = (struct hdspm *) dev_id;
5391         unsigned int status;
5392         int i, audio, midi, schedule = 0;
5393         /* cycles_t now; */
5394
5395         status = hdspm_read(hdspm, HDSPM_statusRegister);
5396
5397         audio = status & HDSPM_audioIRQPending;
5398         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5399                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5400
5401         /* now = get_cycles(); */
5402         /*
5403          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5404          *          6       4096   ~256053425     ~514672358
5405          *          5       2048   ~128024983     ~257373821
5406          *          4       1024    ~64023706     ~128718089
5407          *          3        512    ~32005945      ~64385999
5408          *          2        256    ~16003039      ~32260176
5409          *          1        128     ~7998738      ~16194507
5410          *          0         64     ~3998231       ~8191558
5411          */
5412         /*
5413           dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n",
5414            now-hdspm->last_interrupt, status & 0xFFC0);
5415            hdspm->last_interrupt = now;
5416         */
5417
5418         if (!audio && !midi)
5419                 return IRQ_NONE;
5420
5421         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5422         hdspm->irq_count++;
5423
5424
5425         if (audio) {
5426                 if (hdspm->capture_substream)
5427                         snd_pcm_period_elapsed(hdspm->capture_substream);
5428
5429                 if (hdspm->playback_substream)
5430                         snd_pcm_period_elapsed(hdspm->playback_substream);
5431         }
5432
5433         if (midi) {
5434                 i = 0;
5435                 while (i < hdspm->midiPorts) {
5436                         if ((hdspm_read(hdspm,
5437                                 hdspm->midi[i].statusIn) & 0xff) &&
5438                                         (status & hdspm->midi[i].irq)) {
5439                                 /* we disable interrupts for this input until
5440                                  * processing is done
5441                                  */
5442                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5443                                 hdspm_write(hdspm, HDSPM_controlRegister,
5444                                                 hdspm->control_register);
5445                                 hdspm->midi[i].pending = 1;
5446                                 schedule = 1;
5447                         }
5448
5449                         i++;
5450                 }
5451
5452                 if (schedule)
5453                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5454         }
5455
5456         return IRQ_HANDLED;
5457 }
5458
5459 /*------------------------------------------------------------
5460    pcm interface
5461   ------------------------------------------------------------*/
5462
5463
5464 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5465                                               *substream)
5466 {
5467         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5468         return hdspm_hw_pointer(hdspm);
5469 }
5470
5471
5472 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5473 {
5474         struct snd_pcm_runtime *runtime = substream->runtime;
5475         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5476         struct snd_pcm_substream *other;
5477
5478         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5479                 other = hdspm->capture_substream;
5480         else
5481                 other = hdspm->playback_substream;
5482
5483         if (hdspm->running)
5484                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5485         else
5486                 runtime->status->hw_ptr = 0;
5487         if (other) {
5488                 struct snd_pcm_substream *s;
5489                 struct snd_pcm_runtime *oruntime = other->runtime;
5490                 snd_pcm_group_for_each_entry(s, substream) {
5491                         if (s == other) {
5492                                 oruntime->status->hw_ptr =
5493                                         runtime->status->hw_ptr;
5494                                 break;
5495                         }
5496                 }
5497         }
5498         return 0;
5499 }
5500
5501 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5502                                struct snd_pcm_hw_params *params)
5503 {
5504         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5505         int err;
5506         int i;
5507         pid_t this_pid;
5508         pid_t other_pid;
5509
5510         spin_lock_irq(&hdspm->lock);
5511
5512         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5513                 this_pid = hdspm->playback_pid;
5514                 other_pid = hdspm->capture_pid;
5515         } else {
5516                 this_pid = hdspm->capture_pid;
5517                 other_pid = hdspm->playback_pid;
5518         }
5519
5520         if (other_pid > 0 && this_pid != other_pid) {
5521
5522                 /* The other stream is open, and not by the same
5523                    task as this one. Make sure that the parameters
5524                    that matter are the same.
5525                    */
5526
5527                 if (params_rate(params) != hdspm->system_sample_rate) {
5528                         spin_unlock_irq(&hdspm->lock);
5529                         _snd_pcm_hw_param_setempty(params,
5530                                         SNDRV_PCM_HW_PARAM_RATE);
5531                         return -EBUSY;
5532                 }
5533
5534                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5535                         spin_unlock_irq(&hdspm->lock);
5536                         _snd_pcm_hw_param_setempty(params,
5537                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5538                         return -EBUSY;
5539                 }
5540
5541         }
5542         /* We're fine. */
5543         spin_unlock_irq(&hdspm->lock);
5544
5545         /* how to make sure that the rate matches an externally-set one ?   */
5546
5547         spin_lock_irq(&hdspm->lock);
5548         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5549         if (err < 0) {
5550                 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err);
5551                 spin_unlock_irq(&hdspm->lock);
5552                 _snd_pcm_hw_param_setempty(params,
5553                                 SNDRV_PCM_HW_PARAM_RATE);
5554                 return err;
5555         }
5556         spin_unlock_irq(&hdspm->lock);
5557
5558         err = hdspm_set_interrupt_interval(hdspm,
5559                         params_period_size(params));
5560         if (err < 0) {
5561                 dev_info(hdspm->card->dev,
5562                          "err on hdspm_set_interrupt_interval: %d\n", err);
5563                 _snd_pcm_hw_param_setempty(params,
5564                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5565                 return err;
5566         }
5567
5568         /* Memory allocation, takashi's method, dont know if we should
5569          * spinlock
5570          */
5571         /* malloc all buffer even if not enabled to get sure */
5572         /* Update for MADI rev 204: we need to allocate for all channels,
5573          * otherwise it doesn't work at 96kHz */
5574
5575         err =
5576                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5577         if (err < 0) {
5578                 dev_info(hdspm->card->dev,
5579                          "err on snd_pcm_lib_malloc_pages: %d\n", err);
5580                 return err;
5581         }
5582
5583         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5584
5585                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5586                                 params_channels(params));
5587
5588                 for (i = 0; i < params_channels(params); ++i)
5589                         snd_hdspm_enable_out(hdspm, i, 1);
5590
5591                 hdspm->playback_buffer =
5592                         (unsigned char *) substream->runtime->dma_area;
5593                 dev_dbg(hdspm->card->dev,
5594                         "Allocated sample buffer for playback at %p\n",
5595                                 hdspm->playback_buffer);
5596         } else {
5597                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5598                                 params_channels(params));
5599
5600                 for (i = 0; i < params_channels(params); ++i)
5601                         snd_hdspm_enable_in(hdspm, i, 1);
5602
5603                 hdspm->capture_buffer =
5604                         (unsigned char *) substream->runtime->dma_area;
5605                 dev_dbg(hdspm->card->dev,
5606                         "Allocated sample buffer for capture at %p\n",
5607                                 hdspm->capture_buffer);
5608         }
5609
5610         /*
5611            dev_dbg(hdspm->card->dev,
5612            "Allocated sample buffer for %s at 0x%08X\n",
5613            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5614            "playback" : "capture",
5615            snd_pcm_sgbuf_get_addr(substream, 0));
5616            */
5617         /*
5618            dev_dbg(hdspm->card->dev,
5619            "set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5620            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5621            "playback" : "capture",
5622            params_rate(params), params_channels(params),
5623            params_buffer_size(params));
5624            */
5625
5626
5627         /*  For AES cards, the float format bit is the same as the
5628          *  preferred sync reference. Since we don't want to break
5629          *  sync settings, we have to skip the remaining part of this
5630          *  function.
5631          */
5632         if (hdspm->io_type == AES32) {
5633                 return 0;
5634         }
5635
5636
5637         /* Switch to native float format if requested */
5638         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5639                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5640                         dev_info(hdspm->card->dev,
5641                                  "Switching to native 32bit LE float format.\n");
5642
5643                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5644         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5645                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5646                         dev_info(hdspm->card->dev,
5647                                  "Switching to native 32bit LE integer format.\n");
5648
5649                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5650         }
5651         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5652
5653         return 0;
5654 }
5655
5656 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5657 {
5658         int i;
5659         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5660
5661         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5662
5663                 /* params_channels(params) should be enough,
5664                    but to get sure in case of error */
5665                 for (i = 0; i < hdspm->max_channels_out; ++i)
5666                         snd_hdspm_enable_out(hdspm, i, 0);
5667
5668                 hdspm->playback_buffer = NULL;
5669         } else {
5670                 for (i = 0; i < hdspm->max_channels_in; ++i)
5671                         snd_hdspm_enable_in(hdspm, i, 0);
5672
5673                 hdspm->capture_buffer = NULL;
5674
5675         }
5676
5677         snd_pcm_lib_free_pages(substream);
5678
5679         return 0;
5680 }
5681
5682
5683 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5684                 struct snd_pcm_channel_info *info)
5685 {
5686         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5687
5688         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5689                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5690                         dev_info(hdspm->card->dev,
5691                                  "snd_hdspm_channel_info: output channel out of range (%d)\n",
5692                                  info->channel);
5693                         return -EINVAL;
5694                 }
5695
5696                 if (hdspm->channel_map_out[info->channel] < 0) {
5697                         dev_info(hdspm->card->dev,
5698                                  "snd_hdspm_channel_info: output channel %d mapped out\n",
5699                                  info->channel);
5700                         return -EINVAL;
5701                 }
5702
5703                 info->offset = hdspm->channel_map_out[info->channel] *
5704                         HDSPM_CHANNEL_BUFFER_BYTES;
5705         } else {
5706                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5707                         dev_info(hdspm->card->dev,
5708                                  "snd_hdspm_channel_info: input channel out of range (%d)\n",
5709                                  info->channel);
5710                         return -EINVAL;
5711                 }
5712
5713                 if (hdspm->channel_map_in[info->channel] < 0) {
5714                         dev_info(hdspm->card->dev,
5715                                  "snd_hdspm_channel_info: input channel %d mapped out\n",
5716                                  info->channel);
5717                         return -EINVAL;
5718                 }
5719
5720                 info->offset = hdspm->channel_map_in[info->channel] *
5721                         HDSPM_CHANNEL_BUFFER_BYTES;
5722         }
5723
5724         info->first = 0;
5725         info->step = 32;
5726         return 0;
5727 }
5728
5729
5730 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5731                 unsigned int cmd, void *arg)
5732 {
5733         switch (cmd) {
5734         case SNDRV_PCM_IOCTL1_RESET:
5735                 return snd_hdspm_reset(substream);
5736
5737         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5738                 {
5739                         struct snd_pcm_channel_info *info = arg;
5740                         return snd_hdspm_channel_info(substream, info);
5741                 }
5742         default:
5743                 break;
5744         }
5745
5746         return snd_pcm_lib_ioctl(substream, cmd, arg);
5747 }
5748
5749 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5750 {
5751         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5752         struct snd_pcm_substream *other;
5753         int running;
5754
5755         spin_lock(&hdspm->lock);
5756         running = hdspm->running;
5757         switch (cmd) {
5758         case SNDRV_PCM_TRIGGER_START:
5759                 running |= 1 << substream->stream;
5760                 break;
5761         case SNDRV_PCM_TRIGGER_STOP:
5762                 running &= ~(1 << substream->stream);
5763                 break;
5764         default:
5765                 snd_BUG();
5766                 spin_unlock(&hdspm->lock);
5767                 return -EINVAL;
5768         }
5769         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5770                 other = hdspm->capture_substream;
5771         else
5772                 other = hdspm->playback_substream;
5773
5774         if (other) {
5775                 struct snd_pcm_substream *s;
5776                 snd_pcm_group_for_each_entry(s, substream) {
5777                         if (s == other) {
5778                                 snd_pcm_trigger_done(s, substream);
5779                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5780                                         running |= 1 << s->stream;
5781                                 else
5782                                         running &= ~(1 << s->stream);
5783                                 goto _ok;
5784                         }
5785                 }
5786                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5787                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5788                                         && substream->stream ==
5789                                         SNDRV_PCM_STREAM_CAPTURE)
5790                                 hdspm_silence_playback(hdspm);
5791                 } else {
5792                         if (running &&
5793                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5794                                 hdspm_silence_playback(hdspm);
5795                 }
5796         } else {
5797                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5798                         hdspm_silence_playback(hdspm);
5799         }
5800 _ok:
5801         snd_pcm_trigger_done(substream, substream);
5802         if (!hdspm->running && running)
5803                 hdspm_start_audio(hdspm);
5804         else if (hdspm->running && !running)
5805                 hdspm_stop_audio(hdspm);
5806         hdspm->running = running;
5807         spin_unlock(&hdspm->lock);
5808
5809         return 0;
5810 }
5811
5812 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5813 {
5814         return 0;
5815 }
5816
5817 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5818         .info = (SNDRV_PCM_INFO_MMAP |
5819                  SNDRV_PCM_INFO_MMAP_VALID |
5820                  SNDRV_PCM_INFO_NONINTERLEAVED |
5821                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5822         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5823         .rates = (SNDRV_PCM_RATE_32000 |
5824                   SNDRV_PCM_RATE_44100 |
5825                   SNDRV_PCM_RATE_48000 |
5826                   SNDRV_PCM_RATE_64000 |
5827                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5828                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5829         .rate_min = 32000,
5830         .rate_max = 192000,
5831         .channels_min = 1,
5832         .channels_max = HDSPM_MAX_CHANNELS,
5833         .buffer_bytes_max =
5834             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5835         .period_bytes_min = (32 * 4),
5836         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5837         .periods_min = 2,
5838         .periods_max = 512,
5839         .fifo_size = 0
5840 };
5841
5842 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5843         .info = (SNDRV_PCM_INFO_MMAP |
5844                  SNDRV_PCM_INFO_MMAP_VALID |
5845                  SNDRV_PCM_INFO_NONINTERLEAVED |
5846                  SNDRV_PCM_INFO_SYNC_START),
5847         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5848         .rates = (SNDRV_PCM_RATE_32000 |
5849                   SNDRV_PCM_RATE_44100 |
5850                   SNDRV_PCM_RATE_48000 |
5851                   SNDRV_PCM_RATE_64000 |
5852                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5853                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5854         .rate_min = 32000,
5855         .rate_max = 192000,
5856         .channels_min = 1,
5857         .channels_max = HDSPM_MAX_CHANNELS,
5858         .buffer_bytes_max =
5859             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5860         .period_bytes_min = (32 * 4),
5861         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5862         .periods_min = 2,
5863         .periods_max = 512,
5864         .fifo_size = 0
5865 };
5866
5867 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5868                                            struct snd_pcm_hw_rule *rule)
5869 {
5870         struct hdspm *hdspm = rule->private;
5871         struct snd_interval *c =
5872             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5873         struct snd_interval *r =
5874             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5875
5876         if (r->min > 96000 && r->max <= 192000) {
5877                 struct snd_interval t = {
5878                         .min = hdspm->qs_in_channels,
5879                         .max = hdspm->qs_in_channels,
5880                         .integer = 1,
5881                 };
5882                 return snd_interval_refine(c, &t);
5883         } else if (r->min > 48000 && r->max <= 96000) {
5884                 struct snd_interval t = {
5885                         .min = hdspm->ds_in_channels,
5886                         .max = hdspm->ds_in_channels,
5887                         .integer = 1,
5888                 };
5889                 return snd_interval_refine(c, &t);
5890         } else if (r->max < 64000) {
5891                 struct snd_interval t = {
5892                         .min = hdspm->ss_in_channels,
5893                         .max = hdspm->ss_in_channels,
5894                         .integer = 1,
5895                 };
5896                 return snd_interval_refine(c, &t);
5897         }
5898
5899         return 0;
5900 }
5901
5902 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5903                                            struct snd_pcm_hw_rule * rule)
5904 {
5905         struct hdspm *hdspm = rule->private;
5906         struct snd_interval *c =
5907             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5908         struct snd_interval *r =
5909             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5910
5911         if (r->min > 96000 && r->max <= 192000) {
5912                 struct snd_interval t = {
5913                         .min = hdspm->qs_out_channels,
5914                         .max = hdspm->qs_out_channels,
5915                         .integer = 1,
5916                 };
5917                 return snd_interval_refine(c, &t);
5918         } else if (r->min > 48000 && r->max <= 96000) {
5919                 struct snd_interval t = {
5920                         .min = hdspm->ds_out_channels,
5921                         .max = hdspm->ds_out_channels,
5922                         .integer = 1,
5923                 };
5924                 return snd_interval_refine(c, &t);
5925         } else if (r->max < 64000) {
5926                 struct snd_interval t = {
5927                         .min = hdspm->ss_out_channels,
5928                         .max = hdspm->ss_out_channels,
5929                         .integer = 1,
5930                 };
5931                 return snd_interval_refine(c, &t);
5932         } else {
5933         }
5934         return 0;
5935 }
5936
5937 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5938                                            struct snd_pcm_hw_rule * rule)
5939 {
5940         struct hdspm *hdspm = rule->private;
5941         struct snd_interval *c =
5942             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5943         struct snd_interval *r =
5944             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5945
5946         if (c->min >= hdspm->ss_in_channels) {
5947                 struct snd_interval t = {
5948                         .min = 32000,
5949                         .max = 48000,
5950                         .integer = 1,
5951                 };
5952                 return snd_interval_refine(r, &t);
5953         } else if (c->max <= hdspm->qs_in_channels) {
5954                 struct snd_interval t = {
5955                         .min = 128000,
5956                         .max = 192000,
5957                         .integer = 1,
5958                 };
5959                 return snd_interval_refine(r, &t);
5960         } else if (c->max <= hdspm->ds_in_channels) {
5961                 struct snd_interval t = {
5962                         .min = 64000,
5963                         .max = 96000,
5964                         .integer = 1,
5965                 };
5966                 return snd_interval_refine(r, &t);
5967         }
5968
5969         return 0;
5970 }
5971 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5972                                            struct snd_pcm_hw_rule *rule)
5973 {
5974         struct hdspm *hdspm = rule->private;
5975         struct snd_interval *c =
5976             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5977         struct snd_interval *r =
5978             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5979
5980         if (c->min >= hdspm->ss_out_channels) {
5981                 struct snd_interval t = {
5982                         .min = 32000,
5983                         .max = 48000,
5984                         .integer = 1,
5985                 };
5986                 return snd_interval_refine(r, &t);
5987         } else if (c->max <= hdspm->qs_out_channels) {
5988                 struct snd_interval t = {
5989                         .min = 128000,
5990                         .max = 192000,
5991                         .integer = 1,
5992                 };
5993                 return snd_interval_refine(r, &t);
5994         } else if (c->max <= hdspm->ds_out_channels) {
5995                 struct snd_interval t = {
5996                         .min = 64000,
5997                         .max = 96000,
5998                         .integer = 1,
5999                 };
6000                 return snd_interval_refine(r, &t);
6001         }
6002
6003         return 0;
6004 }
6005
6006 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
6007                                       struct snd_pcm_hw_rule *rule)
6008 {
6009         unsigned int list[3];
6010         struct hdspm *hdspm = rule->private;
6011         struct snd_interval *c = hw_param_interval(params,
6012                         SNDRV_PCM_HW_PARAM_CHANNELS);
6013
6014         list[0] = hdspm->qs_in_channels;
6015         list[1] = hdspm->ds_in_channels;
6016         list[2] = hdspm->ss_in_channels;
6017         return snd_interval_list(c, 3, list, 0);
6018 }
6019
6020 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
6021                                       struct snd_pcm_hw_rule *rule)
6022 {
6023         unsigned int list[3];
6024         struct hdspm *hdspm = rule->private;
6025         struct snd_interval *c = hw_param_interval(params,
6026                         SNDRV_PCM_HW_PARAM_CHANNELS);
6027
6028         list[0] = hdspm->qs_out_channels;
6029         list[1] = hdspm->ds_out_channels;
6030         list[2] = hdspm->ss_out_channels;
6031         return snd_interval_list(c, 3, list, 0);
6032 }
6033
6034
6035 static unsigned int hdspm_aes32_sample_rates[] = {
6036         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
6037 };
6038
6039 static struct snd_pcm_hw_constraint_list
6040 hdspm_hw_constraints_aes32_sample_rates = {
6041         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
6042         .list = hdspm_aes32_sample_rates,
6043         .mask = 0
6044 };
6045
6046 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
6047 {
6048         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6049         struct snd_pcm_runtime *runtime = substream->runtime;
6050
6051         spin_lock_irq(&hdspm->lock);
6052
6053         snd_pcm_set_sync(substream);
6054
6055
6056         runtime->hw = snd_hdspm_playback_subinfo;
6057
6058         if (hdspm->capture_substream == NULL)
6059                 hdspm_stop_audio(hdspm);
6060
6061         hdspm->playback_pid = current->pid;
6062         hdspm->playback_substream = substream;
6063
6064         spin_unlock_irq(&hdspm->lock);
6065
6066         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6067         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6068
6069         switch (hdspm->io_type) {
6070         case AIO:
6071         case RayDAT:
6072                 snd_pcm_hw_constraint_minmax(runtime,
6073                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6074                                              32, 4096);
6075                 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
6076                 snd_pcm_hw_constraint_minmax(runtime,
6077                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6078                                              16384, 16384);
6079                 break;
6080
6081         default:
6082                 snd_pcm_hw_constraint_minmax(runtime,
6083                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6084                                              64, 8192);
6085                 break;
6086         }
6087
6088         if (AES32 == hdspm->io_type) {
6089                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6090                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6091                                 &hdspm_hw_constraints_aes32_sample_rates);
6092         } else {
6093                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6094                                 snd_hdspm_hw_rule_rate_out_channels, hdspm,
6095                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6096         }
6097
6098         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6099                         snd_hdspm_hw_rule_out_channels, hdspm,
6100                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6101
6102         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6103                         snd_hdspm_hw_rule_out_channels_rate, hdspm,
6104                         SNDRV_PCM_HW_PARAM_RATE, -1);
6105
6106         return 0;
6107 }
6108
6109 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
6110 {
6111         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6112
6113         spin_lock_irq(&hdspm->lock);
6114
6115         hdspm->playback_pid = -1;
6116         hdspm->playback_substream = NULL;
6117
6118         spin_unlock_irq(&hdspm->lock);
6119
6120         return 0;
6121 }
6122
6123
6124 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6125 {
6126         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6127         struct snd_pcm_runtime *runtime = substream->runtime;
6128
6129         spin_lock_irq(&hdspm->lock);
6130         snd_pcm_set_sync(substream);
6131         runtime->hw = snd_hdspm_capture_subinfo;
6132
6133         if (hdspm->playback_substream == NULL)
6134                 hdspm_stop_audio(hdspm);
6135
6136         hdspm->capture_pid = current->pid;
6137         hdspm->capture_substream = substream;
6138
6139         spin_unlock_irq(&hdspm->lock);
6140
6141         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6142         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6143
6144         switch (hdspm->io_type) {
6145         case AIO:
6146         case RayDAT:
6147                 snd_pcm_hw_constraint_minmax(runtime,
6148                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6149                                              32, 4096);
6150                 snd_pcm_hw_constraint_minmax(runtime,
6151                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6152                                              16384, 16384);
6153                 break;
6154
6155         default:
6156                 snd_pcm_hw_constraint_minmax(runtime,
6157                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6158                                              64, 8192);
6159                 break;
6160         }
6161
6162         if (AES32 == hdspm->io_type) {
6163                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6164                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6165                                 &hdspm_hw_constraints_aes32_sample_rates);
6166         } else {
6167                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6168                                 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6169                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6170         }
6171
6172         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6173                         snd_hdspm_hw_rule_in_channels, hdspm,
6174                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6175
6176         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6177                         snd_hdspm_hw_rule_in_channels_rate, hdspm,
6178                         SNDRV_PCM_HW_PARAM_RATE, -1);
6179
6180         return 0;
6181 }
6182
6183 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6184 {
6185         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6186
6187         spin_lock_irq(&hdspm->lock);
6188
6189         hdspm->capture_pid = -1;
6190         hdspm->capture_substream = NULL;
6191
6192         spin_unlock_irq(&hdspm->lock);
6193         return 0;
6194 }
6195
6196 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6197 {
6198         /* we have nothing to initialize but the call is required */
6199         return 0;
6200 }
6201
6202 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6203 {
6204         u32 val = readl(src);
6205         return copy_to_user(dest, &val, 4);
6206 }
6207
6208 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6209                 unsigned int cmd, unsigned long arg)
6210 {
6211         void __user *argp = (void __user *)arg;
6212         struct hdspm *hdspm = hw->private_data;
6213         struct hdspm_mixer_ioctl mixer;
6214         struct hdspm_config info;
6215         struct hdspm_status status;
6216         struct hdspm_version hdspm_version;
6217         struct hdspm_peak_rms *levels;
6218         struct hdspm_ltc ltc;
6219         unsigned int statusregister;
6220         long unsigned int s;
6221         int i = 0;
6222
6223         switch (cmd) {
6224
6225         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6226                 levels = &hdspm->peak_rms;
6227                 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6228                         levels->input_peaks[i] =
6229                                 readl(hdspm->iobase +
6230                                                 HDSPM_MADI_INPUT_PEAK + i*4);
6231                         levels->playback_peaks[i] =
6232                                 readl(hdspm->iobase +
6233                                                 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6234                         levels->output_peaks[i] =
6235                                 readl(hdspm->iobase +
6236                                                 HDSPM_MADI_OUTPUT_PEAK + i*4);
6237
6238                         levels->input_rms[i] =
6239                                 ((uint64_t) readl(hdspm->iobase +
6240                                         HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6241                                 (uint64_t) readl(hdspm->iobase +
6242                                                 HDSPM_MADI_INPUT_RMS_L + i*4);
6243                         levels->playback_rms[i] =
6244                                 ((uint64_t)readl(hdspm->iobase +
6245                                         HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6246                                 (uint64_t)readl(hdspm->iobase +
6247                                         HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6248                         levels->output_rms[i] =
6249                                 ((uint64_t)readl(hdspm->iobase +
6250                                         HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6251                                 (uint64_t)readl(hdspm->iobase +
6252                                                 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6253                 }
6254
6255                 if (hdspm->system_sample_rate > 96000) {
6256                         levels->speed = qs;
6257                 } else if (hdspm->system_sample_rate > 48000) {
6258                         levels->speed = ds;
6259                 } else {
6260                         levels->speed = ss;
6261                 }
6262                 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6263
6264                 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6265                 if (0 != s) {
6266                         /* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu
6267                          [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6268                          */
6269                         return -EFAULT;
6270                 }
6271                 break;
6272
6273         case SNDRV_HDSPM_IOCTL_GET_LTC:
6274                 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6275                 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6276                 if (i & HDSPM_TCO1_LTC_Input_valid) {
6277                         switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6278                                 HDSPM_TCO1_LTC_Format_MSB)) {
6279                         case 0:
6280                                 ltc.format = fps_24;
6281                                 break;
6282                         case HDSPM_TCO1_LTC_Format_LSB:
6283                                 ltc.format = fps_25;
6284                                 break;
6285                         case HDSPM_TCO1_LTC_Format_MSB:
6286                                 ltc.format = fps_2997;
6287                                 break;
6288                         default:
6289                                 ltc.format = fps_30;
6290                                 break;
6291                         }
6292                         if (i & HDSPM_TCO1_set_drop_frame_flag) {
6293                                 ltc.frame = drop_frame;
6294                         } else {
6295                                 ltc.frame = full_frame;
6296                         }
6297                 } else {
6298                         ltc.format = format_invalid;
6299                         ltc.frame = frame_invalid;
6300                 }
6301                 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6302                         ltc.input_format = ntsc;
6303                 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6304                         ltc.input_format = pal;
6305                 } else {
6306                         ltc.input_format = no_video;
6307                 }
6308
6309                 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6310                 if (0 != s) {
6311                         /*
6312                           dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6313                         return -EFAULT;
6314                 }
6315
6316                 break;
6317
6318         case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6319
6320                 memset(&info, 0, sizeof(info));
6321                 spin_lock_irq(&hdspm->lock);
6322                 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6323                 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6324
6325                 info.system_sample_rate = hdspm->system_sample_rate;
6326                 info.autosync_sample_rate =
6327                         hdspm_external_sample_rate(hdspm);
6328                 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6329                 info.clock_source = hdspm_clock_source(hdspm);
6330                 info.autosync_ref = hdspm_autosync_ref(hdspm);
6331                 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
6332                 info.passthru = 0;
6333                 spin_unlock_irq(&hdspm->lock);
6334                 if (copy_to_user(argp, &info, sizeof(info)))
6335                         return -EFAULT;
6336                 break;
6337
6338         case SNDRV_HDSPM_IOCTL_GET_STATUS:
6339                 memset(&status, 0, sizeof(status));
6340
6341                 status.card_type = hdspm->io_type;
6342
6343                 status.autosync_source = hdspm_autosync_ref(hdspm);
6344
6345                 status.card_clock = 110069313433624ULL;
6346                 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6347
6348                 switch (hdspm->io_type) {
6349                 case MADI:
6350                 case MADIface:
6351                         status.card_specific.madi.sync_wc =
6352                                 hdspm_wc_sync_check(hdspm);
6353                         status.card_specific.madi.sync_madi =
6354                                 hdspm_madi_sync_check(hdspm);
6355                         status.card_specific.madi.sync_tco =
6356                                 hdspm_tco_sync_check(hdspm);
6357                         status.card_specific.madi.sync_in =
6358                                 hdspm_sync_in_sync_check(hdspm);
6359
6360                         statusregister =
6361                                 hdspm_read(hdspm, HDSPM_statusRegister);
6362                         status.card_specific.madi.madi_input =
6363                                 (statusregister & HDSPM_AB_int) ? 1 : 0;
6364                         status.card_specific.madi.channel_format =
6365                                 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6366                         /* TODO: Mac driver sets it when f_s>48kHz */
6367                         status.card_specific.madi.frame_format = 0;
6368
6369                 default:
6370                         break;
6371                 }
6372
6373                 if (copy_to_user(argp, &status, sizeof(status)))
6374                         return -EFAULT;
6375
6376
6377                 break;
6378
6379         case SNDRV_HDSPM_IOCTL_GET_VERSION:
6380                 memset(&hdspm_version, 0, sizeof(hdspm_version));
6381
6382                 hdspm_version.card_type = hdspm->io_type;
6383                 strlcpy(hdspm_version.cardname, hdspm->card_name,
6384                                 sizeof(hdspm_version.cardname));
6385                 hdspm_version.serial = hdspm->serial;
6386                 hdspm_version.firmware_rev = hdspm->firmware_rev;
6387                 hdspm_version.addons = 0;
6388                 if (hdspm->tco)
6389                         hdspm_version.addons |= HDSPM_ADDON_TCO;
6390
6391                 if (copy_to_user(argp, &hdspm_version,
6392                                         sizeof(hdspm_version)))
6393                         return -EFAULT;
6394                 break;
6395
6396         case SNDRV_HDSPM_IOCTL_GET_MIXER:
6397                 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6398                         return -EFAULT;
6399                 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6400                                         sizeof(struct hdspm_mixer)))
6401                         return -EFAULT;
6402                 break;
6403
6404         default:
6405                 return -EINVAL;
6406         }
6407         return 0;
6408 }
6409
6410 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6411         .open = snd_hdspm_playback_open,
6412         .close = snd_hdspm_playback_release,
6413         .ioctl = snd_hdspm_ioctl,
6414         .hw_params = snd_hdspm_hw_params,
6415         .hw_free = snd_hdspm_hw_free,
6416         .prepare = snd_hdspm_prepare,
6417         .trigger = snd_hdspm_trigger,
6418         .pointer = snd_hdspm_hw_pointer,
6419         .page = snd_pcm_sgbuf_ops_page,
6420 };
6421
6422 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6423         .open = snd_hdspm_capture_open,
6424         .close = snd_hdspm_capture_release,
6425         .ioctl = snd_hdspm_ioctl,
6426         .hw_params = snd_hdspm_hw_params,
6427         .hw_free = snd_hdspm_hw_free,
6428         .prepare = snd_hdspm_prepare,
6429         .trigger = snd_hdspm_trigger,
6430         .pointer = snd_hdspm_hw_pointer,
6431         .page = snd_pcm_sgbuf_ops_page,
6432 };
6433
6434 static int snd_hdspm_create_hwdep(struct snd_card *card,
6435                                   struct hdspm *hdspm)
6436 {
6437         struct snd_hwdep *hw;
6438         int err;
6439
6440         err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6441         if (err < 0)
6442                 return err;
6443
6444         hdspm->hwdep = hw;
6445         hw->private_data = hdspm;
6446         strcpy(hw->name, "HDSPM hwdep interface");
6447
6448         hw->ops.open = snd_hdspm_hwdep_dummy_op;
6449         hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6450         hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6451         hw->ops.release = snd_hdspm_hwdep_dummy_op;
6452
6453         return 0;
6454 }
6455
6456
6457 /*------------------------------------------------------------
6458    memory interface
6459  ------------------------------------------------------------*/
6460 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6461 {
6462         int err;
6463         struct snd_pcm *pcm;
6464         size_t wanted;
6465
6466         pcm = hdspm->pcm;
6467
6468         wanted = HDSPM_DMA_AREA_BYTES;
6469
6470         err =
6471              snd_pcm_lib_preallocate_pages_for_all(pcm,
6472                                                    SNDRV_DMA_TYPE_DEV_SG,
6473                                                    snd_dma_pci_data(hdspm->pci),
6474                                                    wanted,
6475                                                    wanted);
6476         if (err < 0) {
6477                 dev_dbg(hdspm->card->dev,
6478                         "Could not preallocate %zd Bytes\n", wanted);
6479
6480                 return err;
6481         } else
6482                 dev_dbg(hdspm->card->dev,
6483                         " Preallocated %zd Bytes\n", wanted);
6484
6485         return 0;
6486 }
6487
6488
6489 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6490                             struct snd_pcm_substream *substream,
6491                              unsigned int reg, int channels)
6492 {
6493         int i;
6494
6495         /* continuous memory segment */
6496         for (i = 0; i < (channels * 16); i++)
6497                 hdspm_write(hdspm, reg + 4 * i,
6498                                 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6499 }
6500
6501
6502 /* ------------- ALSA Devices ---------------------------- */
6503 static int snd_hdspm_create_pcm(struct snd_card *card,
6504                                 struct hdspm *hdspm)
6505 {
6506         struct snd_pcm *pcm;
6507         int err;
6508
6509         err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6510         if (err < 0)
6511                 return err;
6512
6513         hdspm->pcm = pcm;
6514         pcm->private_data = hdspm;
6515         strcpy(pcm->name, hdspm->card_name);
6516
6517         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6518                         &snd_hdspm_playback_ops);
6519         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6520                         &snd_hdspm_capture_ops);
6521
6522         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6523
6524         err = snd_hdspm_preallocate_memory(hdspm);
6525         if (err < 0)
6526                 return err;
6527
6528         return 0;
6529 }
6530
6531 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6532 {
6533         int i;
6534
6535         for (i = 0; i < hdspm->midiPorts; i++)
6536                 snd_hdspm_flush_midi_input(hdspm, i);
6537 }
6538
6539 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
6540                                          struct hdspm *hdspm)
6541 {
6542         int err, i;
6543
6544         dev_dbg(card->dev, "Create card...\n");
6545         err = snd_hdspm_create_pcm(card, hdspm);
6546         if (err < 0)
6547                 return err;
6548
6549         i = 0;
6550         while (i < hdspm->midiPorts) {
6551                 err = snd_hdspm_create_midi(card, hdspm, i);
6552                 if (err < 0) {
6553                         return err;
6554                 }
6555                 i++;
6556         }
6557
6558         err = snd_hdspm_create_controls(card, hdspm);
6559         if (err < 0)
6560                 return err;
6561
6562         err = snd_hdspm_create_hwdep(card, hdspm);
6563         if (err < 0)
6564                 return err;
6565
6566         dev_dbg(card->dev, "proc init...\n");
6567         snd_hdspm_proc_init(hdspm);
6568
6569         hdspm->system_sample_rate = -1;
6570         hdspm->last_external_sample_rate = -1;
6571         hdspm->last_internal_sample_rate = -1;
6572         hdspm->playback_pid = -1;
6573         hdspm->capture_pid = -1;
6574         hdspm->capture_substream = NULL;
6575         hdspm->playback_substream = NULL;
6576
6577         dev_dbg(card->dev, "Set defaults...\n");
6578         err = snd_hdspm_set_defaults(hdspm);
6579         if (err < 0)
6580                 return err;
6581
6582         dev_dbg(card->dev, "Update mixer controls...\n");
6583         hdspm_update_simple_mixer_controls(hdspm);
6584
6585         dev_dbg(card->dev, "Initializeing complete ???\n");
6586
6587         err = snd_card_register(card);
6588         if (err < 0) {
6589                 dev_err(card->dev, "error registering card\n");
6590                 return err;
6591         }
6592
6593         dev_dbg(card->dev, "... yes now\n");
6594
6595         return 0;
6596 }
6597
6598 static int snd_hdspm_create(struct snd_card *card,
6599                             struct hdspm *hdspm)
6600 {
6601
6602         struct pci_dev *pci = hdspm->pci;
6603         int err;
6604         unsigned long io_extent;
6605
6606         hdspm->irq = -1;
6607         hdspm->card = card;
6608
6609         spin_lock_init(&hdspm->lock);
6610
6611         pci_read_config_word(hdspm->pci,
6612                         PCI_CLASS_REVISION, &hdspm->firmware_rev);
6613
6614         strcpy(card->mixername, "Xilinx FPGA");
6615         strcpy(card->driver, "HDSPM");
6616
6617         switch (hdspm->firmware_rev) {
6618         case HDSPM_RAYDAT_REV:
6619                 hdspm->io_type = RayDAT;
6620                 hdspm->card_name = "RME RayDAT";
6621                 hdspm->midiPorts = 2;
6622                 break;
6623         case HDSPM_AIO_REV:
6624                 hdspm->io_type = AIO;
6625                 hdspm->card_name = "RME AIO";
6626                 hdspm->midiPorts = 1;
6627                 break;
6628         case HDSPM_MADIFACE_REV:
6629                 hdspm->io_type = MADIface;
6630                 hdspm->card_name = "RME MADIface";
6631                 hdspm->midiPorts = 1;
6632                 break;
6633         default:
6634                 if ((hdspm->firmware_rev == 0xf0) ||
6635                         ((hdspm->firmware_rev >= 0xe6) &&
6636                                         (hdspm->firmware_rev <= 0xea))) {
6637                         hdspm->io_type = AES32;
6638                         hdspm->card_name = "RME AES32";
6639                         hdspm->midiPorts = 2;
6640                 } else if ((hdspm->firmware_rev == 0xd2) ||
6641                         ((hdspm->firmware_rev >= 0xc8)  &&
6642                                 (hdspm->firmware_rev <= 0xcf))) {
6643                         hdspm->io_type = MADI;
6644                         hdspm->card_name = "RME MADI";
6645                         hdspm->midiPorts = 3;
6646                 } else {
6647                         dev_err(card->dev,
6648                                 "unknown firmware revision %x\n",
6649                                 hdspm->firmware_rev);
6650                         return -ENODEV;
6651                 }
6652         }
6653
6654         err = pci_enable_device(pci);
6655         if (err < 0)
6656                 return err;
6657
6658         pci_set_master(hdspm->pci);
6659
6660         err = pci_request_regions(pci, "hdspm");
6661         if (err < 0)
6662                 return err;
6663
6664         hdspm->port = pci_resource_start(pci, 0);
6665         io_extent = pci_resource_len(pci, 0);
6666
6667         dev_dbg(card->dev, "grabbed memory region 0x%lx-0x%lx\n",
6668                         hdspm->port, hdspm->port + io_extent - 1);
6669
6670         hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6671         if (!hdspm->iobase) {
6672                 dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n",
6673                                 hdspm->port, hdspm->port + io_extent - 1);
6674                 return -EBUSY;
6675         }
6676         dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n",
6677                         (unsigned long)hdspm->iobase, hdspm->port,
6678                         hdspm->port + io_extent - 1);
6679
6680         if (request_irq(pci->irq, snd_hdspm_interrupt,
6681                         IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6682                 dev_err(card->dev, "unable to use IRQ %d\n", pci->irq);
6683                 return -EBUSY;
6684         }
6685
6686         dev_dbg(card->dev, "use IRQ %d\n", pci->irq);
6687
6688         hdspm->irq = pci->irq;
6689
6690         dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n",
6691                         sizeof(struct hdspm_mixer));
6692         hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6693         if (!hdspm->mixer) {
6694                 dev_err(card->dev,
6695                         "unable to kmalloc Mixer memory of %d Bytes\n",
6696                                 (int)sizeof(struct hdspm_mixer));
6697                 return -ENOMEM;
6698         }
6699
6700         hdspm->port_names_in = NULL;
6701         hdspm->port_names_out = NULL;
6702
6703         switch (hdspm->io_type) {
6704         case AES32:
6705                 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6706                 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6707                 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6708
6709                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6710                         channel_map_aes32;
6711                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6712                         channel_map_aes32;
6713                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6714                         channel_map_aes32;
6715                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6716                         texts_ports_aes32;
6717                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6718                         texts_ports_aes32;
6719                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6720                         texts_ports_aes32;
6721
6722                 hdspm->max_channels_out = hdspm->max_channels_in =
6723                         AES32_CHANNELS;
6724                 hdspm->port_names_in = hdspm->port_names_out =
6725                         texts_ports_aes32;
6726                 hdspm->channel_map_in = hdspm->channel_map_out =
6727                         channel_map_aes32;
6728
6729                 break;
6730
6731         case MADI:
6732         case MADIface:
6733                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6734                         MADI_SS_CHANNELS;
6735                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6736                         MADI_DS_CHANNELS;
6737                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6738                         MADI_QS_CHANNELS;
6739
6740                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6741                         channel_map_unity_ss;
6742                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6743                         channel_map_unity_ss;
6744                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6745                         channel_map_unity_ss;
6746
6747                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6748                         texts_ports_madi;
6749                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6750                         texts_ports_madi;
6751                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6752                         texts_ports_madi;
6753                 break;
6754
6755         case AIO:
6756                 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6757                 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6758                 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6759                 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6760                 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6761                 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6762
6763                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6764                         dev_info(card->dev, "AEB input board found\n");
6765                         hdspm->ss_in_channels += 4;
6766                         hdspm->ds_in_channels += 4;
6767                         hdspm->qs_in_channels += 4;
6768                 }
6769
6770                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) {
6771                         dev_info(card->dev, "AEB output board found\n");
6772                         hdspm->ss_out_channels += 4;
6773                         hdspm->ds_out_channels += 4;
6774                         hdspm->qs_out_channels += 4;
6775                 }
6776
6777                 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6778                 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6779                 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6780
6781                 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6782                 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6783                 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6784
6785                 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6786                 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6787                 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6788                 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6789                 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6790                 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6791
6792                 break;
6793
6794         case RayDAT:
6795                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6796                         RAYDAT_SS_CHANNELS;
6797                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6798                         RAYDAT_DS_CHANNELS;
6799                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6800                         RAYDAT_QS_CHANNELS;
6801
6802                 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6803                 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6804
6805                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6806                         channel_map_raydat_ss;
6807                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6808                         channel_map_raydat_ds;
6809                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6810                         channel_map_raydat_qs;
6811                 hdspm->channel_map_in = hdspm->channel_map_out =
6812                         channel_map_raydat_ss;
6813
6814                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6815                         texts_ports_raydat_ss;
6816                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6817                         texts_ports_raydat_ds;
6818                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6819                         texts_ports_raydat_qs;
6820
6821
6822                 break;
6823
6824         }
6825
6826         /* TCO detection */
6827         switch (hdspm->io_type) {
6828         case AIO:
6829         case RayDAT:
6830                 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6831                                 HDSPM_s2_tco_detect) {
6832                         hdspm->midiPorts++;
6833                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6834                                         GFP_KERNEL);
6835                         if (NULL != hdspm->tco) {
6836                                 hdspm_tco_write(hdspm);
6837                         }
6838                         dev_info(card->dev, "AIO/RayDAT TCO module found\n");
6839                 } else {
6840                         hdspm->tco = NULL;
6841                 }
6842                 break;
6843
6844         case MADI:
6845         case AES32:
6846                 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6847                         hdspm->midiPorts++;
6848                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6849                                         GFP_KERNEL);
6850                         if (NULL != hdspm->tco) {
6851                                 hdspm_tco_write(hdspm);
6852                         }
6853                         dev_info(card->dev, "MADI/AES TCO module found\n");
6854                 } else {
6855                         hdspm->tco = NULL;
6856                 }
6857                 break;
6858
6859         default:
6860                 hdspm->tco = NULL;
6861         }
6862
6863         /* texts */
6864         switch (hdspm->io_type) {
6865         case AES32:
6866                 if (hdspm->tco) {
6867                         hdspm->texts_autosync = texts_autosync_aes_tco;
6868                         hdspm->texts_autosync_items =
6869                                 ARRAY_SIZE(texts_autosync_aes_tco);
6870                 } else {
6871                         hdspm->texts_autosync = texts_autosync_aes;
6872                         hdspm->texts_autosync_items =
6873                                 ARRAY_SIZE(texts_autosync_aes);
6874                 }
6875                 break;
6876
6877         case MADI:
6878                 if (hdspm->tco) {
6879                         hdspm->texts_autosync = texts_autosync_madi_tco;
6880                         hdspm->texts_autosync_items = 4;
6881                 } else {
6882                         hdspm->texts_autosync = texts_autosync_madi;
6883                         hdspm->texts_autosync_items = 3;
6884                 }
6885                 break;
6886
6887         case MADIface:
6888
6889                 break;
6890
6891         case RayDAT:
6892                 if (hdspm->tco) {
6893                         hdspm->texts_autosync = texts_autosync_raydat_tco;
6894                         hdspm->texts_autosync_items = 9;
6895                 } else {
6896                         hdspm->texts_autosync = texts_autosync_raydat;
6897                         hdspm->texts_autosync_items = 8;
6898                 }
6899                 break;
6900
6901         case AIO:
6902                 if (hdspm->tco) {
6903                         hdspm->texts_autosync = texts_autosync_aio_tco;
6904                         hdspm->texts_autosync_items = 6;
6905                 } else {
6906                         hdspm->texts_autosync = texts_autosync_aio;
6907                         hdspm->texts_autosync_items = 5;
6908                 }
6909                 break;
6910
6911         }
6912
6913         tasklet_init(&hdspm->midi_tasklet,
6914                         hdspm_midi_tasklet, (unsigned long) hdspm);
6915
6916
6917         if (hdspm->io_type != MADIface) {
6918                 hdspm->serial = (hdspm_read(hdspm,
6919                                 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6920                 /* id contains either a user-provided value or the default
6921                  * NULL. If it's the default, we're safe to
6922                  * fill card->id with the serial number.
6923                  *
6924                  * If the serial number is 0xFFFFFF, then we're dealing with
6925                  * an old PCI revision that comes without a sane number. In
6926                  * this case, we don't set card->id to avoid collisions
6927                  * when running with multiple cards.
6928                  */
6929                 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6930                         sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6931                         snd_card_set_id(card, card->id);
6932                 }
6933         }
6934
6935         dev_dbg(card->dev, "create alsa devices.\n");
6936         err = snd_hdspm_create_alsa_devices(card, hdspm);
6937         if (err < 0)
6938                 return err;
6939
6940         snd_hdspm_initialize_midi_flush(hdspm);
6941
6942         return 0;
6943 }
6944
6945
6946 static int snd_hdspm_free(struct hdspm * hdspm)
6947 {
6948
6949         if (hdspm->port) {
6950
6951                 /* stop th audio, and cancel all interrupts */
6952                 hdspm->control_register &=
6953                     ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6954                       HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6955                       HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6956                 hdspm_write(hdspm, HDSPM_controlRegister,
6957                             hdspm->control_register);
6958         }
6959
6960         if (hdspm->irq >= 0)
6961                 free_irq(hdspm->irq, (void *) hdspm);
6962
6963         kfree(hdspm->mixer);
6964         iounmap(hdspm->iobase);
6965
6966         if (hdspm->port)
6967                 pci_release_regions(hdspm->pci);
6968
6969         pci_disable_device(hdspm->pci);
6970         return 0;
6971 }
6972
6973
6974 static void snd_hdspm_card_free(struct snd_card *card)
6975 {
6976         struct hdspm *hdspm = card->private_data;
6977
6978         if (hdspm)
6979                 snd_hdspm_free(hdspm);
6980 }
6981
6982
6983 static int snd_hdspm_probe(struct pci_dev *pci,
6984                            const struct pci_device_id *pci_id)
6985 {
6986         static int dev;
6987         struct hdspm *hdspm;
6988         struct snd_card *card;
6989         int err;
6990
6991         if (dev >= SNDRV_CARDS)
6992                 return -ENODEV;
6993         if (!enable[dev]) {
6994                 dev++;
6995                 return -ENOENT;
6996         }
6997
6998         err = snd_card_new(&pci->dev, index[dev], id[dev],
6999                            THIS_MODULE, sizeof(struct hdspm), &card);
7000         if (err < 0)
7001                 return err;
7002
7003         hdspm = card->private_data;
7004         card->private_free = snd_hdspm_card_free;
7005         hdspm->dev = dev;
7006         hdspm->pci = pci;
7007
7008         err = snd_hdspm_create(card, hdspm);
7009         if (err < 0) {
7010                 snd_card_free(card);
7011                 return err;
7012         }
7013
7014         if (hdspm->io_type != MADIface) {
7015                 sprintf(card->shortname, "%s_%x",
7016                         hdspm->card_name,
7017                         hdspm->serial);
7018                 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
7019                         hdspm->card_name,
7020                         hdspm->serial,
7021                         hdspm->port, hdspm->irq);
7022         } else {
7023                 sprintf(card->shortname, "%s", hdspm->card_name);
7024                 sprintf(card->longname, "%s at 0x%lx, irq %d",
7025                                 hdspm->card_name, hdspm->port, hdspm->irq);
7026         }
7027
7028         err = snd_card_register(card);
7029         if (err < 0) {
7030                 snd_card_free(card);
7031                 return err;
7032         }
7033
7034         pci_set_drvdata(pci, card);
7035
7036         dev++;
7037         return 0;
7038 }
7039
7040 static void snd_hdspm_remove(struct pci_dev *pci)
7041 {
7042         snd_card_free(pci_get_drvdata(pci));
7043 }
7044
7045 static struct pci_driver hdspm_driver = {
7046         .name = KBUILD_MODNAME,
7047         .id_table = snd_hdspm_ids,
7048         .probe = snd_hdspm_probe,
7049         .remove = snd_hdspm_remove,
7050 };
7051
7052 module_pci_driver(hdspm_driver);