2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
11 * Modified 2009-04-13 for proper metering by Florian Faber
14 * Modified 2009-04-14 for native float support by Florian Faber
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/module.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/math64.h>
50 #include <sound/core.h>
51 #include <sound/control.h>
52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h>
54 #include <sound/info.h>
55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h>
58 #include <sound/initval.h>
60 #include <sound/hdspm.h>
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
78 "Winfried Ritsch <ritsch_AT_iem.at>, "
79 "Paul Davis <paul@linuxaudiosystems.com>, "
80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81 "Remy Bruno <remy.bruno@trinnov.com>, "
82 "Florian Faber <faberman@linuxproaudio.org>, "
83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
89 /* --- Write registers. ---
90 These are defined as byte-offsets from the iobase value. */
92 #define HDSPM_WR_SETTINGS 0
93 #define HDSPM_outputBufferAddress 32
94 #define HDSPM_inputBufferAddress 36
95 #define HDSPM_controlRegister 64
96 #define HDSPM_interruptConfirmation 96
97 #define HDSPM_control2Reg 256 /* not in specs ???????? */
98 #define HDSPM_freqReg 256 /* for AES32 */
99 #define HDSPM_midiDataOut0 352 /* just believe in old code */
100 #define HDSPM_midiDataOut1 356
101 #define HDSPM_eeprom_wr 384 /* for AES32 */
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut 8192
110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
116 /* --- Read registers. ---
117 These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister 0
119 /*#define HDSPM_statusRegister2 96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121 * offset 192, for AES32 *and* MADI
122 * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2 192
124 #define HDSPM_timecodeRegister 128
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
132 #define HDSPM_RD_TCO 256
133 #define HDSPM_RD_PLL_FREQ 512
134 #define HDSPM_WR_TCO 128
136 #define HDSPM_TCO1_TCO_lock 0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
144 #define HDSPM_TCO1_set_TC 0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800
149 #define HDSPM_TCO2_TC_run 0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
154 #define HDSPM_TCO2_set_jam_sync 0x00200000
155 #define HDSPM_TCO2_set_flywheel 0x00400000
157 #define HDSPM_TCO2_set_01_4 0x01000000
158 #define HDSPM_TCO2_set_pull_down 0x02000000
159 #define HDSPM_TCO2_set_pull_up 0x04000000
160 #define HDSPM_TCO2_set_freq 0x08000000
161 #define HDSPM_TCO2_set_term_75R 0x10000000
162 #define HDSPM_TCO2_set_input_LSB 0x20000000
163 #define HDSPM_TCO2_set_input_MSB 0x40000000
164 #define HDSPM_TCO2_set_freq_from_app 0x80000000
167 #define HDSPM_midiDataOut0 352
168 #define HDSPM_midiDataOut1 356
169 #define HDSPM_midiDataOut2 368
171 #define HDSPM_midiDataIn0 360
172 #define HDSPM_midiDataIn1 364
173 #define HDSPM_midiDataIn2 372
174 #define HDSPM_midiDataIn3 376
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0 384
178 #define HDSPM_midiStatusOut1 388
179 #define HDSPM_midiStatusOut2 400
181 #define HDSPM_midiStatusIn0 392
182 #define HDSPM_midiStatusIn1 396
183 #define HDSPM_midiStatusIn2 404
184 #define HDSPM_midiStatusIn3 408
187 /* the meters are regular i/o-mapped registers, but offset
188 considerably from the rest. the peak registers are reset
189 when read; the least-significant 4 bits are full-scale counters;
190 the actual peak value is in the most-significant 24 bits.
193 #define HDSPM_MADI_INPUT_PEAK 4096
194 #define HDSPM_MADI_PLAYBACK_PEAK 4352
195 #define HDSPM_MADI_OUTPUT_PEAK 4608
197 #define HDSPM_MADI_INPUT_RMS_L 6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400
199 #define HDSPM_MADI_OUTPUT_RMS_L 6656
201 #define HDSPM_MADI_INPUT_RMS_H 7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424
203 #define HDSPM_MADI_OUTPUT_RMS_H 7680
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start (1<<0) /* start engine */
208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1 (1<<2) /* where n is defined */
210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings
214 register [RayDAT, AIO] */
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
225 56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
229 0=off, 1=on */ /* MADI ONLY */
230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
237 #define HDSPM_SyncRef2 (1<<13)
238 #define HDSPM_SyncRef3 (1<<25)
240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
242 AES additional bits in
243 lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT 0x2000000
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
259 #define HDSPM_wclk_sel (1<<30)
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical 0
267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269 HDSPM_SyncRef2|HDSPM_SyncRef3)
271 #define HDSPM_c0_SyncRef0 0x2
272 #define HDSPM_c0_SyncRef1 0x4
273 #define HDSPM_c0_SyncRef2 0x8
274 #define HDSPM_c0_SyncRef3 0x10
275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO 2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
283 #define HDSPM_Frequency32KHz HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK 1
299 #define HDSPM_SYNC_CHECK_SYNC 2
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD 0
303 #define HDSPM_AUTOSYNC_FROM_MADI 1
304 #define HDSPM_AUTOSYNC_FROM_TCO 2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
306 #define HDSPM_AUTOSYNC_FROM_NONE 4
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0 /* optical */
310 #define HDSPM_COAXIAL 1 /* BNC */
312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS (1<<0)
320 #define HDSPM_TCK (1<<1)
321 #define HDSPM_TDI (1<<2)
322 #define HDSPM_JTAG (1<<3)
323 #define HDSPM_PWDN (1<<4)
324 #define HDSPM_PROGRAM (1<<5)
325 #define HDSPM_CONFIG_MODE_0 (1<<6)
326 #define HDSPM_CONFIG_MODE_1 (1<<7)
327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE (1<<9)
329 #define HDSPM_RD_MULTIPLE (1<<10)
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332 that do not conflict with specific bits for AES32 seem to be valid also
335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351 /* since 64byte accurate, last 6 bits are not used */
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
365 #define HDSPM_tco_detect 0x08000000
366 #define HDSPM_tco_lock 0x20000000
368 #define HDSPM_s2_tco_detect 0x00000040
369 #define HDSPM_s2_AEBO_D 0x00000080
370 #define HDSPM_s2_AEBI_D 0x00000100
373 #define HDSPM_midi0IRQPending 0x40000000
374 #define HDSPM_midi1IRQPending 0x80000000
375 #define HDSPM_midi2IRQPending 0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending 0x00200000
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381 HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
392 /* Status2 Register bits */ /* MADI ONLY */
394 #define HDSPM_version0 (1<<0) /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */
406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
432 #define HDSPM_SelSyncRef_WORD 0
433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
440 For AES32, bits for status, status2 and timecode are different
443 #define HDSPM_AES32_wcLock 0x0200000
444 #define HDSPM_AES32_wcFreq_bit 22
445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
447 #define HDSPM_AES32_syncref_bit 16
448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463 #define HDSPM_LockAES 0x80
464 #define HDSPM_LockAES1 0x80
465 #define HDSPM_LockAES2 0x40
466 #define HDSPM_LockAES3 0x20
467 #define HDSPM_LockAES4 0x10
468 #define HDSPM_LockAES5 0x8
469 #define HDSPM_LockAES6 0x4
470 #define HDSPM_LockAES7 0x2
471 #define HDSPM_LockAES8 0x1
474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
486 NB: Timecode register doesn't seem to work on AES32 card revision 230
490 #define UNITY_GAIN 32768 /* = 65536/2 */
491 #define MINUS_INFINITY_GAIN 0
493 /* Number of channels for different Speed Modes */
494 #define MADI_SS_CHANNELS 64
495 #define MADI_DS_CHANNELS 32
496 #define MADI_QS_CHANNELS 16
498 #define RAYDAT_SS_CHANNELS 36
499 #define RAYDAT_DS_CHANNELS 20
500 #define RAYDAT_QS_CHANNELS 12
502 #define AIO_IN_SS_CHANNELS 14
503 #define AIO_IN_DS_CHANNELS 10
504 #define AIO_IN_QS_CHANNELS 8
505 #define AIO_OUT_SS_CHANNELS 16
506 #define AIO_OUT_DS_CHANNELS 12
507 #define AIO_OUT_QS_CHANNELS 10
509 #define AES32_CHANNELS 16
511 /* the size of a substream (1 mono data stream) */
512 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
513 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
515 /* the size of the area we need to allocate for DMA transfers. the
516 size is the same regardless of the number of channels, and
517 also the latency to use.
518 for one direction !!!
520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
523 #define HDSPM_RAYDAT_REV 211
524 #define HDSPM_AIO_REV 212
525 #define HDSPM_MADIFACE_REV 213
527 /* speed factor modes */
528 #define HDSPM_SPEED_SINGLE 0
529 #define HDSPM_SPEED_DOUBLE 1
530 #define HDSPM_SPEED_QUAD 2
532 /* names for speed modes */
533 static char *hdspm_speed_names[] = { "single", "double", "quad" };
535 static char *texts_autosync_aes_tco[] = { "Word Clock",
536 "AES1", "AES2", "AES3", "AES4",
537 "AES5", "AES6", "AES7", "AES8",
539 static char *texts_autosync_aes[] = { "Word Clock",
540 "AES1", "AES2", "AES3", "AES4",
541 "AES5", "AES6", "AES7", "AES8" };
542 static char *texts_autosync_madi_tco[] = { "Word Clock",
543 "MADI", "TCO", "Sync In" };
544 static char *texts_autosync_madi[] = { "Word Clock",
547 static char *texts_autosync_raydat_tco[] = {
549 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
550 "AES", "SPDIF", "TCO", "Sync In"
552 static char *texts_autosync_raydat[] = {
554 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
555 "AES", "SPDIF", "Sync In"
557 static char *texts_autosync_aio_tco[] = {
559 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
561 static char *texts_autosync_aio[] = { "Word Clock",
562 "ADAT", "AES", "SPDIF", "Sync In" };
564 static char *texts_freq[] = {
577 static char *texts_ports_madi[] = {
578 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
579 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
580 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
581 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
582 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
583 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
584 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
585 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
586 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
587 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
588 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
592 static char *texts_ports_raydat_ss[] = {
593 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
594 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
595 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
596 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
597 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
598 "ADAT4.7", "ADAT4.8",
603 static char *texts_ports_raydat_ds[] = {
604 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
605 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
606 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
607 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
612 static char *texts_ports_raydat_qs[] = {
613 "ADAT1.1", "ADAT1.2",
614 "ADAT2.1", "ADAT2.2",
615 "ADAT3.1", "ADAT3.2",
616 "ADAT4.1", "ADAT4.2",
622 static char *texts_ports_aio_in_ss[] = {
623 "Analogue.L", "Analogue.R",
625 "SPDIF.L", "SPDIF.R",
626 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
630 static char *texts_ports_aio_out_ss[] = {
631 "Analogue.L", "Analogue.R",
633 "SPDIF.L", "SPDIF.R",
634 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
639 static char *texts_ports_aio_in_ds[] = {
640 "Analogue.L", "Analogue.R",
642 "SPDIF.L", "SPDIF.R",
643 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
646 static char *texts_ports_aio_out_ds[] = {
647 "Analogue.L", "Analogue.R",
649 "SPDIF.L", "SPDIF.R",
650 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
654 static char *texts_ports_aio_in_qs[] = {
655 "Analogue.L", "Analogue.R",
657 "SPDIF.L", "SPDIF.R",
658 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
661 static char *texts_ports_aio_out_qs[] = {
662 "Analogue.L", "Analogue.R",
664 "SPDIF.L", "SPDIF.R",
665 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
669 static char *texts_ports_aes32[] = {
670 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
671 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
675 /* These tables map the ALSA channels 1..N to the channels that we
676 need to use in order to find the relevant channel buffer. RME
677 refers to this kind of mapping as between "the ADAT channel and
678 the DMA channel." We index it using the logical audio channel,
679 and the value is the DMA channel (i.e. channel buffer number)
680 where the data for that channel can be read/written from/to.
683 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
684 0, 1, 2, 3, 4, 5, 6, 7,
685 8, 9, 10, 11, 12, 13, 14, 15,
686 16, 17, 18, 19, 20, 21, 22, 23,
687 24, 25, 26, 27, 28, 29, 30, 31,
688 32, 33, 34, 35, 36, 37, 38, 39,
689 40, 41, 42, 43, 44, 45, 46, 47,
690 48, 49, 50, 51, 52, 53, 54, 55,
691 56, 57, 58, 59, 60, 61, 62, 63
694 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
695 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
696 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
697 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
698 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
702 -1, -1, -1, -1, -1, -1, -1, -1,
703 -1, -1, -1, -1, -1, -1, -1, -1,
704 -1, -1, -1, -1, -1, -1, -1, -1,
707 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
708 4, 5, 6, 7, /* ADAT 1 */
709 8, 9, 10, 11, /* ADAT 2 */
710 12, 13, 14, 15, /* ADAT 3 */
711 16, 17, 18, 19, /* ADAT 4 */
715 -1, -1, -1, -1, -1, -1, -1, -1,
716 -1, -1, -1, -1, -1, -1, -1, -1,
717 -1, -1, -1, -1, -1, -1, -1, -1,
718 -1, -1, -1, -1, -1, -1, -1, -1,
719 -1, -1, -1, -1, -1, -1, -1, -1,
722 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
730 -1, -1, -1, -1, -1, -1, -1, -1,
731 -1, -1, -1, -1, -1, -1, -1, -1,
732 -1, -1, -1, -1, -1, -1, -1, -1,
733 -1, -1, -1, -1, -1, -1, -1, -1,
734 -1, -1, -1, -1, -1, -1, -1, -1,
735 -1, -1, -1, -1, -1, -1, -1, -1,
738 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
741 10, 11, /* spdif in */
742 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
744 -1, -1, -1, -1, -1, -1, -1, -1,
745 -1, -1, -1, -1, -1, -1, -1, -1,
746 -1, -1, -1, -1, -1, -1, -1, -1,
747 -1, -1, -1, -1, -1, -1, -1, -1,
748 -1, -1, -1, -1, -1, -1, -1, -1,
749 -1, -1, -1, -1, -1, -1, -1, -1,
752 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
755 10, 11, /* spdif out */
756 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
757 6, 7, /* phone out */
758 -1, -1, -1, -1, -1, -1, -1, -1,
759 -1, -1, -1, -1, -1, -1, -1, -1,
760 -1, -1, -1, -1, -1, -1, -1, -1,
761 -1, -1, -1, -1, -1, -1, -1, -1,
762 -1, -1, -1, -1, -1, -1, -1, -1,
763 -1, -1, -1, -1, -1, -1, -1, -1,
766 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
769 10, 11, /* spdif in */
770 12, 14, 16, 18, /* adat in */
771 -1, -1, -1, -1, -1, -1,
772 -1, -1, -1, -1, -1, -1, -1, -1,
773 -1, -1, -1, -1, -1, -1, -1, -1,
774 -1, -1, -1, -1, -1, -1, -1, -1,
775 -1, -1, -1, -1, -1, -1, -1, -1,
776 -1, -1, -1, -1, -1, -1, -1, -1,
777 -1, -1, -1, -1, -1, -1, -1, -1
780 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
783 10, 11, /* spdif out */
784 12, 14, 16, 18, /* adat out */
785 6, 7, /* phone out */
787 -1, -1, -1, -1, -1, -1, -1, -1,
788 -1, -1, -1, -1, -1, -1, -1, -1,
789 -1, -1, -1, -1, -1, -1, -1, -1,
790 -1, -1, -1, -1, -1, -1, -1, -1,
791 -1, -1, -1, -1, -1, -1, -1, -1,
792 -1, -1, -1, -1, -1, -1, -1, -1
795 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
798 10, 11, /* spdif in */
799 12, 16, /* adat in */
800 -1, -1, -1, -1, -1, -1, -1, -1,
801 -1, -1, -1, -1, -1, -1, -1, -1,
802 -1, -1, -1, -1, -1, -1, -1, -1,
803 -1, -1, -1, -1, -1, -1, -1, -1,
804 -1, -1, -1, -1, -1, -1, -1, -1,
805 -1, -1, -1, -1, -1, -1, -1, -1,
806 -1, -1, -1, -1, -1, -1, -1, -1
809 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
812 10, 11, /* spdif out */
813 12, 16, /* adat out */
814 6, 7, /* phone out */
815 -1, -1, -1, -1, -1, -1,
816 -1, -1, -1, -1, -1, -1, -1, -1,
817 -1, -1, -1, -1, -1, -1, -1, -1,
818 -1, -1, -1, -1, -1, -1, -1, -1,
819 -1, -1, -1, -1, -1, -1, -1, -1,
820 -1, -1, -1, -1, -1, -1, -1, -1,
821 -1, -1, -1, -1, -1, -1, -1, -1
824 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
825 0, 1, 2, 3, 4, 5, 6, 7,
826 8, 9, 10, 11, 12, 13, 14, 15,
827 -1, -1, -1, -1, -1, -1, -1, -1,
828 -1, -1, -1, -1, -1, -1, -1, -1,
829 -1, -1, -1, -1, -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1, -1,
831 -1, -1, -1, -1, -1, -1, -1, -1,
832 -1, -1, -1, -1, -1, -1, -1, -1
838 struct snd_rawmidi *rmidi;
839 struct snd_rawmidi_substream *input;
840 struct snd_rawmidi_substream *output;
841 char istimer; /* timer in use */
842 struct timer_list timer;
859 int term; /* 0 = off, 1 = on */
864 /* only one playback and/or capture stream */
865 struct snd_pcm_substream *capture_substream;
866 struct snd_pcm_substream *playback_substream;
868 char *card_name; /* for procinfo */
869 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
873 int monitor_outs; /* set up monitoring outs init flag */
875 u32 control_register; /* cached value */
876 u32 control2_register; /* cached value */
877 u32 settings_register;
879 struct hdspm_midi midi[4];
880 struct tasklet_struct midi_tasklet;
883 unsigned char ss_in_channels;
884 unsigned char ds_in_channels;
885 unsigned char qs_in_channels;
886 unsigned char ss_out_channels;
887 unsigned char ds_out_channels;
888 unsigned char qs_out_channels;
890 unsigned char max_channels_in;
891 unsigned char max_channels_out;
893 signed char *channel_map_in;
894 signed char *channel_map_out;
896 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
897 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
899 char **port_names_in;
900 char **port_names_out;
902 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
903 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
905 unsigned char *playback_buffer; /* suitably aligned address */
906 unsigned char *capture_buffer; /* suitably aligned address */
908 pid_t capture_pid; /* process id which uses capture */
909 pid_t playback_pid; /* process id which uses capture */
910 int running; /* running status */
912 int last_external_sample_rate; /* samplerate mystic ... */
913 int last_internal_sample_rate;
914 int system_sample_rate;
916 int dev; /* Hardware vars... */
919 void __iomem *iobase;
921 int irq_count; /* for debug */
924 struct snd_card *card; /* one card */
925 struct snd_pcm *pcm; /* has one pcm */
926 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
927 struct pci_dev *pci; /* and an pci info */
930 /* fast alsa mixer */
931 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
932 /* but input to much, so not used */
933 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
934 /* full mixer accessible over mixer ioctl or hwdep-device */
935 struct hdspm_mixer *mixer;
937 struct hdspm_tco *tco; /* NULL if no TCO detected */
939 char **texts_autosync;
940 int texts_autosync_items;
942 cycles_t last_interrupt;
946 struct hdspm_peak_rms peak_rms;
950 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
952 .vendor = PCI_VENDOR_ID_XILINX,
953 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
954 .subvendor = PCI_ANY_ID,
955 .subdevice = PCI_ANY_ID,
962 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
965 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
966 struct hdspm * hdspm);
967 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
968 struct hdspm * hdspm);
970 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
971 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
972 static int hdspm_autosync_ref(struct hdspm *hdspm);
973 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
974 static int hdspm_system_clock_mode(struct hdspm *hdspm);
975 static void hdspm_set_sgbuf(struct hdspm *hdspm,
976 struct snd_pcm_substream *substream,
977 unsigned int reg, int channels);
979 static inline int HDSPM_bit2freq(int n)
981 static const int bit2freq_tab[] = {
982 0, 32000, 44100, 48000, 64000, 88200,
983 96000, 128000, 176400, 192000 };
986 return bit2freq_tab[n];
989 /* Write/read to/from HDSPM with Adresses in Bytes
990 not words but only 32Bit writes are allowed */
992 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
995 writel(val, hdspm->iobase + reg);
998 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1000 return readl(hdspm->iobase + reg);
1003 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1004 mixer is write only on hardware so we have to cache him for read
1005 each fader is a u32, but uses only the first 16 bit */
1007 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1010 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1013 return hdspm->mixer->ch[chan].in[in];
1016 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1019 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1021 return hdspm->mixer->ch[chan].pb[pb];
1024 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1025 unsigned int in, unsigned short data)
1027 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1031 HDSPM_MADI_mixerBase +
1032 ((in + 128 * chan) * sizeof(u32)),
1033 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1037 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1038 unsigned int pb, unsigned short data)
1040 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1044 HDSPM_MADI_mixerBase +
1045 ((64 + pb + 128 * chan) * sizeof(u32)),
1046 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1051 /* enable DMA for specific channels, now available for DSP-MADI */
1052 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1054 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1057 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1059 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1062 /* check if same process is writing and reading */
1063 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1065 unsigned long flags;
1068 spin_lock_irqsave(&hdspm->lock, flags);
1069 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1070 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1073 spin_unlock_irqrestore(&hdspm->lock, flags);
1077 /* check for external sample rate */
1078 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1080 unsigned int status, status2, timecode;
1081 int syncref, rate = 0, rate_bits;
1083 switch (hdspm->io_type) {
1085 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1086 status = hdspm_read(hdspm, HDSPM_statusRegister);
1087 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1089 syncref = hdspm_autosync_ref(hdspm);
1091 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1092 status & HDSPM_AES32_wcLock)
1093 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1095 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1096 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1097 status2 & (HDSPM_LockAES >>
1098 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1099 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1104 status = hdspm_read(hdspm, HDSPM_statusRegister);
1106 if (!(status & HDSPM_madiLock)) {
1107 rate = 0; /* no lock */
1109 switch (status & (HDSPM_status1_freqMask)) {
1110 case HDSPM_status1_F_0*1:
1111 rate = 32000; break;
1112 case HDSPM_status1_F_0*2:
1113 rate = 44100; break;
1114 case HDSPM_status1_F_0*3:
1115 rate = 48000; break;
1116 case HDSPM_status1_F_0*4:
1117 rate = 64000; break;
1118 case HDSPM_status1_F_0*5:
1119 rate = 88200; break;
1120 case HDSPM_status1_F_0*6:
1121 rate = 96000; break;
1122 case HDSPM_status1_F_0*7:
1123 rate = 128000; break;
1124 case HDSPM_status1_F_0*8:
1125 rate = 176400; break;
1126 case HDSPM_status1_F_0*9:
1127 rate = 192000; break;
1138 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1139 status = hdspm_read(hdspm, HDSPM_statusRegister);
1142 /* if wordclock has synced freq and wordclock is valid */
1143 if ((status2 & HDSPM_wcLock) != 0 &&
1144 (status2 & HDSPM_SelSyncRef0) == 0) {
1146 rate_bits = status2 & HDSPM_wcFreqMask;
1149 switch (rate_bits) {
1150 case HDSPM_wcFreq32:
1153 case HDSPM_wcFreq44_1:
1156 case HDSPM_wcFreq48:
1159 case HDSPM_wcFreq64:
1162 case HDSPM_wcFreq88_2:
1165 case HDSPM_wcFreq96:
1174 /* if rate detected and Syncref is Word than have it,
1175 * word has priority to MADI
1178 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1181 /* maybe a madi input (which is taken if sel sync is madi) */
1182 if (status & HDSPM_madiLock) {
1183 rate_bits = status & HDSPM_madiFreqMask;
1185 switch (rate_bits) {
1186 case HDSPM_madiFreq32:
1189 case HDSPM_madiFreq44_1:
1192 case HDSPM_madiFreq48:
1195 case HDSPM_madiFreq64:
1198 case HDSPM_madiFreq88_2:
1201 case HDSPM_madiFreq96:
1204 case HDSPM_madiFreq128:
1207 case HDSPM_madiFreq176_4:
1210 case HDSPM_madiFreq192:
1218 /* QS and DS rates normally can not be detected
1219 * automatically by the card. Only exception is MADI
1220 * in 96k frame mode.
1222 * So if we read SS values (32 .. 48k), check for
1223 * user-provided DS/QS bits in the control register
1224 * and multiply the base frequency accordingly.
1226 if (rate <= 48000) {
1227 if (hdspm->control_register & HDSPM_QuadSpeed)
1229 else if (hdspm->control_register &
1240 /* return latency in samples per period */
1241 static int hdspm_get_latency(struct hdspm *hdspm)
1245 n = hdspm_decode_latency(hdspm->control_register);
1247 /* Special case for new RME cards with 32 samples period size.
1248 * The three latency bits in the control register
1249 * (HDSP_LatencyMask) encode latency values of 64 samples as
1250 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1251 * denotes 8192 samples, but on new cards like RayDAT or AIO,
1252 * it corresponds to 32 samples.
1254 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1257 return 1 << (n + 6);
1260 /* Latency function */
1261 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1263 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1267 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1271 position = hdspm_read(hdspm, HDSPM_statusRegister);
1273 switch (hdspm->io_type) {
1276 position &= HDSPM_BufferPositionMask;
1277 position /= 4; /* Bytes per sample */
1280 position = (position & HDSPM_BufferID) ?
1281 (hdspm->period_bytes / 4) : 0;
1288 static inline void hdspm_start_audio(struct hdspm * s)
1290 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1291 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1294 static inline void hdspm_stop_audio(struct hdspm * s)
1296 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1297 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1300 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1301 static void hdspm_silence_playback(struct hdspm *hdspm)
1304 int n = hdspm->period_bytes;
1305 void *buf = hdspm->playback_buffer;
1310 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1312 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1316 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1320 spin_lock_irq(&s->lock);
1323 /* Special case for new RME cards like RayDAT/AIO which
1324 * support period sizes of 32 samples. Since latency is
1325 * encoded in the three bits of HDSP_LatencyMask, we can only
1326 * have values from 0 .. 7. While 0 still means 64 samples and
1327 * 6 represents 4096 samples on all cards, 7 represents 8192
1328 * on older cards and 32 samples on new cards.
1330 * In other words, period size in samples is calculated by
1331 * 2^(n+6) with n ranging from 0 .. 7.
1343 s->control_register &= ~HDSPM_LatencyMask;
1344 s->control_register |= hdspm_encode_latency(n);
1346 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1348 hdspm_compute_period_size(s);
1350 spin_unlock_irq(&s->lock);
1355 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1362 switch (hdspm->io_type) {
1365 freq_const = 110069313433624ULL;
1369 freq_const = 104857600000000ULL;
1372 freq_const = 131072000000000ULL;
1379 return div_u64(freq_const, period);
1383 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1389 else if (rate >= 56000)
1392 switch (hdspm->io_type) {
1394 n = 131072000000000ULL; /* 125 MHz */
1398 n = 110069313433624ULL; /* 105 MHz */
1402 n = 104857600000000ULL; /* 100 MHz */
1409 n = div_u64(n, rate);
1410 /* n should be less than 2^32 for being written to FREQ register */
1411 snd_BUG_ON(n >> 32);
1412 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1415 /* dummy set rate lets see what happens */
1416 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1421 int current_speed, target_speed;
1423 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1424 it (e.g. during module initialization).
1427 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1430 if (called_internally) {
1432 /* request from ctl or card initialization
1433 just make a warning an remember setting
1434 for future master mode switching */
1436 snd_printk(KERN_WARNING "HDSPM: "
1437 "Warning: device is not running "
1438 "as a clock master.\n");
1442 /* hw_param request while in AutoSync mode */
1444 hdspm_external_sample_rate(hdspm);
1446 if (hdspm_autosync_ref(hdspm) ==
1447 HDSPM_AUTOSYNC_FROM_NONE) {
1449 snd_printk(KERN_WARNING "HDSPM: "
1450 "Detected no Externel Sync \n");
1453 } else if (rate != external_freq) {
1455 snd_printk(KERN_WARNING "HDSPM: "
1456 "Warning: No AutoSync source for "
1457 "requested rate\n");
1463 current_rate = hdspm->system_sample_rate;
1465 /* Changing between Singe, Double and Quad speed is not
1466 allowed if any substreams are open. This is because such a change
1467 causes a shift in the location of the DMA buffers and a reduction
1468 in the number of available buffers.
1470 Note that a similar but essentially insoluble problem exists for
1471 externally-driven rate changes. All we can do is to flag rate
1472 changes in the read/write routines.
1475 if (current_rate <= 48000)
1476 current_speed = HDSPM_SPEED_SINGLE;
1477 else if (current_rate <= 96000)
1478 current_speed = HDSPM_SPEED_DOUBLE;
1480 current_speed = HDSPM_SPEED_QUAD;
1483 target_speed = HDSPM_SPEED_SINGLE;
1484 else if (rate <= 96000)
1485 target_speed = HDSPM_SPEED_DOUBLE;
1487 target_speed = HDSPM_SPEED_QUAD;
1491 rate_bits = HDSPM_Frequency32KHz;
1494 rate_bits = HDSPM_Frequency44_1KHz;
1497 rate_bits = HDSPM_Frequency48KHz;
1500 rate_bits = HDSPM_Frequency64KHz;
1503 rate_bits = HDSPM_Frequency88_2KHz;
1506 rate_bits = HDSPM_Frequency96KHz;
1509 rate_bits = HDSPM_Frequency128KHz;
1512 rate_bits = HDSPM_Frequency176_4KHz;
1515 rate_bits = HDSPM_Frequency192KHz;
1521 if (current_speed != target_speed
1522 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1525 "cannot change from %s speed to %s speed mode "
1526 "(capture PID = %d, playback PID = %d)\n",
1527 hdspm_speed_names[current_speed],
1528 hdspm_speed_names[target_speed],
1529 hdspm->capture_pid, hdspm->playback_pid);
1533 hdspm->control_register &= ~HDSPM_FrequencyMask;
1534 hdspm->control_register |= rate_bits;
1535 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1537 /* For AES32, need to set DDS value in FREQ register
1538 For MADI, also apparently */
1539 hdspm_set_dds_value(hdspm, rate);
1541 if (AES32 == hdspm->io_type && rate != current_rate)
1542 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1544 hdspm->system_sample_rate = rate;
1546 if (rate <= 48000) {
1547 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1548 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1549 hdspm->max_channels_in = hdspm->ss_in_channels;
1550 hdspm->max_channels_out = hdspm->ss_out_channels;
1551 hdspm->port_names_in = hdspm->port_names_in_ss;
1552 hdspm->port_names_out = hdspm->port_names_out_ss;
1553 } else if (rate <= 96000) {
1554 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1555 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1556 hdspm->max_channels_in = hdspm->ds_in_channels;
1557 hdspm->max_channels_out = hdspm->ds_out_channels;
1558 hdspm->port_names_in = hdspm->port_names_in_ds;
1559 hdspm->port_names_out = hdspm->port_names_out_ds;
1561 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1562 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1563 hdspm->max_channels_in = hdspm->qs_in_channels;
1564 hdspm->max_channels_out = hdspm->qs_out_channels;
1565 hdspm->port_names_in = hdspm->port_names_in_qs;
1566 hdspm->port_names_out = hdspm->port_names_out_qs;
1575 /* mainly for init to 0 on load */
1576 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1581 if (sgain > UNITY_GAIN)
1588 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1589 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1590 hdspm_write_in_gain(hdspm, i, j, gain);
1591 hdspm_write_pb_gain(hdspm, i, j, gain);
1595 /*----------------------------------------------------------------------------
1597 ----------------------------------------------------------------------------*/
1599 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1602 /* the hardware already does the relevant bit-mask with 0xff */
1603 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1606 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1609 /* the hardware already does the relevant bit-mask with 0xff */
1610 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1613 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1615 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1618 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1620 int fifo_bytes_used;
1622 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1624 if (fifo_bytes_used < 128)
1625 return 128 - fifo_bytes_used;
1630 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1632 while (snd_hdspm_midi_input_available (hdspm, id))
1633 snd_hdspm_midi_read_byte (hdspm, id);
1636 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1638 unsigned long flags;
1642 unsigned char buf[128];
1644 /* Output is not interrupt driven */
1646 spin_lock_irqsave (&hmidi->lock, flags);
1647 if (hmidi->output &&
1648 !snd_rawmidi_transmit_empty (hmidi->output)) {
1649 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1651 if (n_pending > 0) {
1652 if (n_pending > (int)sizeof (buf))
1653 n_pending = sizeof (buf);
1655 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1658 for (i = 0; i < to_write; ++i)
1659 snd_hdspm_midi_write_byte (hmidi->hdspm,
1665 spin_unlock_irqrestore (&hmidi->lock, flags);
1669 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1671 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1674 unsigned long flags;
1678 spin_lock_irqsave (&hmidi->lock, flags);
1679 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1680 if (n_pending > 0) {
1682 if (n_pending > (int)sizeof (buf))
1683 n_pending = sizeof (buf);
1684 for (i = 0; i < n_pending; ++i)
1685 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1688 snd_rawmidi_receive (hmidi->input, buf,
1691 /* flush the MIDI input FIFO */
1693 snd_hdspm_midi_read_byte (hmidi->hdspm,
1698 spin_unlock_irqrestore(&hmidi->lock, flags);
1700 spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1701 hmidi->hdspm->control_register |= hmidi->ie;
1702 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1703 hmidi->hdspm->control_register);
1704 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1706 return snd_hdspm_midi_output_write (hmidi);
1710 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1712 struct hdspm *hdspm;
1713 struct hdspm_midi *hmidi;
1714 unsigned long flags;
1716 hmidi = substream->rmidi->private_data;
1717 hdspm = hmidi->hdspm;
1719 spin_lock_irqsave (&hdspm->lock, flags);
1721 if (!(hdspm->control_register & hmidi->ie)) {
1722 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1723 hdspm->control_register |= hmidi->ie;
1726 hdspm->control_register &= ~hmidi->ie;
1729 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1730 spin_unlock_irqrestore (&hdspm->lock, flags);
1733 static void snd_hdspm_midi_output_timer(unsigned long data)
1735 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1736 unsigned long flags;
1738 snd_hdspm_midi_output_write(hmidi);
1739 spin_lock_irqsave (&hmidi->lock, flags);
1741 /* this does not bump hmidi->istimer, because the
1742 kernel automatically removed the timer when it
1743 expired, and we are now adding it back, thus
1744 leaving istimer wherever it was set before.
1747 if (hmidi->istimer) {
1748 hmidi->timer.expires = 1 + jiffies;
1749 add_timer(&hmidi->timer);
1752 spin_unlock_irqrestore (&hmidi->lock, flags);
1756 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1758 struct hdspm_midi *hmidi;
1759 unsigned long flags;
1761 hmidi = substream->rmidi->private_data;
1762 spin_lock_irqsave (&hmidi->lock, flags);
1764 if (!hmidi->istimer) {
1765 init_timer(&hmidi->timer);
1766 hmidi->timer.function = snd_hdspm_midi_output_timer;
1767 hmidi->timer.data = (unsigned long) hmidi;
1768 hmidi->timer.expires = 1 + jiffies;
1769 add_timer(&hmidi->timer);
1773 if (hmidi->istimer && --hmidi->istimer <= 0)
1774 del_timer (&hmidi->timer);
1776 spin_unlock_irqrestore (&hmidi->lock, flags);
1778 snd_hdspm_midi_output_write(hmidi);
1781 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1783 struct hdspm_midi *hmidi;
1785 hmidi = substream->rmidi->private_data;
1786 spin_lock_irq (&hmidi->lock);
1787 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1788 hmidi->input = substream;
1789 spin_unlock_irq (&hmidi->lock);
1794 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1796 struct hdspm_midi *hmidi;
1798 hmidi = substream->rmidi->private_data;
1799 spin_lock_irq (&hmidi->lock);
1800 hmidi->output = substream;
1801 spin_unlock_irq (&hmidi->lock);
1806 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1808 struct hdspm_midi *hmidi;
1810 snd_hdspm_midi_input_trigger (substream, 0);
1812 hmidi = substream->rmidi->private_data;
1813 spin_lock_irq (&hmidi->lock);
1814 hmidi->input = NULL;
1815 spin_unlock_irq (&hmidi->lock);
1820 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1822 struct hdspm_midi *hmidi;
1824 snd_hdspm_midi_output_trigger (substream, 0);
1826 hmidi = substream->rmidi->private_data;
1827 spin_lock_irq (&hmidi->lock);
1828 hmidi->output = NULL;
1829 spin_unlock_irq (&hmidi->lock);
1834 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1836 .open = snd_hdspm_midi_output_open,
1837 .close = snd_hdspm_midi_output_close,
1838 .trigger = snd_hdspm_midi_output_trigger,
1841 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1843 .open = snd_hdspm_midi_input_open,
1844 .close = snd_hdspm_midi_input_close,
1845 .trigger = snd_hdspm_midi_input_trigger,
1848 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1849 struct hdspm *hdspm, int id)
1854 hdspm->midi[id].id = id;
1855 hdspm->midi[id].hdspm = hdspm;
1856 spin_lock_init (&hdspm->midi[id].lock);
1859 if (MADIface == hdspm->io_type) {
1860 /* MIDI-over-MADI on HDSPe MADIface */
1861 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1862 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1863 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1864 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1865 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1866 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1868 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1869 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1870 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1871 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1872 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1873 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1875 } else if (1 == id) {
1876 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1877 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1878 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1879 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1880 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1881 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1882 } else if ((2 == id) && (MADI == hdspm->io_type)) {
1883 /* MIDI-over-MADI on HDSPe MADI */
1884 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1885 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1886 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1887 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1888 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1889 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1890 } else if (2 == id) {
1891 /* TCO MTC, read only */
1892 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1893 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1894 hdspm->midi[2].dataOut = -1;
1895 hdspm->midi[2].statusOut = -1;
1896 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1897 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1898 } else if (3 == id) {
1899 /* TCO MTC on HDSPe MADI */
1900 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1901 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1902 hdspm->midi[3].dataOut = -1;
1903 hdspm->midi[3].statusOut = -1;
1904 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1905 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1908 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1909 (MADIface == hdspm->io_type)))) {
1910 if ((id == 0) && (MADIface == hdspm->io_type)) {
1911 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1912 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1913 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1915 sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1917 err = snd_rawmidi_new(card, buf, id, 1, 1,
1918 &hdspm->midi[id].rmidi);
1922 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1924 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1926 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1927 SNDRV_RAWMIDI_STREAM_OUTPUT,
1928 &snd_hdspm_midi_output);
1929 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1930 SNDRV_RAWMIDI_STREAM_INPUT,
1931 &snd_hdspm_midi_input);
1933 hdspm->midi[id].rmidi->info_flags |=
1934 SNDRV_RAWMIDI_INFO_OUTPUT |
1935 SNDRV_RAWMIDI_INFO_INPUT |
1936 SNDRV_RAWMIDI_INFO_DUPLEX;
1938 /* TCO MTC, read only */
1939 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1940 err = snd_rawmidi_new(card, buf, id, 1, 1,
1941 &hdspm->midi[id].rmidi);
1945 sprintf(hdspm->midi[id].rmidi->name,
1946 "%s MTC %d", card->id, id+1);
1947 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1949 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1950 SNDRV_RAWMIDI_STREAM_INPUT,
1951 &snd_hdspm_midi_input);
1953 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1960 static void hdspm_midi_tasklet(unsigned long arg)
1962 struct hdspm *hdspm = (struct hdspm *)arg;
1965 while (i < hdspm->midiPorts) {
1966 if (hdspm->midi[i].pending)
1967 snd_hdspm_midi_input_read(&hdspm->midi[i]);
1974 /*-----------------------------------------------------------------------------
1976 ----------------------------------------------------------------------------*/
1978 /* get the system sample rate which is set */
1982 * Calculate the real sample rate from the
1983 * current DDS value.
1985 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1987 unsigned int period, rate;
1989 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1990 rate = hdspm_calc_dds_value(hdspm, period);
1992 if (rate > 207000) {
1993 /* Unreasonable high sample rate as seen on PCI MADI cards. */
1994 if (0 == hdspm_system_clock_mode(hdspm)) {
1995 /* master mode, return internal sample rate */
1996 rate = hdspm->system_sample_rate;
1998 /* slave mode, return external sample rate */
1999 rate = hdspm_external_sample_rate(hdspm);
2007 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2008 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2011 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2012 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2013 .info = snd_hdspm_info_system_sample_rate, \
2014 .put = snd_hdspm_put_system_sample_rate, \
2015 .get = snd_hdspm_get_system_sample_rate \
2018 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2019 struct snd_ctl_elem_info *uinfo)
2021 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2023 uinfo->value.integer.min = 27000;
2024 uinfo->value.integer.max = 207000;
2025 uinfo->value.integer.step = 1;
2030 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2031 struct snd_ctl_elem_value *
2034 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2036 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2040 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2041 struct snd_ctl_elem_value *
2044 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2046 hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2052 * Returns the WordClock sample rate class for the given card.
2054 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2058 switch (hdspm->io_type) {
2061 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2062 return (status >> 16) & 0xF;
2074 * Returns the TCO sample rate class for the given card.
2076 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2081 switch (hdspm->io_type) {
2084 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2085 return (status >> 20) & 0xF;
2097 * Returns the SYNC_IN sample rate class for the given card.
2099 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2104 switch (hdspm->io_type) {
2107 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2108 return (status >> 12) & 0xF;
2120 * Returns the sample rate class for input source <idx> for
2121 * 'new style' cards like the AIO and RayDAT.
2123 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2125 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2127 return (status >> (idx*4)) & 0xF;
2132 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2133 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2135 .private_value = xindex, \
2136 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2137 .info = snd_hdspm_info_autosync_sample_rate, \
2138 .get = snd_hdspm_get_autosync_sample_rate \
2142 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2143 struct snd_ctl_elem_info *uinfo)
2145 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2147 uinfo->value.enumerated.items = 10;
2149 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2150 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2151 strcpy(uinfo->value.enumerated.name,
2152 texts_freq[uinfo->value.enumerated.item]);
2157 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2158 struct snd_ctl_elem_value *
2161 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2163 switch (hdspm->io_type) {
2165 switch (kcontrol->private_value) {
2167 ucontrol->value.enumerated.item[0] =
2168 hdspm_get_wc_sample_rate(hdspm);
2171 ucontrol->value.enumerated.item[0] =
2172 hdspm_get_tco_sample_rate(hdspm);
2175 ucontrol->value.enumerated.item[0] =
2176 hdspm_get_sync_in_sample_rate(hdspm);
2179 ucontrol->value.enumerated.item[0] =
2180 hdspm_get_s1_sample_rate(hdspm,
2181 kcontrol->private_value-1);
2186 switch (kcontrol->private_value) {
2188 ucontrol->value.enumerated.item[0] =
2189 hdspm_get_wc_sample_rate(hdspm);
2192 ucontrol->value.enumerated.item[0] =
2193 hdspm_get_tco_sample_rate(hdspm);
2195 case 5: /* SYNC_IN */
2196 ucontrol->value.enumerated.item[0] =
2197 hdspm_get_sync_in_sample_rate(hdspm);
2200 ucontrol->value.enumerated.item[0] =
2201 hdspm_get_s1_sample_rate(hdspm,
2202 ucontrol->id.index-1);
2208 switch (kcontrol->private_value) {
2210 ucontrol->value.enumerated.item[0] =
2211 hdspm_get_wc_sample_rate(hdspm);
2214 ucontrol->value.enumerated.item[0] =
2215 hdspm_get_tco_sample_rate(hdspm);
2217 case 10: /* SYNC_IN */
2218 ucontrol->value.enumerated.item[0] =
2219 hdspm_get_sync_in_sample_rate(hdspm);
2221 default: /* AES1 to AES8 */
2222 ucontrol->value.enumerated.item[0] =
2223 hdspm_get_s1_sample_rate(hdspm,
2224 kcontrol->private_value-1);
2232 int rate = hdspm_external_sample_rate(hdspm);
2233 int i, selected_rate = 0;
2234 for (i = 1; i < 10; i++)
2235 if (HDSPM_bit2freq(i) == rate) {
2239 ucontrol->value.enumerated.item[0] = selected_rate;
2251 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2252 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2255 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2256 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2257 .info = snd_hdspm_info_system_clock_mode, \
2258 .get = snd_hdspm_get_system_clock_mode, \
2259 .put = snd_hdspm_put_system_clock_mode, \
2264 * Returns the system clock mode for the given card.
2265 * @returns 0 - master, 1 - slave
2267 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2269 switch (hdspm->io_type) {
2272 if (hdspm->settings_register & HDSPM_c0Master)
2277 if (hdspm->control_register & HDSPM_ClockModeMaster)
2286 * Sets the system clock mode.
2287 * @param mode 0 - master, 1 - slave
2289 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2291 switch (hdspm->io_type) {
2295 hdspm->settings_register |= HDSPM_c0Master;
2297 hdspm->settings_register &= ~HDSPM_c0Master;
2299 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2304 hdspm->control_register |= HDSPM_ClockModeMaster;
2306 hdspm->control_register &= ~HDSPM_ClockModeMaster;
2308 hdspm_write(hdspm, HDSPM_controlRegister,
2309 hdspm->control_register);
2314 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2315 struct snd_ctl_elem_info *uinfo)
2317 static char *texts[] = { "Master", "AutoSync" };
2319 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2321 uinfo->value.enumerated.items = 2;
2322 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2323 uinfo->value.enumerated.item =
2324 uinfo->value.enumerated.items - 1;
2325 strcpy(uinfo->value.enumerated.name,
2326 texts[uinfo->value.enumerated.item]);
2330 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2331 struct snd_ctl_elem_value *ucontrol)
2333 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2335 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2339 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2340 struct snd_ctl_elem_value *ucontrol)
2342 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2345 if (!snd_hdspm_use_is_exclusive(hdspm))
2348 val = ucontrol->value.enumerated.item[0];
2354 hdspm_set_system_clock_mode(hdspm, val);
2360 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2361 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2364 .info = snd_hdspm_info_clock_source, \
2365 .get = snd_hdspm_get_clock_source, \
2366 .put = snd_hdspm_put_clock_source \
2370 static int hdspm_clock_source(struct hdspm * hdspm)
2372 switch (hdspm->system_sample_rate) {
2373 case 32000: return 0;
2374 case 44100: return 1;
2375 case 48000: return 2;
2376 case 64000: return 3;
2377 case 88200: return 4;
2378 case 96000: return 5;
2379 case 128000: return 6;
2380 case 176400: return 7;
2381 case 192000: return 8;
2387 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2392 rate = 32000; break;
2394 rate = 44100; break;
2396 rate = 48000; break;
2398 rate = 64000; break;
2400 rate = 88200; break;
2402 rate = 96000; break;
2404 rate = 128000; break;
2406 rate = 176400; break;
2408 rate = 192000; break;
2412 hdspm_set_rate(hdspm, rate, 1);
2416 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2417 struct snd_ctl_elem_info *uinfo)
2419 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2421 uinfo->value.enumerated.items = 9;
2423 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2424 uinfo->value.enumerated.item =
2425 uinfo->value.enumerated.items - 1;
2427 strcpy(uinfo->value.enumerated.name,
2428 texts_freq[uinfo->value.enumerated.item+1]);
2433 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2434 struct snd_ctl_elem_value *ucontrol)
2436 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2438 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2442 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2443 struct snd_ctl_elem_value *ucontrol)
2445 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2449 if (!snd_hdspm_use_is_exclusive(hdspm))
2451 val = ucontrol->value.enumerated.item[0];
2456 spin_lock_irq(&hdspm->lock);
2457 if (val != hdspm_clock_source(hdspm))
2458 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2461 spin_unlock_irq(&hdspm->lock);
2466 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2467 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2470 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2471 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2472 .info = snd_hdspm_info_pref_sync_ref, \
2473 .get = snd_hdspm_get_pref_sync_ref, \
2474 .put = snd_hdspm_put_pref_sync_ref \
2479 * Returns the current preferred sync reference setting.
2480 * The semantics of the return value are depending on the
2481 * card, please see the comments for clarification.
2483 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2485 switch (hdspm->io_type) {
2487 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2488 case 0: return 0; /* WC */
2489 case HDSPM_SyncRef0: return 1; /* AES 1 */
2490 case HDSPM_SyncRef1: return 2; /* AES 2 */
2491 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2492 case HDSPM_SyncRef2: return 4; /* AES 4 */
2493 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2494 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2495 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2496 return 7; /* AES 7 */
2497 case HDSPM_SyncRef3: return 8; /* AES 8 */
2498 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2505 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2506 case 0: return 0; /* WC */
2507 case HDSPM_SyncRef0: return 1; /* MADI */
2508 case HDSPM_SyncRef1: return 2; /* TCO */
2509 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2510 return 3; /* SYNC_IN */
2513 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2514 case 0: return 0; /* WC */
2515 case HDSPM_SyncRef0: return 1; /* MADI */
2516 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2517 return 2; /* SYNC_IN */
2524 switch ((hdspm->settings_register &
2525 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2526 case 0: return 0; /* WC */
2527 case 3: return 1; /* ADAT 1 */
2528 case 4: return 2; /* ADAT 2 */
2529 case 5: return 3; /* ADAT 3 */
2530 case 6: return 4; /* ADAT 4 */
2531 case 1: return 5; /* AES */
2532 case 2: return 6; /* SPDIF */
2533 case 9: return 7; /* TCO */
2534 case 10: return 8; /* SYNC_IN */
2537 switch ((hdspm->settings_register &
2538 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2539 case 0: return 0; /* WC */
2540 case 3: return 1; /* ADAT 1 */
2541 case 4: return 2; /* ADAT 2 */
2542 case 5: return 3; /* ADAT 3 */
2543 case 6: return 4; /* ADAT 4 */
2544 case 1: return 5; /* AES */
2545 case 2: return 6; /* SPDIF */
2546 case 10: return 7; /* SYNC_IN */
2554 switch ((hdspm->settings_register &
2555 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2556 case 0: return 0; /* WC */
2557 case 3: return 1; /* ADAT */
2558 case 1: return 2; /* AES */
2559 case 2: return 3; /* SPDIF */
2560 case 9: return 4; /* TCO */
2561 case 10: return 5; /* SYNC_IN */
2564 switch ((hdspm->settings_register &
2565 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2566 case 0: return 0; /* WC */
2567 case 3: return 1; /* ADAT */
2568 case 1: return 2; /* AES */
2569 case 2: return 3; /* SPDIF */
2570 case 10: return 4; /* SYNC_IN */
2582 * Set the preferred sync reference to <pref>. The semantics
2583 * of <pref> are depending on the card type, see the comments
2584 * for clarification.
2586 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2590 switch (hdspm->io_type) {
2592 hdspm->control_register &= ~HDSPM_SyncRefMask;
2597 hdspm->control_register |= HDSPM_SyncRef0;
2600 hdspm->control_register |= HDSPM_SyncRef1;
2603 hdspm->control_register |=
2604 HDSPM_SyncRef1+HDSPM_SyncRef0;
2607 hdspm->control_register |= HDSPM_SyncRef2;
2610 hdspm->control_register |=
2611 HDSPM_SyncRef2+HDSPM_SyncRef0;
2614 hdspm->control_register |=
2615 HDSPM_SyncRef2+HDSPM_SyncRef1;
2618 hdspm->control_register |=
2619 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2622 hdspm->control_register |= HDSPM_SyncRef3;
2625 hdspm->control_register |=
2626 HDSPM_SyncRef3+HDSPM_SyncRef0;
2636 hdspm->control_register &= ~HDSPM_SyncRefMask;
2642 hdspm->control_register |= HDSPM_SyncRef0;
2645 hdspm->control_register |= HDSPM_SyncRef1;
2647 case 3: /* SYNC_IN */
2648 hdspm->control_register |=
2649 HDSPM_SyncRef0+HDSPM_SyncRef1;
2659 hdspm->control_register |= HDSPM_SyncRef0;
2661 case 2: /* SYNC_IN */
2662 hdspm->control_register |=
2663 HDSPM_SyncRef0+HDSPM_SyncRef1;
2675 case 0: p = 0; break; /* WC */
2676 case 1: p = 3; break; /* ADAT 1 */
2677 case 2: p = 4; break; /* ADAT 2 */
2678 case 3: p = 5; break; /* ADAT 3 */
2679 case 4: p = 6; break; /* ADAT 4 */
2680 case 5: p = 1; break; /* AES */
2681 case 6: p = 2; break; /* SPDIF */
2682 case 7: p = 9; break; /* TCO */
2683 case 8: p = 10; break; /* SYNC_IN */
2688 case 0: p = 0; break; /* WC */
2689 case 1: p = 3; break; /* ADAT 1 */
2690 case 2: p = 4; break; /* ADAT 2 */
2691 case 3: p = 5; break; /* ADAT 3 */
2692 case 4: p = 6; break; /* ADAT 4 */
2693 case 5: p = 1; break; /* AES */
2694 case 6: p = 2; break; /* SPDIF */
2695 case 7: p = 10; break; /* SYNC_IN */
2704 case 0: p = 0; break; /* WC */
2705 case 1: p = 3; break; /* ADAT */
2706 case 2: p = 1; break; /* AES */
2707 case 3: p = 2; break; /* SPDIF */
2708 case 4: p = 9; break; /* TCO */
2709 case 5: p = 10; break; /* SYNC_IN */
2714 case 0: p = 0; break; /* WC */
2715 case 1: p = 3; break; /* ADAT */
2716 case 2: p = 1; break; /* AES */
2717 case 3: p = 2; break; /* SPDIF */
2718 case 4: p = 10; break; /* SYNC_IN */
2725 switch (hdspm->io_type) {
2728 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2729 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2730 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2736 hdspm_write(hdspm, HDSPM_controlRegister,
2737 hdspm->control_register);
2744 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2745 struct snd_ctl_elem_info *uinfo)
2747 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2749 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2751 uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2753 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2754 uinfo->value.enumerated.item =
2755 uinfo->value.enumerated.items - 1;
2757 strcpy(uinfo->value.enumerated.name,
2758 hdspm->texts_autosync[uinfo->value.enumerated.item]);
2763 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2764 struct snd_ctl_elem_value *ucontrol)
2766 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2767 int psf = hdspm_pref_sync_ref(hdspm);
2770 ucontrol->value.enumerated.item[0] = psf;
2777 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2778 struct snd_ctl_elem_value *ucontrol)
2780 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2781 int val, change = 0;
2783 if (!snd_hdspm_use_is_exclusive(hdspm))
2786 val = ucontrol->value.enumerated.item[0];
2790 else if (val >= hdspm->texts_autosync_items)
2791 val = hdspm->texts_autosync_items-1;
2793 spin_lock_irq(&hdspm->lock);
2794 if (val != hdspm_pref_sync_ref(hdspm))
2795 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2797 spin_unlock_irq(&hdspm->lock);
2802 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2803 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2806 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2807 .info = snd_hdspm_info_autosync_ref, \
2808 .get = snd_hdspm_get_autosync_ref, \
2811 static int hdspm_autosync_ref(struct hdspm *hdspm)
2813 if (AES32 == hdspm->io_type) {
2814 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2815 unsigned int syncref =
2816 (status >> HDSPM_AES32_syncref_bit) & 0xF;
2818 return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2821 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2822 } else if (MADI == hdspm->io_type) {
2823 /* This looks at the autosync selected sync reference */
2824 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2826 switch (status2 & HDSPM_SelSyncRefMask) {
2827 case HDSPM_SelSyncRef_WORD:
2828 return HDSPM_AUTOSYNC_FROM_WORD;
2829 case HDSPM_SelSyncRef_MADI:
2830 return HDSPM_AUTOSYNC_FROM_MADI;
2831 case HDSPM_SelSyncRef_TCO:
2832 return HDSPM_AUTOSYNC_FROM_TCO;
2833 case HDSPM_SelSyncRef_SyncIn:
2834 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2835 case HDSPM_SelSyncRef_NVALID:
2836 return HDSPM_AUTOSYNC_FROM_NONE;
2846 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2847 struct snd_ctl_elem_info *uinfo)
2849 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2851 if (AES32 == hdspm->io_type) {
2852 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2853 "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2855 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2857 uinfo->value.enumerated.items = 10;
2858 if (uinfo->value.enumerated.item >=
2859 uinfo->value.enumerated.items)
2860 uinfo->value.enumerated.item =
2861 uinfo->value.enumerated.items - 1;
2862 strcpy(uinfo->value.enumerated.name,
2863 texts[uinfo->value.enumerated.item]);
2864 } else if (MADI == hdspm->io_type) {
2865 static char *texts[] = {"Word Clock", "MADI", "TCO",
2866 "Sync In", "None" };
2868 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2870 uinfo->value.enumerated.items = 5;
2871 if (uinfo->value.enumerated.item >=
2872 uinfo->value.enumerated.items)
2873 uinfo->value.enumerated.item =
2874 uinfo->value.enumerated.items - 1;
2875 strcpy(uinfo->value.enumerated.name,
2876 texts[uinfo->value.enumerated.item]);
2881 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2882 struct snd_ctl_elem_value *ucontrol)
2884 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2886 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2891 #define HDSPM_LINE_OUT(xname, xindex) \
2892 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2895 .info = snd_hdspm_info_line_out, \
2896 .get = snd_hdspm_get_line_out, \
2897 .put = snd_hdspm_put_line_out \
2900 static int hdspm_line_out(struct hdspm * hdspm)
2902 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2906 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2909 hdspm->control_register |= HDSPM_LineOut;
2911 hdspm->control_register &= ~HDSPM_LineOut;
2912 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2917 #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info
2919 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2920 struct snd_ctl_elem_value *ucontrol)
2922 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2924 spin_lock_irq(&hdspm->lock);
2925 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2926 spin_unlock_irq(&hdspm->lock);
2930 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2931 struct snd_ctl_elem_value *ucontrol)
2933 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2937 if (!snd_hdspm_use_is_exclusive(hdspm))
2939 val = ucontrol->value.integer.value[0] & 1;
2940 spin_lock_irq(&hdspm->lock);
2941 change = (int) val != hdspm_line_out(hdspm);
2942 hdspm_set_line_output(hdspm, val);
2943 spin_unlock_irq(&hdspm->lock);
2948 #define HDSPM_TX_64(xname, xindex) \
2949 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2952 .info = snd_hdspm_info_tx_64, \
2953 .get = snd_hdspm_get_tx_64, \
2954 .put = snd_hdspm_put_tx_64 \
2957 static int hdspm_tx_64(struct hdspm * hdspm)
2959 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2962 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2965 hdspm->control_register |= HDSPM_TX_64ch;
2967 hdspm->control_register &= ~HDSPM_TX_64ch;
2968 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2973 #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info
2975 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2976 struct snd_ctl_elem_value *ucontrol)
2978 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2980 spin_lock_irq(&hdspm->lock);
2981 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2982 spin_unlock_irq(&hdspm->lock);
2986 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2987 struct snd_ctl_elem_value *ucontrol)
2989 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2993 if (!snd_hdspm_use_is_exclusive(hdspm))
2995 val = ucontrol->value.integer.value[0] & 1;
2996 spin_lock_irq(&hdspm->lock);
2997 change = (int) val != hdspm_tx_64(hdspm);
2998 hdspm_set_tx_64(hdspm, val);
2999 spin_unlock_irq(&hdspm->lock);
3004 #define HDSPM_C_TMS(xname, xindex) \
3005 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3008 .info = snd_hdspm_info_c_tms, \
3009 .get = snd_hdspm_get_c_tms, \
3010 .put = snd_hdspm_put_c_tms \
3013 static int hdspm_c_tms(struct hdspm * hdspm)
3015 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
3018 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
3021 hdspm->control_register |= HDSPM_clr_tms;
3023 hdspm->control_register &= ~HDSPM_clr_tms;
3024 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3029 #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info
3031 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
3032 struct snd_ctl_elem_value *ucontrol)
3034 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3036 spin_lock_irq(&hdspm->lock);
3037 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
3038 spin_unlock_irq(&hdspm->lock);
3042 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
3043 struct snd_ctl_elem_value *ucontrol)
3045 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3049 if (!snd_hdspm_use_is_exclusive(hdspm))
3051 val = ucontrol->value.integer.value[0] & 1;
3052 spin_lock_irq(&hdspm->lock);
3053 change = (int) val != hdspm_c_tms(hdspm);
3054 hdspm_set_c_tms(hdspm, val);
3055 spin_unlock_irq(&hdspm->lock);
3060 #define HDSPM_SAFE_MODE(xname, xindex) \
3061 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3064 .info = snd_hdspm_info_safe_mode, \
3065 .get = snd_hdspm_get_safe_mode, \
3066 .put = snd_hdspm_put_safe_mode \
3069 static int hdspm_safe_mode(struct hdspm * hdspm)
3071 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
3074 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
3077 hdspm->control_register |= HDSPM_AutoInp;
3079 hdspm->control_register &= ~HDSPM_AutoInp;
3080 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3085 #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info
3087 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
3088 struct snd_ctl_elem_value *ucontrol)
3090 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3092 spin_lock_irq(&hdspm->lock);
3093 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
3094 spin_unlock_irq(&hdspm->lock);
3098 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
3099 struct snd_ctl_elem_value *ucontrol)
3101 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3105 if (!snd_hdspm_use_is_exclusive(hdspm))
3107 val = ucontrol->value.integer.value[0] & 1;
3108 spin_lock_irq(&hdspm->lock);
3109 change = (int) val != hdspm_safe_mode(hdspm);
3110 hdspm_set_safe_mode(hdspm, val);
3111 spin_unlock_irq(&hdspm->lock);
3116 #define HDSPM_EMPHASIS(xname, xindex) \
3117 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3120 .info = snd_hdspm_info_emphasis, \
3121 .get = snd_hdspm_get_emphasis, \
3122 .put = snd_hdspm_put_emphasis \
3125 static int hdspm_emphasis(struct hdspm * hdspm)
3127 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3130 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3133 hdspm->control_register |= HDSPM_Emphasis;
3135 hdspm->control_register &= ~HDSPM_Emphasis;
3136 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3141 #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info
3143 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3144 struct snd_ctl_elem_value *ucontrol)
3146 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3148 spin_lock_irq(&hdspm->lock);
3149 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3150 spin_unlock_irq(&hdspm->lock);
3154 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3155 struct snd_ctl_elem_value *ucontrol)
3157 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3161 if (!snd_hdspm_use_is_exclusive(hdspm))
3163 val = ucontrol->value.integer.value[0] & 1;
3164 spin_lock_irq(&hdspm->lock);
3165 change = (int) val != hdspm_emphasis(hdspm);
3166 hdspm_set_emphasis(hdspm, val);
3167 spin_unlock_irq(&hdspm->lock);
3172 #define HDSPM_DOLBY(xname, xindex) \
3173 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3176 .info = snd_hdspm_info_dolby, \
3177 .get = snd_hdspm_get_dolby, \
3178 .put = snd_hdspm_put_dolby \
3181 static int hdspm_dolby(struct hdspm * hdspm)
3183 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3186 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3189 hdspm->control_register |= HDSPM_Dolby;
3191 hdspm->control_register &= ~HDSPM_Dolby;
3192 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3197 #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info
3199 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3200 struct snd_ctl_elem_value *ucontrol)
3202 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3204 spin_lock_irq(&hdspm->lock);
3205 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3206 spin_unlock_irq(&hdspm->lock);
3210 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3211 struct snd_ctl_elem_value *ucontrol)
3213 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3217 if (!snd_hdspm_use_is_exclusive(hdspm))
3219 val = ucontrol->value.integer.value[0] & 1;
3220 spin_lock_irq(&hdspm->lock);
3221 change = (int) val != hdspm_dolby(hdspm);
3222 hdspm_set_dolby(hdspm, val);
3223 spin_unlock_irq(&hdspm->lock);
3228 #define HDSPM_PROFESSIONAL(xname, xindex) \
3229 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3232 .info = snd_hdspm_info_professional, \
3233 .get = snd_hdspm_get_professional, \
3234 .put = snd_hdspm_put_professional \
3237 static int hdspm_professional(struct hdspm * hdspm)
3239 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3242 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3245 hdspm->control_register |= HDSPM_Professional;
3247 hdspm->control_register &= ~HDSPM_Professional;
3248 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3253 #define snd_hdspm_info_professional snd_ctl_boolean_mono_info
3255 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3256 struct snd_ctl_elem_value *ucontrol)
3258 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3260 spin_lock_irq(&hdspm->lock);
3261 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3262 spin_unlock_irq(&hdspm->lock);
3266 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3267 struct snd_ctl_elem_value *ucontrol)
3269 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3273 if (!snd_hdspm_use_is_exclusive(hdspm))
3275 val = ucontrol->value.integer.value[0] & 1;
3276 spin_lock_irq(&hdspm->lock);
3277 change = (int) val != hdspm_professional(hdspm);
3278 hdspm_set_professional(hdspm, val);
3279 spin_unlock_irq(&hdspm->lock);
3283 #define HDSPM_INPUT_SELECT(xname, xindex) \
3284 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3287 .info = snd_hdspm_info_input_select, \
3288 .get = snd_hdspm_get_input_select, \
3289 .put = snd_hdspm_put_input_select \
3292 static int hdspm_input_select(struct hdspm * hdspm)
3294 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3297 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3300 hdspm->control_register |= HDSPM_InputSelect0;
3302 hdspm->control_register &= ~HDSPM_InputSelect0;
3303 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3308 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3309 struct snd_ctl_elem_info *uinfo)
3311 static char *texts[] = { "optical", "coaxial" };
3313 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3315 uinfo->value.enumerated.items = 2;
3317 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3318 uinfo->value.enumerated.item =
3319 uinfo->value.enumerated.items - 1;
3320 strcpy(uinfo->value.enumerated.name,
3321 texts[uinfo->value.enumerated.item]);
3326 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3327 struct snd_ctl_elem_value *ucontrol)
3329 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3331 spin_lock_irq(&hdspm->lock);
3332 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3333 spin_unlock_irq(&hdspm->lock);
3337 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3338 struct snd_ctl_elem_value *ucontrol)
3340 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3344 if (!snd_hdspm_use_is_exclusive(hdspm))
3346 val = ucontrol->value.integer.value[0] & 1;
3347 spin_lock_irq(&hdspm->lock);
3348 change = (int) val != hdspm_input_select(hdspm);
3349 hdspm_set_input_select(hdspm, val);
3350 spin_unlock_irq(&hdspm->lock);
3355 #define HDSPM_DS_WIRE(xname, xindex) \
3356 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3359 .info = snd_hdspm_info_ds_wire, \
3360 .get = snd_hdspm_get_ds_wire, \
3361 .put = snd_hdspm_put_ds_wire \
3364 static int hdspm_ds_wire(struct hdspm * hdspm)
3366 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3369 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3372 hdspm->control_register |= HDSPM_DS_DoubleWire;
3374 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3375 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3380 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3381 struct snd_ctl_elem_info *uinfo)
3383 static char *texts[] = { "Single", "Double" };
3385 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3387 uinfo->value.enumerated.items = 2;
3389 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3390 uinfo->value.enumerated.item =
3391 uinfo->value.enumerated.items - 1;
3392 strcpy(uinfo->value.enumerated.name,
3393 texts[uinfo->value.enumerated.item]);
3398 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3399 struct snd_ctl_elem_value *ucontrol)
3401 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3403 spin_lock_irq(&hdspm->lock);
3404 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3405 spin_unlock_irq(&hdspm->lock);
3409 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3410 struct snd_ctl_elem_value *ucontrol)
3412 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3416 if (!snd_hdspm_use_is_exclusive(hdspm))
3418 val = ucontrol->value.integer.value[0] & 1;
3419 spin_lock_irq(&hdspm->lock);
3420 change = (int) val != hdspm_ds_wire(hdspm);
3421 hdspm_set_ds_wire(hdspm, val);
3422 spin_unlock_irq(&hdspm->lock);
3427 #define HDSPM_QS_WIRE(xname, xindex) \
3428 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3431 .info = snd_hdspm_info_qs_wire, \
3432 .get = snd_hdspm_get_qs_wire, \
3433 .put = snd_hdspm_put_qs_wire \
3436 static int hdspm_qs_wire(struct hdspm * hdspm)
3438 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3440 if (hdspm->control_register & HDSPM_QS_QuadWire)
3445 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3447 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3452 hdspm->control_register |= HDSPM_QS_DoubleWire;
3455 hdspm->control_register |= HDSPM_QS_QuadWire;
3458 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3463 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3464 struct snd_ctl_elem_info *uinfo)
3466 static char *texts[] = { "Single", "Double", "Quad" };
3468 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3470 uinfo->value.enumerated.items = 3;
3472 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3473 uinfo->value.enumerated.item =
3474 uinfo->value.enumerated.items - 1;
3475 strcpy(uinfo->value.enumerated.name,
3476 texts[uinfo->value.enumerated.item]);
3481 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3482 struct snd_ctl_elem_value *ucontrol)
3484 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3486 spin_lock_irq(&hdspm->lock);
3487 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3488 spin_unlock_irq(&hdspm->lock);
3492 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3493 struct snd_ctl_elem_value *ucontrol)
3495 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3499 if (!snd_hdspm_use_is_exclusive(hdspm))
3501 val = ucontrol->value.integer.value[0];
3506 spin_lock_irq(&hdspm->lock);
3507 change = val != hdspm_qs_wire(hdspm);
3508 hdspm_set_qs_wire(hdspm, val);
3509 spin_unlock_irq(&hdspm->lock);
3513 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3514 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3517 .info = snd_hdspm_info_madi_speedmode, \
3518 .get = snd_hdspm_get_madi_speedmode, \
3519 .put = snd_hdspm_put_madi_speedmode \
3522 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3524 if (hdspm->control_register & HDSPM_QuadSpeed)
3526 if (hdspm->control_register & HDSPM_DoubleSpeed)
3531 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3533 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3538 hdspm->control_register |= HDSPM_DoubleSpeed;
3541 hdspm->control_register |= HDSPM_QuadSpeed;
3544 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3549 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3550 struct snd_ctl_elem_info *uinfo)
3552 static char *texts[] = { "Single", "Double", "Quad" };
3554 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3556 uinfo->value.enumerated.items = 3;
3558 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3559 uinfo->value.enumerated.item =
3560 uinfo->value.enumerated.items - 1;
3561 strcpy(uinfo->value.enumerated.name,
3562 texts[uinfo->value.enumerated.item]);
3567 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3568 struct snd_ctl_elem_value *ucontrol)
3570 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3572 spin_lock_irq(&hdspm->lock);
3573 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3574 spin_unlock_irq(&hdspm->lock);
3578 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3579 struct snd_ctl_elem_value *ucontrol)
3581 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3585 if (!snd_hdspm_use_is_exclusive(hdspm))
3587 val = ucontrol->value.integer.value[0];
3592 spin_lock_irq(&hdspm->lock);
3593 change = val != hdspm_madi_speedmode(hdspm);
3594 hdspm_set_madi_speedmode(hdspm, val);
3595 spin_unlock_irq(&hdspm->lock);
3599 #define HDSPM_MIXER(xname, xindex) \
3600 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3604 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3605 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3606 .info = snd_hdspm_info_mixer, \
3607 .get = snd_hdspm_get_mixer, \
3608 .put = snd_hdspm_put_mixer \
3611 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3612 struct snd_ctl_elem_info *uinfo)
3614 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3616 uinfo->value.integer.min = 0;
3617 uinfo->value.integer.max = 65535;
3618 uinfo->value.integer.step = 1;
3622 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3623 struct snd_ctl_elem_value *ucontrol)
3625 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3629 source = ucontrol->value.integer.value[0];
3632 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3633 source = 2 * HDSPM_MAX_CHANNELS - 1;
3635 destination = ucontrol->value.integer.value[1];
3636 if (destination < 0)
3638 else if (destination >= HDSPM_MAX_CHANNELS)
3639 destination = HDSPM_MAX_CHANNELS - 1;
3641 spin_lock_irq(&hdspm->lock);
3642 if (source >= HDSPM_MAX_CHANNELS)
3643 ucontrol->value.integer.value[2] =
3644 hdspm_read_pb_gain(hdspm, destination,
3645 source - HDSPM_MAX_CHANNELS);
3647 ucontrol->value.integer.value[2] =
3648 hdspm_read_in_gain(hdspm, destination, source);
3650 spin_unlock_irq(&hdspm->lock);
3655 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3656 struct snd_ctl_elem_value *ucontrol)
3658 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3664 if (!snd_hdspm_use_is_exclusive(hdspm))
3667 source = ucontrol->value.integer.value[0];
3668 destination = ucontrol->value.integer.value[1];
3670 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3672 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3675 gain = ucontrol->value.integer.value[2];
3677 spin_lock_irq(&hdspm->lock);
3679 if (source >= HDSPM_MAX_CHANNELS)
3680 change = gain != hdspm_read_pb_gain(hdspm, destination,
3682 HDSPM_MAX_CHANNELS);
3684 change = gain != hdspm_read_in_gain(hdspm, destination,
3688 if (source >= HDSPM_MAX_CHANNELS)
3689 hdspm_write_pb_gain(hdspm, destination,
3690 source - HDSPM_MAX_CHANNELS,
3693 hdspm_write_in_gain(hdspm, destination, source,
3696 spin_unlock_irq(&hdspm->lock);
3701 /* The simple mixer control(s) provide gain control for the
3702 basic 1:1 mappings of playback streams to output
3706 #define HDSPM_PLAYBACK_MIXER \
3707 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3708 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3709 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3710 .info = snd_hdspm_info_playback_mixer, \
3711 .get = snd_hdspm_get_playback_mixer, \
3712 .put = snd_hdspm_put_playback_mixer \
3715 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3716 struct snd_ctl_elem_info *uinfo)
3718 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3720 uinfo->value.integer.min = 0;
3721 uinfo->value.integer.max = 64;
3722 uinfo->value.integer.step = 1;
3726 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3727 struct snd_ctl_elem_value *ucontrol)
3729 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3732 channel = ucontrol->id.index - 1;
3734 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3737 spin_lock_irq(&hdspm->lock);
3738 ucontrol->value.integer.value[0] =
3739 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3740 spin_unlock_irq(&hdspm->lock);
3745 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3746 struct snd_ctl_elem_value *ucontrol)
3748 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3753 if (!snd_hdspm_use_is_exclusive(hdspm))
3756 channel = ucontrol->id.index - 1;
3758 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3761 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3763 spin_lock_irq(&hdspm->lock);
3765 gain != hdspm_read_pb_gain(hdspm, channel,
3768 hdspm_write_pb_gain(hdspm, channel, channel,
3770 spin_unlock_irq(&hdspm->lock);
3774 #define HDSPM_SYNC_CHECK(xname, xindex) \
3775 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3777 .private_value = xindex, \
3778 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3779 .info = snd_hdspm_info_sync_check, \
3780 .get = snd_hdspm_get_sync_check \
3784 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3785 struct snd_ctl_elem_info *uinfo)
3787 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3788 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3790 uinfo->value.enumerated.items = 4;
3791 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3792 uinfo->value.enumerated.item =
3793 uinfo->value.enumerated.items - 1;
3794 strcpy(uinfo->value.enumerated.name,
3795 texts[uinfo->value.enumerated.item]);
3799 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3801 int status, status2;
3803 switch (hdspm->io_type) {
3805 status = hdspm_read(hdspm, HDSPM_statusRegister);
3806 if (status & HDSPM_wcSync)
3808 else if (status & HDSPM_wcLock)
3814 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3815 if (status2 & HDSPM_wcLock) {
3816 if (status2 & HDSPM_wcSync)
3826 status = hdspm_read(hdspm, HDSPM_statusRegister);
3828 if (status & 0x2000000)
3830 else if (status & 0x1000000)
3845 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3847 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3848 if (status & HDSPM_madiLock) {
3849 if (status & HDSPM_madiSync)
3858 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3860 int status, lock, sync;
3862 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3864 lock = (status & (0x1<<idx)) ? 1 : 0;
3865 sync = (status & (0x100<<idx)) ? 1 : 0;
3875 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3877 int status, lock = 0, sync = 0;
3879 switch (hdspm->io_type) {
3882 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3883 lock = (status & 0x400) ? 1 : 0;
3884 sync = (status & 0x800) ? 1 : 0;
3888 status = hdspm_read(hdspm, HDSPM_statusRegister);
3889 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3890 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3894 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3895 lock = (status & 0x100000) ? 1 : 0;
3896 sync = (status & 0x200000) ? 1 : 0;
3911 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3913 int status2, lock, sync;
3914 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3916 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3917 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3927 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3932 switch (hdspm->io_type) {
3935 status = hdspm_read(hdspm, HDSPM_statusRegister);
3936 if (status & HDSPM_tcoLock) {
3937 if (status & HDSPM_tcoSync)
3948 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3950 if (status & 0x8000000)
3951 return 2; /* Sync */
3952 if (status & 0x4000000)
3953 return 1; /* Lock */
3954 return 0; /* No signal */
3966 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3967 struct snd_ctl_elem_value *ucontrol)
3969 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3972 switch (hdspm->io_type) {
3974 switch (kcontrol->private_value) {
3976 val = hdspm_wc_sync_check(hdspm); break;
3978 val = hdspm_tco_sync_check(hdspm); break;
3979 case 8: /* SYNC IN */
3980 val = hdspm_sync_in_sync_check(hdspm); break;
3982 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3987 switch (kcontrol->private_value) {
3989 val = hdspm_wc_sync_check(hdspm); break;
3991 val = hdspm_tco_sync_check(hdspm); break;
3992 case 5: /* SYNC IN */
3993 val = hdspm_sync_in_sync_check(hdspm); break;
3995 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
4000 switch (kcontrol->private_value) {
4002 val = hdspm_wc_sync_check(hdspm); break;
4004 val = hdspm_madi_sync_check(hdspm); break;
4006 val = hdspm_tco_sync_check(hdspm); break;
4007 case 3: /* SYNC_IN */
4008 val = hdspm_sync_in_sync_check(hdspm); break;
4013 val = hdspm_madi_sync_check(hdspm); /* MADI */
4017 switch (kcontrol->private_value) {
4019 val = hdspm_wc_sync_check(hdspm); break;
4021 val = hdspm_tco_sync_check(hdspm); break;
4022 case 10 /* SYNC IN */:
4023 val = hdspm_sync_in_sync_check(hdspm); break;
4024 default: /* AES1 to AES8 */
4025 val = hdspm_aes_sync_check(hdspm,
4026 kcontrol->private_value-1);
4035 ucontrol->value.enumerated.item[0] = val;
4044 static void hdspm_tco_write(struct hdspm *hdspm)
4046 unsigned int tc[4] = { 0, 0, 0, 0};
4048 switch (hdspm->tco->input) {
4050 tc[2] |= HDSPM_TCO2_set_input_MSB;
4053 tc[2] |= HDSPM_TCO2_set_input_LSB;
4059 switch (hdspm->tco->framerate) {
4061 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4064 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4067 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4068 HDSPM_TCO1_set_drop_frame_flag;
4071 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4072 HDSPM_TCO1_LTC_Format_MSB;
4075 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4076 HDSPM_TCO1_LTC_Format_MSB +
4077 HDSPM_TCO1_set_drop_frame_flag;
4083 switch (hdspm->tco->wordclock) {
4085 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4088 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4094 switch (hdspm->tco->samplerate) {
4096 tc[2] |= HDSPM_TCO2_set_freq;
4099 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4105 switch (hdspm->tco->pull) {
4107 tc[2] |= HDSPM_TCO2_set_pull_up;
4110 tc[2] |= HDSPM_TCO2_set_pull_down;
4113 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4116 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4122 if (1 == hdspm->tco->term) {
4123 tc[2] |= HDSPM_TCO2_set_term_75R;
4126 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4127 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4128 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4129 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4133 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4134 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4137 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4138 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4139 .info = snd_hdspm_info_tco_sample_rate, \
4140 .get = snd_hdspm_get_tco_sample_rate, \
4141 .put = snd_hdspm_put_tco_sample_rate \
4144 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4145 struct snd_ctl_elem_info *uinfo)
4147 static char *texts[] = { "44.1 kHz", "48 kHz" };
4148 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4150 uinfo->value.enumerated.items = 2;
4152 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4153 uinfo->value.enumerated.item =
4154 uinfo->value.enumerated.items - 1;
4156 strcpy(uinfo->value.enumerated.name,
4157 texts[uinfo->value.enumerated.item]);
4162 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4163 struct snd_ctl_elem_value *ucontrol)
4165 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4167 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4172 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4173 struct snd_ctl_elem_value *ucontrol)
4175 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4177 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4178 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4180 hdspm_tco_write(hdspm);
4189 #define HDSPM_TCO_PULL(xname, xindex) \
4190 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4193 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4194 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4195 .info = snd_hdspm_info_tco_pull, \
4196 .get = snd_hdspm_get_tco_pull, \
4197 .put = snd_hdspm_put_tco_pull \
4200 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4201 struct snd_ctl_elem_info *uinfo)
4203 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4204 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4206 uinfo->value.enumerated.items = 5;
4208 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4209 uinfo->value.enumerated.item =
4210 uinfo->value.enumerated.items - 1;
4212 strcpy(uinfo->value.enumerated.name,
4213 texts[uinfo->value.enumerated.item]);
4218 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4219 struct snd_ctl_elem_value *ucontrol)
4221 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4223 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4228 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4229 struct snd_ctl_elem_value *ucontrol)
4231 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4233 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4234 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4236 hdspm_tco_write(hdspm);
4244 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4245 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4248 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4249 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4250 .info = snd_hdspm_info_tco_wck_conversion, \
4251 .get = snd_hdspm_get_tco_wck_conversion, \
4252 .put = snd_hdspm_put_tco_wck_conversion \
4255 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4256 struct snd_ctl_elem_info *uinfo)
4258 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4259 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4261 uinfo->value.enumerated.items = 3;
4263 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4264 uinfo->value.enumerated.item =
4265 uinfo->value.enumerated.items - 1;
4267 strcpy(uinfo->value.enumerated.name,
4268 texts[uinfo->value.enumerated.item]);
4273 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4274 struct snd_ctl_elem_value *ucontrol)
4276 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4278 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4283 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4284 struct snd_ctl_elem_value *ucontrol)
4286 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4288 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4289 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4291 hdspm_tco_write(hdspm);
4300 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4301 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4304 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4305 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4306 .info = snd_hdspm_info_tco_frame_rate, \
4307 .get = snd_hdspm_get_tco_frame_rate, \
4308 .put = snd_hdspm_put_tco_frame_rate \
4311 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4312 struct snd_ctl_elem_info *uinfo)
4314 static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4315 "29.97 dfps", "30 fps", "30 dfps" };
4316 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4318 uinfo->value.enumerated.items = 6;
4320 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4321 uinfo->value.enumerated.item =
4322 uinfo->value.enumerated.items - 1;
4324 strcpy(uinfo->value.enumerated.name,
4325 texts[uinfo->value.enumerated.item]);
4330 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4331 struct snd_ctl_elem_value *ucontrol)
4333 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4335 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4340 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4341 struct snd_ctl_elem_value *ucontrol)
4343 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4345 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4346 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4348 hdspm_tco_write(hdspm);
4357 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4358 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4361 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4362 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4363 .info = snd_hdspm_info_tco_sync_source, \
4364 .get = snd_hdspm_get_tco_sync_source, \
4365 .put = snd_hdspm_put_tco_sync_source \
4368 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4369 struct snd_ctl_elem_info *uinfo)
4371 static char *texts[] = { "LTC", "Video", "WCK" };
4372 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4374 uinfo->value.enumerated.items = 3;
4376 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4377 uinfo->value.enumerated.item =
4378 uinfo->value.enumerated.items - 1;
4380 strcpy(uinfo->value.enumerated.name,
4381 texts[uinfo->value.enumerated.item]);
4386 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4387 struct snd_ctl_elem_value *ucontrol)
4389 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4391 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4396 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4397 struct snd_ctl_elem_value *ucontrol)
4399 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4401 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4402 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4404 hdspm_tco_write(hdspm);
4413 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4414 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4417 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4418 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4419 .info = snd_hdspm_info_tco_word_term, \
4420 .get = snd_hdspm_get_tco_word_term, \
4421 .put = snd_hdspm_put_tco_word_term \
4424 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4425 struct snd_ctl_elem_info *uinfo)
4427 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4429 uinfo->value.integer.min = 0;
4430 uinfo->value.integer.max = 1;
4436 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4437 struct snd_ctl_elem_value *ucontrol)
4439 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4441 ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4447 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4448 struct snd_ctl_elem_value *ucontrol)
4450 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4452 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4453 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4455 hdspm_tco_write(hdspm);
4466 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4467 HDSPM_MIXER("Mixer", 0),
4468 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4469 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4470 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4471 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4472 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4473 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4474 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4475 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4476 HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4477 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4478 HDSPM_LINE_OUT("Line Out", 0),
4479 HDSPM_TX_64("TX 64 channels mode", 0),
4480 HDSPM_C_TMS("Clear Track Marker", 0),
4481 HDSPM_SAFE_MODE("Safe Mode", 0),
4482 HDSPM_INPUT_SELECT("Input Select", 0),
4483 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4487 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4488 HDSPM_MIXER("Mixer", 0),
4489 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4490 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4491 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4492 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4493 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4494 HDSPM_TX_64("TX 64 channels mode", 0),
4495 HDSPM_C_TMS("Clear Track Marker", 0),
4496 HDSPM_SAFE_MODE("Safe Mode", 0),
4497 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4500 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4501 HDSPM_MIXER("Mixer", 0),
4502 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4503 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4504 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4505 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4506 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4507 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4508 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4509 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4510 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4511 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4512 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4513 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4514 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4515 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4516 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4517 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4518 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4519 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4522 HDSPM_INPUT_SELECT("Input Select", 0),
4523 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4524 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4525 HDSPM_SPDIF_IN("SPDIF In", 0);
4526 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4527 HDSPM_INPUT_LEVEL("Input Level", 0);
4528 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4529 HDSPM_PHONES("Phones", 0);
4533 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4534 HDSPM_MIXER("Mixer", 0),
4535 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4536 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4537 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4538 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4539 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4540 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4541 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4542 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4543 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4544 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4545 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4546 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4547 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4548 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4549 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4550 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4551 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4552 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4553 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4554 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4555 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4556 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4559 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4560 HDSPM_MIXER("Mixer", 0),
4561 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4562 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4563 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4564 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4565 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4566 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4567 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4568 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4569 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4570 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4571 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4572 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4573 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4574 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4575 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4576 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4577 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4578 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4579 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4580 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4581 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4582 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4583 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4584 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4585 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4586 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4587 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4588 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4589 HDSPM_LINE_OUT("Line Out", 0),
4590 HDSPM_EMPHASIS("Emphasis", 0),
4591 HDSPM_DOLBY("Non Audio", 0),
4592 HDSPM_PROFESSIONAL("Professional", 0),
4593 HDSPM_C_TMS("Clear Track Marker", 0),
4594 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4595 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4600 /* Control elements for the optional TCO module */
4601 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4602 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4603 HDSPM_TCO_PULL("TCO Pull", 0),
4604 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4605 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4606 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4607 HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4611 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4614 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4618 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4619 if (hdspm->system_sample_rate > 48000) {
4620 hdspm->playback_mixer_ctls[i]->vd[0].access =
4621 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4622 SNDRV_CTL_ELEM_ACCESS_READ |
4623 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4625 hdspm->playback_mixer_ctls[i]->vd[0].access =
4626 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4627 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4629 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4630 SNDRV_CTL_EVENT_MASK_INFO,
4631 &hdspm->playback_mixer_ctls[i]->id);
4638 static int snd_hdspm_create_controls(struct snd_card *card,
4639 struct hdspm *hdspm)
4641 unsigned int idx, limit;
4643 struct snd_kcontrol *kctl;
4644 struct snd_kcontrol_new *list = NULL;
4646 switch (hdspm->io_type) {
4648 list = snd_hdspm_controls_madi;
4649 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4652 list = snd_hdspm_controls_madiface;
4653 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4656 list = snd_hdspm_controls_aio;
4657 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4660 list = snd_hdspm_controls_raydat;
4661 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4664 list = snd_hdspm_controls_aes32;
4665 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4670 for (idx = 0; idx < limit; idx++) {
4671 err = snd_ctl_add(card,
4672 snd_ctl_new1(&list[idx], hdspm));
4679 /* create simple 1:1 playback mixer controls */
4680 snd_hdspm_playback_mixer.name = "Chn";
4681 if (hdspm->system_sample_rate >= 128000) {
4682 limit = hdspm->qs_out_channels;
4683 } else if (hdspm->system_sample_rate >= 64000) {
4684 limit = hdspm->ds_out_channels;
4686 limit = hdspm->ss_out_channels;
4688 for (idx = 0; idx < limit; ++idx) {
4689 snd_hdspm_playback_mixer.index = idx + 1;
4690 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4691 err = snd_ctl_add(card, kctl);
4694 hdspm->playback_mixer_ctls[idx] = kctl;
4699 /* add tco control elements */
4700 list = snd_hdspm_controls_tco;
4701 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4702 for (idx = 0; idx < limit; idx++) {
4703 err = snd_ctl_add(card,
4704 snd_ctl_new1(&list[idx], hdspm));
4713 /*------------------------------------------------------------
4715 ------------------------------------------------------------*/
4718 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4719 struct snd_info_buffer *buffer)
4721 struct hdspm *hdspm = entry->private_data;
4722 unsigned int status, status2, control, freq;
4724 char *pref_sync_ref;
4726 char *system_clock_mode;
4731 int a, ltc, frames, seconds, minutes, hours;
4732 unsigned int period;
4736 status = hdspm_read(hdspm, HDSPM_statusRegister);
4737 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4738 control = hdspm->control_register;
4739 freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4741 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4742 hdspm->card_name, hdspm->card->number + 1,
4743 hdspm->firmware_rev,
4744 (status2 & HDSPM_version0) |
4745 (status2 & HDSPM_version1) | (status2 &
4748 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4749 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4752 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4753 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4755 snd_iprintf(buffer, "--- System ---\n");
4758 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4759 status & HDSPM_audioIRQPending,
4760 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4761 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4764 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4765 "estimated= %ld (bytes)\n",
4766 ((status & HDSPM_BufferID) ? 1 : 0),
4767 (status & HDSPM_BufferPositionMask),
4768 (status & HDSPM_BufferPositionMask) %
4769 (2 * (int)hdspm->period_bytes),
4770 ((status & HDSPM_BufferPositionMask) - 64) %
4771 (2 * (int)hdspm->period_bytes),
4772 (long) hdspm_hw_pointer(hdspm) * 4);
4775 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4776 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4777 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4778 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4779 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4781 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4782 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4783 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4785 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4787 hdspm->control_register, hdspm->control2_register,
4789 if (status & HDSPM_tco_detect) {
4790 snd_iprintf(buffer, "TCO module detected.\n");
4791 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4792 if (a & HDSPM_TCO1_LTC_Input_valid) {
4793 snd_iprintf(buffer, " LTC valid, ");
4794 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4795 HDSPM_TCO1_LTC_Format_MSB)) {
4797 snd_iprintf(buffer, "24 fps, ");
4799 case HDSPM_TCO1_LTC_Format_LSB:
4800 snd_iprintf(buffer, "25 fps, ");
4802 case HDSPM_TCO1_LTC_Format_MSB:
4803 snd_iprintf(buffer, "29.97 fps, ");
4806 snd_iprintf(buffer, "30 fps, ");
4809 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4810 snd_iprintf(buffer, "drop frame\n");
4812 snd_iprintf(buffer, "full frame\n");
4815 snd_iprintf(buffer, " no LTC\n");
4817 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4818 snd_iprintf(buffer, " Video: NTSC\n");
4819 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4820 snd_iprintf(buffer, " Video: PAL\n");
4822 snd_iprintf(buffer, " No video\n");
4824 if (a & HDSPM_TCO1_TCO_lock) {
4825 snd_iprintf(buffer, " Sync: lock\n");
4827 snd_iprintf(buffer, " Sync: no lock\n");
4830 switch (hdspm->io_type) {
4833 freq_const = 110069313433624ULL;
4837 freq_const = 104857600000000ULL;
4840 break; /* no TCO possible */
4843 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4844 snd_iprintf(buffer, " period: %u\n", period);
4847 /* rate = freq_const/period; */
4848 rate = div_u64(freq_const, period);
4850 if (control & HDSPM_QuadSpeed) {
4852 } else if (control & HDSPM_DoubleSpeed) {
4856 snd_iprintf(buffer, " Frequency: %u Hz\n",
4857 (unsigned int) rate);
4859 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4862 frames += (ltc & 0x3) * 10;
4864 seconds = ltc & 0xF;
4866 seconds += (ltc & 0x7) * 10;
4868 minutes = ltc & 0xF;
4870 minutes += (ltc & 0x7) * 10;
4874 hours += (ltc & 0x3) * 10;
4876 " LTC In: %02d:%02d:%02d:%02d\n",
4877 hours, minutes, seconds, frames);
4880 snd_iprintf(buffer, "No TCO module detected.\n");
4883 snd_iprintf(buffer, "--- Settings ---\n");
4885 x = hdspm_get_latency(hdspm);
4888 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4889 x, (unsigned long) hdspm->period_bytes);
4891 snd_iprintf(buffer, "Line out: %s\n",
4892 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4894 switch (hdspm->control_register & HDSPM_InputMask) {
4895 case HDSPM_InputOptical:
4898 case HDSPM_InputCoaxial:
4906 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4908 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4909 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4910 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4913 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4914 system_clock_mode = "AutoSync";
4916 system_clock_mode = "Master";
4917 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4919 switch (hdspm_pref_sync_ref(hdspm)) {
4920 case HDSPM_SYNC_FROM_WORD:
4921 pref_sync_ref = "Word Clock";
4923 case HDSPM_SYNC_FROM_MADI:
4924 pref_sync_ref = "MADI Sync";
4926 case HDSPM_SYNC_FROM_TCO:
4927 pref_sync_ref = "TCO";
4929 case HDSPM_SYNC_FROM_SYNC_IN:
4930 pref_sync_ref = "Sync In";
4933 pref_sync_ref = "XXXX Clock";
4936 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4939 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4940 hdspm->system_sample_rate);
4943 snd_iprintf(buffer, "--- Status:\n");
4945 x = status & HDSPM_madiSync;
4946 x2 = status2 & HDSPM_wcSync;
4948 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4949 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4951 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4954 switch (hdspm_autosync_ref(hdspm)) {
4955 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4956 autosync_ref = "Sync In";
4958 case HDSPM_AUTOSYNC_FROM_TCO:
4959 autosync_ref = "TCO";
4961 case HDSPM_AUTOSYNC_FROM_WORD:
4962 autosync_ref = "Word Clock";
4964 case HDSPM_AUTOSYNC_FROM_MADI:
4965 autosync_ref = "MADI Sync";
4967 case HDSPM_AUTOSYNC_FROM_NONE:
4968 autosync_ref = "Input not valid";
4971 autosync_ref = "---";
4975 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4976 autosync_ref, hdspm_external_sample_rate(hdspm),
4977 (status & HDSPM_madiFreqMask) >> 22,
4978 (status2 & HDSPM_wcFreqMask) >> 5);
4980 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4981 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4982 (status & HDSPM_RX_64ch) ? "64 channels" :
4985 snd_iprintf(buffer, "\n");
4989 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4990 struct snd_info_buffer *buffer)
4992 struct hdspm *hdspm = entry->private_data;
4993 unsigned int status;
4994 unsigned int status2;
4995 unsigned int timecode;
5000 status = hdspm_read(hdspm, HDSPM_statusRegister);
5001 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5002 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
5004 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
5005 hdspm->card_name, hdspm->card->number + 1,
5006 hdspm->firmware_rev);
5008 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
5009 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5011 snd_iprintf(buffer, "--- System ---\n");
5014 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
5015 status & HDSPM_audioIRQPending,
5016 (status & HDSPM_midi0IRQPending) ? 1 : 0,
5017 (status & HDSPM_midi1IRQPending) ? 1 : 0,
5020 "HW pointer: id = %d, rawptr = %d (%d->%d) "
5021 "estimated= %ld (bytes)\n",
5022 ((status & HDSPM_BufferID) ? 1 : 0),
5023 (status & HDSPM_BufferPositionMask),
5024 (status & HDSPM_BufferPositionMask) %
5025 (2 * (int)hdspm->period_bytes),
5026 ((status & HDSPM_BufferPositionMask) - 64) %
5027 (2 * (int)hdspm->period_bytes),
5028 (long) hdspm_hw_pointer(hdspm) * 4);
5031 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5032 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5033 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5034 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5035 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5037 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5038 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5039 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5041 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5043 hdspm->control_register, hdspm->control2_register,
5046 snd_iprintf(buffer, "--- Settings ---\n");
5048 x = hdspm_get_latency(hdspm);
5051 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5052 x, (unsigned long) hdspm->period_bytes);
5054 snd_iprintf(buffer, "Line out: %s\n",
5056 control_register & HDSPM_LineOut) ? "on " : "off");
5059 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5061 control_register & HDSPM_clr_tms) ? "on" : "off",
5063 control_register & HDSPM_Emphasis) ? "on" : "off",
5065 control_register & HDSPM_Dolby) ? "on" : "off");
5068 pref_syncref = hdspm_pref_sync_ref(hdspm);
5069 if (pref_syncref == 0)
5070 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5072 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5075 snd_iprintf(buffer, "System Clock Frequency: %d\n",
5076 hdspm->system_sample_rate);
5078 snd_iprintf(buffer, "Double speed: %s\n",
5079 hdspm->control_register & HDSPM_DS_DoubleWire?
5080 "Double wire" : "Single wire");
5081 snd_iprintf(buffer, "Quad speed: %s\n",
5082 hdspm->control_register & HDSPM_QS_DoubleWire?
5084 hdspm->control_register & HDSPM_QS_QuadWire?
5085 "Quad wire" : "Single wire");
5087 snd_iprintf(buffer, "--- Status:\n");
5089 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
5090 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock",
5091 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5093 for (x = 0; x < 8; x++) {
5094 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
5096 (status2 & (HDSPM_LockAES >> x)) ?
5097 "Sync " : "No Lock",
5098 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5101 switch (hdspm_autosync_ref(hdspm)) {
5102 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5103 autosync_ref = "None"; break;
5104 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5105 autosync_ref = "Word Clock"; break;
5106 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5107 autosync_ref = "AES1"; break;
5108 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5109 autosync_ref = "AES2"; break;
5110 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5111 autosync_ref = "AES3"; break;
5112 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5113 autosync_ref = "AES4"; break;
5114 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5115 autosync_ref = "AES5"; break;
5116 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5117 autosync_ref = "AES6"; break;
5118 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5119 autosync_ref = "AES7"; break;
5120 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5121 autosync_ref = "AES8"; break;
5123 autosync_ref = "---"; break;
5125 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5127 snd_iprintf(buffer, "\n");
5131 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5132 struct snd_info_buffer *buffer)
5134 struct hdspm *hdspm = entry->private_data;
5135 unsigned int status1, status2, status3, control, i;
5136 unsigned int lock, sync;
5138 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5139 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5140 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5142 control = hdspm->control_register;
5144 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5145 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5146 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5149 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5151 snd_iprintf(buffer, "Clock mode : %s\n",
5152 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5153 snd_iprintf(buffer, "System frequency: %d Hz\n",
5154 hdspm_get_system_sample_rate(hdspm));
5156 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5161 for (i = 0; i < 8; i++) {
5162 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5164 (status1 & lock) ? 1 : 0,
5165 (status1 & sync) ? 1 : 0,
5166 texts_freq[(status2 >> (i * 4)) & 0xF]);
5172 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5173 (status1 & 0x1000000) ? 1 : 0,
5174 (status1 & 0x2000000) ? 1 : 0,
5175 texts_freq[(status1 >> 16) & 0xF]);
5177 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5178 (status1 & 0x4000000) ? 1 : 0,
5179 (status1 & 0x8000000) ? 1 : 0,
5180 texts_freq[(status1 >> 20) & 0xF]);
5182 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5183 (status3 & 0x400) ? 1 : 0,
5184 (status3 & 0x800) ? 1 : 0,
5185 texts_freq[(status2 >> 12) & 0xF]);
5189 #ifdef CONFIG_SND_DEBUG
5191 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5192 struct snd_info_buffer *buffer)
5194 struct hdspm *hdspm = entry->private_data;
5198 for (i = 0; i < 256 /* 1024*64 */; i += j) {
5199 snd_iprintf(buffer, "0x%08X: ", i);
5200 for (j = 0; j < 16; j += 4)
5201 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5202 snd_iprintf(buffer, "\n");
5208 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5209 struct snd_info_buffer *buffer)
5211 struct hdspm *hdspm = entry->private_data;
5214 snd_iprintf(buffer, "# generated by hdspm\n");
5216 for (i = 0; i < hdspm->max_channels_in; i++) {
5217 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5221 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5222 struct snd_info_buffer *buffer)
5224 struct hdspm *hdspm = entry->private_data;
5227 snd_iprintf(buffer, "# generated by hdspm\n");
5229 for (i = 0; i < hdspm->max_channels_out; i++) {
5230 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5235 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5237 struct snd_info_entry *entry;
5239 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5240 switch (hdspm->io_type) {
5242 snd_info_set_text_ops(entry, hdspm,
5243 snd_hdspm_proc_read_aes32);
5246 snd_info_set_text_ops(entry, hdspm,
5247 snd_hdspm_proc_read_madi);
5250 /* snd_info_set_text_ops(entry, hdspm,
5251 snd_hdspm_proc_read_madiface); */
5254 snd_info_set_text_ops(entry, hdspm,
5255 snd_hdspm_proc_read_raydat);
5262 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5263 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5266 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5267 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5270 #ifdef CONFIG_SND_DEBUG
5271 /* debug file to read all hdspm registers */
5272 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5273 snd_info_set_text_ops(entry, hdspm,
5274 snd_hdspm_proc_read_debug);
5278 /*------------------------------------------------------------
5280 ------------------------------------------------------------*/
5282 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5284 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5285 hold it (e.g. during module initialization).
5290 hdspm->settings_register = 0;
5292 switch (hdspm->io_type) {
5295 hdspm->control_register =
5296 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5301 hdspm->settings_register = 0x1 + 0x1000;
5302 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5304 hdspm->control_register =
5305 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5309 hdspm->control_register =
5310 HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5311 hdspm_encode_latency(7) | /* latency max=8192samples */
5312 HDSPM_SyncRef0 | /* AES1 is syncclock */
5313 HDSPM_LineOut | /* Analog output in */
5314 HDSPM_Professional; /* Professional mode */
5318 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5320 if (AES32 == hdspm->io_type) {
5321 /* No control2 register for AES32 */
5322 #ifdef SNDRV_BIG_ENDIAN
5323 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5325 hdspm->control2_register = 0;
5328 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5330 hdspm_compute_period_size(hdspm);
5332 /* silence everything */
5334 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5336 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5337 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5340 /* set a default rate so that the channel map is set up. */
5341 hdspm_set_rate(hdspm, 48000, 1);
5347 /*------------------------------------------------------------
5349 ------------------------------------------------------------*/
5351 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5353 struct hdspm *hdspm = (struct hdspm *) dev_id;
5354 unsigned int status;
5355 int i, audio, midi, schedule = 0;
5358 status = hdspm_read(hdspm, HDSPM_statusRegister);
5360 audio = status & HDSPM_audioIRQPending;
5361 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5362 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5364 /* now = get_cycles(); */
5366 * LAT_2..LAT_0 period counter (win) counter (mac)
5367 * 6 4096 ~256053425 ~514672358
5368 * 5 2048 ~128024983 ~257373821
5369 * 4 1024 ~64023706 ~128718089
5370 * 3 512 ~32005945 ~64385999
5371 * 2 256 ~16003039 ~32260176
5372 * 1 128 ~7998738 ~16194507
5373 * 0 64 ~3998231 ~8191558
5376 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5377 now-hdspm->last_interrupt, status & 0xFFC0);
5378 hdspm->last_interrupt = now;
5381 if (!audio && !midi)
5384 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5389 if (hdspm->capture_substream)
5390 snd_pcm_period_elapsed(hdspm->capture_substream);
5392 if (hdspm->playback_substream)
5393 snd_pcm_period_elapsed(hdspm->playback_substream);
5398 while (i < hdspm->midiPorts) {
5399 if ((hdspm_read(hdspm,
5400 hdspm->midi[i].statusIn) & 0xff) &&
5401 (status & hdspm->midi[i].irq)) {
5402 /* we disable interrupts for this input until
5403 * processing is done
5405 hdspm->control_register &= ~hdspm->midi[i].ie;
5406 hdspm_write(hdspm, HDSPM_controlRegister,
5407 hdspm->control_register);
5408 hdspm->midi[i].pending = 1;
5416 tasklet_hi_schedule(&hdspm->midi_tasklet);
5422 /*------------------------------------------------------------
5424 ------------------------------------------------------------*/
5427 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5430 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5431 return hdspm_hw_pointer(hdspm);
5435 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5437 struct snd_pcm_runtime *runtime = substream->runtime;
5438 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5439 struct snd_pcm_substream *other;
5441 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5442 other = hdspm->capture_substream;
5444 other = hdspm->playback_substream;
5447 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5449 runtime->status->hw_ptr = 0;
5451 struct snd_pcm_substream *s;
5452 struct snd_pcm_runtime *oruntime = other->runtime;
5453 snd_pcm_group_for_each_entry(s, substream) {
5455 oruntime->status->hw_ptr =
5456 runtime->status->hw_ptr;
5464 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5465 struct snd_pcm_hw_params *params)
5467 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5473 spin_lock_irq(&hdspm->lock);
5475 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5476 this_pid = hdspm->playback_pid;
5477 other_pid = hdspm->capture_pid;
5479 this_pid = hdspm->capture_pid;
5480 other_pid = hdspm->playback_pid;
5483 if (other_pid > 0 && this_pid != other_pid) {
5485 /* The other stream is open, and not by the same
5486 task as this one. Make sure that the parameters
5487 that matter are the same.
5490 if (params_rate(params) != hdspm->system_sample_rate) {
5491 spin_unlock_irq(&hdspm->lock);
5492 _snd_pcm_hw_param_setempty(params,
5493 SNDRV_PCM_HW_PARAM_RATE);
5497 if (params_period_size(params) != hdspm->period_bytes / 4) {
5498 spin_unlock_irq(&hdspm->lock);
5499 _snd_pcm_hw_param_setempty(params,
5500 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5506 spin_unlock_irq(&hdspm->lock);
5508 /* how to make sure that the rate matches an externally-set one ? */
5510 spin_lock_irq(&hdspm->lock);
5511 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5513 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5514 spin_unlock_irq(&hdspm->lock);
5515 _snd_pcm_hw_param_setempty(params,
5516 SNDRV_PCM_HW_PARAM_RATE);
5519 spin_unlock_irq(&hdspm->lock);
5521 err = hdspm_set_interrupt_interval(hdspm,
5522 params_period_size(params));
5524 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5525 _snd_pcm_hw_param_setempty(params,
5526 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5530 /* Memory allocation, takashi's method, dont know if we should
5533 /* malloc all buffer even if not enabled to get sure */
5534 /* Update for MADI rev 204: we need to allocate for all channels,
5535 * otherwise it doesn't work at 96kHz */
5538 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5540 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5544 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5546 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5547 params_channels(params));
5549 for (i = 0; i < params_channels(params); ++i)
5550 snd_hdspm_enable_out(hdspm, i, 1);
5552 hdspm->playback_buffer =
5553 (unsigned char *) substream->runtime->dma_area;
5554 snd_printdd("Allocated sample buffer for playback at %p\n",
5555 hdspm->playback_buffer);
5557 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5558 params_channels(params));
5560 for (i = 0; i < params_channels(params); ++i)
5561 snd_hdspm_enable_in(hdspm, i, 1);
5563 hdspm->capture_buffer =
5564 (unsigned char *) substream->runtime->dma_area;
5565 snd_printdd("Allocated sample buffer for capture at %p\n",
5566 hdspm->capture_buffer);
5570 snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5571 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5572 "playback" : "capture",
5573 snd_pcm_sgbuf_get_addr(substream, 0));
5576 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5577 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5578 "playback" : "capture",
5579 params_rate(params), params_channels(params),
5580 params_buffer_size(params));
5584 /* Switch to native float format if requested */
5585 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5586 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5587 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5589 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5590 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5591 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5592 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5594 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5596 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5601 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5604 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5606 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5608 /* params_channels(params) should be enough,
5609 but to get sure in case of error */
5610 for (i = 0; i < hdspm->max_channels_out; ++i)
5611 snd_hdspm_enable_out(hdspm, i, 0);
5613 hdspm->playback_buffer = NULL;
5615 for (i = 0; i < hdspm->max_channels_in; ++i)
5616 snd_hdspm_enable_in(hdspm, i, 0);
5618 hdspm->capture_buffer = NULL;
5622 snd_pcm_lib_free_pages(substream);
5628 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5629 struct snd_pcm_channel_info *info)
5631 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5633 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5634 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5635 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5639 if (hdspm->channel_map_out[info->channel] < 0) {
5640 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5644 info->offset = hdspm->channel_map_out[info->channel] *
5645 HDSPM_CHANNEL_BUFFER_BYTES;
5647 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5648 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5652 if (hdspm->channel_map_in[info->channel] < 0) {
5653 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5657 info->offset = hdspm->channel_map_in[info->channel] *
5658 HDSPM_CHANNEL_BUFFER_BYTES;
5667 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5668 unsigned int cmd, void *arg)
5671 case SNDRV_PCM_IOCTL1_RESET:
5672 return snd_hdspm_reset(substream);
5674 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5676 struct snd_pcm_channel_info *info = arg;
5677 return snd_hdspm_channel_info(substream, info);
5683 return snd_pcm_lib_ioctl(substream, cmd, arg);
5686 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5688 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5689 struct snd_pcm_substream *other;
5692 spin_lock(&hdspm->lock);
5693 running = hdspm->running;
5695 case SNDRV_PCM_TRIGGER_START:
5696 running |= 1 << substream->stream;
5698 case SNDRV_PCM_TRIGGER_STOP:
5699 running &= ~(1 << substream->stream);
5703 spin_unlock(&hdspm->lock);
5706 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5707 other = hdspm->capture_substream;
5709 other = hdspm->playback_substream;
5712 struct snd_pcm_substream *s;
5713 snd_pcm_group_for_each_entry(s, substream) {
5715 snd_pcm_trigger_done(s, substream);
5716 if (cmd == SNDRV_PCM_TRIGGER_START)
5717 running |= 1 << s->stream;
5719 running &= ~(1 << s->stream);
5723 if (cmd == SNDRV_PCM_TRIGGER_START) {
5724 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5725 && substream->stream ==
5726 SNDRV_PCM_STREAM_CAPTURE)
5727 hdspm_silence_playback(hdspm);
5730 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5731 hdspm_silence_playback(hdspm);
5734 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5735 hdspm_silence_playback(hdspm);
5738 snd_pcm_trigger_done(substream, substream);
5739 if (!hdspm->running && running)
5740 hdspm_start_audio(hdspm);
5741 else if (hdspm->running && !running)
5742 hdspm_stop_audio(hdspm);
5743 hdspm->running = running;
5744 spin_unlock(&hdspm->lock);
5749 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5754 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5755 .info = (SNDRV_PCM_INFO_MMAP |
5756 SNDRV_PCM_INFO_MMAP_VALID |
5757 SNDRV_PCM_INFO_NONINTERLEAVED |
5758 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5759 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5760 .rates = (SNDRV_PCM_RATE_32000 |
5761 SNDRV_PCM_RATE_44100 |
5762 SNDRV_PCM_RATE_48000 |
5763 SNDRV_PCM_RATE_64000 |
5764 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5765 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5769 .channels_max = HDSPM_MAX_CHANNELS,
5771 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5772 .period_bytes_min = (32 * 4),
5773 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5779 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5780 .info = (SNDRV_PCM_INFO_MMAP |
5781 SNDRV_PCM_INFO_MMAP_VALID |
5782 SNDRV_PCM_INFO_NONINTERLEAVED |
5783 SNDRV_PCM_INFO_SYNC_START),
5784 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5785 .rates = (SNDRV_PCM_RATE_32000 |
5786 SNDRV_PCM_RATE_44100 |
5787 SNDRV_PCM_RATE_48000 |
5788 SNDRV_PCM_RATE_64000 |
5789 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5790 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5794 .channels_max = HDSPM_MAX_CHANNELS,
5796 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5797 .period_bytes_min = (32 * 4),
5798 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5804 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5805 struct snd_pcm_hw_rule *rule)
5807 struct hdspm *hdspm = rule->private;
5808 struct snd_interval *c =
5809 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5810 struct snd_interval *r =
5811 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5813 if (r->min > 96000 && r->max <= 192000) {
5814 struct snd_interval t = {
5815 .min = hdspm->qs_in_channels,
5816 .max = hdspm->qs_in_channels,
5819 return snd_interval_refine(c, &t);
5820 } else if (r->min > 48000 && r->max <= 96000) {
5821 struct snd_interval t = {
5822 .min = hdspm->ds_in_channels,
5823 .max = hdspm->ds_in_channels,
5826 return snd_interval_refine(c, &t);
5827 } else if (r->max < 64000) {
5828 struct snd_interval t = {
5829 .min = hdspm->ss_in_channels,
5830 .max = hdspm->ss_in_channels,
5833 return snd_interval_refine(c, &t);
5839 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5840 struct snd_pcm_hw_rule * rule)
5842 struct hdspm *hdspm = rule->private;
5843 struct snd_interval *c =
5844 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5845 struct snd_interval *r =
5846 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5848 if (r->min > 96000 && r->max <= 192000) {
5849 struct snd_interval t = {
5850 .min = hdspm->qs_out_channels,
5851 .max = hdspm->qs_out_channels,
5854 return snd_interval_refine(c, &t);
5855 } else if (r->min > 48000 && r->max <= 96000) {
5856 struct snd_interval t = {
5857 .min = hdspm->ds_out_channels,
5858 .max = hdspm->ds_out_channels,
5861 return snd_interval_refine(c, &t);
5862 } else if (r->max < 64000) {
5863 struct snd_interval t = {
5864 .min = hdspm->ss_out_channels,
5865 .max = hdspm->ss_out_channels,
5868 return snd_interval_refine(c, &t);
5874 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5875 struct snd_pcm_hw_rule * rule)
5877 struct hdspm *hdspm = rule->private;
5878 struct snd_interval *c =
5879 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5880 struct snd_interval *r =
5881 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5883 if (c->min >= hdspm->ss_in_channels) {
5884 struct snd_interval t = {
5889 return snd_interval_refine(r, &t);
5890 } else if (c->max <= hdspm->qs_in_channels) {
5891 struct snd_interval t = {
5896 return snd_interval_refine(r, &t);
5897 } else if (c->max <= hdspm->ds_in_channels) {
5898 struct snd_interval t = {
5903 return snd_interval_refine(r, &t);
5908 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5909 struct snd_pcm_hw_rule *rule)
5911 struct hdspm *hdspm = rule->private;
5912 struct snd_interval *c =
5913 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5914 struct snd_interval *r =
5915 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5917 if (c->min >= hdspm->ss_out_channels) {
5918 struct snd_interval t = {
5923 return snd_interval_refine(r, &t);
5924 } else if (c->max <= hdspm->qs_out_channels) {
5925 struct snd_interval t = {
5930 return snd_interval_refine(r, &t);
5931 } else if (c->max <= hdspm->ds_out_channels) {
5932 struct snd_interval t = {
5937 return snd_interval_refine(r, &t);
5943 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5944 struct snd_pcm_hw_rule *rule)
5946 unsigned int list[3];
5947 struct hdspm *hdspm = rule->private;
5948 struct snd_interval *c = hw_param_interval(params,
5949 SNDRV_PCM_HW_PARAM_CHANNELS);
5951 list[0] = hdspm->qs_in_channels;
5952 list[1] = hdspm->ds_in_channels;
5953 list[2] = hdspm->ss_in_channels;
5954 return snd_interval_list(c, 3, list, 0);
5957 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5958 struct snd_pcm_hw_rule *rule)
5960 unsigned int list[3];
5961 struct hdspm *hdspm = rule->private;
5962 struct snd_interval *c = hw_param_interval(params,
5963 SNDRV_PCM_HW_PARAM_CHANNELS);
5965 list[0] = hdspm->qs_out_channels;
5966 list[1] = hdspm->ds_out_channels;
5967 list[2] = hdspm->ss_out_channels;
5968 return snd_interval_list(c, 3, list, 0);
5972 static unsigned int hdspm_aes32_sample_rates[] = {
5973 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5976 static struct snd_pcm_hw_constraint_list
5977 hdspm_hw_constraints_aes32_sample_rates = {
5978 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5979 .list = hdspm_aes32_sample_rates,
5983 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5985 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5986 struct snd_pcm_runtime *runtime = substream->runtime;
5988 spin_lock_irq(&hdspm->lock);
5990 snd_pcm_set_sync(substream);
5993 runtime->hw = snd_hdspm_playback_subinfo;
5995 if (hdspm->capture_substream == NULL)
5996 hdspm_stop_audio(hdspm);
5998 hdspm->playback_pid = current->pid;
5999 hdspm->playback_substream = substream;
6001 spin_unlock_irq(&hdspm->lock);
6003 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6004 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6006 switch (hdspm->io_type) {
6009 snd_pcm_hw_constraint_minmax(runtime,
6010 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6012 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
6013 snd_pcm_hw_constraint_minmax(runtime,
6014 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6019 snd_pcm_hw_constraint_minmax(runtime,
6020 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6025 if (AES32 == hdspm->io_type) {
6026 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6027 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6028 &hdspm_hw_constraints_aes32_sample_rates);
6030 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6031 snd_hdspm_hw_rule_rate_out_channels, hdspm,
6032 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6035 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6036 snd_hdspm_hw_rule_out_channels, hdspm,
6037 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6039 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6040 snd_hdspm_hw_rule_out_channels_rate, hdspm,
6041 SNDRV_PCM_HW_PARAM_RATE, -1);
6046 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
6048 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6050 spin_lock_irq(&hdspm->lock);
6052 hdspm->playback_pid = -1;
6053 hdspm->playback_substream = NULL;
6055 spin_unlock_irq(&hdspm->lock);
6061 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6063 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6064 struct snd_pcm_runtime *runtime = substream->runtime;
6066 spin_lock_irq(&hdspm->lock);
6067 snd_pcm_set_sync(substream);
6068 runtime->hw = snd_hdspm_capture_subinfo;
6070 if (hdspm->playback_substream == NULL)
6071 hdspm_stop_audio(hdspm);
6073 hdspm->capture_pid = current->pid;
6074 hdspm->capture_substream = substream;
6076 spin_unlock_irq(&hdspm->lock);
6078 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6079 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6081 switch (hdspm->io_type) {
6084 snd_pcm_hw_constraint_minmax(runtime,
6085 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6087 snd_pcm_hw_constraint_minmax(runtime,
6088 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6093 snd_pcm_hw_constraint_minmax(runtime,
6094 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6099 if (AES32 == hdspm->io_type) {
6100 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6101 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6102 &hdspm_hw_constraints_aes32_sample_rates);
6104 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6105 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6106 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6109 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6110 snd_hdspm_hw_rule_in_channels, hdspm,
6111 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6113 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6114 snd_hdspm_hw_rule_in_channels_rate, hdspm,
6115 SNDRV_PCM_HW_PARAM_RATE, -1);
6120 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6122 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6124 spin_lock_irq(&hdspm->lock);
6126 hdspm->capture_pid = -1;
6127 hdspm->capture_substream = NULL;
6129 spin_unlock_irq(&hdspm->lock);
6133 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6135 /* we have nothing to initialize but the call is required */
6139 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6141 u32 val = readl(src);
6142 return copy_to_user(dest, &val, 4);
6145 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6146 unsigned int cmd, unsigned long arg)
6148 void __user *argp = (void __user *)arg;
6149 struct hdspm *hdspm = hw->private_data;
6150 struct hdspm_mixer_ioctl mixer;
6151 struct hdspm_config info;
6152 struct hdspm_status status;
6153 struct hdspm_version hdspm_version;
6154 struct hdspm_peak_rms *levels;
6155 struct hdspm_ltc ltc;
6156 unsigned int statusregister;
6157 long unsigned int s;
6162 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6163 levels = &hdspm->peak_rms;
6164 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6165 levels->input_peaks[i] =
6166 readl(hdspm->iobase +
6167 HDSPM_MADI_INPUT_PEAK + i*4);
6168 levels->playback_peaks[i] =
6169 readl(hdspm->iobase +
6170 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6171 levels->output_peaks[i] =
6172 readl(hdspm->iobase +
6173 HDSPM_MADI_OUTPUT_PEAK + i*4);
6175 levels->input_rms[i] =
6176 ((uint64_t) readl(hdspm->iobase +
6177 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6178 (uint64_t) readl(hdspm->iobase +
6179 HDSPM_MADI_INPUT_RMS_L + i*4);
6180 levels->playback_rms[i] =
6181 ((uint64_t)readl(hdspm->iobase +
6182 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6183 (uint64_t)readl(hdspm->iobase +
6184 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6185 levels->output_rms[i] =
6186 ((uint64_t)readl(hdspm->iobase +
6187 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6188 (uint64_t)readl(hdspm->iobase +
6189 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6192 if (hdspm->system_sample_rate > 96000) {
6194 } else if (hdspm->system_sample_rate > 48000) {
6199 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6201 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6203 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6204 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6210 case SNDRV_HDSPM_IOCTL_GET_LTC:
6211 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6212 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6213 if (i & HDSPM_TCO1_LTC_Input_valid) {
6214 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6215 HDSPM_TCO1_LTC_Format_MSB)) {
6217 ltc.format = fps_24;
6219 case HDSPM_TCO1_LTC_Format_LSB:
6220 ltc.format = fps_25;
6222 case HDSPM_TCO1_LTC_Format_MSB:
6223 ltc.format = fps_2997;
6229 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6230 ltc.frame = drop_frame;
6232 ltc.frame = full_frame;
6235 ltc.format = format_invalid;
6236 ltc.frame = frame_invalid;
6238 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6239 ltc.input_format = ntsc;
6240 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6241 ltc.input_format = pal;
6243 ltc.input_format = no_video;
6246 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc));
6249 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6255 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6257 memset(&info, 0, sizeof(info));
6258 spin_lock_irq(&hdspm->lock);
6259 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6260 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6262 info.system_sample_rate = hdspm->system_sample_rate;
6263 info.autosync_sample_rate =
6264 hdspm_external_sample_rate(hdspm);
6265 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6266 info.clock_source = hdspm_clock_source(hdspm);
6267 info.autosync_ref = hdspm_autosync_ref(hdspm);
6268 info.line_out = hdspm_line_out(hdspm);
6270 spin_unlock_irq(&hdspm->lock);
6271 if (copy_to_user(argp, &info, sizeof(info)))
6275 case SNDRV_HDSPM_IOCTL_GET_STATUS:
6276 memset(&status, 0, sizeof(status));
6278 status.card_type = hdspm->io_type;
6280 status.autosync_source = hdspm_autosync_ref(hdspm);
6282 status.card_clock = 110069313433624ULL;
6283 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6285 switch (hdspm->io_type) {
6288 status.card_specific.madi.sync_wc =
6289 hdspm_wc_sync_check(hdspm);
6290 status.card_specific.madi.sync_madi =
6291 hdspm_madi_sync_check(hdspm);
6292 status.card_specific.madi.sync_tco =
6293 hdspm_tco_sync_check(hdspm);
6294 status.card_specific.madi.sync_in =
6295 hdspm_sync_in_sync_check(hdspm);
6298 hdspm_read(hdspm, HDSPM_statusRegister);
6299 status.card_specific.madi.madi_input =
6300 (statusregister & HDSPM_AB_int) ? 1 : 0;
6301 status.card_specific.madi.channel_format =
6302 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6303 /* TODO: Mac driver sets it when f_s>48kHz */
6304 status.card_specific.madi.frame_format = 0;
6310 if (copy_to_user(argp, &status, sizeof(status)))
6316 case SNDRV_HDSPM_IOCTL_GET_VERSION:
6317 memset(&hdspm_version, 0, sizeof(hdspm_version));
6319 hdspm_version.card_type = hdspm->io_type;
6320 strncpy(hdspm_version.cardname, hdspm->card_name,
6321 sizeof(hdspm_version.cardname));
6322 hdspm_version.serial = hdspm->serial;
6323 hdspm_version.firmware_rev = hdspm->firmware_rev;
6324 hdspm_version.addons = 0;
6326 hdspm_version.addons |= HDSPM_ADDON_TCO;
6328 if (copy_to_user(argp, &hdspm_version,
6329 sizeof(hdspm_version)))
6333 case SNDRV_HDSPM_IOCTL_GET_MIXER:
6334 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6336 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6337 sizeof(struct hdspm_mixer)))
6347 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6348 .open = snd_hdspm_playback_open,
6349 .close = snd_hdspm_playback_release,
6350 .ioctl = snd_hdspm_ioctl,
6351 .hw_params = snd_hdspm_hw_params,
6352 .hw_free = snd_hdspm_hw_free,
6353 .prepare = snd_hdspm_prepare,
6354 .trigger = snd_hdspm_trigger,
6355 .pointer = snd_hdspm_hw_pointer,
6356 .page = snd_pcm_sgbuf_ops_page,
6359 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6360 .open = snd_hdspm_capture_open,
6361 .close = snd_hdspm_capture_release,
6362 .ioctl = snd_hdspm_ioctl,
6363 .hw_params = snd_hdspm_hw_params,
6364 .hw_free = snd_hdspm_hw_free,
6365 .prepare = snd_hdspm_prepare,
6366 .trigger = snd_hdspm_trigger,
6367 .pointer = snd_hdspm_hw_pointer,
6368 .page = snd_pcm_sgbuf_ops_page,
6371 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6372 struct hdspm * hdspm)
6374 struct snd_hwdep *hw;
6377 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6382 hw->private_data = hdspm;
6383 strcpy(hw->name, "HDSPM hwdep interface");
6385 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6386 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6387 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6388 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6394 /*------------------------------------------------------------
6396 ------------------------------------------------------------*/
6397 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6400 struct snd_pcm *pcm;
6405 wanted = HDSPM_DMA_AREA_BYTES;
6408 snd_pcm_lib_preallocate_pages_for_all(pcm,
6409 SNDRV_DMA_TYPE_DEV_SG,
6410 snd_dma_pci_data(hdspm->pci),
6414 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6418 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6424 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6425 struct snd_pcm_substream *substream,
6426 unsigned int reg, int channels)
6430 /* continuous memory segment */
6431 for (i = 0; i < (channels * 16); i++)
6432 hdspm_write(hdspm, reg + 4 * i,
6433 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6437 /* ------------- ALSA Devices ---------------------------- */
6438 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6439 struct hdspm *hdspm)
6441 struct snd_pcm *pcm;
6444 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6449 pcm->private_data = hdspm;
6450 strcpy(pcm->name, hdspm->card_name);
6452 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6453 &snd_hdspm_playback_ops);
6454 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6455 &snd_hdspm_capture_ops);
6457 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6459 err = snd_hdspm_preallocate_memory(hdspm);
6466 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6470 for (i = 0; i < hdspm->midiPorts; i++)
6471 snd_hdspm_flush_midi_input(hdspm, i);
6474 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6475 struct hdspm * hdspm)
6479 snd_printdd("Create card...\n");
6480 err = snd_hdspm_create_pcm(card, hdspm);
6485 while (i < hdspm->midiPorts) {
6486 err = snd_hdspm_create_midi(card, hdspm, i);
6493 err = snd_hdspm_create_controls(card, hdspm);
6497 err = snd_hdspm_create_hwdep(card, hdspm);
6501 snd_printdd("proc init...\n");
6502 snd_hdspm_proc_init(hdspm);
6504 hdspm->system_sample_rate = -1;
6505 hdspm->last_external_sample_rate = -1;
6506 hdspm->last_internal_sample_rate = -1;
6507 hdspm->playback_pid = -1;
6508 hdspm->capture_pid = -1;
6509 hdspm->capture_substream = NULL;
6510 hdspm->playback_substream = NULL;
6512 snd_printdd("Set defaults...\n");
6513 err = snd_hdspm_set_defaults(hdspm);
6517 snd_printdd("Update mixer controls...\n");
6518 hdspm_update_simple_mixer_controls(hdspm);
6520 snd_printdd("Initializeing complete ???\n");
6522 err = snd_card_register(card);
6524 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6528 snd_printdd("... yes now\n");
6533 static int __devinit snd_hdspm_create(struct snd_card *card,
6534 struct hdspm *hdspm) {
6536 struct pci_dev *pci = hdspm->pci;
6538 unsigned long io_extent;
6543 spin_lock_init(&hdspm->lock);
6545 pci_read_config_word(hdspm->pci,
6546 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6548 strcpy(card->mixername, "Xilinx FPGA");
6549 strcpy(card->driver, "HDSPM");
6551 switch (hdspm->firmware_rev) {
6552 case HDSPM_RAYDAT_REV:
6553 hdspm->io_type = RayDAT;
6554 hdspm->card_name = "RME RayDAT";
6555 hdspm->midiPorts = 2;
6558 hdspm->io_type = AIO;
6559 hdspm->card_name = "RME AIO";
6560 hdspm->midiPorts = 1;
6562 case HDSPM_MADIFACE_REV:
6563 hdspm->io_type = MADIface;
6564 hdspm->card_name = "RME MADIface";
6565 hdspm->midiPorts = 1;
6568 if ((hdspm->firmware_rev == 0xf0) ||
6569 ((hdspm->firmware_rev >= 0xe6) &&
6570 (hdspm->firmware_rev <= 0xea))) {
6571 hdspm->io_type = AES32;
6572 hdspm->card_name = "RME AES32";
6573 hdspm->midiPorts = 2;
6574 } else if ((hdspm->firmware_rev == 0xd2) ||
6575 ((hdspm->firmware_rev >= 0xc8) &&
6576 (hdspm->firmware_rev <= 0xcf))) {
6577 hdspm->io_type = MADI;
6578 hdspm->card_name = "RME MADI";
6579 hdspm->midiPorts = 3;
6582 "HDSPM: unknown firmware revision %x\n",
6583 hdspm->firmware_rev);
6588 err = pci_enable_device(pci);
6592 pci_set_master(hdspm->pci);
6594 err = pci_request_regions(pci, "hdspm");
6598 hdspm->port = pci_resource_start(pci, 0);
6599 io_extent = pci_resource_len(pci, 0);
6601 snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6602 hdspm->port, hdspm->port + io_extent - 1);
6604 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6605 if (!hdspm->iobase) {
6606 snd_printk(KERN_ERR "HDSPM: "
6607 "unable to remap region 0x%lx-0x%lx\n",
6608 hdspm->port, hdspm->port + io_extent - 1);
6611 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6612 (unsigned long)hdspm->iobase, hdspm->port,
6613 hdspm->port + io_extent - 1);
6615 if (request_irq(pci->irq, snd_hdspm_interrupt,
6616 IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6617 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6621 snd_printdd("use IRQ %d\n", pci->irq);
6623 hdspm->irq = pci->irq;
6625 snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6626 sizeof(struct hdspm_mixer));
6627 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6628 if (!hdspm->mixer) {
6629 snd_printk(KERN_ERR "HDSPM: "
6630 "unable to kmalloc Mixer memory of %d Bytes\n",
6631 (int)sizeof(struct hdspm_mixer));
6635 hdspm->port_names_in = NULL;
6636 hdspm->port_names_out = NULL;
6638 switch (hdspm->io_type) {
6640 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6641 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6642 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6644 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6646 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6648 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6650 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6652 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6654 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6657 hdspm->max_channels_out = hdspm->max_channels_in =
6659 hdspm->port_names_in = hdspm->port_names_out =
6661 hdspm->channel_map_in = hdspm->channel_map_out =
6668 hdspm->ss_in_channels = hdspm->ss_out_channels =
6670 hdspm->ds_in_channels = hdspm->ds_out_channels =
6672 hdspm->qs_in_channels = hdspm->qs_out_channels =
6675 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6676 channel_map_unity_ss;
6677 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6678 channel_map_unity_ss;
6679 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6680 channel_map_unity_ss;
6682 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6684 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6686 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6691 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6692 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6695 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6696 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6697 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6698 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6699 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6700 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6702 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6703 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6704 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6706 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6707 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6708 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6710 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6711 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6712 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6713 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6714 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6715 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6720 hdspm->ss_in_channels = hdspm->ss_out_channels =
6722 hdspm->ds_in_channels = hdspm->ds_out_channels =
6724 hdspm->qs_in_channels = hdspm->qs_out_channels =
6727 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6728 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6730 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6731 channel_map_raydat_ss;
6732 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6733 channel_map_raydat_ds;
6734 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6735 channel_map_raydat_qs;
6736 hdspm->channel_map_in = hdspm->channel_map_out =
6737 channel_map_raydat_ss;
6739 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6740 texts_ports_raydat_ss;
6741 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6742 texts_ports_raydat_ds;
6743 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6744 texts_ports_raydat_qs;
6752 switch (hdspm->io_type) {
6755 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6756 HDSPM_s2_tco_detect) {
6758 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6760 if (NULL != hdspm->tco) {
6761 hdspm_tco_write(hdspm);
6763 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6770 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6772 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6774 if (NULL != hdspm->tco) {
6775 hdspm_tco_write(hdspm);
6777 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6788 switch (hdspm->io_type) {
6791 hdspm->texts_autosync = texts_autosync_aes_tco;
6792 hdspm->texts_autosync_items = 10;
6794 hdspm->texts_autosync = texts_autosync_aes;
6795 hdspm->texts_autosync_items = 9;
6801 hdspm->texts_autosync = texts_autosync_madi_tco;
6802 hdspm->texts_autosync_items = 4;
6804 hdspm->texts_autosync = texts_autosync_madi;
6805 hdspm->texts_autosync_items = 3;
6815 hdspm->texts_autosync = texts_autosync_raydat_tco;
6816 hdspm->texts_autosync_items = 9;
6818 hdspm->texts_autosync = texts_autosync_raydat;
6819 hdspm->texts_autosync_items = 8;
6825 hdspm->texts_autosync = texts_autosync_aio_tco;
6826 hdspm->texts_autosync_items = 6;
6828 hdspm->texts_autosync = texts_autosync_aio;
6829 hdspm->texts_autosync_items = 5;
6835 tasklet_init(&hdspm->midi_tasklet,
6836 hdspm_midi_tasklet, (unsigned long) hdspm);
6839 if (hdspm->io_type != MADIface) {
6840 hdspm->serial = (hdspm_read(hdspm,
6841 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6842 /* id contains either a user-provided value or the default
6843 * NULL. If it's the default, we're safe to
6844 * fill card->id with the serial number.
6846 * If the serial number is 0xFFFFFF, then we're dealing with
6847 * an old PCI revision that comes without a sane number. In
6848 * this case, we don't set card->id to avoid collisions
6849 * when running with multiple cards.
6851 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6852 sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6853 snd_card_set_id(card, card->id);
6857 snd_printdd("create alsa devices.\n");
6858 err = snd_hdspm_create_alsa_devices(card, hdspm);
6862 snd_hdspm_initialize_midi_flush(hdspm);
6868 static int snd_hdspm_free(struct hdspm * hdspm)
6873 /* stop th audio, and cancel all interrupts */
6874 hdspm->control_register &=
6875 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6876 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6877 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6878 hdspm_write(hdspm, HDSPM_controlRegister,
6879 hdspm->control_register);
6882 if (hdspm->irq >= 0)
6883 free_irq(hdspm->irq, (void *) hdspm);
6885 kfree(hdspm->mixer);
6888 iounmap(hdspm->iobase);
6891 pci_release_regions(hdspm->pci);
6893 pci_disable_device(hdspm->pci);
6898 static void snd_hdspm_card_free(struct snd_card *card)
6900 struct hdspm *hdspm = card->private_data;
6903 snd_hdspm_free(hdspm);
6907 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6908 const struct pci_device_id *pci_id)
6911 struct hdspm *hdspm;
6912 struct snd_card *card;
6915 if (dev >= SNDRV_CARDS)
6922 err = snd_card_create(index[dev], id[dev],
6923 THIS_MODULE, sizeof(struct hdspm), &card);
6927 hdspm = card->private_data;
6928 card->private_free = snd_hdspm_card_free;
6932 snd_card_set_dev(card, &pci->dev);
6934 err = snd_hdspm_create(card, hdspm);
6936 snd_card_free(card);
6940 if (hdspm->io_type != MADIface) {
6941 sprintf(card->shortname, "%s_%x",
6944 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6947 hdspm->port, hdspm->irq);
6949 sprintf(card->shortname, "%s", hdspm->card_name);
6950 sprintf(card->longname, "%s at 0x%lx, irq %d",
6951 hdspm->card_name, hdspm->port, hdspm->irq);
6954 err = snd_card_register(card);
6956 snd_card_free(card);
6960 pci_set_drvdata(pci, card);
6966 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6968 snd_card_free(pci_get_drvdata(pci));
6969 pci_set_drvdata(pci, NULL);
6972 static struct pci_driver hdspm_driver = {
6973 .name = KBUILD_MODNAME,
6974 .id_table = snd_hdspm_ids,
6975 .probe = snd_hdspm_probe,
6976 .remove = __devexit_p(snd_hdspm_remove),
6979 module_pci_driver(hdspm_driver);