2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
11 * Modified 2009-04-13 for proper metering by Florian Faber
14 * Modified 2009-04-14 for native float support by Florian Faber
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/moduleparam.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/math64.h>
50 #include <sound/core.h>
51 #include <sound/control.h>
52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h>
54 #include <sound/info.h>
55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h>
58 #include <sound/initval.h>
60 #include <sound/hdspm.h>
62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
66 module_param_array(index, int, NULL, 0444);
67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
69 module_param_array(id, charp, NULL, 0444);
70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
72 module_param_array(enable, bool, NULL, 0444);
73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
78 "Winfried Ritsch <ritsch_AT_iem.at>, "
79 "Paul Davis <paul@linuxaudiosystems.com>, "
80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81 "Remy Bruno <remy.bruno@trinnov.com>, "
82 "Florian Faber <faberman@linuxproaudio.org>, "
83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
89 /* --- Write registers. ---
90 These are defined as byte-offsets from the iobase value. */
92 #define HDSPM_WR_SETTINGS 0
93 #define HDSPM_outputBufferAddress 32
94 #define HDSPM_inputBufferAddress 36
95 #define HDSPM_controlRegister 64
96 #define HDSPM_interruptConfirmation 96
97 #define HDSPM_control2Reg 256 /* not in specs ???????? */
98 #define HDSPM_freqReg 256 /* for AES32 */
99 #define HDSPM_midiDataOut0 352 /* just believe in old code */
100 #define HDSPM_midiDataOut1 356
101 #define HDSPM_eeprom_wr 384 /* for AES32 */
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut 8192
110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
116 /* --- Read registers. ---
117 These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister 0
119 /*#define HDSPM_statusRegister2 96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121 * offset 192, for AES32 *and* MADI
122 * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2 192
124 #define HDSPM_timecodeRegister 128
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
132 #define HDSPM_RD_TCO 256
133 #define HDSPM_RD_PLL_FREQ 512
134 #define HDSPM_WR_TCO 128
136 #define HDSPM_TCO1_TCO_lock 0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
144 #define HDSPM_TCO1_set_TC 0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800
149 #define HDSPM_TCO2_TC_run 0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
154 #define HDSPM_TCO2_set_jam_sync 0x00200000
155 #define HDSPM_TCO2_set_flywheel 0x00400000
157 #define HDSPM_TCO2_set_01_4 0x01000000
158 #define HDSPM_TCO2_set_pull_down 0x02000000
159 #define HDSPM_TCO2_set_pull_up 0x04000000
160 #define HDSPM_TCO2_set_freq 0x08000000
161 #define HDSPM_TCO2_set_term_75R 0x10000000
162 #define HDSPM_TCO2_set_input_LSB 0x20000000
163 #define HDSPM_TCO2_set_input_MSB 0x40000000
164 #define HDSPM_TCO2_set_freq_from_app 0x80000000
167 #define HDSPM_midiDataOut0 352
168 #define HDSPM_midiDataOut1 356
169 #define HDSPM_midiDataOut2 368
171 #define HDSPM_midiDataIn0 360
172 #define HDSPM_midiDataIn1 364
173 #define HDSPM_midiDataIn2 372
174 #define HDSPM_midiDataIn3 376
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0 384
178 #define HDSPM_midiStatusOut1 388
179 #define HDSPM_midiStatusOut2 400
181 #define HDSPM_midiStatusIn0 392
182 #define HDSPM_midiStatusIn1 396
183 #define HDSPM_midiStatusIn2 404
184 #define HDSPM_midiStatusIn3 408
187 /* the meters are regular i/o-mapped registers, but offset
188 considerably from the rest. the peak registers are reset
189 when read; the least-significant 4 bits are full-scale counters;
190 the actual peak value is in the most-significant 24 bits.
193 #define HDSPM_MADI_INPUT_PEAK 4096
194 #define HDSPM_MADI_PLAYBACK_PEAK 4352
195 #define HDSPM_MADI_OUTPUT_PEAK 4608
197 #define HDSPM_MADI_INPUT_RMS_L 6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400
199 #define HDSPM_MADI_OUTPUT_RMS_L 6656
201 #define HDSPM_MADI_INPUT_RMS_H 7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424
203 #define HDSPM_MADI_OUTPUT_RMS_H 7680
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start (1<<0) /* start engine */
208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1 (1<<2) /* where n is defined */
210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings
214 register [RayDAT, AIO] */
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
225 56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
229 0=off, 1=on */ /* MADI ONLY */
230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
237 #define HDSPM_SyncRef2 (1<<13)
238 #define HDSPM_SyncRef3 (1<<25)
240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
242 AES additional bits in
243 lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT 0x2000000
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
259 #define HDSPM_wclk_sel (1<<30)
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical 0
267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269 HDSPM_SyncRef2|HDSPM_SyncRef3)
271 #define HDSPM_c0_SyncRef0 0x2
272 #define HDSPM_c0_SyncRef1 0x4
273 #define HDSPM_c0_SyncRef2 0x8
274 #define HDSPM_c0_SyncRef3 0x10
275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO 2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
283 #define HDSPM_Frequency32KHz HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK 1
299 #define HDSPM_SYNC_CHECK_SYNC 2
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD 0
303 #define HDSPM_AUTOSYNC_FROM_MADI 1
304 #define HDSPM_AUTOSYNC_FROM_TCO 2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
306 #define HDSPM_AUTOSYNC_FROM_NONE 4
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0 /* optical */
310 #define HDSPM_COAXIAL 1 /* BNC */
312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS (1<<0)
320 #define HDSPM_TCK (1<<1)
321 #define HDSPM_TDI (1<<2)
322 #define HDSPM_JTAG (1<<3)
323 #define HDSPM_PWDN (1<<4)
324 #define HDSPM_PROGRAM (1<<5)
325 #define HDSPM_CONFIG_MODE_0 (1<<6)
326 #define HDSPM_CONFIG_MODE_1 (1<<7)
327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE (1<<9)
329 #define HDSPM_RD_MULTIPLE (1<<10)
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332 that do not conflict with specific bits for AES32 seem to be valid also
335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351 /* since 64byte accurate, last 6 bits are not used */
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
365 #define HDSPM_tco_detect 0x08000000
366 #define HDSPM_tco_lock 0x20000000
368 #define HDSPM_s2_tco_detect 0x00000040
369 #define HDSPM_s2_AEBO_D 0x00000080
370 #define HDSPM_s2_AEBI_D 0x00000100
373 #define HDSPM_midi0IRQPending 0x40000000
374 #define HDSPM_midi1IRQPending 0x80000000
375 #define HDSPM_midi2IRQPending 0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending 0x00200000
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381 HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
392 /* Status2 Register bits */ /* MADI ONLY */
394 #define HDSPM_version0 (1<<0) /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */
406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
432 #define HDSPM_SelSyncRef_WORD 0
433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
440 For AES32, bits for status, status2 and timecode are different
443 #define HDSPM_AES32_wcLock 0x0200000
444 #define HDSPM_AES32_wcFreq_bit 22
445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
447 #define HDSPM_AES32_syncref_bit 16
448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
463 #define HDSPM_LockAES 0x80
464 #define HDSPM_LockAES1 0x80
465 #define HDSPM_LockAES2 0x40
466 #define HDSPM_LockAES3 0x20
467 #define HDSPM_LockAES4 0x10
468 #define HDSPM_LockAES5 0x8
469 #define HDSPM_LockAES6 0x4
470 #define HDSPM_LockAES7 0x2
471 #define HDSPM_LockAES8 0x1
474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
486 NB: Timecode register doesn't seem to work on AES32 card revision 230
490 #define UNITY_GAIN 32768 /* = 65536/2 */
491 #define MINUS_INFINITY_GAIN 0
493 /* Number of channels for different Speed Modes */
494 #define MADI_SS_CHANNELS 64
495 #define MADI_DS_CHANNELS 32
496 #define MADI_QS_CHANNELS 16
498 #define RAYDAT_SS_CHANNELS 36
499 #define RAYDAT_DS_CHANNELS 20
500 #define RAYDAT_QS_CHANNELS 12
502 #define AIO_IN_SS_CHANNELS 14
503 #define AIO_IN_DS_CHANNELS 10
504 #define AIO_IN_QS_CHANNELS 8
505 #define AIO_OUT_SS_CHANNELS 16
506 #define AIO_OUT_DS_CHANNELS 12
507 #define AIO_OUT_QS_CHANNELS 10
509 #define AES32_CHANNELS 16
511 /* the size of a substream (1 mono data stream) */
512 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
513 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
515 /* the size of the area we need to allocate for DMA transfers. the
516 size is the same regardless of the number of channels, and
517 also the latency to use.
518 for one direction !!!
520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
523 /* revisions >= 230 indicate AES32 card */
524 #define HDSPM_MADI_REV 210
525 #define HDSPM_RAYDAT_REV 211
526 #define HDSPM_AIO_REV 212
527 #define HDSPM_MADIFACE_REV 213
528 #define HDSPM_AES_REV 240
529 #define HDSPM_AES32_REV 234
530 #define HDSPM_AES32_OLD_REV 233
532 /* speed factor modes */
533 #define HDSPM_SPEED_SINGLE 0
534 #define HDSPM_SPEED_DOUBLE 1
535 #define HDSPM_SPEED_QUAD 2
537 /* names for speed modes */
538 static char *hdspm_speed_names[] = { "single", "double", "quad" };
540 static char *texts_autosync_aes_tco[] = { "Word Clock",
541 "AES1", "AES2", "AES3", "AES4",
542 "AES5", "AES6", "AES7", "AES8",
544 static char *texts_autosync_aes[] = { "Word Clock",
545 "AES1", "AES2", "AES3", "AES4",
546 "AES5", "AES6", "AES7", "AES8" };
547 static char *texts_autosync_madi_tco[] = { "Word Clock",
548 "MADI", "TCO", "Sync In" };
549 static char *texts_autosync_madi[] = { "Word Clock",
552 static char *texts_autosync_raydat_tco[] = {
554 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
555 "AES", "SPDIF", "TCO", "Sync In"
557 static char *texts_autosync_raydat[] = {
559 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
560 "AES", "SPDIF", "Sync In"
562 static char *texts_autosync_aio_tco[] = {
564 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
566 static char *texts_autosync_aio[] = { "Word Clock",
567 "ADAT", "AES", "SPDIF", "Sync In" };
569 static char *texts_freq[] = {
582 static char *texts_ports_madi[] = {
583 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
584 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
585 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
586 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
587 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
588 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
589 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
590 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
591 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
592 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
593 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
597 static char *texts_ports_raydat_ss[] = {
598 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
599 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
600 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
601 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
602 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
603 "ADAT4.7", "ADAT4.8",
608 static char *texts_ports_raydat_ds[] = {
609 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
610 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
611 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
612 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
617 static char *texts_ports_raydat_qs[] = {
618 "ADAT1.1", "ADAT1.2",
619 "ADAT2.1", "ADAT2.2",
620 "ADAT3.1", "ADAT3.2",
621 "ADAT4.1", "ADAT4.2",
627 static char *texts_ports_aio_in_ss[] = {
628 "Analogue.L", "Analogue.R",
630 "SPDIF.L", "SPDIF.R",
631 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
635 static char *texts_ports_aio_out_ss[] = {
636 "Analogue.L", "Analogue.R",
638 "SPDIF.L", "SPDIF.R",
639 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
644 static char *texts_ports_aio_in_ds[] = {
645 "Analogue.L", "Analogue.R",
647 "SPDIF.L", "SPDIF.R",
648 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
651 static char *texts_ports_aio_out_ds[] = {
652 "Analogue.L", "Analogue.R",
654 "SPDIF.L", "SPDIF.R",
655 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
659 static char *texts_ports_aio_in_qs[] = {
660 "Analogue.L", "Analogue.R",
662 "SPDIF.L", "SPDIF.R",
663 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
666 static char *texts_ports_aio_out_qs[] = {
667 "Analogue.L", "Analogue.R",
669 "SPDIF.L", "SPDIF.R",
670 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
674 static char *texts_ports_aes32[] = {
675 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
676 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
680 /* These tables map the ALSA channels 1..N to the channels that we
681 need to use in order to find the relevant channel buffer. RME
682 refers to this kind of mapping as between "the ADAT channel and
683 the DMA channel." We index it using the logical audio channel,
684 and the value is the DMA channel (i.e. channel buffer number)
685 where the data for that channel can be read/written from/to.
688 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
689 0, 1, 2, 3, 4, 5, 6, 7,
690 8, 9, 10, 11, 12, 13, 14, 15,
691 16, 17, 18, 19, 20, 21, 22, 23,
692 24, 25, 26, 27, 28, 29, 30, 31,
693 32, 33, 34, 35, 36, 37, 38, 39,
694 40, 41, 42, 43, 44, 45, 46, 47,
695 48, 49, 50, 51, 52, 53, 54, 55,
696 56, 57, 58, 59, 60, 61, 62, 63
699 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
700 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
701 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
702 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
703 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
707 -1, -1, -1, -1, -1, -1, -1, -1,
708 -1, -1, -1, -1, -1, -1, -1, -1,
709 -1, -1, -1, -1, -1, -1, -1, -1,
712 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
713 4, 5, 6, 7, /* ADAT 1 */
714 8, 9, 10, 11, /* ADAT 2 */
715 12, 13, 14, 15, /* ADAT 3 */
716 16, 17, 18, 19, /* ADAT 4 */
720 -1, -1, -1, -1, -1, -1, -1, -1,
721 -1, -1, -1, -1, -1, -1, -1, -1,
722 -1, -1, -1, -1, -1, -1, -1, -1,
723 -1, -1, -1, -1, -1, -1, -1, -1,
724 -1, -1, -1, -1, -1, -1, -1, -1,
727 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
735 -1, -1, -1, -1, -1, -1, -1, -1,
736 -1, -1, -1, -1, -1, -1, -1, -1,
737 -1, -1, -1, -1, -1, -1, -1, -1,
738 -1, -1, -1, -1, -1, -1, -1, -1,
739 -1, -1, -1, -1, -1, -1, -1, -1,
740 -1, -1, -1, -1, -1, -1, -1, -1,
743 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
746 10, 11, /* spdif in */
747 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
749 -1, -1, -1, -1, -1, -1, -1, -1,
750 -1, -1, -1, -1, -1, -1, -1, -1,
751 -1, -1, -1, -1, -1, -1, -1, -1,
752 -1, -1, -1, -1, -1, -1, -1, -1,
753 -1, -1, -1, -1, -1, -1, -1, -1,
754 -1, -1, -1, -1, -1, -1, -1, -1,
757 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
760 10, 11, /* spdif out */
761 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
762 6, 7, /* phone out */
763 -1, -1, -1, -1, -1, -1, -1, -1,
764 -1, -1, -1, -1, -1, -1, -1, -1,
765 -1, -1, -1, -1, -1, -1, -1, -1,
766 -1, -1, -1, -1, -1, -1, -1, -1,
767 -1, -1, -1, -1, -1, -1, -1, -1,
768 -1, -1, -1, -1, -1, -1, -1, -1,
771 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
774 10, 11, /* spdif in */
775 12, 14, 16, 18, /* adat in */
776 -1, -1, -1, -1, -1, -1,
777 -1, -1, -1, -1, -1, -1, -1, -1,
778 -1, -1, -1, -1, -1, -1, -1, -1,
779 -1, -1, -1, -1, -1, -1, -1, -1,
780 -1, -1, -1, -1, -1, -1, -1, -1,
781 -1, -1, -1, -1, -1, -1, -1, -1,
782 -1, -1, -1, -1, -1, -1, -1, -1
785 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
788 10, 11, /* spdif out */
789 12, 14, 16, 18, /* adat out */
790 6, 7, /* phone out */
792 -1, -1, -1, -1, -1, -1, -1, -1,
793 -1, -1, -1, -1, -1, -1, -1, -1,
794 -1, -1, -1, -1, -1, -1, -1, -1,
795 -1, -1, -1, -1, -1, -1, -1, -1,
796 -1, -1, -1, -1, -1, -1, -1, -1,
797 -1, -1, -1, -1, -1, -1, -1, -1
800 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
803 10, 11, /* spdif in */
804 12, 16, /* adat in */
805 -1, -1, -1, -1, -1, -1, -1, -1,
806 -1, -1, -1, -1, -1, -1, -1, -1,
807 -1, -1, -1, -1, -1, -1, -1, -1,
808 -1, -1, -1, -1, -1, -1, -1, -1,
809 -1, -1, -1, -1, -1, -1, -1, -1,
810 -1, -1, -1, -1, -1, -1, -1, -1,
811 -1, -1, -1, -1, -1, -1, -1, -1
814 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
817 10, 11, /* spdif out */
818 12, 16, /* adat out */
819 6, 7, /* phone out */
820 -1, -1, -1, -1, -1, -1,
821 -1, -1, -1, -1, -1, -1, -1, -1,
822 -1, -1, -1, -1, -1, -1, -1, -1,
823 -1, -1, -1, -1, -1, -1, -1, -1,
824 -1, -1, -1, -1, -1, -1, -1, -1,
825 -1, -1, -1, -1, -1, -1, -1, -1,
826 -1, -1, -1, -1, -1, -1, -1, -1
829 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
830 0, 1, 2, 3, 4, 5, 6, 7,
831 8, 9, 10, 11, 12, 13, 14, 15,
832 -1, -1, -1, -1, -1, -1, -1, -1,
833 -1, -1, -1, -1, -1, -1, -1, -1,
834 -1, -1, -1, -1, -1, -1, -1, -1,
835 -1, -1, -1, -1, -1, -1, -1, -1,
836 -1, -1, -1, -1, -1, -1, -1, -1,
837 -1, -1, -1, -1, -1, -1, -1, -1
843 struct snd_rawmidi *rmidi;
844 struct snd_rawmidi_substream *input;
845 struct snd_rawmidi_substream *output;
846 char istimer; /* timer in use */
847 struct timer_list timer;
864 int term; /* 0 = off, 1 = on */
869 /* only one playback and/or capture stream */
870 struct snd_pcm_substream *capture_substream;
871 struct snd_pcm_substream *playback_substream;
873 char *card_name; /* for procinfo */
874 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
878 int monitor_outs; /* set up monitoring outs init flag */
880 u32 control_register; /* cached value */
881 u32 control2_register; /* cached value */
882 u32 settings_register;
884 struct hdspm_midi midi[4];
885 struct tasklet_struct midi_tasklet;
888 unsigned char ss_in_channels;
889 unsigned char ds_in_channels;
890 unsigned char qs_in_channels;
891 unsigned char ss_out_channels;
892 unsigned char ds_out_channels;
893 unsigned char qs_out_channels;
895 unsigned char max_channels_in;
896 unsigned char max_channels_out;
898 char *channel_map_in;
899 char *channel_map_out;
901 char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
902 char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
904 char **port_names_in;
905 char **port_names_out;
907 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
908 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
910 unsigned char *playback_buffer; /* suitably aligned address */
911 unsigned char *capture_buffer; /* suitably aligned address */
913 pid_t capture_pid; /* process id which uses capture */
914 pid_t playback_pid; /* process id which uses capture */
915 int running; /* running status */
917 int last_external_sample_rate; /* samplerate mystic ... */
918 int last_internal_sample_rate;
919 int system_sample_rate;
921 int dev; /* Hardware vars... */
924 void __iomem *iobase;
926 int irq_count; /* for debug */
929 struct snd_card *card; /* one card */
930 struct snd_pcm *pcm; /* has one pcm */
931 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
932 struct pci_dev *pci; /* and an pci info */
935 /* fast alsa mixer */
936 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
937 /* but input to much, so not used */
938 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
939 /* full mixer accessible over mixer ioctl or hwdep-device */
940 struct hdspm_mixer *mixer;
942 struct hdspm_tco *tco; /* NULL if no TCO detected */
944 char **texts_autosync;
945 int texts_autosync_items;
947 cycles_t last_interrupt;
949 struct hdspm_peak_rms peak_rms;
953 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
955 .vendor = PCI_VENDOR_ID_XILINX,
956 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
957 .subvendor = PCI_ANY_ID,
958 .subdevice = PCI_ANY_ID,
965 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
968 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
969 struct hdspm * hdspm);
970 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
971 struct hdspm * hdspm);
973 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
974 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
975 static int hdspm_autosync_ref(struct hdspm *hdspm);
976 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
977 static void hdspm_set_sgbuf(struct hdspm *hdspm,
978 struct snd_pcm_substream *substream,
979 unsigned int reg, int channels);
981 static inline int HDSPM_bit2freq(int n)
983 static const int bit2freq_tab[] = {
984 0, 32000, 44100, 48000, 64000, 88200,
985 96000, 128000, 176400, 192000 };
988 return bit2freq_tab[n];
991 /* Write/read to/from HDSPM with Adresses in Bytes
992 not words but only 32Bit writes are allowed */
994 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
997 writel(val, hdspm->iobase + reg);
1000 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1002 return readl(hdspm->iobase + reg);
1005 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1006 mixer is write only on hardware so we have to cache him for read
1007 each fader is a u32, but uses only the first 16 bit */
1009 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1012 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1015 return hdspm->mixer->ch[chan].in[in];
1018 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1021 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1023 return hdspm->mixer->ch[chan].pb[pb];
1026 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1027 unsigned int in, unsigned short data)
1029 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1033 HDSPM_MADI_mixerBase +
1034 ((in + 128 * chan) * sizeof(u32)),
1035 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1039 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1040 unsigned int pb, unsigned short data)
1042 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1046 HDSPM_MADI_mixerBase +
1047 ((64 + pb + 128 * chan) * sizeof(u32)),
1048 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1053 /* enable DMA for specific channels, now available for DSP-MADI */
1054 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1056 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1059 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1061 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1064 /* check if same process is writing and reading */
1065 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1067 unsigned long flags;
1070 spin_lock_irqsave(&hdspm->lock, flags);
1071 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1072 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1075 spin_unlock_irqrestore(&hdspm->lock, flags);
1079 /* check for external sample rate */
1080 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1082 unsigned int status, status2, timecode;
1083 int syncref, rate = 0, rate_bits;
1085 switch (hdspm->io_type) {
1087 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1088 status = hdspm_read(hdspm, HDSPM_statusRegister);
1089 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1091 syncref = hdspm_autosync_ref(hdspm);
1093 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1094 status & HDSPM_AES32_wcLock)
1095 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1097 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1098 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1099 status2 & (HDSPM_LockAES >>
1100 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1101 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1106 status = hdspm_read(hdspm, HDSPM_statusRegister);
1108 if (!(status & HDSPM_madiLock)) {
1109 rate = 0; /* no lock */
1111 switch (status & (HDSPM_status1_freqMask)) {
1112 case HDSPM_status1_F_0*1:
1113 rate = 32000; break;
1114 case HDSPM_status1_F_0*2:
1115 rate = 44100; break;
1116 case HDSPM_status1_F_0*3:
1117 rate = 48000; break;
1118 case HDSPM_status1_F_0*4:
1119 rate = 64000; break;
1120 case HDSPM_status1_F_0*5:
1121 rate = 88200; break;
1122 case HDSPM_status1_F_0*6:
1123 rate = 96000; break;
1124 case HDSPM_status1_F_0*7:
1125 rate = 128000; break;
1126 case HDSPM_status1_F_0*8:
1127 rate = 176400; break;
1128 case HDSPM_status1_F_0*9:
1129 rate = 192000; break;
1140 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1141 status = hdspm_read(hdspm, HDSPM_statusRegister);
1144 /* if wordclock has synced freq and wordclock is valid */
1145 if ((status2 & HDSPM_wcLock) != 0 &&
1146 (status & HDSPM_SelSyncRef0) == 0) {
1148 rate_bits = status2 & HDSPM_wcFreqMask;
1151 switch (rate_bits) {
1152 case HDSPM_wcFreq32:
1155 case HDSPM_wcFreq44_1:
1158 case HDSPM_wcFreq48:
1161 case HDSPM_wcFreq64:
1164 case HDSPM_wcFreq88_2:
1167 case HDSPM_wcFreq96:
1176 /* if rate detected and Syncref is Word than have it,
1177 * word has priority to MADI
1180 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1183 /* maybe a madi input (which is taken if sel sync is madi) */
1184 if (status & HDSPM_madiLock) {
1185 rate_bits = status & HDSPM_madiFreqMask;
1187 switch (rate_bits) {
1188 case HDSPM_madiFreq32:
1191 case HDSPM_madiFreq44_1:
1194 case HDSPM_madiFreq48:
1197 case HDSPM_madiFreq64:
1200 case HDSPM_madiFreq88_2:
1203 case HDSPM_madiFreq96:
1206 case HDSPM_madiFreq128:
1209 case HDSPM_madiFreq176_4:
1212 case HDSPM_madiFreq192:
1226 /* Latency function */
1227 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1229 hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8));
1233 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1237 position = hdspm_read(hdspm, HDSPM_statusRegister);
1239 switch (hdspm->io_type) {
1242 position &= HDSPM_BufferPositionMask;
1243 position /= 4; /* Bytes per sample */
1246 position = (position & HDSPM_BufferID) ?
1247 (hdspm->period_bytes / 4) : 0;
1254 static inline void hdspm_start_audio(struct hdspm * s)
1256 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1257 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1260 static inline void hdspm_stop_audio(struct hdspm * s)
1262 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1263 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1266 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1267 static void hdspm_silence_playback(struct hdspm *hdspm)
1270 int n = hdspm->period_bytes;
1271 void *buf = hdspm->playback_buffer;
1276 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1278 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1282 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1286 spin_lock_irq(&s->lock);
1294 s->control_register &= ~HDSPM_LatencyMask;
1295 s->control_register |= hdspm_encode_latency(n);
1297 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1299 hdspm_compute_period_size(s);
1301 spin_unlock_irq(&s->lock);
1306 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1313 switch (hdspm->io_type) {
1316 freq_const = 110069313433624ULL;
1320 freq_const = 104857600000000ULL;
1323 freq_const = 131072000000000ULL;
1326 return div_u64(freq_const, period);
1330 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1336 else if (rate >= 56000)
1339 switch (hdspm->io_type) {
1341 n = 131072000000000ULL; /* 125 MHz */
1345 n = 110069313433624ULL; /* 105 MHz */
1349 n = 104857600000000ULL; /* 100 MHz */
1353 n = div_u64(n, rate);
1354 /* n should be less than 2^32 for being written to FREQ register */
1355 snd_BUG_ON(n >> 32);
1356 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1359 /* dummy set rate lets see what happens */
1360 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1365 int current_speed, target_speed;
1367 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1368 it (e.g. during module initialization).
1371 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1374 if (called_internally) {
1376 /* request from ctl or card initialization
1377 just make a warning an remember setting
1378 for future master mode switching */
1380 snd_printk(KERN_WARNING "HDSPM: "
1381 "Warning: device is not running "
1382 "as a clock master.\n");
1386 /* hw_param request while in AutoSync mode */
1388 hdspm_external_sample_rate(hdspm);
1390 if (hdspm_autosync_ref(hdspm) ==
1391 HDSPM_AUTOSYNC_FROM_NONE) {
1393 snd_printk(KERN_WARNING "HDSPM: "
1394 "Detected no Externel Sync \n");
1397 } else if (rate != external_freq) {
1399 snd_printk(KERN_WARNING "HDSPM: "
1400 "Warning: No AutoSync source for "
1401 "requested rate\n");
1407 current_rate = hdspm->system_sample_rate;
1409 /* Changing between Singe, Double and Quad speed is not
1410 allowed if any substreams are open. This is because such a change
1411 causes a shift in the location of the DMA buffers and a reduction
1412 in the number of available buffers.
1414 Note that a similar but essentially insoluble problem exists for
1415 externally-driven rate changes. All we can do is to flag rate
1416 changes in the read/write routines.
1419 if (current_rate <= 48000)
1420 current_speed = HDSPM_SPEED_SINGLE;
1421 else if (current_rate <= 96000)
1422 current_speed = HDSPM_SPEED_DOUBLE;
1424 current_speed = HDSPM_SPEED_QUAD;
1427 target_speed = HDSPM_SPEED_SINGLE;
1428 else if (rate <= 96000)
1429 target_speed = HDSPM_SPEED_DOUBLE;
1431 target_speed = HDSPM_SPEED_QUAD;
1435 rate_bits = HDSPM_Frequency32KHz;
1438 rate_bits = HDSPM_Frequency44_1KHz;
1441 rate_bits = HDSPM_Frequency48KHz;
1444 rate_bits = HDSPM_Frequency64KHz;
1447 rate_bits = HDSPM_Frequency88_2KHz;
1450 rate_bits = HDSPM_Frequency96KHz;
1453 rate_bits = HDSPM_Frequency128KHz;
1456 rate_bits = HDSPM_Frequency176_4KHz;
1459 rate_bits = HDSPM_Frequency192KHz;
1465 if (current_speed != target_speed
1466 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1469 "cannot change from %s speed to %s speed mode "
1470 "(capture PID = %d, playback PID = %d)\n",
1471 hdspm_speed_names[current_speed],
1472 hdspm_speed_names[target_speed],
1473 hdspm->capture_pid, hdspm->playback_pid);
1477 hdspm->control_register &= ~HDSPM_FrequencyMask;
1478 hdspm->control_register |= rate_bits;
1479 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1481 /* For AES32, need to set DDS value in FREQ register
1482 For MADI, also apparently */
1483 hdspm_set_dds_value(hdspm, rate);
1485 if (AES32 == hdspm->io_type && rate != current_rate)
1486 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1488 hdspm->system_sample_rate = rate;
1490 if (rate <= 48000) {
1491 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1492 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1493 hdspm->max_channels_in = hdspm->ss_in_channels;
1494 hdspm->max_channels_out = hdspm->ss_out_channels;
1495 hdspm->port_names_in = hdspm->port_names_in_ss;
1496 hdspm->port_names_out = hdspm->port_names_out_ss;
1497 } else if (rate <= 96000) {
1498 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1499 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1500 hdspm->max_channels_in = hdspm->ds_in_channels;
1501 hdspm->max_channels_out = hdspm->ds_out_channels;
1502 hdspm->port_names_in = hdspm->port_names_in_ds;
1503 hdspm->port_names_out = hdspm->port_names_out_ds;
1505 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1506 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1507 hdspm->max_channels_in = hdspm->qs_in_channels;
1508 hdspm->max_channels_out = hdspm->qs_out_channels;
1509 hdspm->port_names_in = hdspm->port_names_in_qs;
1510 hdspm->port_names_out = hdspm->port_names_out_qs;
1519 /* mainly for init to 0 on load */
1520 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1525 if (sgain > UNITY_GAIN)
1532 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1533 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1534 hdspm_write_in_gain(hdspm, i, j, gain);
1535 hdspm_write_pb_gain(hdspm, i, j, gain);
1539 /*----------------------------------------------------------------------------
1541 ----------------------------------------------------------------------------*/
1543 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1546 /* the hardware already does the relevant bit-mask with 0xff */
1547 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1550 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1553 /* the hardware already does the relevant bit-mask with 0xff */
1554 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1557 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1559 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1562 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1564 int fifo_bytes_used;
1566 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1568 if (fifo_bytes_used < 128)
1569 return 128 - fifo_bytes_used;
1574 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1576 while (snd_hdspm_midi_input_available (hdspm, id))
1577 snd_hdspm_midi_read_byte (hdspm, id);
1580 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1582 unsigned long flags;
1586 unsigned char buf[128];
1588 /* Output is not interrupt driven */
1590 spin_lock_irqsave (&hmidi->lock, flags);
1591 if (hmidi->output &&
1592 !snd_rawmidi_transmit_empty (hmidi->output)) {
1593 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1595 if (n_pending > 0) {
1596 if (n_pending > (int)sizeof (buf))
1597 n_pending = sizeof (buf);
1599 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1602 for (i = 0; i < to_write; ++i)
1603 snd_hdspm_midi_write_byte (hmidi->hdspm,
1609 spin_unlock_irqrestore (&hmidi->lock, flags);
1613 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1615 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1618 unsigned long flags;
1622 spin_lock_irqsave (&hmidi->lock, flags);
1623 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1624 if (n_pending > 0) {
1626 if (n_pending > (int)sizeof (buf))
1627 n_pending = sizeof (buf);
1628 for (i = 0; i < n_pending; ++i)
1629 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1632 snd_rawmidi_receive (hmidi->input, buf,
1635 /* flush the MIDI input FIFO */
1637 snd_hdspm_midi_read_byte (hmidi->hdspm,
1642 spin_unlock_irqrestore(&hmidi->lock, flags);
1644 spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1645 hmidi->hdspm->control_register |= hmidi->ie;
1646 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1647 hmidi->hdspm->control_register);
1648 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1650 return snd_hdspm_midi_output_write (hmidi);
1654 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1656 struct hdspm *hdspm;
1657 struct hdspm_midi *hmidi;
1658 unsigned long flags;
1660 hmidi = substream->rmidi->private_data;
1661 hdspm = hmidi->hdspm;
1663 spin_lock_irqsave (&hdspm->lock, flags);
1665 if (!(hdspm->control_register & hmidi->ie)) {
1666 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1667 hdspm->control_register |= hmidi->ie;
1670 hdspm->control_register &= ~hmidi->ie;
1673 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1674 spin_unlock_irqrestore (&hdspm->lock, flags);
1677 static void snd_hdspm_midi_output_timer(unsigned long data)
1679 struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1680 unsigned long flags;
1682 snd_hdspm_midi_output_write(hmidi);
1683 spin_lock_irqsave (&hmidi->lock, flags);
1685 /* this does not bump hmidi->istimer, because the
1686 kernel automatically removed the timer when it
1687 expired, and we are now adding it back, thus
1688 leaving istimer wherever it was set before.
1691 if (hmidi->istimer) {
1692 hmidi->timer.expires = 1 + jiffies;
1693 add_timer(&hmidi->timer);
1696 spin_unlock_irqrestore (&hmidi->lock, flags);
1700 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1702 struct hdspm_midi *hmidi;
1703 unsigned long flags;
1705 hmidi = substream->rmidi->private_data;
1706 spin_lock_irqsave (&hmidi->lock, flags);
1708 if (!hmidi->istimer) {
1709 init_timer(&hmidi->timer);
1710 hmidi->timer.function = snd_hdspm_midi_output_timer;
1711 hmidi->timer.data = (unsigned long) hmidi;
1712 hmidi->timer.expires = 1 + jiffies;
1713 add_timer(&hmidi->timer);
1717 if (hmidi->istimer && --hmidi->istimer <= 0)
1718 del_timer (&hmidi->timer);
1720 spin_unlock_irqrestore (&hmidi->lock, flags);
1722 snd_hdspm_midi_output_write(hmidi);
1725 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1727 struct hdspm_midi *hmidi;
1729 hmidi = substream->rmidi->private_data;
1730 spin_lock_irq (&hmidi->lock);
1731 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1732 hmidi->input = substream;
1733 spin_unlock_irq (&hmidi->lock);
1738 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1740 struct hdspm_midi *hmidi;
1742 hmidi = substream->rmidi->private_data;
1743 spin_lock_irq (&hmidi->lock);
1744 hmidi->output = substream;
1745 spin_unlock_irq (&hmidi->lock);
1750 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1752 struct hdspm_midi *hmidi;
1754 snd_hdspm_midi_input_trigger (substream, 0);
1756 hmidi = substream->rmidi->private_data;
1757 spin_lock_irq (&hmidi->lock);
1758 hmidi->input = NULL;
1759 spin_unlock_irq (&hmidi->lock);
1764 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1766 struct hdspm_midi *hmidi;
1768 snd_hdspm_midi_output_trigger (substream, 0);
1770 hmidi = substream->rmidi->private_data;
1771 spin_lock_irq (&hmidi->lock);
1772 hmidi->output = NULL;
1773 spin_unlock_irq (&hmidi->lock);
1778 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1780 .open = snd_hdspm_midi_output_open,
1781 .close = snd_hdspm_midi_output_close,
1782 .trigger = snd_hdspm_midi_output_trigger,
1785 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1787 .open = snd_hdspm_midi_input_open,
1788 .close = snd_hdspm_midi_input_close,
1789 .trigger = snd_hdspm_midi_input_trigger,
1792 static int __devinit snd_hdspm_create_midi (struct snd_card *card,
1793 struct hdspm *hdspm, int id)
1798 hdspm->midi[id].id = id;
1799 hdspm->midi[id].hdspm = hdspm;
1800 spin_lock_init (&hdspm->midi[id].lock);
1803 if (MADIface == hdspm->io_type) {
1804 /* MIDI-over-MADI on HDSPe MADIface */
1805 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1806 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1807 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1808 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1809 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1810 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1812 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1813 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1814 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1815 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1816 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1817 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1819 } else if (1 == id) {
1820 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1821 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1822 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1823 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1824 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1825 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1826 } else if ((2 == id) && (MADI == hdspm->io_type)) {
1827 /* MIDI-over-MADI on HDSPe MADI */
1828 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1829 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1830 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1831 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1832 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1833 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1834 } else if (2 == id) {
1835 /* TCO MTC, read only */
1836 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1837 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1838 hdspm->midi[2].dataOut = -1;
1839 hdspm->midi[2].statusOut = -1;
1840 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1841 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
1842 } else if (3 == id) {
1843 /* TCO MTC on HDSPe MADI */
1844 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
1845 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
1846 hdspm->midi[3].dataOut = -1;
1847 hdspm->midi[3].statusOut = -1;
1848 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
1849 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
1852 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
1853 (MADIface == hdspm->io_type)))) {
1854 if ((id == 0) && (MADIface == hdspm->io_type)) {
1855 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1856 } else if ((id == 2) && (MADI == hdspm->io_type)) {
1857 sprintf(buf, "%s MIDIoverMADI", card->shortname);
1859 sprintf(buf, "%s MIDI %d", card->shortname, id+1);
1861 err = snd_rawmidi_new(card, buf, id, 1, 1,
1862 &hdspm->midi[id].rmidi);
1866 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
1868 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1870 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1871 SNDRV_RAWMIDI_STREAM_OUTPUT,
1872 &snd_hdspm_midi_output);
1873 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1874 SNDRV_RAWMIDI_STREAM_INPUT,
1875 &snd_hdspm_midi_input);
1877 hdspm->midi[id].rmidi->info_flags |=
1878 SNDRV_RAWMIDI_INFO_OUTPUT |
1879 SNDRV_RAWMIDI_INFO_INPUT |
1880 SNDRV_RAWMIDI_INFO_DUPLEX;
1882 /* TCO MTC, read only */
1883 sprintf(buf, "%s MTC %d", card->shortname, id+1);
1884 err = snd_rawmidi_new(card, buf, id, 1, 1,
1885 &hdspm->midi[id].rmidi);
1889 sprintf(hdspm->midi[id].rmidi->name,
1890 "%s MTC %d", card->id, id+1);
1891 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
1893 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
1894 SNDRV_RAWMIDI_STREAM_INPUT,
1895 &snd_hdspm_midi_input);
1897 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
1904 static void hdspm_midi_tasklet(unsigned long arg)
1906 struct hdspm *hdspm = (struct hdspm *)arg;
1909 while (i < hdspm->midiPorts) {
1910 if (hdspm->midi[i].pending)
1911 snd_hdspm_midi_input_read(&hdspm->midi[i]);
1918 /*-----------------------------------------------------------------------------
1920 ----------------------------------------------------------------------------*/
1922 /* get the system sample rate which is set */
1926 * Calculate the real sample rate from the
1927 * current DDS value.
1929 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
1931 unsigned int period, rate;
1933 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
1934 rate = hdspm_calc_dds_value(hdspm, period);
1940 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
1941 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1944 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1945 .info = snd_hdspm_info_system_sample_rate, \
1946 .get = snd_hdspm_get_system_sample_rate \
1949 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
1950 struct snd_ctl_elem_info *uinfo)
1952 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1954 uinfo->value.integer.min = 27000;
1955 uinfo->value.integer.max = 207000;
1956 uinfo->value.integer.step = 1;
1961 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
1962 struct snd_ctl_elem_value *
1965 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
1967 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
1973 * Returns the WordClock sample rate class for the given card.
1975 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
1979 switch (hdspm->io_type) {
1982 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
1983 return (status >> 16) & 0xF;
1995 * Returns the TCO sample rate class for the given card.
1997 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2002 switch (hdspm->io_type) {
2005 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2006 return (status >> 20) & 0xF;
2018 * Returns the SYNC_IN sample rate class for the given card.
2020 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2025 switch (hdspm->io_type) {
2028 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2029 return (status >> 12) & 0xF;
2041 * Returns the sample rate class for input source <idx> for
2042 * 'new style' cards like the AIO and RayDAT.
2044 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2046 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2048 return (status >> (idx*4)) & 0xF;
2053 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2054 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2056 .private_value = xindex, \
2057 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2058 .info = snd_hdspm_info_autosync_sample_rate, \
2059 .get = snd_hdspm_get_autosync_sample_rate \
2063 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2064 struct snd_ctl_elem_info *uinfo)
2066 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2068 uinfo->value.enumerated.items = 10;
2070 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2071 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2072 strcpy(uinfo->value.enumerated.name,
2073 texts_freq[uinfo->value.enumerated.item]);
2078 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2079 struct snd_ctl_elem_value *
2082 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2084 switch (hdspm->io_type) {
2086 switch (kcontrol->private_value) {
2088 ucontrol->value.enumerated.item[0] =
2089 hdspm_get_wc_sample_rate(hdspm);
2092 ucontrol->value.enumerated.item[0] =
2093 hdspm_get_tco_sample_rate(hdspm);
2096 ucontrol->value.enumerated.item[0] =
2097 hdspm_get_sync_in_sample_rate(hdspm);
2100 ucontrol->value.enumerated.item[0] =
2101 hdspm_get_s1_sample_rate(hdspm,
2102 kcontrol->private_value-1);
2106 switch (kcontrol->private_value) {
2108 ucontrol->value.enumerated.item[0] =
2109 hdspm_get_wc_sample_rate(hdspm);
2112 ucontrol->value.enumerated.item[0] =
2113 hdspm_get_tco_sample_rate(hdspm);
2115 case 5: /* SYNC_IN */
2116 ucontrol->value.enumerated.item[0] =
2117 hdspm_get_sync_in_sample_rate(hdspm);
2120 ucontrol->value.enumerated.item[0] =
2121 hdspm_get_s1_sample_rate(hdspm,
2122 ucontrol->id.index-1);
2127 switch (kcontrol->private_value) {
2129 ucontrol->value.enumerated.item[0] =
2130 hdspm_get_wc_sample_rate(hdspm);
2133 ucontrol->value.enumerated.item[0] =
2134 hdspm_get_tco_sample_rate(hdspm);
2136 case 10: /* SYNC_IN */
2137 ucontrol->value.enumerated.item[0] =
2138 hdspm_get_sync_in_sample_rate(hdspm);
2140 default: /* AES1 to AES8 */
2141 ucontrol->value.enumerated.item[0] =
2142 hdspm_get_s1_sample_rate(hdspm,
2143 kcontrol->private_value-1);
2155 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2156 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2159 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2160 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2161 .info = snd_hdspm_info_system_clock_mode, \
2162 .get = snd_hdspm_get_system_clock_mode, \
2163 .put = snd_hdspm_put_system_clock_mode, \
2168 * Returns the system clock mode for the given card.
2169 * @returns 0 - master, 1 - slave
2171 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2173 switch (hdspm->io_type) {
2176 if (hdspm->settings_register & HDSPM_c0Master)
2181 if (hdspm->control_register & HDSPM_ClockModeMaster)
2190 * Sets the system clock mode.
2191 * @param mode 0 - master, 1 - slave
2193 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2195 switch (hdspm->io_type) {
2199 hdspm->settings_register |= HDSPM_c0Master;
2201 hdspm->settings_register &= ~HDSPM_c0Master;
2203 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2208 hdspm->control_register |= HDSPM_ClockModeMaster;
2210 hdspm->control_register &= ~HDSPM_ClockModeMaster;
2212 hdspm_write(hdspm, HDSPM_controlRegister,
2213 hdspm->control_register);
2218 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2219 struct snd_ctl_elem_info *uinfo)
2221 static char *texts[] = { "Master", "AutoSync" };
2223 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2225 uinfo->value.enumerated.items = 2;
2226 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2227 uinfo->value.enumerated.item =
2228 uinfo->value.enumerated.items - 1;
2229 strcpy(uinfo->value.enumerated.name,
2230 texts[uinfo->value.enumerated.item]);
2234 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2235 struct snd_ctl_elem_value *ucontrol)
2237 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2239 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2243 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2244 struct snd_ctl_elem_value *ucontrol)
2246 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2249 if (!snd_hdspm_use_is_exclusive(hdspm))
2252 val = ucontrol->value.enumerated.item[0];
2258 hdspm_set_system_clock_mode(hdspm, val);
2264 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2265 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2268 .info = snd_hdspm_info_clock_source, \
2269 .get = snd_hdspm_get_clock_source, \
2270 .put = snd_hdspm_put_clock_source \
2274 static int hdspm_clock_source(struct hdspm * hdspm)
2276 switch (hdspm->system_sample_rate) {
2277 case 32000: return 0;
2278 case 44100: return 1;
2279 case 48000: return 2;
2280 case 64000: return 3;
2281 case 88200: return 4;
2282 case 96000: return 5;
2283 case 128000: return 6;
2284 case 176400: return 7;
2285 case 192000: return 8;
2291 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2296 rate = 32000; break;
2298 rate = 44100; break;
2300 rate = 48000; break;
2302 rate = 64000; break;
2304 rate = 88200; break;
2306 rate = 96000; break;
2308 rate = 128000; break;
2310 rate = 176400; break;
2312 rate = 192000; break;
2316 hdspm_set_rate(hdspm, rate, 1);
2320 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2321 struct snd_ctl_elem_info *uinfo)
2323 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2325 uinfo->value.enumerated.items = 9;
2327 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2328 uinfo->value.enumerated.item =
2329 uinfo->value.enumerated.items - 1;
2331 strcpy(uinfo->value.enumerated.name,
2332 texts_freq[uinfo->value.enumerated.item+1]);
2337 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2338 struct snd_ctl_elem_value *ucontrol)
2340 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2342 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2346 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2347 struct snd_ctl_elem_value *ucontrol)
2349 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2353 if (!snd_hdspm_use_is_exclusive(hdspm))
2355 val = ucontrol->value.enumerated.item[0];
2360 spin_lock_irq(&hdspm->lock);
2361 if (val != hdspm_clock_source(hdspm))
2362 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2365 spin_unlock_irq(&hdspm->lock);
2370 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2371 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2374 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2375 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2376 .info = snd_hdspm_info_pref_sync_ref, \
2377 .get = snd_hdspm_get_pref_sync_ref, \
2378 .put = snd_hdspm_put_pref_sync_ref \
2383 * Returns the current preferred sync reference setting.
2384 * The semantics of the return value are depending on the
2385 * card, please see the comments for clarification.
2387 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2389 switch (hdspm->io_type) {
2391 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2392 case 0: return 0; /* WC */
2393 case HDSPM_SyncRef0: return 1; /* AES 1 */
2394 case HDSPM_SyncRef1: return 2; /* AES 2 */
2395 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2396 case HDSPM_SyncRef2: return 4; /* AES 4 */
2397 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2398 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2399 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2400 return 7; /* AES 7 */
2401 case HDSPM_SyncRef3: return 8; /* AES 8 */
2402 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2409 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2410 case 0: return 0; /* WC */
2411 case HDSPM_SyncRef0: return 1; /* MADI */
2412 case HDSPM_SyncRef1: return 2; /* TCO */
2413 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2414 return 3; /* SYNC_IN */
2417 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2418 case 0: return 0; /* WC */
2419 case HDSPM_SyncRef0: return 1; /* MADI */
2420 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2421 return 2; /* SYNC_IN */
2428 switch ((hdspm->settings_register &
2429 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2430 case 0: return 0; /* WC */
2431 case 3: return 1; /* ADAT 1 */
2432 case 4: return 2; /* ADAT 2 */
2433 case 5: return 3; /* ADAT 3 */
2434 case 6: return 4; /* ADAT 4 */
2435 case 1: return 5; /* AES */
2436 case 2: return 6; /* SPDIF */
2437 case 9: return 7; /* TCO */
2438 case 10: return 8; /* SYNC_IN */
2441 switch ((hdspm->settings_register &
2442 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2443 case 0: return 0; /* WC */
2444 case 3: return 1; /* ADAT 1 */
2445 case 4: return 2; /* ADAT 2 */
2446 case 5: return 3; /* ADAT 3 */
2447 case 6: return 4; /* ADAT 4 */
2448 case 1: return 5; /* AES */
2449 case 2: return 6; /* SPDIF */
2450 case 10: return 7; /* SYNC_IN */
2458 switch ((hdspm->settings_register &
2459 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2460 case 0: return 0; /* WC */
2461 case 3: return 1; /* ADAT */
2462 case 1: return 2; /* AES */
2463 case 2: return 3; /* SPDIF */
2464 case 9: return 4; /* TCO */
2465 case 10: return 5; /* SYNC_IN */
2468 switch ((hdspm->settings_register &
2469 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2470 case 0: return 0; /* WC */
2471 case 3: return 1; /* ADAT */
2472 case 1: return 2; /* AES */
2473 case 2: return 3; /* SPDIF */
2474 case 10: return 4; /* SYNC_IN */
2486 * Set the preferred sync reference to <pref>. The semantics
2487 * of <pref> are depending on the card type, see the comments
2488 * for clarification.
2490 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2494 switch (hdspm->io_type) {
2496 hdspm->control_register &= ~HDSPM_SyncRefMask;
2501 hdspm->control_register |= HDSPM_SyncRef0;
2504 hdspm->control_register |= HDSPM_SyncRef1;
2507 hdspm->control_register |=
2508 HDSPM_SyncRef1+HDSPM_SyncRef0;
2511 hdspm->control_register |= HDSPM_SyncRef2;
2514 hdspm->control_register |=
2515 HDSPM_SyncRef2+HDSPM_SyncRef0;
2518 hdspm->control_register |=
2519 HDSPM_SyncRef2+HDSPM_SyncRef1;
2522 hdspm->control_register |=
2523 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2526 hdspm->control_register |= HDSPM_SyncRef3;
2529 hdspm->control_register |=
2530 HDSPM_SyncRef3+HDSPM_SyncRef0;
2540 hdspm->control_register &= ~HDSPM_SyncRefMask;
2546 hdspm->control_register |= HDSPM_SyncRef0;
2549 hdspm->control_register |= HDSPM_SyncRef1;
2551 case 3: /* SYNC_IN */
2552 hdspm->control_register |=
2553 HDSPM_SyncRef0+HDSPM_SyncRef1;
2563 hdspm->control_register |= HDSPM_SyncRef0;
2565 case 2: /* SYNC_IN */
2566 hdspm->control_register |=
2567 HDSPM_SyncRef0+HDSPM_SyncRef1;
2579 case 0: p = 0; break; /* WC */
2580 case 1: p = 3; break; /* ADAT 1 */
2581 case 2: p = 4; break; /* ADAT 2 */
2582 case 3: p = 5; break; /* ADAT 3 */
2583 case 4: p = 6; break; /* ADAT 4 */
2584 case 5: p = 1; break; /* AES */
2585 case 6: p = 2; break; /* SPDIF */
2586 case 7: p = 9; break; /* TCO */
2587 case 8: p = 10; break; /* SYNC_IN */
2592 case 0: p = 0; break; /* WC */
2593 case 1: p = 3; break; /* ADAT 1 */
2594 case 2: p = 4; break; /* ADAT 2 */
2595 case 3: p = 5; break; /* ADAT 3 */
2596 case 4: p = 6; break; /* ADAT 4 */
2597 case 5: p = 1; break; /* AES */
2598 case 6: p = 2; break; /* SPDIF */
2599 case 7: p = 10; break; /* SYNC_IN */
2608 case 0: p = 0; break; /* WC */
2609 case 1: p = 3; break; /* ADAT */
2610 case 2: p = 1; break; /* AES */
2611 case 3: p = 2; break; /* SPDIF */
2612 case 4: p = 9; break; /* TCO */
2613 case 5: p = 10; break; /* SYNC_IN */
2618 case 0: p = 0; break; /* WC */
2619 case 1: p = 3; break; /* ADAT */
2620 case 2: p = 1; break; /* AES */
2621 case 3: p = 2; break; /* SPDIF */
2622 case 4: p = 10; break; /* SYNC_IN */
2629 switch (hdspm->io_type) {
2632 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2633 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2634 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2640 hdspm_write(hdspm, HDSPM_controlRegister,
2641 hdspm->control_register);
2648 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2649 struct snd_ctl_elem_info *uinfo)
2651 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2653 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2655 uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2657 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2658 uinfo->value.enumerated.item =
2659 uinfo->value.enumerated.items - 1;
2661 strcpy(uinfo->value.enumerated.name,
2662 hdspm->texts_autosync[uinfo->value.enumerated.item]);
2667 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2668 struct snd_ctl_elem_value *ucontrol)
2670 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2671 int psf = hdspm_pref_sync_ref(hdspm);
2674 ucontrol->value.enumerated.item[0] = psf;
2681 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2682 struct snd_ctl_elem_value *ucontrol)
2684 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2685 int val, change = 0;
2687 if (!snd_hdspm_use_is_exclusive(hdspm))
2690 val = ucontrol->value.enumerated.item[0];
2694 else if (val >= hdspm->texts_autosync_items)
2695 val = hdspm->texts_autosync_items-1;
2697 spin_lock_irq(&hdspm->lock);
2698 if (val != hdspm_pref_sync_ref(hdspm))
2699 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2701 spin_unlock_irq(&hdspm->lock);
2706 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2707 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2710 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2711 .info = snd_hdspm_info_autosync_ref, \
2712 .get = snd_hdspm_get_autosync_ref, \
2715 static int hdspm_autosync_ref(struct hdspm *hdspm)
2717 if (AES32 == hdspm->io_type) {
2718 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2719 unsigned int syncref =
2720 (status >> HDSPM_AES32_syncref_bit) & 0xF;
2722 return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2725 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2726 } else if (MADI == hdspm->io_type) {
2727 /* This looks at the autosync selected sync reference */
2728 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2730 switch (status2 & HDSPM_SelSyncRefMask) {
2731 case HDSPM_SelSyncRef_WORD:
2732 return HDSPM_AUTOSYNC_FROM_WORD;
2733 case HDSPM_SelSyncRef_MADI:
2734 return HDSPM_AUTOSYNC_FROM_MADI;
2735 case HDSPM_SelSyncRef_TCO:
2736 return HDSPM_AUTOSYNC_FROM_TCO;
2737 case HDSPM_SelSyncRef_SyncIn:
2738 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2739 case HDSPM_SelSyncRef_NVALID:
2740 return HDSPM_AUTOSYNC_FROM_NONE;
2750 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2751 struct snd_ctl_elem_info *uinfo)
2753 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2755 if (AES32 == hdspm->io_type) {
2756 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2757 "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2759 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2761 uinfo->value.enumerated.items = 10;
2762 if (uinfo->value.enumerated.item >=
2763 uinfo->value.enumerated.items)
2764 uinfo->value.enumerated.item =
2765 uinfo->value.enumerated.items - 1;
2766 strcpy(uinfo->value.enumerated.name,
2767 texts[uinfo->value.enumerated.item]);
2768 } else if (MADI == hdspm->io_type) {
2769 static char *texts[] = {"Word Clock", "MADI", "TCO",
2770 "Sync In", "None" };
2772 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2774 uinfo->value.enumerated.items = 5;
2775 if (uinfo->value.enumerated.item >=
2776 uinfo->value.enumerated.items)
2777 uinfo->value.enumerated.item =
2778 uinfo->value.enumerated.items - 1;
2779 strcpy(uinfo->value.enumerated.name,
2780 texts[uinfo->value.enumerated.item]);
2785 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
2786 struct snd_ctl_elem_value *ucontrol)
2788 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2790 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
2795 #define HDSPM_LINE_OUT(xname, xindex) \
2796 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2799 .info = snd_hdspm_info_line_out, \
2800 .get = snd_hdspm_get_line_out, \
2801 .put = snd_hdspm_put_line_out \
2804 static int hdspm_line_out(struct hdspm * hdspm)
2806 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0;
2810 static int hdspm_set_line_output(struct hdspm * hdspm, int out)
2813 hdspm->control_register |= HDSPM_LineOut;
2815 hdspm->control_register &= ~HDSPM_LineOut;
2816 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2821 #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info
2823 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol,
2824 struct snd_ctl_elem_value *ucontrol)
2826 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2828 spin_lock_irq(&hdspm->lock);
2829 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm);
2830 spin_unlock_irq(&hdspm->lock);
2834 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol,
2835 struct snd_ctl_elem_value *ucontrol)
2837 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2841 if (!snd_hdspm_use_is_exclusive(hdspm))
2843 val = ucontrol->value.integer.value[0] & 1;
2844 spin_lock_irq(&hdspm->lock);
2845 change = (int) val != hdspm_line_out(hdspm);
2846 hdspm_set_line_output(hdspm, val);
2847 spin_unlock_irq(&hdspm->lock);
2852 #define HDSPM_TX_64(xname, xindex) \
2853 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2856 .info = snd_hdspm_info_tx_64, \
2857 .get = snd_hdspm_get_tx_64, \
2858 .put = snd_hdspm_put_tx_64 \
2861 static int hdspm_tx_64(struct hdspm * hdspm)
2863 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0;
2866 static int hdspm_set_tx_64(struct hdspm * hdspm, int out)
2869 hdspm->control_register |= HDSPM_TX_64ch;
2871 hdspm->control_register &= ~HDSPM_TX_64ch;
2872 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2877 #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info
2879 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol,
2880 struct snd_ctl_elem_value *ucontrol)
2882 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2884 spin_lock_irq(&hdspm->lock);
2885 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm);
2886 spin_unlock_irq(&hdspm->lock);
2890 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol,
2891 struct snd_ctl_elem_value *ucontrol)
2893 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2897 if (!snd_hdspm_use_is_exclusive(hdspm))
2899 val = ucontrol->value.integer.value[0] & 1;
2900 spin_lock_irq(&hdspm->lock);
2901 change = (int) val != hdspm_tx_64(hdspm);
2902 hdspm_set_tx_64(hdspm, val);
2903 spin_unlock_irq(&hdspm->lock);
2908 #define HDSPM_C_TMS(xname, xindex) \
2909 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2912 .info = snd_hdspm_info_c_tms, \
2913 .get = snd_hdspm_get_c_tms, \
2914 .put = snd_hdspm_put_c_tms \
2917 static int hdspm_c_tms(struct hdspm * hdspm)
2919 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0;
2922 static int hdspm_set_c_tms(struct hdspm * hdspm, int out)
2925 hdspm->control_register |= HDSPM_clr_tms;
2927 hdspm->control_register &= ~HDSPM_clr_tms;
2928 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2933 #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info
2935 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol,
2936 struct snd_ctl_elem_value *ucontrol)
2938 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2940 spin_lock_irq(&hdspm->lock);
2941 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm);
2942 spin_unlock_irq(&hdspm->lock);
2946 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol,
2947 struct snd_ctl_elem_value *ucontrol)
2949 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2953 if (!snd_hdspm_use_is_exclusive(hdspm))
2955 val = ucontrol->value.integer.value[0] & 1;
2956 spin_lock_irq(&hdspm->lock);
2957 change = (int) val != hdspm_c_tms(hdspm);
2958 hdspm_set_c_tms(hdspm, val);
2959 spin_unlock_irq(&hdspm->lock);
2964 #define HDSPM_SAFE_MODE(xname, xindex) \
2965 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2968 .info = snd_hdspm_info_safe_mode, \
2969 .get = snd_hdspm_get_safe_mode, \
2970 .put = snd_hdspm_put_safe_mode \
2973 static int hdspm_safe_mode(struct hdspm * hdspm)
2975 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0;
2978 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out)
2981 hdspm->control_register |= HDSPM_AutoInp;
2983 hdspm->control_register &= ~HDSPM_AutoInp;
2984 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
2989 #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info
2991 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol,
2992 struct snd_ctl_elem_value *ucontrol)
2994 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2996 spin_lock_irq(&hdspm->lock);
2997 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm);
2998 spin_unlock_irq(&hdspm->lock);
3002 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol,
3003 struct snd_ctl_elem_value *ucontrol)
3005 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3009 if (!snd_hdspm_use_is_exclusive(hdspm))
3011 val = ucontrol->value.integer.value[0] & 1;
3012 spin_lock_irq(&hdspm->lock);
3013 change = (int) val != hdspm_safe_mode(hdspm);
3014 hdspm_set_safe_mode(hdspm, val);
3015 spin_unlock_irq(&hdspm->lock);
3020 #define HDSPM_EMPHASIS(xname, xindex) \
3021 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3024 .info = snd_hdspm_info_emphasis, \
3025 .get = snd_hdspm_get_emphasis, \
3026 .put = snd_hdspm_put_emphasis \
3029 static int hdspm_emphasis(struct hdspm * hdspm)
3031 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0;
3034 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp)
3037 hdspm->control_register |= HDSPM_Emphasis;
3039 hdspm->control_register &= ~HDSPM_Emphasis;
3040 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3045 #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info
3047 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol,
3048 struct snd_ctl_elem_value *ucontrol)
3050 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3052 spin_lock_irq(&hdspm->lock);
3053 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm);
3054 spin_unlock_irq(&hdspm->lock);
3058 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol,
3059 struct snd_ctl_elem_value *ucontrol)
3061 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3065 if (!snd_hdspm_use_is_exclusive(hdspm))
3067 val = ucontrol->value.integer.value[0] & 1;
3068 spin_lock_irq(&hdspm->lock);
3069 change = (int) val != hdspm_emphasis(hdspm);
3070 hdspm_set_emphasis(hdspm, val);
3071 spin_unlock_irq(&hdspm->lock);
3076 #define HDSPM_DOLBY(xname, xindex) \
3077 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3080 .info = snd_hdspm_info_dolby, \
3081 .get = snd_hdspm_get_dolby, \
3082 .put = snd_hdspm_put_dolby \
3085 static int hdspm_dolby(struct hdspm * hdspm)
3087 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0;
3090 static int hdspm_set_dolby(struct hdspm * hdspm, int dol)
3093 hdspm->control_register |= HDSPM_Dolby;
3095 hdspm->control_register &= ~HDSPM_Dolby;
3096 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3101 #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info
3103 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol,
3104 struct snd_ctl_elem_value *ucontrol)
3106 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3108 spin_lock_irq(&hdspm->lock);
3109 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm);
3110 spin_unlock_irq(&hdspm->lock);
3114 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol,
3115 struct snd_ctl_elem_value *ucontrol)
3117 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3121 if (!snd_hdspm_use_is_exclusive(hdspm))
3123 val = ucontrol->value.integer.value[0] & 1;
3124 spin_lock_irq(&hdspm->lock);
3125 change = (int) val != hdspm_dolby(hdspm);
3126 hdspm_set_dolby(hdspm, val);
3127 spin_unlock_irq(&hdspm->lock);
3132 #define HDSPM_PROFESSIONAL(xname, xindex) \
3133 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3136 .info = snd_hdspm_info_professional, \
3137 .get = snd_hdspm_get_professional, \
3138 .put = snd_hdspm_put_professional \
3141 static int hdspm_professional(struct hdspm * hdspm)
3143 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0;
3146 static int hdspm_set_professional(struct hdspm * hdspm, int dol)
3149 hdspm->control_register |= HDSPM_Professional;
3151 hdspm->control_register &= ~HDSPM_Professional;
3152 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3157 #define snd_hdspm_info_professional snd_ctl_boolean_mono_info
3159 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol,
3160 struct snd_ctl_elem_value *ucontrol)
3162 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3164 spin_lock_irq(&hdspm->lock);
3165 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm);
3166 spin_unlock_irq(&hdspm->lock);
3170 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol,
3171 struct snd_ctl_elem_value *ucontrol)
3173 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3177 if (!snd_hdspm_use_is_exclusive(hdspm))
3179 val = ucontrol->value.integer.value[0] & 1;
3180 spin_lock_irq(&hdspm->lock);
3181 change = (int) val != hdspm_professional(hdspm);
3182 hdspm_set_professional(hdspm, val);
3183 spin_unlock_irq(&hdspm->lock);
3187 #define HDSPM_INPUT_SELECT(xname, xindex) \
3188 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3191 .info = snd_hdspm_info_input_select, \
3192 .get = snd_hdspm_get_input_select, \
3193 .put = snd_hdspm_put_input_select \
3196 static int hdspm_input_select(struct hdspm * hdspm)
3198 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3201 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3204 hdspm->control_register |= HDSPM_InputSelect0;
3206 hdspm->control_register &= ~HDSPM_InputSelect0;
3207 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3212 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3213 struct snd_ctl_elem_info *uinfo)
3215 static char *texts[] = { "optical", "coaxial" };
3217 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3219 uinfo->value.enumerated.items = 2;
3221 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3222 uinfo->value.enumerated.item =
3223 uinfo->value.enumerated.items - 1;
3224 strcpy(uinfo->value.enumerated.name,
3225 texts[uinfo->value.enumerated.item]);
3230 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3231 struct snd_ctl_elem_value *ucontrol)
3233 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3235 spin_lock_irq(&hdspm->lock);
3236 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3237 spin_unlock_irq(&hdspm->lock);
3241 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3242 struct snd_ctl_elem_value *ucontrol)
3244 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3248 if (!snd_hdspm_use_is_exclusive(hdspm))
3250 val = ucontrol->value.integer.value[0] & 1;
3251 spin_lock_irq(&hdspm->lock);
3252 change = (int) val != hdspm_input_select(hdspm);
3253 hdspm_set_input_select(hdspm, val);
3254 spin_unlock_irq(&hdspm->lock);
3259 #define HDSPM_DS_WIRE(xname, xindex) \
3260 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3263 .info = snd_hdspm_info_ds_wire, \
3264 .get = snd_hdspm_get_ds_wire, \
3265 .put = snd_hdspm_put_ds_wire \
3268 static int hdspm_ds_wire(struct hdspm * hdspm)
3270 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3273 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3276 hdspm->control_register |= HDSPM_DS_DoubleWire;
3278 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3279 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3284 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3285 struct snd_ctl_elem_info *uinfo)
3287 static char *texts[] = { "Single", "Double" };
3289 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3291 uinfo->value.enumerated.items = 2;
3293 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3294 uinfo->value.enumerated.item =
3295 uinfo->value.enumerated.items - 1;
3296 strcpy(uinfo->value.enumerated.name,
3297 texts[uinfo->value.enumerated.item]);
3302 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3303 struct snd_ctl_elem_value *ucontrol)
3305 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3307 spin_lock_irq(&hdspm->lock);
3308 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3309 spin_unlock_irq(&hdspm->lock);
3313 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3314 struct snd_ctl_elem_value *ucontrol)
3316 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3320 if (!snd_hdspm_use_is_exclusive(hdspm))
3322 val = ucontrol->value.integer.value[0] & 1;
3323 spin_lock_irq(&hdspm->lock);
3324 change = (int) val != hdspm_ds_wire(hdspm);
3325 hdspm_set_ds_wire(hdspm, val);
3326 spin_unlock_irq(&hdspm->lock);
3331 #define HDSPM_QS_WIRE(xname, xindex) \
3332 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3335 .info = snd_hdspm_info_qs_wire, \
3336 .get = snd_hdspm_get_qs_wire, \
3337 .put = snd_hdspm_put_qs_wire \
3340 static int hdspm_qs_wire(struct hdspm * hdspm)
3342 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3344 if (hdspm->control_register & HDSPM_QS_QuadWire)
3349 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3351 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3356 hdspm->control_register |= HDSPM_QS_DoubleWire;
3359 hdspm->control_register |= HDSPM_QS_QuadWire;
3362 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3367 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3368 struct snd_ctl_elem_info *uinfo)
3370 static char *texts[] = { "Single", "Double", "Quad" };
3372 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3374 uinfo->value.enumerated.items = 3;
3376 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3377 uinfo->value.enumerated.item =
3378 uinfo->value.enumerated.items - 1;
3379 strcpy(uinfo->value.enumerated.name,
3380 texts[uinfo->value.enumerated.item]);
3385 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3386 struct snd_ctl_elem_value *ucontrol)
3388 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3390 spin_lock_irq(&hdspm->lock);
3391 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3392 spin_unlock_irq(&hdspm->lock);
3396 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3397 struct snd_ctl_elem_value *ucontrol)
3399 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3403 if (!snd_hdspm_use_is_exclusive(hdspm))
3405 val = ucontrol->value.integer.value[0];
3410 spin_lock_irq(&hdspm->lock);
3411 change = val != hdspm_qs_wire(hdspm);
3412 hdspm_set_qs_wire(hdspm, val);
3413 spin_unlock_irq(&hdspm->lock);
3418 #define HDSPM_MIXER(xname, xindex) \
3419 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3423 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3424 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3425 .info = snd_hdspm_info_mixer, \
3426 .get = snd_hdspm_get_mixer, \
3427 .put = snd_hdspm_put_mixer \
3430 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3431 struct snd_ctl_elem_info *uinfo)
3433 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3435 uinfo->value.integer.min = 0;
3436 uinfo->value.integer.max = 65535;
3437 uinfo->value.integer.step = 1;
3441 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3442 struct snd_ctl_elem_value *ucontrol)
3444 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3448 source = ucontrol->value.integer.value[0];
3451 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3452 source = 2 * HDSPM_MAX_CHANNELS - 1;
3454 destination = ucontrol->value.integer.value[1];
3455 if (destination < 0)
3457 else if (destination >= HDSPM_MAX_CHANNELS)
3458 destination = HDSPM_MAX_CHANNELS - 1;
3460 spin_lock_irq(&hdspm->lock);
3461 if (source >= HDSPM_MAX_CHANNELS)
3462 ucontrol->value.integer.value[2] =
3463 hdspm_read_pb_gain(hdspm, destination,
3464 source - HDSPM_MAX_CHANNELS);
3466 ucontrol->value.integer.value[2] =
3467 hdspm_read_in_gain(hdspm, destination, source);
3469 spin_unlock_irq(&hdspm->lock);
3474 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3475 struct snd_ctl_elem_value *ucontrol)
3477 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3483 if (!snd_hdspm_use_is_exclusive(hdspm))
3486 source = ucontrol->value.integer.value[0];
3487 destination = ucontrol->value.integer.value[1];
3489 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3491 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3494 gain = ucontrol->value.integer.value[2];
3496 spin_lock_irq(&hdspm->lock);
3498 if (source >= HDSPM_MAX_CHANNELS)
3499 change = gain != hdspm_read_pb_gain(hdspm, destination,
3501 HDSPM_MAX_CHANNELS);
3503 change = gain != hdspm_read_in_gain(hdspm, destination,
3507 if (source >= HDSPM_MAX_CHANNELS)
3508 hdspm_write_pb_gain(hdspm, destination,
3509 source - HDSPM_MAX_CHANNELS,
3512 hdspm_write_in_gain(hdspm, destination, source,
3515 spin_unlock_irq(&hdspm->lock);
3520 /* The simple mixer control(s) provide gain control for the
3521 basic 1:1 mappings of playback streams to output
3525 #define HDSPM_PLAYBACK_MIXER \
3526 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3527 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3528 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3529 .info = snd_hdspm_info_playback_mixer, \
3530 .get = snd_hdspm_get_playback_mixer, \
3531 .put = snd_hdspm_put_playback_mixer \
3534 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3535 struct snd_ctl_elem_info *uinfo)
3537 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3539 uinfo->value.integer.min = 0;
3540 uinfo->value.integer.max = 64;
3541 uinfo->value.integer.step = 1;
3545 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3546 struct snd_ctl_elem_value *ucontrol)
3548 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3551 channel = ucontrol->id.index - 1;
3553 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3556 spin_lock_irq(&hdspm->lock);
3557 ucontrol->value.integer.value[0] =
3558 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3559 spin_unlock_irq(&hdspm->lock);
3564 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3565 struct snd_ctl_elem_value *ucontrol)
3567 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3572 if (!snd_hdspm_use_is_exclusive(hdspm))
3575 channel = ucontrol->id.index - 1;
3577 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3580 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3582 spin_lock_irq(&hdspm->lock);
3584 gain != hdspm_read_pb_gain(hdspm, channel,
3587 hdspm_write_pb_gain(hdspm, channel, channel,
3589 spin_unlock_irq(&hdspm->lock);
3593 #define HDSPM_SYNC_CHECK(xname, xindex) \
3594 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3596 .private_value = xindex, \
3597 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3598 .info = snd_hdspm_info_sync_check, \
3599 .get = snd_hdspm_get_sync_check \
3603 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3604 struct snd_ctl_elem_info *uinfo)
3606 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3607 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3609 uinfo->value.enumerated.items = 4;
3610 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3611 uinfo->value.enumerated.item =
3612 uinfo->value.enumerated.items - 1;
3613 strcpy(uinfo->value.enumerated.name,
3614 texts[uinfo->value.enumerated.item]);
3618 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3620 int status, status2;
3622 switch (hdspm->io_type) {
3624 status = hdspm_read(hdspm, HDSPM_statusRegister);
3625 if (status & HDSPM_wcSync)
3627 else if (status & HDSPM_wcLock)
3633 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3634 if (status2 & HDSPM_wcLock) {
3635 if (status2 & HDSPM_wcSync)
3645 status = hdspm_read(hdspm, HDSPM_statusRegister);
3647 if (status & 0x2000000)
3649 else if (status & 0x1000000)
3664 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3666 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3667 if (status & HDSPM_madiLock) {
3668 if (status & HDSPM_madiSync)
3677 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3679 int status, lock, sync;
3681 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3683 lock = (status & (0x1<<idx)) ? 1 : 0;
3684 sync = (status & (0x100<<idx)) ? 1 : 0;
3694 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3696 int status, lock = 0, sync = 0;
3698 switch (hdspm->io_type) {
3701 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3702 lock = (status & 0x400) ? 1 : 0;
3703 sync = (status & 0x800) ? 1 : 0;
3708 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3709 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3710 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3725 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3727 int status2, lock, sync;
3728 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3730 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3731 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3741 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3746 switch (hdspm->io_type) {
3749 status = hdspm_read(hdspm, HDSPM_statusRegister);
3750 if (status & HDSPM_tcoLock) {
3751 if (status & HDSPM_tcoSync)
3762 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3764 if (status & 0x8000000)
3765 return 2; /* Sync */
3766 if (status & 0x4000000)
3767 return 1; /* Lock */
3768 return 0; /* No signal */
3780 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3781 struct snd_ctl_elem_value *ucontrol)
3783 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3786 switch (hdspm->io_type) {
3788 switch (kcontrol->private_value) {
3790 val = hdspm_wc_sync_check(hdspm); break;
3792 val = hdspm_tco_sync_check(hdspm); break;
3793 case 8: /* SYNC IN */
3794 val = hdspm_sync_in_sync_check(hdspm); break;
3796 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3800 switch (kcontrol->private_value) {
3802 val = hdspm_wc_sync_check(hdspm); break;
3804 val = hdspm_tco_sync_check(hdspm); break;
3805 case 5: /* SYNC IN */
3806 val = hdspm_sync_in_sync_check(hdspm); break;
3808 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1);
3812 switch (kcontrol->private_value) {
3814 val = hdspm_wc_sync_check(hdspm); break;
3816 val = hdspm_madi_sync_check(hdspm); break;
3818 val = hdspm_tco_sync_check(hdspm); break;
3819 case 3: /* SYNC_IN */
3820 val = hdspm_sync_in_sync_check(hdspm); break;
3824 val = hdspm_madi_sync_check(hdspm); /* MADI */
3828 switch (kcontrol->private_value) {
3830 val = hdspm_wc_sync_check(hdspm); break;
3832 val = hdspm_tco_sync_check(hdspm); break;
3833 case 10 /* SYNC IN */:
3834 val = hdspm_sync_in_sync_check(hdspm); break;
3835 default: /* AES1 to AES8 */
3836 val = hdspm_aes_sync_check(hdspm,
3837 kcontrol->private_value-1);
3845 ucontrol->value.enumerated.item[0] = val;
3854 static void hdspm_tco_write(struct hdspm *hdspm)
3856 unsigned int tc[4] = { 0, 0, 0, 0};
3858 switch (hdspm->tco->input) {
3860 tc[2] |= HDSPM_TCO2_set_input_MSB;
3863 tc[2] |= HDSPM_TCO2_set_input_LSB;
3869 switch (hdspm->tco->framerate) {
3871 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
3874 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
3877 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
3878 HDSPM_TCO1_set_drop_frame_flag;
3881 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3882 HDSPM_TCO1_LTC_Format_MSB;
3885 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
3886 HDSPM_TCO1_LTC_Format_MSB +
3887 HDSPM_TCO1_set_drop_frame_flag;
3893 switch (hdspm->tco->wordclock) {
3895 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
3898 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
3904 switch (hdspm->tco->samplerate) {
3906 tc[2] |= HDSPM_TCO2_set_freq;
3909 tc[2] |= HDSPM_TCO2_set_freq_from_app;
3915 switch (hdspm->tco->pull) {
3917 tc[2] |= HDSPM_TCO2_set_pull_up;
3920 tc[2] |= HDSPM_TCO2_set_pull_down;
3923 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
3926 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
3932 if (1 == hdspm->tco->term) {
3933 tc[2] |= HDSPM_TCO2_set_term_75R;
3936 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
3937 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
3938 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
3939 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
3943 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
3944 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3947 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
3948 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3949 .info = snd_hdspm_info_tco_sample_rate, \
3950 .get = snd_hdspm_get_tco_sample_rate, \
3951 .put = snd_hdspm_put_tco_sample_rate \
3954 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
3955 struct snd_ctl_elem_info *uinfo)
3957 static char *texts[] = { "44.1 kHz", "48 kHz" };
3958 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3960 uinfo->value.enumerated.items = 2;
3962 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3963 uinfo->value.enumerated.item =
3964 uinfo->value.enumerated.items - 1;
3966 strcpy(uinfo->value.enumerated.name,
3967 texts[uinfo->value.enumerated.item]);
3972 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
3973 struct snd_ctl_elem_value *ucontrol)
3975 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3977 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
3982 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
3983 struct snd_ctl_elem_value *ucontrol)
3985 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3987 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
3988 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
3990 hdspm_tco_write(hdspm);
3999 #define HDSPM_TCO_PULL(xname, xindex) \
4000 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4003 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4004 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4005 .info = snd_hdspm_info_tco_pull, \
4006 .get = snd_hdspm_get_tco_pull, \
4007 .put = snd_hdspm_put_tco_pull \
4010 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4011 struct snd_ctl_elem_info *uinfo)
4013 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4014 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4016 uinfo->value.enumerated.items = 5;
4018 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4019 uinfo->value.enumerated.item =
4020 uinfo->value.enumerated.items - 1;
4022 strcpy(uinfo->value.enumerated.name,
4023 texts[uinfo->value.enumerated.item]);
4028 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4029 struct snd_ctl_elem_value *ucontrol)
4031 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4033 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4038 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4039 struct snd_ctl_elem_value *ucontrol)
4041 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4043 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4044 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4046 hdspm_tco_write(hdspm);
4054 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4055 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4058 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4059 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4060 .info = snd_hdspm_info_tco_wck_conversion, \
4061 .get = snd_hdspm_get_tco_wck_conversion, \
4062 .put = snd_hdspm_put_tco_wck_conversion \
4065 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4066 struct snd_ctl_elem_info *uinfo)
4068 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4069 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4071 uinfo->value.enumerated.items = 3;
4073 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4074 uinfo->value.enumerated.item =
4075 uinfo->value.enumerated.items - 1;
4077 strcpy(uinfo->value.enumerated.name,
4078 texts[uinfo->value.enumerated.item]);
4083 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4084 struct snd_ctl_elem_value *ucontrol)
4086 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4088 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4093 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4094 struct snd_ctl_elem_value *ucontrol)
4096 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4098 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4099 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4101 hdspm_tco_write(hdspm);
4110 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4111 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4114 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4115 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4116 .info = snd_hdspm_info_tco_frame_rate, \
4117 .get = snd_hdspm_get_tco_frame_rate, \
4118 .put = snd_hdspm_put_tco_frame_rate \
4121 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4122 struct snd_ctl_elem_info *uinfo)
4124 static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4125 "29.97 dfps", "30 fps", "30 dfps" };
4126 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4128 uinfo->value.enumerated.items = 6;
4130 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4131 uinfo->value.enumerated.item =
4132 uinfo->value.enumerated.items - 1;
4134 strcpy(uinfo->value.enumerated.name,
4135 texts[uinfo->value.enumerated.item]);
4140 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4141 struct snd_ctl_elem_value *ucontrol)
4143 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4145 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4150 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4151 struct snd_ctl_elem_value *ucontrol)
4153 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4155 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4156 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4158 hdspm_tco_write(hdspm);
4167 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4168 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4171 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4172 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4173 .info = snd_hdspm_info_tco_sync_source, \
4174 .get = snd_hdspm_get_tco_sync_source, \
4175 .put = snd_hdspm_put_tco_sync_source \
4178 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4179 struct snd_ctl_elem_info *uinfo)
4181 static char *texts[] = { "LTC", "Video", "WCK" };
4182 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4184 uinfo->value.enumerated.items = 3;
4186 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
4187 uinfo->value.enumerated.item =
4188 uinfo->value.enumerated.items - 1;
4190 strcpy(uinfo->value.enumerated.name,
4191 texts[uinfo->value.enumerated.item]);
4196 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4197 struct snd_ctl_elem_value *ucontrol)
4199 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4201 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4206 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4207 struct snd_ctl_elem_value *ucontrol)
4209 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4211 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4212 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4214 hdspm_tco_write(hdspm);
4223 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4224 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4227 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4228 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4229 .info = snd_hdspm_info_tco_word_term, \
4230 .get = snd_hdspm_get_tco_word_term, \
4231 .put = snd_hdspm_put_tco_word_term \
4234 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4235 struct snd_ctl_elem_info *uinfo)
4237 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4239 uinfo->value.integer.min = 0;
4240 uinfo->value.integer.max = 1;
4246 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4247 struct snd_ctl_elem_value *ucontrol)
4249 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4251 ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4257 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4258 struct snd_ctl_elem_value *ucontrol)
4260 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4262 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4263 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4265 hdspm_tco_write(hdspm);
4276 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4277 HDSPM_MIXER("Mixer", 0),
4278 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4279 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4280 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4281 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4282 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4283 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4284 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4285 HDSPM_SYNC_CHECK("TCO SyncCHeck", 2),
4286 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4287 HDSPM_LINE_OUT("Line Out", 0),
4288 HDSPM_TX_64("TX 64 channels mode", 0),
4289 HDSPM_C_TMS("Clear Track Marker", 0),
4290 HDSPM_SAFE_MODE("Safe Mode", 0),
4291 HDSPM_INPUT_SELECT("Input Select", 0)
4295 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4296 HDSPM_MIXER("Mixer", 0),
4297 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4298 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4299 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4300 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4301 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4302 HDSPM_TX_64("TX 64 channels mode", 0),
4303 HDSPM_C_TMS("Clear Track Marker", 0),
4304 HDSPM_SAFE_MODE("Safe Mode", 0)
4307 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4308 HDSPM_MIXER("Mixer", 0),
4309 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4310 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4311 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4312 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4313 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4314 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4315 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4316 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4317 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4318 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4319 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4320 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4321 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4322 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4323 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4324 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4325 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4326 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4329 HDSPM_INPUT_SELECT("Input Select", 0),
4330 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4331 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4332 HDSPM_SPDIF_IN("SPDIF In", 0);
4333 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4334 HDSPM_INPUT_LEVEL("Input Level", 0);
4335 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4336 HDSPM_PHONES("Phones", 0);
4340 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4341 HDSPM_MIXER("Mixer", 0),
4342 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4343 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4344 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4345 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4346 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4347 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4348 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4349 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4350 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4351 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4352 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4353 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4354 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4355 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4356 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4357 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4358 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4359 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4360 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4361 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4362 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4363 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4366 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4367 HDSPM_MIXER("Mixer", 0),
4368 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4369 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4370 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4371 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4372 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4373 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4374 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4375 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4376 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4377 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4378 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4379 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4380 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4381 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4382 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4383 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4384 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4385 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4386 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4387 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4388 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4389 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4390 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4391 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4392 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4393 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4394 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4395 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4396 HDSPM_LINE_OUT("Line Out", 0),
4397 HDSPM_EMPHASIS("Emphasis", 0),
4398 HDSPM_DOLBY("Non Audio", 0),
4399 HDSPM_PROFESSIONAL("Professional", 0),
4400 HDSPM_C_TMS("Clear Track Marker", 0),
4401 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4402 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4407 /* Control elements for the optional TCO module */
4408 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4409 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4410 HDSPM_TCO_PULL("TCO Pull", 0),
4411 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4412 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4413 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4414 HDSPM_TCO_WORD_TERM("TCO Word Term", 0)
4418 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4421 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4425 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4426 if (hdspm->system_sample_rate > 48000) {
4427 hdspm->playback_mixer_ctls[i]->vd[0].access =
4428 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4429 SNDRV_CTL_ELEM_ACCESS_READ |
4430 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4432 hdspm->playback_mixer_ctls[i]->vd[0].access =
4433 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4434 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4436 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4437 SNDRV_CTL_EVENT_MASK_INFO,
4438 &hdspm->playback_mixer_ctls[i]->id);
4445 static int snd_hdspm_create_controls(struct snd_card *card,
4446 struct hdspm *hdspm)
4448 unsigned int idx, limit;
4450 struct snd_kcontrol *kctl;
4451 struct snd_kcontrol_new *list = NULL;
4453 switch (hdspm->io_type) {
4455 list = snd_hdspm_controls_madi;
4456 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4459 list = snd_hdspm_controls_madiface;
4460 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4463 list = snd_hdspm_controls_aio;
4464 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4467 list = snd_hdspm_controls_raydat;
4468 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4471 list = snd_hdspm_controls_aes32;
4472 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4477 for (idx = 0; idx < limit; idx++) {
4478 err = snd_ctl_add(card,
4479 snd_ctl_new1(&list[idx], hdspm));
4486 /* create simple 1:1 playback mixer controls */
4487 snd_hdspm_playback_mixer.name = "Chn";
4488 if (hdspm->system_sample_rate >= 128000) {
4489 limit = hdspm->qs_out_channels;
4490 } else if (hdspm->system_sample_rate >= 64000) {
4491 limit = hdspm->ds_out_channels;
4493 limit = hdspm->ss_out_channels;
4495 for (idx = 0; idx < limit; ++idx) {
4496 snd_hdspm_playback_mixer.index = idx + 1;
4497 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4498 err = snd_ctl_add(card, kctl);
4501 hdspm->playback_mixer_ctls[idx] = kctl;
4506 /* add tco control elements */
4507 list = snd_hdspm_controls_tco;
4508 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4509 for (idx = 0; idx < limit; idx++) {
4510 err = snd_ctl_add(card,
4511 snd_ctl_new1(&list[idx], hdspm));
4520 /*------------------------------------------------------------
4522 ------------------------------------------------------------*/
4525 snd_hdspm_proc_read_madi(struct snd_info_entry * entry,
4526 struct snd_info_buffer *buffer)
4528 struct hdspm *hdspm = entry->private_data;
4529 unsigned int status, status2, control, freq;
4531 char *pref_sync_ref;
4533 char *system_clock_mode;
4538 int a, ltc, frames, seconds, minutes, hours;
4539 unsigned int period;
4543 status = hdspm_read(hdspm, HDSPM_statusRegister);
4544 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4545 control = hdspm->control_register;
4546 freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4548 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4549 hdspm->card_name, hdspm->card->number + 1,
4550 hdspm->firmware_rev,
4551 (status2 & HDSPM_version0) |
4552 (status2 & HDSPM_version1) | (status2 &
4555 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4556 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4557 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
4559 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4560 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4562 snd_iprintf(buffer, "--- System ---\n");
4565 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4566 status & HDSPM_audioIRQPending,
4567 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4568 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4571 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4572 "estimated= %ld (bytes)\n",
4573 ((status & HDSPM_BufferID) ? 1 : 0),
4574 (status & HDSPM_BufferPositionMask),
4575 (status & HDSPM_BufferPositionMask) %
4576 (2 * (int)hdspm->period_bytes),
4577 ((status & HDSPM_BufferPositionMask) - 64) %
4578 (2 * (int)hdspm->period_bytes),
4579 (long) hdspm_hw_pointer(hdspm) * 4);
4582 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4583 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4584 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4585 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4586 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4588 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4589 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4590 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4592 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4594 hdspm->control_register, hdspm->control2_register,
4596 if (status & HDSPM_tco_detect) {
4597 snd_iprintf(buffer, "TCO module detected.\n");
4598 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4599 if (a & HDSPM_TCO1_LTC_Input_valid) {
4600 snd_iprintf(buffer, " LTC valid, ");
4601 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4602 HDSPM_TCO1_LTC_Format_MSB)) {
4604 snd_iprintf(buffer, "24 fps, ");
4606 case HDSPM_TCO1_LTC_Format_LSB:
4607 snd_iprintf(buffer, "25 fps, ");
4609 case HDSPM_TCO1_LTC_Format_MSB:
4610 snd_iprintf(buffer, "29.97 fps, ");
4613 snd_iprintf(buffer, "30 fps, ");
4616 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4617 snd_iprintf(buffer, "drop frame\n");
4619 snd_iprintf(buffer, "full frame\n");
4622 snd_iprintf(buffer, " no LTC\n");
4624 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4625 snd_iprintf(buffer, " Video: NTSC\n");
4626 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4627 snd_iprintf(buffer, " Video: PAL\n");
4629 snd_iprintf(buffer, " No video\n");
4631 if (a & HDSPM_TCO1_TCO_lock) {
4632 snd_iprintf(buffer, " Sync: lock\n");
4634 snd_iprintf(buffer, " Sync: no lock\n");
4637 switch (hdspm->io_type) {
4640 freq_const = 110069313433624ULL;
4644 freq_const = 104857600000000ULL;
4647 break; /* no TCO possible */
4650 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4651 snd_iprintf(buffer, " period: %u\n", period);
4654 /* rate = freq_const/period; */
4655 rate = div_u64(freq_const, period);
4657 if (control & HDSPM_QuadSpeed) {
4659 } else if (control & HDSPM_DoubleSpeed) {
4663 snd_iprintf(buffer, " Frequency: %u Hz\n",
4664 (unsigned int) rate);
4666 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4669 frames += (ltc & 0x3) * 10;
4671 seconds = ltc & 0xF;
4673 seconds += (ltc & 0x7) * 10;
4675 minutes = ltc & 0xF;
4677 minutes += (ltc & 0x7) * 10;
4681 hours += (ltc & 0x3) * 10;
4683 " LTC In: %02d:%02d:%02d:%02d\n",
4684 hours, minutes, seconds, frames);
4687 snd_iprintf(buffer, "No TCO module detected.\n");
4690 snd_iprintf(buffer, "--- Settings ---\n");
4692 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4693 HDSPM_LatencyMask));
4696 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4697 x, (unsigned long) hdspm->period_bytes);
4699 snd_iprintf(buffer, "Line out: %s\n",
4700 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4702 switch (hdspm->control_register & HDSPM_InputMask) {
4703 case HDSPM_InputOptical:
4706 case HDSPM_InputCoaxial:
4714 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4716 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4717 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4718 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4721 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4722 system_clock_mode = "AutoSync";
4724 system_clock_mode = "Master";
4725 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4727 switch (hdspm_pref_sync_ref(hdspm)) {
4728 case HDSPM_SYNC_FROM_WORD:
4729 pref_sync_ref = "Word Clock";
4731 case HDSPM_SYNC_FROM_MADI:
4732 pref_sync_ref = "MADI Sync";
4734 case HDSPM_SYNC_FROM_TCO:
4735 pref_sync_ref = "TCO";
4737 case HDSPM_SYNC_FROM_SYNC_IN:
4738 pref_sync_ref = "Sync In";
4741 pref_sync_ref = "XXXX Clock";
4744 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4747 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4748 hdspm->system_sample_rate);
4751 snd_iprintf(buffer, "--- Status:\n");
4753 x = status & HDSPM_madiSync;
4754 x2 = status2 & HDSPM_wcSync;
4756 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4757 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4759 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4762 switch (hdspm_autosync_ref(hdspm)) {
4763 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4764 autosync_ref = "Sync In";
4766 case HDSPM_AUTOSYNC_FROM_TCO:
4767 autosync_ref = "TCO";
4769 case HDSPM_AUTOSYNC_FROM_WORD:
4770 autosync_ref = "Word Clock";
4772 case HDSPM_AUTOSYNC_FROM_MADI:
4773 autosync_ref = "MADI Sync";
4775 case HDSPM_AUTOSYNC_FROM_NONE:
4776 autosync_ref = "Input not valid";
4779 autosync_ref = "---";
4783 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4784 autosync_ref, hdspm_external_sample_rate(hdspm),
4785 (status & HDSPM_madiFreqMask) >> 22,
4786 (status2 & HDSPM_wcFreqMask) >> 5);
4788 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4789 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4790 (status & HDSPM_RX_64ch) ? "64 channels" :
4793 snd_iprintf(buffer, "\n");
4797 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4798 struct snd_info_buffer *buffer)
4800 struct hdspm *hdspm = entry->private_data;
4801 unsigned int status;
4802 unsigned int status2;
4803 unsigned int timecode;
4808 status = hdspm_read(hdspm, HDSPM_statusRegister);
4809 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4810 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4812 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4813 hdspm->card_name, hdspm->card->number + 1,
4814 hdspm->firmware_rev);
4816 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4817 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4819 snd_iprintf(buffer, "--- System ---\n");
4822 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4823 status & HDSPM_audioIRQPending,
4824 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4825 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4828 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4829 "estimated= %ld (bytes)\n",
4830 ((status & HDSPM_BufferID) ? 1 : 0),
4831 (status & HDSPM_BufferPositionMask),
4832 (status & HDSPM_BufferPositionMask) %
4833 (2 * (int)hdspm->period_bytes),
4834 ((status & HDSPM_BufferPositionMask) - 64) %
4835 (2 * (int)hdspm->period_bytes),
4836 (long) hdspm_hw_pointer(hdspm) * 4);
4839 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4840 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4841 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4842 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4843 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4845 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4846 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4847 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4849 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4851 hdspm->control_register, hdspm->control2_register,
4854 snd_iprintf(buffer, "--- Settings ---\n");
4856 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register &
4857 HDSPM_LatencyMask));
4860 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4861 x, (unsigned long) hdspm->period_bytes);
4863 snd_iprintf(buffer, "Line out: %s\n",
4865 control_register & HDSPM_LineOut) ? "on " : "off");
4868 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4870 control_register & HDSPM_clr_tms) ? "on" : "off",
4872 control_register & HDSPM_Emphasis) ? "on" : "off",
4874 control_register & HDSPM_Dolby) ? "on" : "off");
4877 pref_syncref = hdspm_pref_sync_ref(hdspm);
4878 if (pref_syncref == 0)
4879 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
4881 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
4884 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4885 hdspm->system_sample_rate);
4887 snd_iprintf(buffer, "Double speed: %s\n",
4888 hdspm->control_register & HDSPM_DS_DoubleWire?
4889 "Double wire" : "Single wire");
4890 snd_iprintf(buffer, "Quad speed: %s\n",
4891 hdspm->control_register & HDSPM_QS_DoubleWire?
4893 hdspm->control_register & HDSPM_QS_QuadWire?
4894 "Quad wire" : "Single wire");
4896 snd_iprintf(buffer, "--- Status:\n");
4898 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
4899 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock",
4900 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
4902 for (x = 0; x < 8; x++) {
4903 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
4905 (status2 & (HDSPM_LockAES >> x)) ?
4906 "Sync " : "No Lock",
4907 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
4910 switch (hdspm_autosync_ref(hdspm)) {
4911 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
4912 autosync_ref = "None"; break;
4913 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
4914 autosync_ref = "Word Clock"; break;
4915 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
4916 autosync_ref = "AES1"; break;
4917 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
4918 autosync_ref = "AES2"; break;
4919 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
4920 autosync_ref = "AES3"; break;
4921 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
4922 autosync_ref = "AES4"; break;
4923 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
4924 autosync_ref = "AES5"; break;
4925 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
4926 autosync_ref = "AES6"; break;
4927 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
4928 autosync_ref = "AES7"; break;
4929 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
4930 autosync_ref = "AES8"; break;
4932 autosync_ref = "---"; break;
4934 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
4936 snd_iprintf(buffer, "\n");
4940 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
4941 struct snd_info_buffer *buffer)
4943 struct hdspm *hdspm = entry->private_data;
4944 unsigned int status1, status2, status3, control, i;
4945 unsigned int lock, sync;
4947 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
4948 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
4949 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
4951 control = hdspm->control_register;
4953 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
4954 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
4955 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
4958 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
4960 snd_iprintf(buffer, "Clock mode : %s\n",
4961 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
4962 snd_iprintf(buffer, "System frequency: %d Hz\n",
4963 hdspm_get_system_sample_rate(hdspm));
4965 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
4970 for (i = 0; i < 8; i++) {
4971 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
4973 (status1 & lock) ? 1 : 0,
4974 (status1 & sync) ? 1 : 0,
4975 texts_freq[(status2 >> (i * 4)) & 0xF]);
4981 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
4982 (status1 & 0x1000000) ? 1 : 0,
4983 (status1 & 0x2000000) ? 1 : 0,
4984 texts_freq[(status1 >> 16) & 0xF]);
4986 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
4987 (status1 & 0x4000000) ? 1 : 0,
4988 (status1 & 0x8000000) ? 1 : 0,
4989 texts_freq[(status1 >> 20) & 0xF]);
4991 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
4992 (status3 & 0x400) ? 1 : 0,
4993 (status3 & 0x800) ? 1 : 0,
4994 texts_freq[(status2 >> 12) & 0xF]);
4998 #ifdef CONFIG_SND_DEBUG
5000 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5001 struct snd_info_buffer *buffer)
5003 struct hdspm *hdspm = entry->private_data;
5007 for (i = 0; i < 256 /* 1024*64 */; i += j) {
5008 snd_iprintf(buffer, "0x%08X: ", i);
5009 for (j = 0; j < 16; j += 4)
5010 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5011 snd_iprintf(buffer, "\n");
5017 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5018 struct snd_info_buffer *buffer)
5020 struct hdspm *hdspm = entry->private_data;
5023 snd_iprintf(buffer, "# generated by hdspm\n");
5025 for (i = 0; i < hdspm->max_channels_in; i++) {
5026 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5030 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5031 struct snd_info_buffer *buffer)
5033 struct hdspm *hdspm = entry->private_data;
5036 snd_iprintf(buffer, "# generated by hdspm\n");
5038 for (i = 0; i < hdspm->max_channels_out; i++) {
5039 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5044 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm)
5046 struct snd_info_entry *entry;
5048 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5049 switch (hdspm->io_type) {
5051 snd_info_set_text_ops(entry, hdspm,
5052 snd_hdspm_proc_read_aes32);
5055 snd_info_set_text_ops(entry, hdspm,
5056 snd_hdspm_proc_read_madi);
5059 /* snd_info_set_text_ops(entry, hdspm,
5060 snd_hdspm_proc_read_madiface); */
5063 snd_info_set_text_ops(entry, hdspm,
5064 snd_hdspm_proc_read_raydat);
5071 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5072 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5075 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5076 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5079 #ifdef CONFIG_SND_DEBUG
5080 /* debug file to read all hdspm registers */
5081 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5082 snd_info_set_text_ops(entry, hdspm,
5083 snd_hdspm_proc_read_debug);
5087 /*------------------------------------------------------------
5089 ------------------------------------------------------------*/
5091 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5093 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5094 hold it (e.g. during module initialization).
5099 hdspm->settings_register = 0;
5101 switch (hdspm->io_type) {
5104 hdspm->control_register =
5105 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5110 hdspm->settings_register = 0x1 + 0x1000;
5111 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5113 hdspm->control_register =
5114 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5118 hdspm->control_register =
5119 HDSPM_ClockModeMaster | /* Master Cloack Mode on */
5120 hdspm_encode_latency(7) | /* latency max=8192samples */
5121 HDSPM_SyncRef0 | /* AES1 is syncclock */
5122 HDSPM_LineOut | /* Analog output in */
5123 HDSPM_Professional; /* Professional mode */
5127 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5129 if (AES32 == hdspm->io_type) {
5130 /* No control2 register for AES32 */
5131 #ifdef SNDRV_BIG_ENDIAN
5132 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5134 hdspm->control2_register = 0;
5137 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5139 hdspm_compute_period_size(hdspm);
5141 /* silence everything */
5143 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5145 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) {
5146 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5149 /* set a default rate so that the channel map is set up. */
5150 hdspm_set_rate(hdspm, 48000, 1);
5156 /*------------------------------------------------------------
5158 ------------------------------------------------------------*/
5160 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5162 struct hdspm *hdspm = (struct hdspm *) dev_id;
5163 unsigned int status;
5164 int i, audio, midi, schedule = 0;
5167 status = hdspm_read(hdspm, HDSPM_statusRegister);
5169 audio = status & HDSPM_audioIRQPending;
5170 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5171 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5173 /* now = get_cycles(); */
5175 * LAT_2..LAT_0 period counter (win) counter (mac)
5176 * 6 4096 ~256053425 ~514672358
5177 * 5 2048 ~128024983 ~257373821
5178 * 4 1024 ~64023706 ~128718089
5179 * 3 512 ~32005945 ~64385999
5180 * 2 256 ~16003039 ~32260176
5181 * 1 128 ~7998738 ~16194507
5182 * 0 64 ~3998231 ~8191558
5185 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5186 now-hdspm->last_interrupt, status & 0xFFC0);
5187 hdspm->last_interrupt = now;
5190 if (!audio && !midi)
5193 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5198 if (hdspm->capture_substream)
5199 snd_pcm_period_elapsed(hdspm->capture_substream);
5201 if (hdspm->playback_substream)
5202 snd_pcm_period_elapsed(hdspm->playback_substream);
5207 while (i < hdspm->midiPorts) {
5208 if ((hdspm_read(hdspm,
5209 hdspm->midi[i].statusIn) & 0xff) &&
5210 (status & hdspm->midi[i].irq)) {
5211 /* we disable interrupts for this input until
5212 * processing is done
5214 hdspm->control_register &= ~hdspm->midi[i].ie;
5215 hdspm_write(hdspm, HDSPM_controlRegister,
5216 hdspm->control_register);
5217 hdspm->midi[i].pending = 1;
5225 tasklet_hi_schedule(&hdspm->midi_tasklet);
5231 /*------------------------------------------------------------
5233 ------------------------------------------------------------*/
5236 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5239 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5240 return hdspm_hw_pointer(hdspm);
5244 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5246 struct snd_pcm_runtime *runtime = substream->runtime;
5247 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5248 struct snd_pcm_substream *other;
5250 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5251 other = hdspm->capture_substream;
5253 other = hdspm->playback_substream;
5256 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5258 runtime->status->hw_ptr = 0;
5260 struct snd_pcm_substream *s;
5261 struct snd_pcm_runtime *oruntime = other->runtime;
5262 snd_pcm_group_for_each_entry(s, substream) {
5264 oruntime->status->hw_ptr =
5265 runtime->status->hw_ptr;
5273 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5274 struct snd_pcm_hw_params *params)
5276 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5282 spin_lock_irq(&hdspm->lock);
5284 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5285 this_pid = hdspm->playback_pid;
5286 other_pid = hdspm->capture_pid;
5288 this_pid = hdspm->capture_pid;
5289 other_pid = hdspm->playback_pid;
5292 if (other_pid > 0 && this_pid != other_pid) {
5294 /* The other stream is open, and not by the same
5295 task as this one. Make sure that the parameters
5296 that matter are the same.
5299 if (params_rate(params) != hdspm->system_sample_rate) {
5300 spin_unlock_irq(&hdspm->lock);
5301 _snd_pcm_hw_param_setempty(params,
5302 SNDRV_PCM_HW_PARAM_RATE);
5306 if (params_period_size(params) != hdspm->period_bytes / 4) {
5307 spin_unlock_irq(&hdspm->lock);
5308 _snd_pcm_hw_param_setempty(params,
5309 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5315 spin_unlock_irq(&hdspm->lock);
5317 /* how to make sure that the rate matches an externally-set one ? */
5319 spin_lock_irq(&hdspm->lock);
5320 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5322 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5323 spin_unlock_irq(&hdspm->lock);
5324 _snd_pcm_hw_param_setempty(params,
5325 SNDRV_PCM_HW_PARAM_RATE);
5328 spin_unlock_irq(&hdspm->lock);
5330 err = hdspm_set_interrupt_interval(hdspm,
5331 params_period_size(params));
5333 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5334 _snd_pcm_hw_param_setempty(params,
5335 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5339 /* Memory allocation, takashi's method, dont know if we should
5342 /* malloc all buffer even if not enabled to get sure */
5343 /* Update for MADI rev 204: we need to allocate for all channels,
5344 * otherwise it doesn't work at 96kHz */
5347 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5349 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5353 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5355 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5356 params_channels(params));
5358 for (i = 0; i < params_channels(params); ++i)
5359 snd_hdspm_enable_out(hdspm, i, 1);
5361 hdspm->playback_buffer =
5362 (unsigned char *) substream->runtime->dma_area;
5363 snd_printdd("Allocated sample buffer for playback at %p\n",
5364 hdspm->playback_buffer);
5366 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5367 params_channels(params));
5369 for (i = 0; i < params_channels(params); ++i)
5370 snd_hdspm_enable_in(hdspm, i, 1);
5372 hdspm->capture_buffer =
5373 (unsigned char *) substream->runtime->dma_area;
5374 snd_printdd("Allocated sample buffer for capture at %p\n",
5375 hdspm->capture_buffer);
5379 snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5380 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5381 "playback" : "capture",
5382 snd_pcm_sgbuf_get_addr(substream, 0));
5385 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5386 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5387 "playback" : "capture",
5388 params_rate(params), params_channels(params),
5389 params_buffer_size(params));
5393 /* Switch to native float format if requested */
5394 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5395 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5396 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5398 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5399 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5400 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5401 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5403 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5405 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5410 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5413 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5415 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5417 /* params_channels(params) should be enough,
5418 but to get sure in case of error */
5419 for (i = 0; i < hdspm->max_channels_out; ++i)
5420 snd_hdspm_enable_out(hdspm, i, 0);
5422 hdspm->playback_buffer = NULL;
5424 for (i = 0; i < hdspm->max_channels_in; ++i)
5425 snd_hdspm_enable_in(hdspm, i, 0);
5427 hdspm->capture_buffer = NULL;
5431 snd_pcm_lib_free_pages(substream);
5437 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5438 struct snd_pcm_channel_info *info)
5440 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5442 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5443 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5444 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5448 if (hdspm->channel_map_out[info->channel] < 0) {
5449 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5453 info->offset = hdspm->channel_map_out[info->channel] *
5454 HDSPM_CHANNEL_BUFFER_BYTES;
5456 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5457 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5461 if (hdspm->channel_map_in[info->channel] < 0) {
5462 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5466 info->offset = hdspm->channel_map_in[info->channel] *
5467 HDSPM_CHANNEL_BUFFER_BYTES;
5476 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5477 unsigned int cmd, void *arg)
5480 case SNDRV_PCM_IOCTL1_RESET:
5481 return snd_hdspm_reset(substream);
5483 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5485 struct snd_pcm_channel_info *info = arg;
5486 return snd_hdspm_channel_info(substream, info);
5492 return snd_pcm_lib_ioctl(substream, cmd, arg);
5495 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5497 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5498 struct snd_pcm_substream *other;
5501 spin_lock(&hdspm->lock);
5502 running = hdspm->running;
5504 case SNDRV_PCM_TRIGGER_START:
5505 running |= 1 << substream->stream;
5507 case SNDRV_PCM_TRIGGER_STOP:
5508 running &= ~(1 << substream->stream);
5512 spin_unlock(&hdspm->lock);
5515 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5516 other = hdspm->capture_substream;
5518 other = hdspm->playback_substream;
5521 struct snd_pcm_substream *s;
5522 snd_pcm_group_for_each_entry(s, substream) {
5524 snd_pcm_trigger_done(s, substream);
5525 if (cmd == SNDRV_PCM_TRIGGER_START)
5526 running |= 1 << s->stream;
5528 running &= ~(1 << s->stream);
5532 if (cmd == SNDRV_PCM_TRIGGER_START) {
5533 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5534 && substream->stream ==
5535 SNDRV_PCM_STREAM_CAPTURE)
5536 hdspm_silence_playback(hdspm);
5539 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5540 hdspm_silence_playback(hdspm);
5543 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5544 hdspm_silence_playback(hdspm);
5547 snd_pcm_trigger_done(substream, substream);
5548 if (!hdspm->running && running)
5549 hdspm_start_audio(hdspm);
5550 else if (hdspm->running && !running)
5551 hdspm_stop_audio(hdspm);
5552 hdspm->running = running;
5553 spin_unlock(&hdspm->lock);
5558 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5563 static unsigned int period_sizes_old[] = {
5564 64, 128, 256, 512, 1024, 2048, 4096
5567 static unsigned int period_sizes_new[] = {
5568 32, 64, 128, 256, 512, 1024, 2048, 4096
5571 /* RayDAT and AIO always have a buffer of 16384 samples per channel */
5572 static unsigned int raydat_aio_buffer_sizes[] = {
5576 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5577 .info = (SNDRV_PCM_INFO_MMAP |
5578 SNDRV_PCM_INFO_MMAP_VALID |
5579 SNDRV_PCM_INFO_NONINTERLEAVED |
5580 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5581 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5582 .rates = (SNDRV_PCM_RATE_32000 |
5583 SNDRV_PCM_RATE_44100 |
5584 SNDRV_PCM_RATE_48000 |
5585 SNDRV_PCM_RATE_64000 |
5586 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5587 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5591 .channels_max = HDSPM_MAX_CHANNELS,
5593 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5594 .period_bytes_min = (64 * 4),
5595 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5601 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5602 .info = (SNDRV_PCM_INFO_MMAP |
5603 SNDRV_PCM_INFO_MMAP_VALID |
5604 SNDRV_PCM_INFO_NONINTERLEAVED |
5605 SNDRV_PCM_INFO_SYNC_START),
5606 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5607 .rates = (SNDRV_PCM_RATE_32000 |
5608 SNDRV_PCM_RATE_44100 |
5609 SNDRV_PCM_RATE_48000 |
5610 SNDRV_PCM_RATE_64000 |
5611 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5612 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5616 .channels_max = HDSPM_MAX_CHANNELS,
5618 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5619 .period_bytes_min = (64 * 4),
5620 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS,
5626 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = {
5627 .count = ARRAY_SIZE(period_sizes_old),
5628 .list = period_sizes_old,
5632 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = {
5633 .count = ARRAY_SIZE(period_sizes_new),
5634 .list = period_sizes_new,
5638 static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = {
5639 .count = ARRAY_SIZE(raydat_aio_buffer_sizes),
5640 .list = raydat_aio_buffer_sizes,
5644 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5645 struct snd_pcm_hw_rule *rule)
5647 struct hdspm *hdspm = rule->private;
5648 struct snd_interval *c =
5649 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5650 struct snd_interval *r =
5651 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5653 if (r->min > 96000 && r->max <= 192000) {
5654 struct snd_interval t = {
5655 .min = hdspm->qs_in_channels,
5656 .max = hdspm->qs_in_channels,
5659 return snd_interval_refine(c, &t);
5660 } else if (r->min > 48000 && r->max <= 96000) {
5661 struct snd_interval t = {
5662 .min = hdspm->ds_in_channels,
5663 .max = hdspm->ds_in_channels,
5666 return snd_interval_refine(c, &t);
5667 } else if (r->max < 64000) {
5668 struct snd_interval t = {
5669 .min = hdspm->ss_in_channels,
5670 .max = hdspm->ss_in_channels,
5673 return snd_interval_refine(c, &t);
5679 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5680 struct snd_pcm_hw_rule * rule)
5682 struct hdspm *hdspm = rule->private;
5683 struct snd_interval *c =
5684 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5685 struct snd_interval *r =
5686 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5688 if (r->min > 96000 && r->max <= 192000) {
5689 struct snd_interval t = {
5690 .min = hdspm->qs_out_channels,
5691 .max = hdspm->qs_out_channels,
5694 return snd_interval_refine(c, &t);
5695 } else if (r->min > 48000 && r->max <= 96000) {
5696 struct snd_interval t = {
5697 .min = hdspm->ds_out_channels,
5698 .max = hdspm->ds_out_channels,
5701 return snd_interval_refine(c, &t);
5702 } else if (r->max < 64000) {
5703 struct snd_interval t = {
5704 .min = hdspm->ss_out_channels,
5705 .max = hdspm->ss_out_channels,
5708 return snd_interval_refine(c, &t);
5714 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5715 struct snd_pcm_hw_rule * rule)
5717 struct hdspm *hdspm = rule->private;
5718 struct snd_interval *c =
5719 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5720 struct snd_interval *r =
5721 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5723 if (c->min >= hdspm->ss_in_channels) {
5724 struct snd_interval t = {
5729 return snd_interval_refine(r, &t);
5730 } else if (c->max <= hdspm->qs_in_channels) {
5731 struct snd_interval t = {
5736 return snd_interval_refine(r, &t);
5737 } else if (c->max <= hdspm->ds_in_channels) {
5738 struct snd_interval t = {
5743 return snd_interval_refine(r, &t);
5748 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5749 struct snd_pcm_hw_rule *rule)
5751 struct hdspm *hdspm = rule->private;
5752 struct snd_interval *c =
5753 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5754 struct snd_interval *r =
5755 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5757 if (c->min >= hdspm->ss_out_channels) {
5758 struct snd_interval t = {
5763 return snd_interval_refine(r, &t);
5764 } else if (c->max <= hdspm->qs_out_channels) {
5765 struct snd_interval t = {
5770 return snd_interval_refine(r, &t);
5771 } else if (c->max <= hdspm->ds_out_channels) {
5772 struct snd_interval t = {
5777 return snd_interval_refine(r, &t);
5783 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5784 struct snd_pcm_hw_rule *rule)
5786 unsigned int list[3];
5787 struct hdspm *hdspm = rule->private;
5788 struct snd_interval *c = hw_param_interval(params,
5789 SNDRV_PCM_HW_PARAM_CHANNELS);
5791 list[0] = hdspm->qs_in_channels;
5792 list[1] = hdspm->ds_in_channels;
5793 list[2] = hdspm->ss_in_channels;
5794 return snd_interval_list(c, 3, list, 0);
5797 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5798 struct snd_pcm_hw_rule *rule)
5800 unsigned int list[3];
5801 struct hdspm *hdspm = rule->private;
5802 struct snd_interval *c = hw_param_interval(params,
5803 SNDRV_PCM_HW_PARAM_CHANNELS);
5805 list[0] = hdspm->qs_out_channels;
5806 list[1] = hdspm->ds_out_channels;
5807 list[2] = hdspm->ss_out_channels;
5808 return snd_interval_list(c, 3, list, 0);
5812 static unsigned int hdspm_aes32_sample_rates[] = {
5813 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5816 static struct snd_pcm_hw_constraint_list
5817 hdspm_hw_constraints_aes32_sample_rates = {
5818 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5819 .list = hdspm_aes32_sample_rates,
5823 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5825 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5826 struct snd_pcm_runtime *runtime = substream->runtime;
5828 spin_lock_irq(&hdspm->lock);
5830 snd_pcm_set_sync(substream);
5833 runtime->hw = snd_hdspm_playback_subinfo;
5835 if (hdspm->capture_substream == NULL)
5836 hdspm_stop_audio(hdspm);
5838 hdspm->playback_pid = current->pid;
5839 hdspm->playback_substream = substream;
5841 spin_unlock_irq(&hdspm->lock);
5843 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5845 switch (hdspm->io_type) {
5848 snd_pcm_hw_constraint_list(runtime, 0,
5849 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5850 &hw_constraints_period_sizes_new);
5851 snd_pcm_hw_constraint_list(runtime, 0,
5852 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5853 &hw_constraints_raydat_io_buffer);
5858 snd_pcm_hw_constraint_list(runtime, 0,
5859 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5860 &hw_constraints_period_sizes_old);
5863 if (AES32 == hdspm->io_type) {
5864 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5865 &hdspm_hw_constraints_aes32_sample_rates);
5867 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5868 snd_hdspm_hw_rule_rate_out_channels, hdspm,
5869 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5872 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5873 snd_hdspm_hw_rule_out_channels, hdspm,
5874 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5876 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5877 snd_hdspm_hw_rule_out_channels_rate, hdspm,
5878 SNDRV_PCM_HW_PARAM_RATE, -1);
5883 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
5885 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5887 spin_lock_irq(&hdspm->lock);
5889 hdspm->playback_pid = -1;
5890 hdspm->playback_substream = NULL;
5892 spin_unlock_irq(&hdspm->lock);
5898 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
5900 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5901 struct snd_pcm_runtime *runtime = substream->runtime;
5903 spin_lock_irq(&hdspm->lock);
5904 snd_pcm_set_sync(substream);
5905 runtime->hw = snd_hdspm_capture_subinfo;
5907 if (hdspm->playback_substream == NULL)
5908 hdspm_stop_audio(hdspm);
5910 hdspm->capture_pid = current->pid;
5911 hdspm->capture_substream = substream;
5913 spin_unlock_irq(&hdspm->lock);
5915 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5916 switch (hdspm->io_type) {
5919 snd_pcm_hw_constraint_list(runtime, 0,
5920 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5921 &hw_constraints_period_sizes_new);
5922 snd_pcm_hw_constraint_list(runtime, 0,
5923 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
5924 &hw_constraints_raydat_io_buffer);
5928 snd_pcm_hw_constraint_list(runtime, 0,
5929 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
5930 &hw_constraints_period_sizes_old);
5933 if (AES32 == hdspm->io_type) {
5934 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5935 &hdspm_hw_constraints_aes32_sample_rates);
5937 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
5938 snd_hdspm_hw_rule_rate_in_channels, hdspm,
5939 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5942 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5943 snd_hdspm_hw_rule_in_channels, hdspm,
5944 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
5946 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
5947 snd_hdspm_hw_rule_in_channels_rate, hdspm,
5948 SNDRV_PCM_HW_PARAM_RATE, -1);
5953 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
5955 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5957 spin_lock_irq(&hdspm->lock);
5959 hdspm->capture_pid = -1;
5960 hdspm->capture_substream = NULL;
5962 spin_unlock_irq(&hdspm->lock);
5966 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
5968 /* we have nothing to initialize but the call is required */
5972 static inline int copy_u32_le(void __user *dest, void __iomem *src)
5974 u32 val = readl(src);
5975 return copy_to_user(dest, &val, 4);
5978 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
5979 unsigned int cmd, unsigned long __user arg)
5981 void __user *argp = (void __user *)arg;
5982 struct hdspm *hdspm = hw->private_data;
5983 struct hdspm_mixer_ioctl mixer;
5984 struct hdspm_config info;
5985 struct hdspm_status status;
5986 struct hdspm_version hdspm_version;
5987 struct hdspm_peak_rms *levels;
5988 struct hdspm_ltc ltc;
5989 unsigned int statusregister;
5990 long unsigned int s;
5995 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
5996 levels = &hdspm->peak_rms;
5997 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
5998 levels->input_peaks[i] =
5999 readl(hdspm->iobase +
6000 HDSPM_MADI_INPUT_PEAK + i*4);
6001 levels->playback_peaks[i] =
6002 readl(hdspm->iobase +
6003 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6004 levels->output_peaks[i] =
6005 readl(hdspm->iobase +
6006 HDSPM_MADI_OUTPUT_PEAK + i*4);
6008 levels->input_rms[i] =
6009 ((uint64_t) readl(hdspm->iobase +
6010 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6011 (uint64_t) readl(hdspm->iobase +
6012 HDSPM_MADI_INPUT_RMS_L + i*4);
6013 levels->playback_rms[i] =
6014 ((uint64_t)readl(hdspm->iobase +
6015 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6016 (uint64_t)readl(hdspm->iobase +
6017 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6018 levels->output_rms[i] =
6019 ((uint64_t)readl(hdspm->iobase +
6020 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6021 (uint64_t)readl(hdspm->iobase +
6022 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6025 if (hdspm->system_sample_rate > 96000) {
6027 } else if (hdspm->system_sample_rate > 48000) {
6032 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6034 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6036 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6037 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6043 case SNDRV_HDSPM_IOCTL_GET_LTC:
6044 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6045 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6046 if (i & HDSPM_TCO1_LTC_Input_valid) {
6047 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6048 HDSPM_TCO1_LTC_Format_MSB)) {
6050 ltc.format = fps_24;
6052 case HDSPM_TCO1_LTC_Format_LSB:
6053 ltc.format = fps_25;
6055 case HDSPM_TCO1_LTC_Format_MSB:
6056 ltc.format = fps_2997;
6062 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6063 ltc.frame = drop_frame;
6065 ltc.frame = full_frame;
6068 ltc.format = format_invalid;
6069 ltc.frame = frame_invalid;
6071 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6072 ltc.input_format = ntsc;
6073 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6074 ltc.input_format = pal;
6076 ltc.input_format = no_video;
6079 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc));
6082 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6088 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6090 memset(&info, 0, sizeof(info));
6091 spin_lock_irq(&hdspm->lock);
6092 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6093 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6095 info.system_sample_rate = hdspm->system_sample_rate;
6096 info.autosync_sample_rate =
6097 hdspm_external_sample_rate(hdspm);
6098 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6099 info.clock_source = hdspm_clock_source(hdspm);
6100 info.autosync_ref = hdspm_autosync_ref(hdspm);
6101 info.line_out = hdspm_line_out(hdspm);
6103 spin_unlock_irq(&hdspm->lock);
6104 if (copy_to_user((void __user *) arg, &info, sizeof(info)))
6108 case SNDRV_HDSPM_IOCTL_GET_STATUS:
6109 status.card_type = hdspm->io_type;
6111 status.autosync_source = hdspm_autosync_ref(hdspm);
6113 status.card_clock = 110069313433624ULL;
6114 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6116 switch (hdspm->io_type) {
6119 status.card_specific.madi.sync_wc =
6120 hdspm_wc_sync_check(hdspm);
6121 status.card_specific.madi.sync_madi =
6122 hdspm_madi_sync_check(hdspm);
6123 status.card_specific.madi.sync_tco =
6124 hdspm_tco_sync_check(hdspm);
6125 status.card_specific.madi.sync_in =
6126 hdspm_sync_in_sync_check(hdspm);
6129 hdspm_read(hdspm, HDSPM_statusRegister);
6130 status.card_specific.madi.madi_input =
6131 (statusregister & HDSPM_AB_int) ? 1 : 0;
6132 status.card_specific.madi.channel_format =
6133 (statusregister & HDSPM_TX_64ch) ? 1 : 0;
6134 /* TODO: Mac driver sets it when f_s>48kHz */
6135 status.card_specific.madi.frame_format = 0;
6141 if (copy_to_user((void __user *) arg, &status, sizeof(status)))
6147 case SNDRV_HDSPM_IOCTL_GET_VERSION:
6148 hdspm_version.card_type = hdspm->io_type;
6149 strncpy(hdspm_version.cardname, hdspm->card_name,
6150 sizeof(hdspm_version.cardname));
6151 hdspm_version.serial = (hdspm_read(hdspm,
6152 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6153 hdspm_version.firmware_rev = hdspm->firmware_rev;
6154 hdspm_version.addons = 0;
6156 hdspm_version.addons |= HDSPM_ADDON_TCO;
6158 if (copy_to_user((void __user *) arg, &hdspm_version,
6159 sizeof(hdspm_version)))
6163 case SNDRV_HDSPM_IOCTL_GET_MIXER:
6164 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer)))
6166 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6167 sizeof(struct hdspm_mixer)))
6177 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6178 .open = snd_hdspm_playback_open,
6179 .close = snd_hdspm_playback_release,
6180 .ioctl = snd_hdspm_ioctl,
6181 .hw_params = snd_hdspm_hw_params,
6182 .hw_free = snd_hdspm_hw_free,
6183 .prepare = snd_hdspm_prepare,
6184 .trigger = snd_hdspm_trigger,
6185 .pointer = snd_hdspm_hw_pointer,
6186 .page = snd_pcm_sgbuf_ops_page,
6189 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6190 .open = snd_hdspm_capture_open,
6191 .close = snd_hdspm_capture_release,
6192 .ioctl = snd_hdspm_ioctl,
6193 .hw_params = snd_hdspm_hw_params,
6194 .hw_free = snd_hdspm_hw_free,
6195 .prepare = snd_hdspm_prepare,
6196 .trigger = snd_hdspm_trigger,
6197 .pointer = snd_hdspm_hw_pointer,
6198 .page = snd_pcm_sgbuf_ops_page,
6201 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card,
6202 struct hdspm * hdspm)
6204 struct snd_hwdep *hw;
6207 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6212 hw->private_data = hdspm;
6213 strcpy(hw->name, "HDSPM hwdep interface");
6215 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6216 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6217 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6223 /*------------------------------------------------------------
6225 ------------------------------------------------------------*/
6226 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6229 struct snd_pcm *pcm;
6234 wanted = HDSPM_DMA_AREA_BYTES;
6237 snd_pcm_lib_preallocate_pages_for_all(pcm,
6238 SNDRV_DMA_TYPE_DEV_SG,
6239 snd_dma_pci_data(hdspm->pci),
6243 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6247 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6253 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6254 struct snd_pcm_substream *substream,
6255 unsigned int reg, int channels)
6259 /* continuous memory segment */
6260 for (i = 0; i < (channels * 16); i++)
6261 hdspm_write(hdspm, reg + 4 * i,
6262 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6266 /* ------------- ALSA Devices ---------------------------- */
6267 static int __devinit snd_hdspm_create_pcm(struct snd_card *card,
6268 struct hdspm *hdspm)
6270 struct snd_pcm *pcm;
6273 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6278 pcm->private_data = hdspm;
6279 strcpy(pcm->name, hdspm->card_name);
6281 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6282 &snd_hdspm_playback_ops);
6283 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6284 &snd_hdspm_capture_ops);
6286 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6288 err = snd_hdspm_preallocate_memory(hdspm);
6295 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6299 for (i = 0; i < hdspm->midiPorts; i++)
6300 snd_hdspm_flush_midi_input(hdspm, i);
6303 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card,
6304 struct hdspm * hdspm)
6308 snd_printdd("Create card...\n");
6309 err = snd_hdspm_create_pcm(card, hdspm);
6314 while (i < hdspm->midiPorts) {
6315 err = snd_hdspm_create_midi(card, hdspm, i);
6322 err = snd_hdspm_create_controls(card, hdspm);
6326 err = snd_hdspm_create_hwdep(card, hdspm);
6330 snd_printdd("proc init...\n");
6331 snd_hdspm_proc_init(hdspm);
6333 hdspm->system_sample_rate = -1;
6334 hdspm->last_external_sample_rate = -1;
6335 hdspm->last_internal_sample_rate = -1;
6336 hdspm->playback_pid = -1;
6337 hdspm->capture_pid = -1;
6338 hdspm->capture_substream = NULL;
6339 hdspm->playback_substream = NULL;
6341 snd_printdd("Set defaults...\n");
6342 err = snd_hdspm_set_defaults(hdspm);
6346 snd_printdd("Update mixer controls...\n");
6347 hdspm_update_simple_mixer_controls(hdspm);
6349 snd_printdd("Initializeing complete ???\n");
6351 err = snd_card_register(card);
6353 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6357 snd_printdd("... yes now\n");
6362 static int __devinit snd_hdspm_create(struct snd_card *card,
6363 struct hdspm *hdspm) {
6365 struct pci_dev *pci = hdspm->pci;
6367 unsigned long io_extent;
6372 spin_lock_init(&hdspm->lock);
6374 pci_read_config_word(hdspm->pci,
6375 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6377 strcpy(card->mixername, "Xilinx FPGA");
6378 strcpy(card->driver, "HDSPM");
6380 switch (hdspm->firmware_rev) {
6381 case HDSPM_MADI_REV:
6382 hdspm->io_type = MADI;
6383 hdspm->card_name = "RME MADI";
6384 hdspm->midiPorts = 3;
6386 case HDSPM_RAYDAT_REV:
6387 hdspm->io_type = RayDAT;
6388 hdspm->card_name = "RME RayDAT";
6389 hdspm->midiPorts = 2;
6392 hdspm->io_type = AIO;
6393 hdspm->card_name = "RME AIO";
6394 hdspm->midiPorts = 1;
6396 case HDSPM_MADIFACE_REV:
6397 hdspm->io_type = MADIface;
6398 hdspm->card_name = "RME MADIface";
6399 hdspm->midiPorts = 1;
6402 case HDSPM_AES32_REV:
6403 case HDSPM_AES32_OLD_REV:
6404 hdspm->io_type = AES32;
6405 hdspm->card_name = "RME AES32";
6406 hdspm->midiPorts = 2;
6409 snd_printk(KERN_ERR "HDSPM: unknown firmware revision %x\n",
6410 hdspm->firmware_rev);
6414 err = pci_enable_device(pci);
6418 pci_set_master(hdspm->pci);
6420 err = pci_request_regions(pci, "hdspm");
6424 hdspm->port = pci_resource_start(pci, 0);
6425 io_extent = pci_resource_len(pci, 0);
6427 snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6428 hdspm->port, hdspm->port + io_extent - 1);
6430 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6431 if (!hdspm->iobase) {
6432 snd_printk(KERN_ERR "HDSPM: "
6433 "unable to remap region 0x%lx-0x%lx\n",
6434 hdspm->port, hdspm->port + io_extent - 1);
6437 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6438 (unsigned long)hdspm->iobase, hdspm->port,
6439 hdspm->port + io_extent - 1);
6441 if (request_irq(pci->irq, snd_hdspm_interrupt,
6442 IRQF_SHARED, "hdspm", hdspm)) {
6443 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6447 snd_printdd("use IRQ %d\n", pci->irq);
6449 hdspm->irq = pci->irq;
6451 snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6452 sizeof(struct hdspm_mixer));
6453 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6454 if (!hdspm->mixer) {
6455 snd_printk(KERN_ERR "HDSPM: "
6456 "unable to kmalloc Mixer memory of %d Bytes\n",
6457 (int)sizeof(struct hdspm_mixer));
6461 hdspm->port_names_in = NULL;
6462 hdspm->port_names_out = NULL;
6464 switch (hdspm->io_type) {
6466 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6467 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6468 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6470 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6472 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6474 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6476 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6478 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6480 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6483 hdspm->max_channels_out = hdspm->max_channels_in =
6485 hdspm->port_names_in = hdspm->port_names_out =
6487 hdspm->channel_map_in = hdspm->channel_map_out =
6494 hdspm->ss_in_channels = hdspm->ss_out_channels =
6496 hdspm->ds_in_channels = hdspm->ds_out_channels =
6498 hdspm->qs_in_channels = hdspm->qs_out_channels =
6501 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6502 channel_map_unity_ss;
6503 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6504 channel_map_unity_ss;
6505 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6506 channel_map_unity_ss;
6508 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6510 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6512 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6517 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6518 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n");
6521 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6522 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6523 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6524 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6525 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6526 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6528 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6529 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6530 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6532 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6533 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6534 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6536 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6537 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6538 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6539 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6540 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6541 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6546 hdspm->ss_in_channels = hdspm->ss_out_channels =
6548 hdspm->ds_in_channels = hdspm->ds_out_channels =
6550 hdspm->qs_in_channels = hdspm->qs_out_channels =
6553 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6554 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6556 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6557 channel_map_raydat_ss;
6558 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6559 channel_map_raydat_ds;
6560 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6561 channel_map_raydat_qs;
6562 hdspm->channel_map_in = hdspm->channel_map_out =
6563 channel_map_raydat_ss;
6565 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6566 texts_ports_raydat_ss;
6567 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6568 texts_ports_raydat_ds;
6569 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6570 texts_ports_raydat_qs;
6578 switch (hdspm->io_type) {
6581 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6582 HDSPM_s2_tco_detect) {
6584 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6586 if (NULL != hdspm->tco) {
6587 hdspm_tco_write(hdspm);
6589 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6596 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6598 hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6600 if (NULL != hdspm->tco) {
6601 hdspm_tco_write(hdspm);
6603 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n");
6614 switch (hdspm->io_type) {
6617 hdspm->texts_autosync = texts_autosync_aes_tco;
6618 hdspm->texts_autosync_items = 10;
6620 hdspm->texts_autosync = texts_autosync_aes;
6621 hdspm->texts_autosync_items = 9;
6627 hdspm->texts_autosync = texts_autosync_madi_tco;
6628 hdspm->texts_autosync_items = 4;
6630 hdspm->texts_autosync = texts_autosync_madi;
6631 hdspm->texts_autosync_items = 3;
6641 hdspm->texts_autosync = texts_autosync_raydat_tco;
6642 hdspm->texts_autosync_items = 9;
6644 hdspm->texts_autosync = texts_autosync_raydat;
6645 hdspm->texts_autosync_items = 8;
6651 hdspm->texts_autosync = texts_autosync_aio_tco;
6652 hdspm->texts_autosync_items = 6;
6654 hdspm->texts_autosync = texts_autosync_aio;
6655 hdspm->texts_autosync_items = 5;
6661 tasklet_init(&hdspm->midi_tasklet,
6662 hdspm_midi_tasklet, (unsigned long) hdspm);
6664 snd_printdd("create alsa devices.\n");
6665 err = snd_hdspm_create_alsa_devices(card, hdspm);
6669 snd_hdspm_initialize_midi_flush(hdspm);
6675 static int snd_hdspm_free(struct hdspm * hdspm)
6680 /* stop th audio, and cancel all interrupts */
6681 hdspm->control_register &=
6682 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6683 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6684 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6685 hdspm_write(hdspm, HDSPM_controlRegister,
6686 hdspm->control_register);
6689 if (hdspm->irq >= 0)
6690 free_irq(hdspm->irq, (void *) hdspm);
6692 kfree(hdspm->mixer);
6695 iounmap(hdspm->iobase);
6698 pci_release_regions(hdspm->pci);
6700 pci_disable_device(hdspm->pci);
6705 static void snd_hdspm_card_free(struct snd_card *card)
6707 struct hdspm *hdspm = card->private_data;
6710 snd_hdspm_free(hdspm);
6714 static int __devinit snd_hdspm_probe(struct pci_dev *pci,
6715 const struct pci_device_id *pci_id)
6718 struct hdspm *hdspm;
6719 struct snd_card *card;
6722 if (dev >= SNDRV_CARDS)
6729 err = snd_card_create(index[dev], id[dev],
6730 THIS_MODULE, sizeof(struct hdspm), &card);
6734 hdspm = card->private_data;
6735 card->private_free = snd_hdspm_card_free;
6739 snd_card_set_dev(card, &pci->dev);
6741 err = snd_hdspm_create(card, hdspm);
6743 snd_card_free(card);
6747 if (hdspm->io_type != MADIface) {
6748 sprintf(card->shortname, "%s_%x",
6750 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF);
6751 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6753 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF,
6754 hdspm->port, hdspm->irq);
6756 sprintf(card->shortname, "%s", hdspm->card_name);
6757 sprintf(card->longname, "%s at 0x%lx, irq %d",
6758 hdspm->card_name, hdspm->port, hdspm->irq);
6761 err = snd_card_register(card);
6763 snd_card_free(card);
6767 pci_set_drvdata(pci, card);
6773 static void __devexit snd_hdspm_remove(struct pci_dev *pci)
6775 snd_card_free(pci_get_drvdata(pci));
6776 pci_set_drvdata(pci, NULL);
6779 static struct pci_driver driver = {
6780 .name = "RME Hammerfall DSP MADI",
6781 .id_table = snd_hdspm_ids,
6782 .probe = snd_hdspm_probe,
6783 .remove = __devexit_p(snd_hdspm_remove),
6787 static int __init alsa_card_hdspm_init(void)
6789 return pci_register_driver(&driver);
6792 static void __exit alsa_card_hdspm_exit(void)
6794 pci_unregister_driver(&driver);
6797 module_init(alsa_card_hdspm_init)
6798 module_exit(alsa_card_hdspm_exit)