sound/soc/atmel/atmel_ssc_dai.c

   1 /*
   2  * atmel_ssc_dai.c  --  ALSA SoC ATMEL SSC Audio Layer Platform driver
   3  *
   4  * Copyright (C) 2005 SAN People
   5  * Copyright (C) 2008 Atmel
   6  *
   7  * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
   8  *         ATMEL CORP.
   9  *
  10  * Based on at91-ssc.c by
  11  * Frank Mandarino <fmandarino@endrelia.com>
  12  * Based on pxa2xx Platform drivers by
  13  * Liam Girdwood <lrg@slimlogic.co.uk>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  28  */
  29
  30 #include <linux/init.h>
  31 #include <linux/module.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/device.h>
  34 #include <linux/delay.h>
  35 #include <linux/clk.h>
  36 #include <linux/atmel_pdc.h>
  37
  38 #include <linux/atmel-ssc.h>
  39 #include <sound/core.h>
  40 #include <sound/pcm.h>
  41 #include <sound/pcm_params.h>
  42 #include <sound/initval.h>
  43 #include <sound/soc.h>
  44
  45 #include "atmel-pcm.h"
  46 #include "atmel_ssc_dai.h"
  47
  48
  49 #define NUM_SSC_DEVICES         3
  50
  51 /*
  52  * SSC PDC registers required by the PCM DMA engine.
  53  */
  54 static struct atmel_pdc_regs pdc_tx_reg = {
  55         .xpr            = ATMEL_PDC_TPR,
  56         .xcr            = ATMEL_PDC_TCR,
  57         .xnpr           = ATMEL_PDC_TNPR,
  58         .xncr           = ATMEL_PDC_TNCR,
  59 };
  60
  61 static struct atmel_pdc_regs pdc_rx_reg = {
  62         .xpr            = ATMEL_PDC_RPR,
  63         .xcr            = ATMEL_PDC_RCR,
  64         .xnpr           = ATMEL_PDC_RNPR,
  65         .xncr           = ATMEL_PDC_RNCR,
  66 };
  67
  68 /*
  69  * SSC & PDC status bits for transmit and receive.
  70  */
  71 static struct atmel_ssc_mask ssc_tx_mask = {
  72         .ssc_enable     = SSC_BIT(CR_TXEN),
  73         .ssc_disable    = SSC_BIT(CR_TXDIS),
  74         .ssc_endx       = SSC_BIT(SR_ENDTX),
  75         .ssc_endbuf     = SSC_BIT(SR_TXBUFE),
  76         .ssc_error      = SSC_BIT(SR_OVRUN),
  77         .pdc_enable     = ATMEL_PDC_TXTEN,
  78         .pdc_disable    = ATMEL_PDC_TXTDIS,
  79 };
  80
  81 static struct atmel_ssc_mask ssc_rx_mask = {
  82         .ssc_enable     = SSC_BIT(CR_RXEN),
  83         .ssc_disable    = SSC_BIT(CR_RXDIS),
  84         .ssc_endx       = SSC_BIT(SR_ENDRX),
  85         .ssc_endbuf     = SSC_BIT(SR_RXBUFF),
  86         .ssc_error      = SSC_BIT(SR_OVRUN),
  87         .pdc_enable     = ATMEL_PDC_RXTEN,
  88         .pdc_disable    = ATMEL_PDC_RXTDIS,
  89 };
  90
  91
  92 /*
  93  * DMA parameters.
  94  */
  95 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
  96         {{
  97         .name           = "SSC0 PCM out",
  98         .pdc            = &pdc_tx_reg,
  99         .mask           = &ssc_tx_mask,
 100         },
 101         {
 102         .name           = "SSC0 PCM in",
 103         .pdc            = &pdc_rx_reg,
 104         .mask           = &ssc_rx_mask,
 105         } },
 106         {{
 107         .name           = "SSC1 PCM out",
 108         .pdc            = &pdc_tx_reg,
 109         .mask           = &ssc_tx_mask,
 110         },
 111         {
 112         .name           = "SSC1 PCM in",
 113         .pdc            = &pdc_rx_reg,
 114         .mask           = &ssc_rx_mask,
 115         } },
 116         {{
 117         .name           = "SSC2 PCM out",
 118         .pdc            = &pdc_tx_reg,
 119         .mask           = &ssc_tx_mask,
 120         },
 121         {
 122         .name           = "SSC2 PCM in",
 123         .pdc            = &pdc_rx_reg,
 124         .mask           = &ssc_rx_mask,
 125         } },
 126 };
 127
 128
 129 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
 130         {
 131         .name           = "ssc0",
 132         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
 133         .dir_mask       = SSC_DIR_MASK_UNUSED,
 134         .initialized    = 0,
 135         },
 136         {
 137         .name           = "ssc1",
 138         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
 139         .dir_mask       = SSC_DIR_MASK_UNUSED,
 140         .initialized    = 0,
 141         },
 142         {
 143         .name           = "ssc2",
 144         .lock           = __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
 145         .dir_mask       = SSC_DIR_MASK_UNUSED,
 146         .initialized    = 0,
 147         },
 148 };
 149
 150
 151 /*
 152  * SSC interrupt handler.  Passes PDC interrupts to the DMA
 153  * interrupt handler in the PCM driver.
 154  */
 155 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
 156 {
 157         struct atmel_ssc_info *ssc_p = dev_id;
 158         struct atmel_pcm_dma_params *dma_params;
 159         u32 ssc_sr;
 160         u32 ssc_substream_mask;
 161         int i;
 162
 163         ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
 164                         & (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
 165
 166         /*
 167          * Loop through the substreams attached to this SSC.  If
 168          * a DMA-related interrupt occurred on that substream, call
 169          * the DMA interrupt handler function, if one has been
 170          * registered in the dma_params structure by the PCM driver.
 171          */
 172         for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
 173                 dma_params = ssc_p->dma_params[i];
 174
 175                 if ((dma_params != NULL) &&
 176                         (dma_params->dma_intr_handler != NULL)) {
 177                         ssc_substream_mask = (dma_params->mask->ssc_endx |
 178                                         dma_params->mask->ssc_endbuf);
 179                         if (ssc_sr & ssc_substream_mask) {
 180                                 dma_params->dma_intr_handler(ssc_sr,
 181                                                 dma_params->
 182                                                 substream);
 183                         }
 184                 }
 185         }
 186
 187         return IRQ_HANDLED;
 188 }
 189
 190
 191 /*-------------------------------------------------------------------------*\
 192  * DAI functions
 193 \*-------------------------------------------------------------------------*/
 194 /*
 195  * Startup.  Only that one substream allowed in each direction.
 196  */
 197 static int atmel_ssc_startup(struct snd_pcm_substream *substream,
 198                              struct snd_soc_dai *dai)
 199 {
 200         struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
 201         struct atmel_pcm_dma_params *dma_params;
 202         int dir, dir_mask;
 203
 204         pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n",
 205                 ssc_readl(ssc_p->ssc->regs, SR));
 206
 207         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 208                 dir = 0;
 209                 dir_mask = SSC_DIR_MASK_PLAYBACK;
 210         } else {
 211                 dir = 1;
 212                 dir_mask = SSC_DIR_MASK_CAPTURE;
 213         }
 214
 215         dma_params = &ssc_dma_params[dai->id][dir];
 216         dma_params->ssc = ssc_p->ssc;
 217         dma_params->substream = substream;
 218
 219         ssc_p->dma_params[dir] = dma_params;
 220
 221         snd_soc_dai_set_dma_data(dai, substream, dma_params);
 222
 223         spin_lock_irq(&ssc_p->lock);
 224         if (ssc_p->dir_mask & dir_mask) {
 225                 spin_unlock_irq(&ssc_p->lock);
 226                 return -EBUSY;
 227         }
 228         ssc_p->dir_mask |= dir_mask;
 229         spin_unlock_irq(&ssc_p->lock);
 230
 231         return 0;
 232 }
 233
 234 /*
 235  * Shutdown.  Clear DMA parameters and shutdown the SSC if there
 236  * are no other substreams open.
 237  */
 238 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
 239                                struct snd_soc_dai *dai)
 240 {
 241         struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
 242         struct atmel_pcm_dma_params *dma_params;
 243         int dir, dir_mask;
 244
 245         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 246                 dir = 0;
 247         else
 248                 dir = 1;
 249
 250         dma_params = ssc_p->dma_params[dir];
 251
 252         if (dma_params != NULL) {
 253                 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
 254                 pr_debug("atmel_ssc_shutdown: %s disabled SSC_SR=0x%08x\n",
 255                         (dir ? "receive" : "transmit"),
 256                         ssc_readl(ssc_p->ssc->regs, SR));
 257
 258                 dma_params->ssc = NULL;
 259                 dma_params->substream = NULL;
 260                 ssc_p->dma_params[dir] = NULL;
 261         }
 262
 263         dir_mask = 1 << dir;
 264
 265         spin_lock_irq(&ssc_p->lock);
 266         ssc_p->dir_mask &= ~dir_mask;
 267         if (!ssc_p->dir_mask) {
 268                 if (ssc_p->initialized) {
 269                         /* Shutdown the SSC clock. */
 270                         pr_debug("atmel_ssc_dai: Stopping clock\n");
 271                         clk_disable(ssc_p->ssc->clk);
 272
 273                         free_irq(ssc_p->ssc->irq, ssc_p);
 274                         ssc_p->initialized = 0;
 275                 }
 276
 277                 /* Reset the SSC */
 278                 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
 279                 /* Clear the SSC dividers */
 280                 ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
 281         }
 282         spin_unlock_irq(&ssc_p->lock);
 283 }
 284
 285
 286 /*
 287  * Record the DAI format for use in hw_params().
 288  */
 289 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 290                 unsigned int fmt)
 291 {
 292         struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
 293
 294         ssc_p->daifmt = fmt;
 295         return 0;
 296 }
 297
 298 /*
 299  * Record SSC clock dividers for use in hw_params().
 300  */
 301 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
 302         int div_id, int div)
 303 {
 304         struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
 305
 306         switch (div_id) {
 307         case ATMEL_SSC_CMR_DIV:
 308                 /*
 309                  * The same master clock divider is used for both
 310                  * transmit and receive, so if a value has already
 311                  * been set, it must match this value.
 312                  */
 313                 if (ssc_p->dir_mask !=
 314                         (SSC_DIR_MASK_PLAYBACK | SSC_DIR_MASK_CAPTURE))
 315                         ssc_p->cmr_div = div;
 316                 else if (ssc_p->cmr_div == 0)
 317                         ssc_p->cmr_div = div;
 318                 else
 319                         if (div != ssc_p->cmr_div)
 320                                 return -EBUSY;
 321                 break;
 322
 323         case ATMEL_SSC_TCMR_PERIOD:
 324                 ssc_p->tcmr_period = div;
 325                 break;
 326
 327         case ATMEL_SSC_RCMR_PERIOD:
 328                 ssc_p->rcmr_period = div;
 329                 break;
 330
 331         default:
 332                 return -EINVAL;
 333         }
 334
 335         return 0;
 336 }
 337
 338 /*
 339  * Configure the SSC.
 340  */
 341 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
 342         struct snd_pcm_hw_params *params,
 343         struct snd_soc_dai *dai)
 344 {
 345         int id = dai->id;
 346         struct atmel_ssc_info *ssc_p = &ssc_info[id];
 347         struct ssc_device *ssc = ssc_p->ssc;
 348         struct atmel_pcm_dma_params *dma_params;
 349         int dir, channels, bits;
 350         u32 tfmr, rfmr, tcmr, rcmr;
 351         int ret;
 352         int fslen, fslen_ext;
 353
 354         /*
 355          * Currently, there is only one set of dma params for
 356          * each direction.  If more are added, this code will
 357          * have to be changed to select the proper set.
 358          */
 359         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 360                 dir = 0;
 361         else
 362                 dir = 1;
 363
 364         dma_params = ssc_p->dma_params[dir];
 365
 366         channels = params_channels(params);
 367
 368         /*
 369          * Determine sample size in bits and the PDC increment.
 370          */
 371         switch (params_format(params)) {
 372         case SNDRV_PCM_FORMAT_S8:
 373                 bits = 8;
 374                 dma_params->pdc_xfer_size = 1;
 375                 break;
 376         case SNDRV_PCM_FORMAT_S16_LE:
 377                 bits = 16;
 378                 dma_params->pdc_xfer_size = 2;
 379                 break;
 380         case SNDRV_PCM_FORMAT_S24_LE:
 381                 bits = 24;
 382                 dma_params->pdc_xfer_size = 4;
 383                 break;
 384         case SNDRV_PCM_FORMAT_S32_LE:
 385                 bits = 32;
 386                 dma_params->pdc_xfer_size = 4;
 387                 break;
 388         default:
 389                 printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
 390                 return -EINVAL;
 391         }
 392
 393         /*
 394          * Compute SSC register settings.
 395          */
 396         switch (ssc_p->daifmt
 397                 & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
 398
 399         case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
 400                 /*
 401                  * I2S format, SSC provides BCLK and LRC clocks.
 402                  *
 403                  * The SSC transmit and receive clocks are generated
 404                  * from the MCK divider, and the BCLK signal
 405                  * is output on the SSC TK line.
 406                  */
 407
 408                 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
 409                         dev_err(dai->dev,
 410                                 "sample size %d is too large for SSC device\n",
 411                                 bits);
 412                         return -EINVAL;
 413                 }
 414
 415                 fslen_ext = (bits - 1) / 16;
 416                 fslen = (bits - 1) % 16;
 417
 418                 rcmr =    SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
 419                         | SSC_BF(RCMR_STTDLY, START_DELAY)
 420                         | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
 421                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 422                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 423                         | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
 424
 425                 rfmr =    SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
 426                         | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 427                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
 428                         | SSC_BF(RFMR_FSLEN, fslen)
 429                         | SSC_BF(RFMR_DATNB, (channels - 1))
 430                         | SSC_BIT(RFMR_MSBF)
 431                         | SSC_BF(RFMR_LOOP, 0)
 432                         | SSC_BF(RFMR_DATLEN, (bits - 1));
 433
 434                 tcmr =    SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
 435                         | SSC_BF(TCMR_STTDLY, START_DELAY)
 436                         | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
 437                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
 438                         | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
 439                         | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
 440
 441                 tfmr =    SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
 442                         | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 443                         | SSC_BF(TFMR_FSDEN, 0)
 444                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
 445                         | SSC_BF(TFMR_FSLEN, fslen)
 446                         | SSC_BF(TFMR_DATNB, (channels - 1))
 447                         | SSC_BIT(TFMR_MSBF)
 448                         | SSC_BF(TFMR_DATDEF, 0)
 449                         | SSC_BF(TFMR_DATLEN, (bits - 1));
 450                 break;
 451
 452         case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
 453                 /* I2S format, CODEC supplies BCLK and LRC clocks. */
 454                 rcmr =    SSC_BF(RCMR_PERIOD, 0)
 455                         | SSC_BF(RCMR_STTDLY, START_DELAY)
 456                         | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
 457                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 458                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 459                         | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
 460                                            SSC_CKS_PIN : SSC_CKS_CLOCK);
 461
 462                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 463                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
 464                         | SSC_BF(RFMR_FSLEN, 0)
 465                         | SSC_BF(RFMR_DATNB, (channels - 1))
 466                         | SSC_BIT(RFMR_MSBF)
 467                         | SSC_BF(RFMR_LOOP, 0)
 468                         | SSC_BF(RFMR_DATLEN, (bits - 1));
 469
 470                 tcmr =    SSC_BF(TCMR_PERIOD, 0)
 471                         | SSC_BF(TCMR_STTDLY, START_DELAY)
 472                         | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
 473                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
 474                         | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
 475                         | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
 476                                            SSC_CKS_CLOCK : SSC_CKS_PIN);
 477
 478                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 479                         | SSC_BF(TFMR_FSDEN, 0)
 480                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
 481                         | SSC_BF(TFMR_FSLEN, 0)
 482                         | SSC_BF(TFMR_DATNB, (channels - 1))
 483                         | SSC_BIT(TFMR_MSBF)
 484                         | SSC_BF(TFMR_DATDEF, 0)
 485                         | SSC_BF(TFMR_DATLEN, (bits - 1));
 486                 break;
 487
 488         case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFS:
 489                 /* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */
 490                 if (bits > 16 && !ssc->pdata->has_fslen_ext) {
 491                         dev_err(dai->dev,
 492                                 "sample size %d is too large for SSC device\n",
 493                                 bits);
 494                         return -EINVAL;
 495                 }
 496
 497                 fslen_ext = (bits - 1) / 16;
 498                 fslen = (bits - 1) % 16;
 499
 500                 rcmr =    SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
 501                         | SSC_BF(RCMR_STTDLY, START_DELAY)
 502                         | SSC_BF(RCMR_START, SSC_START_FALLING_RF)
 503                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 504                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 505                         | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
 506                                            SSC_CKS_PIN : SSC_CKS_CLOCK);
 507
 508                 rfmr =    SSC_BF(RFMR_FSLEN_EXT, fslen_ext)
 509                         | SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 510                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
 511                         | SSC_BF(RFMR_FSLEN, fslen)
 512                         | SSC_BF(RFMR_DATNB, (channels - 1))
 513                         | SSC_BIT(RFMR_MSBF)
 514                         | SSC_BF(RFMR_LOOP, 0)
 515                         | SSC_BF(RFMR_DATLEN, (bits - 1));
 516
 517                 tcmr =    SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
 518                         | SSC_BF(TCMR_STTDLY, START_DELAY)
 519                         | SSC_BF(TCMR_START, SSC_START_FALLING_RF)
 520                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
 521                         | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
 522                         | SSC_BF(TCMR_CKS, ssc->clk_from_rk_pin ?
 523                                            SSC_CKS_CLOCK : SSC_CKS_PIN);
 524
 525                 tfmr =    SSC_BF(TFMR_FSLEN_EXT, fslen_ext)
 526                         | SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_NEGATIVE)
 527                         | SSC_BF(TFMR_FSDEN, 0)
 528                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
 529                         | SSC_BF(TFMR_FSLEN, fslen)
 530                         | SSC_BF(TFMR_DATNB, (channels - 1))
 531                         | SSC_BIT(TFMR_MSBF)
 532                         | SSC_BF(TFMR_DATDEF, 0)
 533                         | SSC_BF(TFMR_DATLEN, (bits - 1));
 534                 break;
 535
 536         case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
 537                 /*
 538                  * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
 539                  *
 540                  * The SSC transmit and receive clocks are generated from the
 541                  * MCK divider, and the BCLK signal is output
 542                  * on the SSC TK line.
 543                  */
 544                 rcmr =    SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
 545                         | SSC_BF(RCMR_STTDLY, 1)
 546                         | SSC_BF(RCMR_START, SSC_START_RISING_RF)
 547                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 548                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 549                         | SSC_BF(RCMR_CKS, SSC_CKS_DIV);
 550
 551                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 552                         | SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
 553                         | SSC_BF(RFMR_FSLEN, 0)
 554                         | SSC_BF(RFMR_DATNB, (channels - 1))
 555                         | SSC_BIT(RFMR_MSBF)
 556                         | SSC_BF(RFMR_LOOP, 0)
 557                         | SSC_BF(RFMR_DATLEN, (bits - 1));
 558
 559                 tcmr =    SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
 560                         | SSC_BF(TCMR_STTDLY, 1)
 561                         | SSC_BF(TCMR_START, SSC_START_RISING_RF)
 562                         | SSC_BF(TCMR_CKI, SSC_CKI_RISING)
 563                         | SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
 564                         | SSC_BF(TCMR_CKS, SSC_CKS_DIV);
 565
 566                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 567                         | SSC_BF(TFMR_FSDEN, 0)
 568                         | SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
 569                         | SSC_BF(TFMR_FSLEN, 0)
 570                         | SSC_BF(TFMR_DATNB, (channels - 1))
 571                         | SSC_BIT(TFMR_MSBF)
 572                         | SSC_BF(TFMR_DATDEF, 0)
 573                         | SSC_BF(TFMR_DATLEN, (bits - 1));
 574                 break;
 575
 576         case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
 577                 /*
 578                  * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
 579                  *
 580                  * Data is transferred on first BCLK after LRC pulse rising
 581                  * edge.If stereo, the right channel data is contiguous with
 582                  * the left channel data.
 583                  */
 584                 rcmr =    SSC_BF(RCMR_PERIOD, 0)
 585                         | SSC_BF(RCMR_STTDLY, START_DELAY)
 586                         | SSC_BF(RCMR_START, SSC_START_RISING_RF)
 587                         | SSC_BF(RCMR_CKI, SSC_CKI_RISING)
 588                         | SSC_BF(RCMR_CKO, SSC_CKO_NONE)
 589                         | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
 590                                            SSC_CKS_PIN : SSC_CKS_CLOCK);
 591
 592                 rfmr =    SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 593                         | SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
 594                         | SSC_BF(RFMR_FSLEN, 0)
 595                         | SSC_BF(RFMR_DATNB, (channels - 1))
 596                         | SSC_BIT(RFMR_MSBF)
 597                         | SSC_BF(RFMR_LOOP, 0)
 598                         | SSC_BF(RFMR_DATLEN, (bits - 1));
 599
 600                 tcmr =    SSC_BF(TCMR_PERIOD, 0)
 601                         | SSC_BF(TCMR_STTDLY, START_DELAY)
 602                         | SSC_BF(TCMR_START, SSC_START_RISING_RF)
 603                         | SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
 604                         | SSC_BF(TCMR_CKO, SSC_CKO_NONE)
 605                         | SSC_BF(RCMR_CKS, ssc->clk_from_rk_pin ?
 606                                            SSC_CKS_CLOCK : SSC_CKS_PIN);
 607
 608                 tfmr =    SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
 609                         | SSC_BF(TFMR_FSDEN, 0)
 610                         | SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
 611                         | SSC_BF(TFMR_FSLEN, 0)
 612                         | SSC_BF(TFMR_DATNB, (channels - 1))
 613                         | SSC_BIT(TFMR_MSBF)
 614                         | SSC_BF(TFMR_DATDEF, 0)
 615                         | SSC_BF(TFMR_DATLEN, (bits - 1));
 616                 break;
 617
 618         default:
 619                 printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
 620                         ssc_p->daifmt);
 621                 return -EINVAL;
 622         }
 623         pr_debug("atmel_ssc_hw_params: "
 624                         "RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
 625                         rcmr, rfmr, tcmr, tfmr);
 626
 627         if (!ssc_p->initialized) {
 628
 629                 /* Enable PMC peripheral clock for this SSC */
 630                 pr_debug("atmel_ssc_dai: Starting clock\n");
 631                 clk_enable(ssc_p->ssc->clk);
 632
 633                 /* Reset the SSC and its PDC registers */
 634                 ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
 635
 636                 ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
 637                 ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
 638                 ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
 639                 ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
 640
 641                 ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
 642                 ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
 643                 ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
 644                 ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
 645
 646                 ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
 647                                 ssc_p->name, ssc_p);
 648                 if (ret < 0) {
 649                         printk(KERN_WARNING
 650                                         "atmel_ssc_dai: request_irq failure\n");
 651                         pr_debug("Atmel_ssc_dai: Stoping clock\n");
 652                         clk_disable(ssc_p->ssc->clk);
 653                         return ret;
 654                 }
 655
 656                 ssc_p->initialized = 1;
 657         }
 658
 659         /* set SSC clock mode register */
 660         ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
 661
 662         /* set receive clock mode and format */
 663         ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
 664         ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
 665
 666         /* set transmit clock mode and format */
 667         ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
 668         ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
 669
 670         pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
 671         return 0;
 672 }
 673
 674
 675 static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
 676                              struct snd_soc_dai *dai)
 677 {
 678         struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
 679         struct atmel_pcm_dma_params *dma_params;
 680         int dir;
 681
 682         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 683                 dir = 0;
 684         else
 685                 dir = 1;
 686
 687         dma_params = ssc_p->dma_params[dir];
 688
 689         ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
 690         ssc_writel(ssc_p->ssc->regs, IDR, dma_params->mask->ssc_error);
 691
 692         pr_debug("%s enabled SSC_SR=0x%08x\n",
 693                         dir ? "receive" : "transmit",
 694                         ssc_readl(ssc_p->ssc->regs, SR));
 695         return 0;
 696 }
 697
 698 static int atmel_ssc_trigger(struct snd_pcm_substream *substream,
 699                              int cmd, struct snd_soc_dai *dai)
 700 {
 701         struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
 702         struct atmel_pcm_dma_params *dma_params;
 703         int dir;
 704
 705         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 706                 dir = 0;
 707         else
 708                 dir = 1;
 709
 710         dma_params = ssc_p->dma_params[dir];
 711
 712         switch (cmd) {
 713         case SNDRV_PCM_TRIGGER_START:
 714         case SNDRV_PCM_TRIGGER_RESUME:
 715         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 716                 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
 717                 break;
 718         default:
 719                 ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
 720                 break;
 721         }
 722
 723         return 0;
 724 }
 725
 726 #ifdef CONFIG_PM
 727 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
 728 {
 729         struct atmel_ssc_info *ssc_p;
 730
 731         if (!cpu_dai->active)
 732                 return 0;
 733
 734         ssc_p = &ssc_info[cpu_dai->id];
 735
 736         /* Save the status register before disabling transmit and receive */
 737         ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
 738         ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
 739
 740         /* Save the current interrupt mask, then disable unmasked interrupts */
 741         ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
 742         ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
 743
 744         ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
 745         ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
 746         ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
 747         ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
 748         ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
 749
 750         return 0;
 751 }
 752
 753
 754
 755 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
 756 {
 757         struct atmel_ssc_info *ssc_p;
 758         u32 cr;
 759
 760         if (!cpu_dai->active)
 761                 return 0;
 762
 763         ssc_p = &ssc_info[cpu_dai->id];
 764
 765         /* restore SSC register settings */
 766         ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
 767         ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
 768         ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
 769         ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
 770         ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
 771
 772         /* re-enable interrupts */
 773         ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
 774
 775         /* Re-enable receive and transmit as appropriate */
 776         cr = 0;
 777         cr |=
 778             (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
 779         cr |=
 780             (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
 781         ssc_writel(ssc_p->ssc->regs, CR, cr);
 782
 783         return 0;
 784 }
 785 #else /* CONFIG_PM */
 786 #  define atmel_ssc_suspend     NULL
 787 #  define atmel_ssc_resume      NULL
 788 #endif /* CONFIG_PM */
 789
 790 #define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000)
 791
 792 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8     | SNDRV_PCM_FMTBIT_S16_LE |\
 793                           SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 794
 795 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
 796         .startup        = atmel_ssc_startup,
 797         .shutdown       = atmel_ssc_shutdown,
 798         .prepare        = atmel_ssc_prepare,
 799         .trigger        = atmel_ssc_trigger,
 800         .hw_params      = atmel_ssc_hw_params,
 801         .set_fmt        = atmel_ssc_set_dai_fmt,
 802         .set_clkdiv     = atmel_ssc_set_dai_clkdiv,
 803 };
 804
 805 static struct snd_soc_dai_driver atmel_ssc_dai = {
 806                 .suspend = atmel_ssc_suspend,
 807                 .resume = atmel_ssc_resume,
 808                 .playback = {
 809                         .channels_min = 1,
 810                         .channels_max = 2,
 811                         .rates = ATMEL_SSC_RATES,
 812                         .formats = ATMEL_SSC_FORMATS,},
 813                 .capture = {
 814                         .channels_min = 1,
 815                         .channels_max = 2,
 816                         .rates = ATMEL_SSC_RATES,
 817                         .formats = ATMEL_SSC_FORMATS,},
 818                 .ops = &atmel_ssc_dai_ops,
 819 };
 820
 821 static const struct snd_soc_component_driver atmel_ssc_component = {
 822         .name           = "atmel-ssc",
 823 };
 824
 825 static int asoc_ssc_init(struct device *dev)
 826 {
 827         struct platform_device *pdev = to_platform_device(dev);
 828         struct ssc_device *ssc = platform_get_drvdata(pdev);
 829         int ret;
 830
 831         ret = snd_soc_register_component(dev, &atmel_ssc_component,
 832                                          &atmel_ssc_dai, 1);
 833         if (ret) {
 834                 dev_err(dev, "Could not register DAI: %d\n", ret);
 835                 goto err;
 836         }
 837
 838         if (ssc->pdata->use_dma)
 839                 ret = atmel_pcm_dma_platform_register(dev);
 840         else
 841                 ret = atmel_pcm_pdc_platform_register(dev);
 842
 843         if (ret) {
 844                 dev_err(dev, "Could not register PCM: %d\n", ret);
 845                 goto err_unregister_dai;
 846         }
 847
 848         return 0;
 849
 850 err_unregister_dai:
 851         snd_soc_unregister_component(dev);
 852 err:
 853         return ret;
 854 }
 855
 856 static void asoc_ssc_exit(struct device *dev)
 857 {
 858         struct platform_device *pdev = to_platform_device(dev);
 859         struct ssc_device *ssc = platform_get_drvdata(pdev);
 860
 861         if (ssc->pdata->use_dma)
 862                 atmel_pcm_dma_platform_unregister(dev);
 863         else
 864                 atmel_pcm_pdc_platform_unregister(dev);
 865
 866         snd_soc_unregister_component(dev);
 867 }
 868
 869 /**
 870  * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
 871  */
 872 int atmel_ssc_set_audio(int ssc_id)
 873 {
 874         struct ssc_device *ssc;
 875         int ret;
 876
 877         /* If we can grab the SSC briefly to parent the DAI device off it */
 878         ssc = ssc_request(ssc_id);
 879         if (IS_ERR(ssc)) {
 880                 pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
 881                         PTR_ERR(ssc));
 882                 return PTR_ERR(ssc);
 883         } else {
 884                 ssc_info[ssc_id].ssc = ssc;
 885         }
 886
 887         ret = asoc_ssc_init(&ssc->pdev->dev);
 888
 889         return ret;
 890 }
 891 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
 892
 893 void atmel_ssc_put_audio(int ssc_id)
 894 {
 895         struct ssc_device *ssc = ssc_info[ssc_id].ssc;
 896
 897         asoc_ssc_exit(&ssc->pdev->dev);
 898         ssc_free(ssc);
 899 }
 900 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
 901
 902 /* Module information */
 903 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
 904 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
 905 MODULE_LICENSE("GPL");