1 /* sound/soc/at32/playpaq_wm8510.c
2 * ASoC machine driver for PlayPaq using WM8510 codec
4 * Copyright (C) 2008 Long Range Systems
5 * Geoffrey Wossum <gwossum@acm.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This code is largely inspired by sound/soc/at91/eti_b1_wm8731.c
13 * NOTE: If you don't have the AT32 enhanced portmux configured (which
14 * isn't currently in the mainline or Atmel patched kernel), you will
15 * need to set the MCLK pin (PA30) to peripheral A in your board initialization
16 * code. Something like:
17 * at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/kernel.h>
26 #include <linux/errno.h>
27 #include <linux/clk.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/platform_device.h>
32 #include <sound/core.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/soc.h>
37 #include <mach/at32ap700x.h>
38 #include <mach/portmux.h>
40 #include "../codecs/wm8510.h"
41 #include "atmel-pcm.h"
42 #include "atmel_ssc_dai.h"
45 /*-------------------------------------------------------------------------*\
47 \*-------------------------------------------------------------------------*/
48 #define MCLK_PIN GPIO_PIN_PA(30)
49 #define MCLK_PERIPH GPIO_PERIPH_A
52 /*-------------------------------------------------------------------------*\
54 \*-------------------------------------------------------------------------*/
55 /* SSC clocking data */
56 struct ssc_clock_data {
60 /* Frame period (as needed by xCMR.PERIOD) */
63 /* The SSC clock rate these settings where calculated for */
64 unsigned long ssc_rate;
68 /*-------------------------------------------------------------------------*\
70 \*-------------------------------------------------------------------------*/
71 static struct clk *_gclk0;
72 static struct clk *_pll0;
74 #define CODEC_CLK (_gclk0)
77 /*-------------------------------------------------------------------------*\
78 * Sound SOC operations
79 \*-------------------------------------------------------------------------*/
80 #if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
81 static struct ssc_clock_data playpaq_wm8510_calc_ssc_clock(
82 struct snd_pcm_hw_params *params,
83 struct snd_soc_dai *cpu_dai)
85 struct at32_ssc_info *ssc_p = snd_soc_dai_get_drvdata(cpu_dai);
86 struct ssc_device *ssc = ssc_p->ssc;
87 struct ssc_clock_data cd;
88 unsigned int rate, width_bits, channels;
89 unsigned int bitrate, ssc_div;
94 * Figure out required bitrate
96 rate = params_rate(params);
97 channels = params_channels(params);
98 width_bits = snd_pcm_format_physical_width(params_format(params));
99 bitrate = rate * width_bits * channels;
103 * Figure out required SSC divider and period for required bitrate
105 cd.ssc_rate = clk_get_rate(ssc->clk);
106 ssc_div = cd.ssc_rate / bitrate;
107 cd.cmr_div = ssc_div / 2;
109 /* round cmr_div up */
112 cd.period = width_bits - 1;
116 * Find actual rate, compare to requested rate
118 actual_rate = (cd.ssc_rate / (cd.cmr_div * 2)) / (2 * (cd.period + 1));
119 pr_debug("playpaq_wm8510: Request rate = %u, actual rate = %u\n",
125 #endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
129 static int playpaq_wm8510_hw_params(struct snd_pcm_substream *substream,
130 struct snd_pcm_hw_params *params)
132 struct snd_soc_pcm_runtime *rtd = substream->private_data;
133 struct snd_soc_dai *codec_dai = rtd->codec_dai;
134 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
135 struct at32_ssc_info *ssc_p = snd_soc_dai_get_drvdata(cpu_dai);
136 struct ssc_device *ssc = ssc_p->ssc;
137 unsigned int pll_out = 0, bclk = 0, mclk_div = 0;
141 /* Due to difficulties with getting the correct clocks from the AT32's
142 * PLL0, we're going to let the CODEC be in charge of all the clocks
144 #if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
145 const unsigned int fmt = (SND_SOC_DAIFMT_I2S |
146 SND_SOC_DAIFMT_NB_NF |
147 SND_SOC_DAIFMT_CBM_CFM);
149 struct ssc_clock_data cd;
150 const unsigned int fmt = (SND_SOC_DAIFMT_I2S |
151 SND_SOC_DAIFMT_NB_NF |
152 SND_SOC_DAIFMT_CBS_CFS);
156 pr_warning("playpaq_wm8510_hw_params: ssc is NULL!\n");
162 * Figure out PLL and BCLK dividers for WM8510
164 switch (params_rate(params)) {
167 mclk_div = WM8510_MCLKDIV_2;
168 bclk = WM8510_BCLKDIV_8;
173 mclk_div = WM8510_MCLKDIV_2;
174 bclk = WM8510_BCLKDIV_8;
179 mclk_div = WM8510_MCLKDIV_4;
180 bclk = WM8510_BCLKDIV_8;
185 mclk_div = WM8510_MCLKDIV_6;
186 bclk = WM8510_BCLKDIV_8;
191 mclk_div = WM8510_MCLKDIV_8;
192 bclk = WM8510_BCLKDIV_8;
197 mclk_div = WM8510_MCLKDIV_12;
198 bclk = WM8510_BCLKDIV_8;
202 pr_warning("playpaq_wm8510: Unsupported sample rate %d\n",
203 params_rate(params));
209 * set CPU and CODEC DAI configuration
211 ret = snd_soc_dai_set_fmt(codec_dai, fmt);
213 pr_warning("playpaq_wm8510: "
214 "Failed to set CODEC DAI format (%d)\n",
218 ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
220 pr_warning("playpaq_wm8510: "
221 "Failed to set CPU DAI format (%d)\n",
228 * Set CPU clock configuration
230 #if defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
231 cd = playpaq_wm8510_calc_ssc_clock(params, cpu_dai);
232 pr_debug("playpaq_wm8510: cmr_div = %d, period = %d\n",
233 cd.cmr_div, cd.period);
234 ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_CMR_DIV, cd.cmr_div);
236 pr_warning("playpaq_wm8510: Failed to set CPU CMR_DIV (%d)\n",
240 ret = snd_soc_dai_set_clkdiv(cpu_dai, AT32_SSC_TCMR_PERIOD,
243 pr_warning("playpaq_wm8510: "
244 "Failed to set CPU transmit period (%d)\n",
248 #endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
252 * Set CODEC clock configuration
254 pr_debug("playpaq_wm8510: "
255 "pll_in = %ld, pll_out = %u, bclk = %x, mclk = %x\n",
256 clk_get_rate(CODEC_CLK), pll_out, bclk, mclk_div);
259 #if !defined CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE
260 ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_BCLKDIV, bclk);
263 ("playpaq_wm8510: Failed to set CODEC DAI BCLKDIV (%d)\n",
267 #endif /* CONFIG_SND_AT32_SOC_PLAYPAQ_SLAVE */
270 ret = snd_soc_dai_set_pll(codec_dai, 0, 0,
271 clk_get_rate(CODEC_CLK), pll_out);
273 pr_warning("playpaq_wm8510: Failed to set CODEC DAI PLL (%d)\n",
279 ret = snd_soc_dai_set_clkdiv(codec_dai, WM8510_MCLKDIV, mclk_div);
281 pr_warning("playpaq_wm8510: Failed to set CODEC MCLKDIV (%d)\n",
292 static struct snd_soc_ops playpaq_wm8510_ops = {
293 .hw_params = playpaq_wm8510_hw_params,
298 static const struct snd_soc_dapm_widget playpaq_dapm_widgets[] = {
299 SND_SOC_DAPM_MIC("Int Mic", NULL),
300 SND_SOC_DAPM_SPK("Ext Spk", NULL),
305 static const struct snd_soc_dapm_route intercon[] = {
306 /* speaker connected to SPKOUT */
307 {"Ext Spk", NULL, "SPKOUTP"},
308 {"Ext Spk", NULL, "SPKOUTN"},
310 {"Mic Bias", NULL, "Int Mic"},
311 {"MICN", NULL, "Mic Bias"},
312 {"MICP", NULL, "Mic Bias"},
317 static int playpaq_wm8510_init(struct snd_soc_pcm_runtime *rtd)
319 struct snd_soc_codec *codec = rtd->codec;
320 struct snd_soc_dapm_context *dapm = &codec->dapm;
326 for (i = 0; i < ARRAY_SIZE(playpaq_dapm_widgets); i++)
327 snd_soc_dapm_new_control(dapm, &playpaq_dapm_widgets[i]);
332 * Setup audio path interconnects
334 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
338 /* always connected pins */
339 snd_soc_dapm_enable_pin(dapm, "Int Mic");
340 snd_soc_dapm_enable_pin(dapm, "Ext Spk");
341 snd_soc_dapm_sync(dapm);
345 /* Make CSB show PLL rate */
346 snd_soc_dai_set_clkdiv(rtd->codec_dai, WM8510_OPCLKDIV,
347 WM8510_OPCLKDIV_1 | 4);
354 static struct snd_soc_dai_link playpaq_wm8510_dai = {
356 .stream_name = "WM8510 PCM",
357 .cpu_dai_name= "atmel-ssc-dai.0",
358 .platform_name = "atmel-pcm-audio",
359 .codec_name = "wm8510-codec.0-0x1a",
360 .codec_dai_name = "wm8510-hifi",
361 .init = playpaq_wm8510_init,
362 .ops = &playpaq_wm8510_ops,
367 static struct snd_soc_card snd_soc_playpaq = {
368 .name = "LRS_PlayPaq_WM8510",
369 .dai_link = &playpaq_wm8510_dai,
373 static struct platform_device *playpaq_snd_device;
376 static int __init playpaq_asoc_init(void)
381 * Configure MCLK for WM8510
383 _gclk0 = clk_get(NULL, "gclk0");
384 if (IS_ERR(_gclk0)) {
388 _pll0 = clk_get(NULL, "pll0");
393 if (clk_set_parent(_gclk0, _pll0)) {
394 pr_warning("snd-soc-playpaq: "
395 "Failed to set PLL0 as parent for DAC clock\n");
398 clk_set_rate(CODEC_CLK, 12000000);
399 clk_enable(CODEC_CLK);
401 #if defined CONFIG_AT32_ENHANCED_PORTMUX
402 at32_select_periph(MCLK_PIN, MCLK_PERIPH, 0);
407 * Create and register platform device
409 playpaq_snd_device = platform_device_alloc("soc-audio", 0);
410 if (playpaq_snd_device == NULL) {
412 goto err_device_alloc;
415 platform_set_drvdata(playpaq_snd_device, &snd_soc_playpaq);
417 ret = platform_device_add(playpaq_snd_device);
419 pr_warning("playpaq_wm8510: platform_device_add failed (%d)\n",
428 if (playpaq_snd_device != NULL) {
429 platform_device_put(playpaq_snd_device);
430 playpaq_snd_device = NULL;
439 if (_gclk0 != NULL) {
447 static void __exit playpaq_asoc_exit(void)
449 if (_gclk0 != NULL) {
458 #if defined CONFIG_AT32_ENHANCED_PORTMUX
459 at32_free_pin(MCLK_PIN);
462 platform_device_unregister(playpaq_snd_device);
463 playpaq_snd_device = NULL;
466 module_init(playpaq_asoc_init);
467 module_exit(playpaq_asoc_exit);
469 MODULE_AUTHOR("Geoffrey Wossum <gwossum@acm.org>");
470 MODULE_DESCRIPTION("ASoC machine driver for LRS PlayPaq");
471 MODULE_LICENSE("GPL");