2 * Common code for ADAU1X61 and ADAU1X81 codecs
4 * Copyright 2011-2014 Analog Devices Inc.
5 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 * Licensed under the GPL-2 or later.
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/slab.h>
15 #include <sound/core.h>
16 #include <sound/pcm.h>
17 #include <sound/pcm_params.h>
18 #include <sound/soc.h>
19 #include <sound/tlv.h>
20 #include <linux/gcd.h>
21 #include <linux/i2c.h>
22 #include <linux/spi/spi.h>
23 #include <linux/regmap.h>
27 #include "adau-utils.h"
29 static const char * const adau17x1_capture_mixer_boost_text[] = {
30 "Normal operation", "Boost Level 1", "Boost Level 2", "Boost Level 3",
33 static SOC_ENUM_SINGLE_DECL(adau17x1_capture_boost_enum,
34 ADAU17X1_REC_POWER_MGMT, 5, adau17x1_capture_mixer_boost_text);
36 static const char * const adau17x1_mic_bias_mode_text[] = {
37 "Normal operation", "High performance",
40 static SOC_ENUM_SINGLE_DECL(adau17x1_mic_bias_mode_enum,
41 ADAU17X1_MICBIAS, 3, adau17x1_mic_bias_mode_text);
43 static const DECLARE_TLV_DB_MINMAX(adau17x1_digital_tlv, -9563, 0);
45 static const struct snd_kcontrol_new adau17x1_controls[] = {
46 SOC_DOUBLE_R_TLV("Digital Capture Volume",
47 ADAU17X1_LEFT_INPUT_DIGITAL_VOL,
48 ADAU17X1_RIGHT_INPUT_DIGITAL_VOL,
49 0, 0xff, 1, adau17x1_digital_tlv),
50 SOC_DOUBLE_R_TLV("Digital Playback Volume", ADAU17X1_DAC_CONTROL1,
51 ADAU17X1_DAC_CONTROL2, 0, 0xff, 1, adau17x1_digital_tlv),
53 SOC_SINGLE("ADC High Pass Filter Switch", ADAU17X1_ADC_CONTROL,
55 SOC_SINGLE("Playback De-emphasis Switch", ADAU17X1_DAC_CONTROL0,
58 SOC_ENUM("Capture Boost", adau17x1_capture_boost_enum),
60 SOC_ENUM("Mic Bias Mode", adau17x1_mic_bias_mode_enum),
63 static int adau17x1_pll_event(struct snd_soc_dapm_widget *w,
64 struct snd_kcontrol *kcontrol, int event)
66 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
67 struct adau *adau = snd_soc_codec_get_drvdata(codec);
69 if (SND_SOC_DAPM_EVENT_ON(event)) {
70 adau->pll_regs[5] = 1;
72 adau->pll_regs[5] = 0;
73 /* Bypass the PLL when disabled, otherwise registers will become
75 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
76 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL, 0);
79 /* The PLL register is 6 bytes long and can only be written at once. */
80 regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
81 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
83 if (SND_SOC_DAPM_EVENT_ON(event)) {
85 regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL,
86 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL,
87 ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL);
93 static const char * const adau17x1_mono_stereo_text[] = {
95 "Mono Left Channel (L+R)",
96 "Mono Right Channel (L+R)",
100 static SOC_ENUM_SINGLE_DECL(adau17x1_dac_mode_enum,
101 ADAU17X1_DAC_CONTROL0, 6, adau17x1_mono_stereo_text);
103 static const struct snd_kcontrol_new adau17x1_dac_mode_mux =
104 SOC_DAPM_ENUM("DAC Mono-Stereo-Mode", adau17x1_dac_mode_enum);
106 static const struct snd_soc_dapm_widget adau17x1_dapm_widgets[] = {
107 SND_SOC_DAPM_SUPPLY_S("PLL", 3, SND_SOC_NOPM, 0, 0, adau17x1_pll_event,
108 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
110 SND_SOC_DAPM_SUPPLY("AIFCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
112 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU17X1_MICBIAS, 0, 0, NULL, 0),
114 SND_SOC_DAPM_SUPPLY("Left Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
116 SND_SOC_DAPM_SUPPLY("Right Playback Enable", ADAU17X1_PLAY_POWER_MGMT,
119 SND_SOC_DAPM_MUX("Left DAC Mode Mux", SND_SOC_NOPM, 0, 0,
120 &adau17x1_dac_mode_mux),
121 SND_SOC_DAPM_MUX("Right DAC Mode Mux", SND_SOC_NOPM, 0, 0,
122 &adau17x1_dac_mode_mux),
124 SND_SOC_DAPM_ADC("Left Decimator", NULL, ADAU17X1_ADC_CONTROL, 0, 0),
125 SND_SOC_DAPM_ADC("Right Decimator", NULL, ADAU17X1_ADC_CONTROL, 1, 0),
126 SND_SOC_DAPM_DAC("Left DAC", NULL, ADAU17X1_DAC_CONTROL0, 0, 0),
127 SND_SOC_DAPM_DAC("Right DAC", NULL, ADAU17X1_DAC_CONTROL0, 1, 0),
130 static const struct snd_soc_dapm_route adau17x1_dapm_routes[] = {
131 { "Left Decimator", NULL, "SYSCLK" },
132 { "Right Decimator", NULL, "SYSCLK" },
133 { "Left DAC", NULL, "SYSCLK" },
134 { "Right DAC", NULL, "SYSCLK" },
135 { "Capture", NULL, "SYSCLK" },
136 { "Playback", NULL, "SYSCLK" },
138 { "Left DAC", NULL, "Left DAC Mode Mux" },
139 { "Right DAC", NULL, "Right DAC Mode Mux" },
141 { "Capture", NULL, "AIFCLK" },
142 { "Playback", NULL, "AIFCLK" },
145 static const struct snd_soc_dapm_route adau17x1_dapm_pll_route = {
146 "SYSCLK", NULL, "PLL",
150 * The MUX register for the Capture and Playback MUXs selects either DSP as
151 * source/destination or one of the TDM slots. The TDM slot is selected via
152 * snd_soc_dai_set_tdm_slot(), so we only expose whether to go to the DSP or
153 * directly to the DAI interface with this control.
155 static int adau17x1_dsp_mux_enum_put(struct snd_kcontrol *kcontrol,
156 struct snd_ctl_elem_value *ucontrol)
158 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
159 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
160 struct adau *adau = snd_soc_codec_get_drvdata(codec);
161 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
162 struct snd_soc_dapm_update update = { 0 };
163 unsigned int stream = e->shift_l;
164 unsigned int val, change;
167 if (ucontrol->value.enumerated.item[0] >= e->items)
170 switch (ucontrol->value.enumerated.item[0]) {
173 adau->dsp_bypass[stream] = false;
176 val = (adau->tdm_slot[stream] * 2) + 1;
177 adau->dsp_bypass[stream] = true;
181 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
182 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
184 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
186 change = snd_soc_test_bits(codec, reg, 0xff, val);
188 update.kcontrol = kcontrol;
193 snd_soc_dapm_mux_update_power(dapm, kcontrol,
194 ucontrol->value.enumerated.item[0], e, &update);
200 static int adau17x1_dsp_mux_enum_get(struct snd_kcontrol *kcontrol,
201 struct snd_ctl_elem_value *ucontrol)
203 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
204 struct adau *adau = snd_soc_codec_get_drvdata(codec);
205 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
206 unsigned int stream = e->shift_l;
207 unsigned int reg, val;
210 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
211 reg = ADAU17X1_SERIAL_INPUT_ROUTE;
213 reg = ADAU17X1_SERIAL_OUTPUT_ROUTE;
215 ret = regmap_read(adau->regmap, reg, &val);
221 ucontrol->value.enumerated.item[0] = val;
226 #define DECLARE_ADAU17X1_DSP_MUX_CTRL(_name, _label, _stream, _text) \
227 const struct snd_kcontrol_new _name = \
228 SOC_DAPM_ENUM_EXT(_label, (const struct soc_enum)\
229 SOC_ENUM_SINGLE(SND_SOC_NOPM, _stream, \
230 ARRAY_SIZE(_text), _text), \
231 adau17x1_dsp_mux_enum_get, adau17x1_dsp_mux_enum_put)
233 static const char * const adau17x1_dac_mux_text[] = {
238 static const char * const adau17x1_capture_mux_text[] = {
243 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_dac_mux, "DAC Playback Mux",
244 SNDRV_PCM_STREAM_PLAYBACK, adau17x1_dac_mux_text);
246 static DECLARE_ADAU17X1_DSP_MUX_CTRL(adau17x1_capture_mux, "Capture Mux",
247 SNDRV_PCM_STREAM_CAPTURE, adau17x1_capture_mux_text);
249 static const struct snd_soc_dapm_widget adau17x1_dsp_dapm_widgets[] = {
250 SND_SOC_DAPM_PGA("DSP", ADAU17X1_DSP_RUN, 0, 0, NULL, 0),
251 SND_SOC_DAPM_SIGGEN("DSP Siggen"),
253 SND_SOC_DAPM_MUX("DAC Playback Mux", SND_SOC_NOPM, 0, 0,
255 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
256 &adau17x1_capture_mux),
259 static const struct snd_soc_dapm_route adau17x1_dsp_dapm_routes[] = {
260 { "DAC Playback Mux", "DSP", "DSP" },
261 { "DAC Playback Mux", "AIFIN", "Playback" },
263 { "Left DAC Mode Mux", "Stereo", "DAC Playback Mux" },
264 { "Left DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
265 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "DAC Playback Mux" },
266 { "Right DAC Mode Mux", "Stereo", "DAC Playback Mux" },
267 { "Right DAC Mode Mux", "Mono (L+R)", "DAC Playback Mux" },
268 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "DAC Playback Mux" },
270 { "Capture Mux", "DSP", "DSP" },
271 { "Capture Mux", "Decimator", "Left Decimator" },
272 { "Capture Mux", "Decimator", "Right Decimator" },
274 { "Capture", NULL, "Capture Mux" },
276 { "DSP", NULL, "DSP Siggen" },
278 { "DSP", NULL, "Left Decimator" },
279 { "DSP", NULL, "Right Decimator" },
282 static const struct snd_soc_dapm_route adau17x1_no_dsp_dapm_routes[] = {
283 { "Left DAC Mode Mux", "Stereo", "Playback" },
284 { "Left DAC Mode Mux", "Mono (L+R)", "Playback" },
285 { "Left DAC Mode Mux", "Mono Left Channel (L+R)", "Playback" },
286 { "Right DAC Mode Mux", "Stereo", "Playback" },
287 { "Right DAC Mode Mux", "Mono (L+R)", "Playback" },
288 { "Right DAC Mode Mux", "Mono Right Channel (L+R)", "Playback" },
289 { "Capture", NULL, "Left Decimator" },
290 { "Capture", NULL, "Right Decimator" },
293 bool adau17x1_has_dsp(struct adau *adau)
295 switch (adau->type) {
304 EXPORT_SYMBOL_GPL(adau17x1_has_dsp);
306 static int adau17x1_set_dai_pll(struct snd_soc_dai *dai, int pll_id,
307 int source, unsigned int freq_in, unsigned int freq_out)
309 struct snd_soc_codec *codec = dai->codec;
310 struct adau *adau = snd_soc_codec_get_drvdata(codec);
313 if (freq_in < 8000000 || freq_in > 27000000)
316 ret = adau_calc_pll_cfg(freq_in, freq_out, adau->pll_regs);
320 /* The PLL register is 6 bytes long and can only be written at once. */
321 ret = regmap_raw_write(adau->regmap, ADAU17X1_PLL_CONTROL,
322 adau->pll_regs, ARRAY_SIZE(adau->pll_regs));
326 adau->pll_freq = freq_out;
331 static int adau17x1_set_dai_sysclk(struct snd_soc_dai *dai,
332 int clk_id, unsigned int freq, int dir)
334 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(dai->codec);
335 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
340 case ADAU17X1_CLK_SRC_MCLK:
343 case ADAU17X1_CLK_SRC_PLL_AUTO:
347 case ADAU17X1_CLK_SRC_PLL:
354 switch (adau->clk_src) {
355 case ADAU17X1_CLK_SRC_MCLK:
358 case ADAU17X1_CLK_SRC_PLL:
359 case ADAU17X1_CLK_SRC_PLL_AUTO:
368 if (is_pll != was_pll) {
370 snd_soc_dapm_add_routes(dapm,
371 &adau17x1_dapm_pll_route, 1);
373 snd_soc_dapm_del_routes(dapm,
374 &adau17x1_dapm_pll_route, 1);
378 adau->clk_src = clk_id;
383 static int adau17x1_auto_pll(struct snd_soc_dai *dai,
384 struct snd_pcm_hw_params *params)
386 struct adau *adau = snd_soc_dai_get_drvdata(dai);
387 unsigned int pll_rate;
389 switch (params_rate(params)) {
397 pll_rate = 48000 * 1024;
406 pll_rate = 44100 * 1024;
412 return adau17x1_set_dai_pll(dai, ADAU17X1_PLL, ADAU17X1_PLL_SRC_MCLK,
413 clk_get_rate(adau->mclk), pll_rate);
416 static int adau17x1_hw_params(struct snd_pcm_substream *substream,
417 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
419 struct snd_soc_codec *codec = dai->codec;
420 struct adau *adau = snd_soc_codec_get_drvdata(codec);
421 unsigned int val, div, dsp_div;
425 switch (adau->clk_src) {
426 case ADAU17X1_CLK_SRC_PLL_AUTO:
427 ret = adau17x1_auto_pll(dai, params);
431 case ADAU17X1_CLK_SRC_PLL:
432 freq = adau->pll_freq;
439 if (freq % params_rate(params) != 0)
442 switch (freq / params_rate(params)) {
447 case 6144: /* fs / 6 */
451 case 4096: /* fs / 4 */
455 case 3072: /* fs / 3 */
459 case 2048: /* fs / 2 */
463 case 1536: /* fs / 1.5 */
467 case 512: /* fs / 0.5 */
475 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
476 ADAU17X1_CONVERTER0_CONVSR_MASK, div);
477 if (adau17x1_has_dsp(adau)) {
478 regmap_write(adau->regmap, ADAU17X1_SERIAL_SAMPLING_RATE, div);
479 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dsp_div);
482 if (adau->sigmadsp) {
483 ret = adau17x1_setup_firmware(adau, params_rate(params));
488 if (adau->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
491 switch (params_width(params)) {
493 val = ADAU17X1_SERIAL_PORT1_DELAY16;
496 val = ADAU17X1_SERIAL_PORT1_DELAY8;
499 val = ADAU17X1_SERIAL_PORT1_DELAY0;
505 return regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
506 ADAU17X1_SERIAL_PORT1_DELAY_MASK, val);
509 static int adau17x1_set_dai_fmt(struct snd_soc_dai *dai,
512 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
513 unsigned int ctrl0, ctrl1;
516 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
517 case SND_SOC_DAIFMT_CBM_CFM:
518 ctrl0 = ADAU17X1_SERIAL_PORT0_MASTER;
521 case SND_SOC_DAIFMT_CBS_CFS:
523 adau->master = false;
529 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
530 case SND_SOC_DAIFMT_I2S:
532 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
534 case SND_SOC_DAIFMT_LEFT_J:
535 case SND_SOC_DAIFMT_RIGHT_J:
537 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
539 case SND_SOC_DAIFMT_DSP_A:
541 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
542 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY1;
544 case SND_SOC_DAIFMT_DSP_B:
546 ctrl0 |= ADAU17X1_SERIAL_PORT0_PULSE_MODE;
547 ctrl1 = ADAU17X1_SERIAL_PORT1_DELAY0;
553 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
554 case SND_SOC_DAIFMT_NB_NF:
556 case SND_SOC_DAIFMT_IB_NF:
557 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
559 case SND_SOC_DAIFMT_NB_IF:
560 lrclk_pol = !lrclk_pol;
562 case SND_SOC_DAIFMT_IB_IF:
563 ctrl0 |= ADAU17X1_SERIAL_PORT0_BCLK_POL;
564 lrclk_pol = !lrclk_pol;
571 ctrl0 |= ADAU17X1_SERIAL_PORT0_LRCLK_POL;
573 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT0, ctrl0);
574 regmap_write(adau->regmap, ADAU17X1_SERIAL_PORT1, ctrl1);
576 adau->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
581 static int adau17x1_set_dai_tdm_slot(struct snd_soc_dai *dai,
582 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
584 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
585 unsigned int ser_ctrl0, ser_ctrl1;
586 unsigned int conv_ctrl0, conv_ctrl1;
598 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_STEREO;
601 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM4;
604 if (adau->type == ADAU1361)
607 ser_ctrl0 = ADAU17X1_SERIAL_PORT0_TDM8;
613 switch (slot_width * slots) {
615 if (adau->type == ADAU1761)
618 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK32;
621 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK64;
624 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK48;
627 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK128;
630 if (adau->type == ADAU1361)
633 ser_ctrl1 = ADAU17X1_SERIAL_PORT1_BCLK256;
641 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(1);
642 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 0;
645 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(2);
646 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 1;
649 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(3);
650 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 2;
653 conv_ctrl1 = ADAU17X1_CONVERTER1_ADC_PAIR(4);
654 adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] = 3;
662 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(1);
663 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 0;
666 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(2);
667 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 1;
670 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(3);
671 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 2;
674 conv_ctrl0 = ADAU17X1_CONVERTER0_DAC_PAIR(4);
675 adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] = 3;
681 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER0,
682 ADAU17X1_CONVERTER0_DAC_PAIR_MASK, conv_ctrl0);
683 regmap_update_bits(adau->regmap, ADAU17X1_CONVERTER1,
684 ADAU17X1_CONVERTER1_ADC_PAIR_MASK, conv_ctrl1);
685 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT0,
686 ADAU17X1_SERIAL_PORT0_TDM_MASK, ser_ctrl0);
687 regmap_update_bits(adau->regmap, ADAU17X1_SERIAL_PORT1,
688 ADAU17X1_SERIAL_PORT1_BCLK_MASK, ser_ctrl1);
690 if (!adau17x1_has_dsp(adau))
693 if (adau->dsp_bypass[SNDRV_PCM_STREAM_PLAYBACK]) {
694 regmap_write(adau->regmap, ADAU17X1_SERIAL_INPUT_ROUTE,
695 (adau->tdm_slot[SNDRV_PCM_STREAM_PLAYBACK] * 2) + 1);
698 if (adau->dsp_bypass[SNDRV_PCM_STREAM_CAPTURE]) {
699 regmap_write(adau->regmap, ADAU17X1_SERIAL_OUTPUT_ROUTE,
700 (adau->tdm_slot[SNDRV_PCM_STREAM_CAPTURE] * 2) + 1);
706 static int adau17x1_startup(struct snd_pcm_substream *substream,
707 struct snd_soc_dai *dai)
709 struct adau *adau = snd_soc_codec_get_drvdata(dai->codec);
712 return sigmadsp_restrict_params(adau->sigmadsp, substream);
717 const struct snd_soc_dai_ops adau17x1_dai_ops = {
718 .hw_params = adau17x1_hw_params,
719 .set_sysclk = adau17x1_set_dai_sysclk,
720 .set_fmt = adau17x1_set_dai_fmt,
721 .set_pll = adau17x1_set_dai_pll,
722 .set_tdm_slot = adau17x1_set_dai_tdm_slot,
723 .startup = adau17x1_startup,
725 EXPORT_SYMBOL_GPL(adau17x1_dai_ops);
727 int adau17x1_set_micbias_voltage(struct snd_soc_codec *codec,
728 enum adau17x1_micbias_voltage micbias)
730 struct adau *adau = snd_soc_codec_get_drvdata(codec);
733 case ADAU17X1_MICBIAS_0_90_AVDD:
734 case ADAU17X1_MICBIAS_0_65_AVDD:
740 return regmap_write(adau->regmap, ADAU17X1_MICBIAS, micbias << 2);
742 EXPORT_SYMBOL_GPL(adau17x1_set_micbias_voltage);
744 bool adau17x1_precious_register(struct device *dev, unsigned int reg)
746 /* SigmaDSP parameter memory */
752 EXPORT_SYMBOL_GPL(adau17x1_precious_register);
754 bool adau17x1_readable_register(struct device *dev, unsigned int reg)
756 /* SigmaDSP parameter memory */
761 case ADAU17X1_CLOCK_CONTROL:
762 case ADAU17X1_PLL_CONTROL:
763 case ADAU17X1_REC_POWER_MGMT:
764 case ADAU17X1_MICBIAS:
765 case ADAU17X1_SERIAL_PORT0:
766 case ADAU17X1_SERIAL_PORT1:
767 case ADAU17X1_CONVERTER0:
768 case ADAU17X1_CONVERTER1:
769 case ADAU17X1_LEFT_INPUT_DIGITAL_VOL:
770 case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL:
771 case ADAU17X1_ADC_CONTROL:
772 case ADAU17X1_PLAY_POWER_MGMT:
773 case ADAU17X1_DAC_CONTROL0:
774 case ADAU17X1_DAC_CONTROL1:
775 case ADAU17X1_DAC_CONTROL2:
776 case ADAU17X1_SERIAL_PORT_PAD:
777 case ADAU17X1_CONTROL_PORT_PAD0:
778 case ADAU17X1_CONTROL_PORT_PAD1:
779 case ADAU17X1_DSP_SAMPLING_RATE:
780 case ADAU17X1_SERIAL_INPUT_ROUTE:
781 case ADAU17X1_SERIAL_OUTPUT_ROUTE:
782 case ADAU17X1_DSP_ENABLE:
783 case ADAU17X1_DSP_RUN:
784 case ADAU17X1_SERIAL_SAMPLING_RATE:
791 EXPORT_SYMBOL_GPL(adau17x1_readable_register);
793 bool adau17x1_volatile_register(struct device *dev, unsigned int reg)
795 /* SigmaDSP parameter and program memory */
800 /* The PLL register is 6 bytes long */
801 case ADAU17X1_PLL_CONTROL:
802 case ADAU17X1_PLL_CONTROL + 1:
803 case ADAU17X1_PLL_CONTROL + 2:
804 case ADAU17X1_PLL_CONTROL + 3:
805 case ADAU17X1_PLL_CONTROL + 4:
806 case ADAU17X1_PLL_CONTROL + 5:
814 EXPORT_SYMBOL_GPL(adau17x1_volatile_register);
816 int adau17x1_setup_firmware(struct adau *adau, unsigned int rate)
821 ret = regmap_read(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, &dspsr);
825 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 1);
826 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, 0xf);
828 ret = sigmadsp_setup(adau->sigmadsp, rate);
830 regmap_write(adau->regmap, ADAU17X1_DSP_ENABLE, 0);
833 regmap_write(adau->regmap, ADAU17X1_DSP_SAMPLING_RATE, dspsr);
837 EXPORT_SYMBOL_GPL(adau17x1_setup_firmware);
839 int adau17x1_add_widgets(struct snd_soc_codec *codec)
841 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
842 struct adau *adau = snd_soc_codec_get_drvdata(codec);
845 ret = snd_soc_add_codec_controls(codec, adau17x1_controls,
846 ARRAY_SIZE(adau17x1_controls));
849 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dapm_widgets,
850 ARRAY_SIZE(adau17x1_dapm_widgets));
854 if (adau17x1_has_dsp(adau)) {
855 ret = snd_soc_dapm_new_controls(dapm, adau17x1_dsp_dapm_widgets,
856 ARRAY_SIZE(adau17x1_dsp_dapm_widgets));
863 ret = sigmadsp_attach(adau->sigmadsp, &codec->component);
865 dev_err(codec->dev, "Failed to attach firmware: %d\n",
873 EXPORT_SYMBOL_GPL(adau17x1_add_widgets);
875 int adau17x1_add_routes(struct snd_soc_codec *codec)
877 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
878 struct adau *adau = snd_soc_codec_get_drvdata(codec);
881 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dapm_routes,
882 ARRAY_SIZE(adau17x1_dapm_routes));
886 if (adau17x1_has_dsp(adau)) {
887 ret = snd_soc_dapm_add_routes(dapm, adau17x1_dsp_dapm_routes,
888 ARRAY_SIZE(adau17x1_dsp_dapm_routes));
890 ret = snd_soc_dapm_add_routes(dapm, adau17x1_no_dsp_dapm_routes,
891 ARRAY_SIZE(adau17x1_no_dsp_dapm_routes));
894 if (adau->clk_src != ADAU17X1_CLK_SRC_MCLK)
895 snd_soc_dapm_add_routes(dapm, &adau17x1_dapm_pll_route, 1);
899 EXPORT_SYMBOL_GPL(adau17x1_add_routes);
901 int adau17x1_resume(struct snd_soc_codec *codec)
903 struct adau *adau = snd_soc_codec_get_drvdata(codec);
905 if (adau->switch_mode)
906 adau->switch_mode(codec->dev);
908 regcache_sync(adau->regmap);
912 EXPORT_SYMBOL_GPL(adau17x1_resume);
914 int adau17x1_probe(struct device *dev, struct regmap *regmap,
915 enum adau17x1_type type, void (*switch_mode)(struct device *dev),
916 const char *firmware_name)
922 return PTR_ERR(regmap);
924 adau = devm_kzalloc(dev, sizeof(*adau), GFP_KERNEL);
928 adau->mclk = devm_clk_get(dev, "mclk");
929 if (IS_ERR(adau->mclk)) {
930 if (PTR_ERR(adau->mclk) != -ENOENT)
931 return PTR_ERR(adau->mclk);
932 /* Clock is optional (for the driver) */
934 } else if (adau->mclk) {
935 adau->clk_src = ADAU17X1_CLK_SRC_PLL_AUTO;
938 * Any valid PLL output rate will work at this point, use one
939 * that is likely to be chosen later as well. The register will
940 * be written when the PLL is powered up for the first time.
942 ret = adau_calc_pll_cfg(clk_get_rate(adau->mclk), 48000 * 1024,
947 ret = clk_prepare_enable(adau->mclk);
952 adau->regmap = regmap;
953 adau->switch_mode = switch_mode;
956 dev_set_drvdata(dev, adau);
959 adau->sigmadsp = devm_sigmadsp_init_regmap(dev, regmap, NULL,
961 if (IS_ERR(adau->sigmadsp)) {
962 dev_warn(dev, "Could not find firmware file: %ld\n",
963 PTR_ERR(adau->sigmadsp));
964 adau->sigmadsp = NULL;
973 EXPORT_SYMBOL_GPL(adau17x1_probe);
975 void adau17x1_remove(struct device *dev)
977 struct adau *adau = dev_get_drvdata(dev);
979 snd_soc_unregister_codec(dev);
981 clk_disable_unprepare(adau->mclk);
983 EXPORT_SYMBOL_GPL(adau17x1_remove);
985 MODULE_DESCRIPTION("ASoC ADAU1X61/ADAU1X81 common code");
986 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
987 MODULE_LICENSE("GPL");