2 * arizona.c - Wolfson Arizona class device shared support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/gcd.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/tlv.h>
21 #include <linux/mfd/arizona/core.h>
22 #include <linux/mfd/arizona/gpio.h>
23 #include <linux/mfd/arizona/registers.h>
27 #define ARIZONA_AIF_BCLK_CTRL 0x00
28 #define ARIZONA_AIF_TX_PIN_CTRL 0x01
29 #define ARIZONA_AIF_RX_PIN_CTRL 0x02
30 #define ARIZONA_AIF_RATE_CTRL 0x03
31 #define ARIZONA_AIF_FORMAT 0x04
32 #define ARIZONA_AIF_TX_BCLK_RATE 0x05
33 #define ARIZONA_AIF_RX_BCLK_RATE 0x06
34 #define ARIZONA_AIF_FRAME_CTRL_1 0x07
35 #define ARIZONA_AIF_FRAME_CTRL_2 0x08
36 #define ARIZONA_AIF_FRAME_CTRL_3 0x09
37 #define ARIZONA_AIF_FRAME_CTRL_4 0x0A
38 #define ARIZONA_AIF_FRAME_CTRL_5 0x0B
39 #define ARIZONA_AIF_FRAME_CTRL_6 0x0C
40 #define ARIZONA_AIF_FRAME_CTRL_7 0x0D
41 #define ARIZONA_AIF_FRAME_CTRL_8 0x0E
42 #define ARIZONA_AIF_FRAME_CTRL_9 0x0F
43 #define ARIZONA_AIF_FRAME_CTRL_10 0x10
44 #define ARIZONA_AIF_FRAME_CTRL_11 0x11
45 #define ARIZONA_AIF_FRAME_CTRL_12 0x12
46 #define ARIZONA_AIF_FRAME_CTRL_13 0x13
47 #define ARIZONA_AIF_FRAME_CTRL_14 0x14
48 #define ARIZONA_AIF_FRAME_CTRL_15 0x15
49 #define ARIZONA_AIF_FRAME_CTRL_16 0x16
50 #define ARIZONA_AIF_FRAME_CTRL_17 0x17
51 #define ARIZONA_AIF_FRAME_CTRL_18 0x18
52 #define ARIZONA_AIF_TX_ENABLES 0x19
53 #define ARIZONA_AIF_RX_ENABLES 0x1A
54 #define ARIZONA_AIF_FORCE_WRITE 0x1B
56 #define arizona_fll_err(_fll, fmt, ...) \
57 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
58 #define arizona_fll_warn(_fll, fmt, ...) \
59 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
60 #define arizona_fll_dbg(_fll, fmt, ...) \
61 dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
63 #define arizona_aif_err(_dai, fmt, ...) \
64 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
65 #define arizona_aif_warn(_dai, fmt, ...) \
66 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
67 #define arizona_aif_dbg(_dai, fmt, ...) \
68 dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
70 static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
71 struct snd_kcontrol *kcontrol,
74 struct snd_soc_codec *codec = w->codec;
75 struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
76 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
77 bool manual_ena = false;
80 switch (arizona->type) {
82 switch (arizona->rev) {
94 case SND_SOC_DAPM_PRE_PMU:
95 if (!priv->spk_ena && manual_ena) {
96 snd_soc_write(codec, 0x4f5, 0x25a);
97 priv->spk_ena_pending = true;
100 case SND_SOC_DAPM_POST_PMU:
101 val = snd_soc_read(codec, ARIZONA_INTERRUPT_RAW_STATUS_3);
102 if (val & ARIZONA_SPK_SHUTDOWN_STS) {
103 dev_crit(arizona->dev,
104 "Speaker not enabled due to temperature\n");
108 snd_soc_update_bits(codec, ARIZONA_OUTPUT_ENABLES_1,
109 1 << w->shift, 1 << w->shift);
111 if (priv->spk_ena_pending) {
113 snd_soc_write(codec, 0x4f5, 0xda);
114 priv->spk_ena_pending = false;
118 case SND_SOC_DAPM_PRE_PMD:
122 snd_soc_write(codec, 0x4f5, 0x25a);
125 snd_soc_update_bits(codec, ARIZONA_OUTPUT_ENABLES_1,
128 case SND_SOC_DAPM_POST_PMD:
131 snd_soc_write(codec, 0x4f5, 0x0da);
139 static irqreturn_t arizona_thermal_warn(int irq, void *data)
141 struct arizona *arizona = data;
145 ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
148 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
150 } else if (val & ARIZONA_SPK_SHUTDOWN_WARN_STS) {
151 dev_crit(arizona->dev, "Thermal warning\n");
157 static irqreturn_t arizona_thermal_shutdown(int irq, void *data)
159 struct arizona *arizona = data;
163 ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
166 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
168 } else if (val & ARIZONA_SPK_SHUTDOWN_STS) {
169 dev_crit(arizona->dev, "Thermal shutdown\n");
170 ret = regmap_update_bits(arizona->regmap,
171 ARIZONA_OUTPUT_ENABLES_1,
173 ARIZONA_OUT4R_ENA, 0);
175 dev_crit(arizona->dev,
176 "Failed to disable speaker outputs: %d\n",
183 static const struct snd_soc_dapm_widget arizona_spkl =
184 SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
185 ARIZONA_OUT4L_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
186 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
188 static const struct snd_soc_dapm_widget arizona_spkr =
189 SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM,
190 ARIZONA_OUT4R_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
191 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
193 int arizona_init_spk(struct snd_soc_codec *codec)
195 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
196 struct arizona *arizona = priv->arizona;
199 ret = snd_soc_dapm_new_controls(&codec->dapm, &arizona_spkl, 1);
203 switch (arizona->type) {
207 ret = snd_soc_dapm_new_controls(&codec->dapm,
214 ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_SHUTDOWN_WARN,
215 "Thermal warning", arizona_thermal_warn,
218 dev_err(arizona->dev,
219 "Failed to get thermal warning IRQ: %d\n",
222 ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_SHUTDOWN,
223 "Thermal shutdown", arizona_thermal_shutdown,
226 dev_err(arizona->dev,
227 "Failed to get thermal shutdown IRQ: %d\n",
232 EXPORT_SYMBOL_GPL(arizona_init_spk);
234 int arizona_init_gpio(struct snd_soc_codec *codec)
236 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
237 struct arizona *arizona = priv->arizona;
240 switch (arizona->type) {
242 snd_soc_dapm_disable_pin(&codec->dapm, "DRC2 Signal Activity");
248 snd_soc_dapm_disable_pin(&codec->dapm, "DRC1 Signal Activity");
250 for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
251 switch (arizona->pdata.gpio_defaults[i] & ARIZONA_GPN_FN_MASK) {
252 case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT:
253 snd_soc_dapm_enable_pin(&codec->dapm,
254 "DRC1 Signal Activity");
256 case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT:
257 snd_soc_dapm_enable_pin(&codec->dapm,
258 "DRC2 Signal Activity");
267 EXPORT_SYMBOL_GPL(arizona_init_gpio);
269 const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
370 EXPORT_SYMBOL_GPL(arizona_mixer_texts);
372 int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
378 0x0c, /* Noise mixer */
379 0x0d, /* Comfort noise */
448 0xa0, /* ISRC1INT1 */
452 0xa4, /* ISRC1DEC1 */
456 0xa8, /* ISRC2DEC1 */
460 0xac, /* ISRC2INT1 */
464 0xb0, /* ISRC3DEC1 */
468 0xb4, /* ISRC3INT1 */
473 EXPORT_SYMBOL_GPL(arizona_mixer_values);
475 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0);
476 EXPORT_SYMBOL_GPL(arizona_mixer_tlv);
478 const char *arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = {
479 "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate",
481 EXPORT_SYMBOL_GPL(arizona_rate_text);
483 const int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = {
486 EXPORT_SYMBOL_GPL(arizona_rate_val);
489 const struct soc_enum arizona_isrc_fsl[] = {
490 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2,
491 ARIZONA_ISRC1_FSL_SHIFT, 0xf,
492 ARIZONA_RATE_ENUM_SIZE,
493 arizona_rate_text, arizona_rate_val),
494 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2,
495 ARIZONA_ISRC2_FSL_SHIFT, 0xf,
496 ARIZONA_RATE_ENUM_SIZE,
497 arizona_rate_text, arizona_rate_val),
498 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2,
499 ARIZONA_ISRC3_FSL_SHIFT, 0xf,
500 ARIZONA_RATE_ENUM_SIZE,
501 arizona_rate_text, arizona_rate_val),
503 EXPORT_SYMBOL_GPL(arizona_isrc_fsl);
505 static const char *arizona_vol_ramp_text[] = {
506 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
507 "15ms/6dB", "30ms/6dB",
510 const struct soc_enum arizona_in_vd_ramp =
511 SOC_ENUM_SINGLE(ARIZONA_INPUT_VOLUME_RAMP,
512 ARIZONA_IN_VD_RAMP_SHIFT, 7, arizona_vol_ramp_text);
513 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp);
515 const struct soc_enum arizona_in_vi_ramp =
516 SOC_ENUM_SINGLE(ARIZONA_INPUT_VOLUME_RAMP,
517 ARIZONA_IN_VI_RAMP_SHIFT, 7, arizona_vol_ramp_text);
518 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp);
520 const struct soc_enum arizona_out_vd_ramp =
521 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_VOLUME_RAMP,
522 ARIZONA_OUT_VD_RAMP_SHIFT, 7, arizona_vol_ramp_text);
523 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp);
525 const struct soc_enum arizona_out_vi_ramp =
526 SOC_ENUM_SINGLE(ARIZONA_OUTPUT_VOLUME_RAMP,
527 ARIZONA_OUT_VI_RAMP_SHIFT, 7, arizona_vol_ramp_text);
528 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
530 static const char *arizona_lhpf_mode_text[] = {
531 "Low-pass", "High-pass"
534 const struct soc_enum arizona_lhpf1_mode =
535 SOC_ENUM_SINGLE(ARIZONA_HPLPF1_1, ARIZONA_LHPF1_MODE_SHIFT, 2,
536 arizona_lhpf_mode_text);
537 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode);
539 const struct soc_enum arizona_lhpf2_mode =
540 SOC_ENUM_SINGLE(ARIZONA_HPLPF2_1, ARIZONA_LHPF2_MODE_SHIFT, 2,
541 arizona_lhpf_mode_text);
542 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode);
544 const struct soc_enum arizona_lhpf3_mode =
545 SOC_ENUM_SINGLE(ARIZONA_HPLPF3_1, ARIZONA_LHPF3_MODE_SHIFT, 2,
546 arizona_lhpf_mode_text);
547 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode);
549 const struct soc_enum arizona_lhpf4_mode =
550 SOC_ENUM_SINGLE(ARIZONA_HPLPF4_1, ARIZONA_LHPF4_MODE_SHIFT, 2,
551 arizona_lhpf_mode_text);
552 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
554 static const char *arizona_ng_hold_text[] = {
555 "30ms", "120ms", "250ms", "500ms",
558 const struct soc_enum arizona_ng_hold =
559 SOC_ENUM_SINGLE(ARIZONA_NOISE_GATE_CONTROL, ARIZONA_NGATE_HOLD_SHIFT,
560 4, arizona_ng_hold_text);
561 EXPORT_SYMBOL_GPL(arizona_ng_hold);
563 static const char * const arizona_in_dmic_osr_text[] = {
564 "1.536MHz", "3.072MHz", "6.144MHz",
567 const struct soc_enum arizona_in_dmic_osr[] = {
568 SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT,
569 ARRAY_SIZE(arizona_in_dmic_osr_text),
570 arizona_in_dmic_osr_text),
571 SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL, ARIZONA_IN2_OSR_SHIFT,
572 ARRAY_SIZE(arizona_in_dmic_osr_text),
573 arizona_in_dmic_osr_text),
574 SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL, ARIZONA_IN3_OSR_SHIFT,
575 ARRAY_SIZE(arizona_in_dmic_osr_text),
576 arizona_in_dmic_osr_text),
577 SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL, ARIZONA_IN4_OSR_SHIFT,
578 ARRAY_SIZE(arizona_in_dmic_osr_text),
579 arizona_in_dmic_osr_text),
581 EXPORT_SYMBOL_GPL(arizona_in_dmic_osr);
583 static void arizona_in_set_vu(struct snd_soc_codec *codec, int ena)
585 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
594 for (i = 0; i < priv->num_inputs; i++)
595 snd_soc_update_bits(codec,
596 ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 4),
600 int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
603 struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
607 reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8);
609 reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8);
612 case SND_SOC_DAPM_PRE_PMU:
615 case SND_SOC_DAPM_POST_PMU:
616 snd_soc_update_bits(w->codec, reg, ARIZONA_IN1L_MUTE, 0);
618 /* If this is the last input pending then allow VU */
620 if (priv->in_pending == 0) {
622 arizona_in_set_vu(w->codec, 1);
625 case SND_SOC_DAPM_PRE_PMD:
626 snd_soc_update_bits(w->codec, reg,
627 ARIZONA_IN1L_MUTE | ARIZONA_IN_VU,
628 ARIZONA_IN1L_MUTE | ARIZONA_IN_VU);
630 case SND_SOC_DAPM_POST_PMD:
631 /* Disable volume updates if no inputs are enabled */
632 reg = snd_soc_read(w->codec, ARIZONA_INPUT_ENABLES);
634 arizona_in_set_vu(w->codec, 0);
639 EXPORT_SYMBOL_GPL(arizona_in_ev);
641 int arizona_out_ev(struct snd_soc_dapm_widget *w,
642 struct snd_kcontrol *kcontrol,
646 case SND_SOC_DAPM_POST_PMU:
648 case ARIZONA_OUT1L_ENA_SHIFT:
649 case ARIZONA_OUT1R_ENA_SHIFT:
650 case ARIZONA_OUT2L_ENA_SHIFT:
651 case ARIZONA_OUT2R_ENA_SHIFT:
652 case ARIZONA_OUT3L_ENA_SHIFT:
653 case ARIZONA_OUT3R_ENA_SHIFT:
665 EXPORT_SYMBOL_GPL(arizona_out_ev);
667 int arizona_hp_ev(struct snd_soc_dapm_widget *w,
668 struct snd_kcontrol *kcontrol,
671 struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
672 unsigned int mask = 1 << w->shift;
676 case SND_SOC_DAPM_POST_PMU:
679 case SND_SOC_DAPM_PRE_PMD:
686 /* Store the desired state for the HP outputs */
687 priv->arizona->hp_ena &= ~mask;
688 priv->arizona->hp_ena |= val;
690 /* Force off if HPDET magic is active */
691 if (priv->arizona->hpdet_magic)
694 snd_soc_update_bits(w->codec, ARIZONA_OUTPUT_ENABLES_1, mask, val);
696 return arizona_out_ev(w, kcontrol, event);
698 EXPORT_SYMBOL_GPL(arizona_hp_ev);
700 static unsigned int arizona_sysclk_48k_rates[] = {
710 static unsigned int arizona_sysclk_44k1_rates[] = {
720 static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk,
723 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
726 int ref, div, refclk;
729 case ARIZONA_CLK_OPCLK:
730 reg = ARIZONA_OUTPUT_SYSTEM_CLOCK;
731 refclk = priv->sysclk;
733 case ARIZONA_CLK_ASYNC_OPCLK:
734 reg = ARIZONA_OUTPUT_ASYNC_CLOCK;
735 refclk = priv->asyncclk;
742 rates = arizona_sysclk_44k1_rates;
744 rates = arizona_sysclk_48k_rates;
746 for (ref = 0; ref < ARRAY_SIZE(arizona_sysclk_48k_rates) &&
747 rates[ref] <= refclk; ref++) {
749 while (rates[ref] / div >= freq && div < 32) {
750 if (rates[ref] / div == freq) {
751 dev_dbg(codec->dev, "Configured %dHz OPCLK\n",
753 snd_soc_update_bits(codec, reg,
754 ARIZONA_OPCLK_DIV_MASK |
755 ARIZONA_OPCLK_SEL_MASK,
757 ARIZONA_OPCLK_DIV_SHIFT) |
765 dev_err(codec->dev, "Unable to generate %dHz OPCLK\n", freq);
769 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
770 int source, unsigned int freq, int dir)
772 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
773 struct arizona *arizona = priv->arizona;
776 unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
777 unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
781 case ARIZONA_CLK_SYSCLK:
783 reg = ARIZONA_SYSTEM_CLOCK_1;
785 mask |= ARIZONA_SYSCLK_FRAC;
787 case ARIZONA_CLK_ASYNCCLK:
789 reg = ARIZONA_ASYNC_CLOCK_1;
790 clk = &priv->asyncclk;
792 case ARIZONA_CLK_OPCLK:
793 case ARIZONA_CLK_ASYNC_OPCLK:
794 return arizona_set_opclk(codec, clk_id, freq);
805 val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
809 val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
813 val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
817 val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
821 val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
825 val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
828 dev_dbg(arizona->dev, "%s cleared\n", name);
838 val |= ARIZONA_SYSCLK_FRAC;
840 dev_dbg(arizona->dev, "%s set to %uHz", name, freq);
842 return regmap_update_bits(arizona->regmap, reg, mask, val);
844 EXPORT_SYMBOL_GPL(arizona_set_sysclk);
846 static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
848 struct snd_soc_codec *codec = dai->codec;
849 int lrclk, bclk, mode, base;
851 base = dai->driver->base;
856 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
857 case SND_SOC_DAIFMT_DSP_A:
860 case SND_SOC_DAIFMT_I2S:
864 arizona_aif_err(dai, "Unsupported DAI format %d\n",
865 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
869 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
870 case SND_SOC_DAIFMT_CBS_CFS:
872 case SND_SOC_DAIFMT_CBS_CFM:
873 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
875 case SND_SOC_DAIFMT_CBM_CFS:
876 bclk |= ARIZONA_AIF1_BCLK_MSTR;
878 case SND_SOC_DAIFMT_CBM_CFM:
879 bclk |= ARIZONA_AIF1_BCLK_MSTR;
880 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
883 arizona_aif_err(dai, "Unsupported master mode %d\n",
884 fmt & SND_SOC_DAIFMT_MASTER_MASK);
888 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
889 case SND_SOC_DAIFMT_NB_NF:
891 case SND_SOC_DAIFMT_IB_IF:
892 bclk |= ARIZONA_AIF1_BCLK_INV;
893 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
895 case SND_SOC_DAIFMT_IB_NF:
896 bclk |= ARIZONA_AIF1_BCLK_INV;
898 case SND_SOC_DAIFMT_NB_IF:
899 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
905 snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL,
906 ARIZONA_AIF1_BCLK_INV | ARIZONA_AIF1_BCLK_MSTR,
908 snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_PIN_CTRL,
909 ARIZONA_AIF1TX_LRCLK_INV |
910 ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
911 snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_PIN_CTRL,
912 ARIZONA_AIF1RX_LRCLK_INV |
913 ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
914 snd_soc_update_bits(codec, base + ARIZONA_AIF_FORMAT,
915 ARIZONA_AIF1_FMT_MASK, mode);
920 static const int arizona_48k_bclk_rates[] = {
942 static const unsigned int arizona_48k_rates[] = {
960 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint = {
961 .count = ARRAY_SIZE(arizona_48k_rates),
962 .list = arizona_48k_rates,
965 static const int arizona_44k1_bclk_rates[] = {
987 static const unsigned int arizona_44k1_rates[] = {
997 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint = {
998 .count = ARRAY_SIZE(arizona_44k1_rates),
999 .list = arizona_44k1_rates,
1002 static int arizona_sr_vals[] = {
1029 static int arizona_startup(struct snd_pcm_substream *substream,
1030 struct snd_soc_dai *dai)
1032 struct snd_soc_codec *codec = dai->codec;
1033 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1034 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1035 const struct snd_pcm_hw_constraint_list *constraint;
1036 unsigned int base_rate;
1038 switch (dai_priv->clk) {
1039 case ARIZONA_CLK_SYSCLK:
1040 base_rate = priv->sysclk;
1042 case ARIZONA_CLK_ASYNCCLK:
1043 base_rate = priv->asyncclk;
1052 if (base_rate % 8000)
1053 constraint = &arizona_44k1_constraint;
1055 constraint = &arizona_48k_constraint;
1057 return snd_pcm_hw_constraint_list(substream->runtime, 0,
1058 SNDRV_PCM_HW_PARAM_RATE,
1062 static int arizona_hw_params_rate(struct snd_pcm_substream *substream,
1063 struct snd_pcm_hw_params *params,
1064 struct snd_soc_dai *dai)
1066 struct snd_soc_codec *codec = dai->codec;
1067 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1068 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1069 int base = dai->driver->base;
1073 * We will need to be more flexible than this in future,
1074 * currently we use a single sample rate for SYSCLK.
1076 for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
1077 if (arizona_sr_vals[i] == params_rate(params))
1079 if (i == ARRAY_SIZE(arizona_sr_vals)) {
1080 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1081 params_rate(params));
1086 switch (dai_priv->clk) {
1087 case ARIZONA_CLK_SYSCLK:
1088 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
1089 ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
1091 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1092 ARIZONA_AIF1_RATE_MASK, 0);
1094 case ARIZONA_CLK_ASYNCCLK:
1095 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
1096 ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val);
1098 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1099 ARIZONA_AIF1_RATE_MASK,
1100 8 << ARIZONA_AIF1_RATE_SHIFT);
1103 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
1110 static int arizona_hw_params(struct snd_pcm_substream *substream,
1111 struct snd_pcm_hw_params *params,
1112 struct snd_soc_dai *dai)
1114 struct snd_soc_codec *codec = dai->codec;
1115 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1116 struct arizona *arizona = priv->arizona;
1117 int base = dai->driver->base;
1120 int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1];
1121 int bclk, lrclk, wl, frame, bclk_target;
1123 if (params_rate(params) % 8000)
1124 rates = &arizona_44k1_bclk_rates[0];
1126 rates = &arizona_48k_bclk_rates[0];
1128 bclk_target = snd_soc_params_to_bclk(params);
1129 if (chan_limit && chan_limit < params_channels(params)) {
1130 arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit);
1131 bclk_target /= params_channels(params);
1132 bclk_target *= chan_limit;
1135 /* Force stereo for I2S mode */
1136 val = snd_soc_read(codec, base + ARIZONA_AIF_FORMAT);
1137 if (params_channels(params) == 1 && (val & ARIZONA_AIF1_FMT_MASK)) {
1138 arizona_aif_dbg(dai, "Forcing stereo mode\n");
1142 for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
1143 if (rates[i] >= bclk_target &&
1144 rates[i] % params_rate(params) == 0) {
1149 if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
1150 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1151 params_rate(params));
1155 lrclk = rates[bclk] / params_rate(params);
1157 arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
1158 rates[bclk], rates[bclk] / lrclk);
1160 wl = snd_pcm_format_width(params_format(params));
1161 frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl;
1163 ret = arizona_hw_params_rate(substream, params, dai);
1167 snd_soc_update_bits(codec, base + ARIZONA_AIF_BCLK_CTRL,
1168 ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
1169 snd_soc_update_bits(codec, base + ARIZONA_AIF_TX_BCLK_RATE,
1170 ARIZONA_AIF1TX_BCPF_MASK, lrclk);
1171 snd_soc_update_bits(codec, base + ARIZONA_AIF_RX_BCLK_RATE,
1172 ARIZONA_AIF1RX_BCPF_MASK, lrclk);
1173 snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_1,
1174 ARIZONA_AIF1TX_WL_MASK |
1175 ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
1176 snd_soc_update_bits(codec, base + ARIZONA_AIF_FRAME_CTRL_2,
1177 ARIZONA_AIF1RX_WL_MASK |
1178 ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
1183 static const char *arizona_dai_clk_str(int clk_id)
1186 case ARIZONA_CLK_SYSCLK:
1188 case ARIZONA_CLK_ASYNCCLK:
1191 return "Unknown clock";
1195 static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
1196 int clk_id, unsigned int freq, int dir)
1198 struct snd_soc_codec *codec = dai->codec;
1199 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1200 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1201 struct snd_soc_dapm_route routes[2];
1204 case ARIZONA_CLK_SYSCLK:
1205 case ARIZONA_CLK_ASYNCCLK:
1211 if (clk_id == dai_priv->clk)
1215 dev_err(codec->dev, "Can't change clock on active DAI %d\n",
1220 dev_dbg(codec->dev, "Setting AIF%d to %s\n", dai->id + 1,
1221 arizona_dai_clk_str(clk_id));
1223 memset(&routes, 0, sizeof(routes));
1224 routes[0].sink = dai->driver->capture.stream_name;
1225 routes[1].sink = dai->driver->playback.stream_name;
1227 routes[0].source = arizona_dai_clk_str(dai_priv->clk);
1228 routes[1].source = arizona_dai_clk_str(dai_priv->clk);
1229 snd_soc_dapm_del_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
1231 routes[0].source = arizona_dai_clk_str(clk_id);
1232 routes[1].source = arizona_dai_clk_str(clk_id);
1233 snd_soc_dapm_add_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
1235 dai_priv->clk = clk_id;
1237 return snd_soc_dapm_sync(&codec->dapm);
1240 static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate)
1242 struct snd_soc_codec *codec = dai->codec;
1243 int base = dai->driver->base;
1247 reg = ARIZONA_AIF1_TRI;
1251 return snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1252 ARIZONA_AIF1_TRI, reg);
1255 const struct snd_soc_dai_ops arizona_dai_ops = {
1256 .startup = arizona_startup,
1257 .set_fmt = arizona_set_fmt,
1258 .hw_params = arizona_hw_params,
1259 .set_sysclk = arizona_dai_set_sysclk,
1260 .set_tristate = arizona_set_tristate,
1262 EXPORT_SYMBOL_GPL(arizona_dai_ops);
1264 const struct snd_soc_dai_ops arizona_simple_dai_ops = {
1265 .startup = arizona_startup,
1266 .hw_params = arizona_hw_params_rate,
1267 .set_sysclk = arizona_dai_set_sysclk,
1269 EXPORT_SYMBOL_GPL(arizona_simple_dai_ops);
1271 int arizona_init_dai(struct arizona_priv *priv, int id)
1273 struct arizona_dai_priv *dai_priv = &priv->dai[id];
1275 dai_priv->clk = ARIZONA_CLK_SYSCLK;
1279 EXPORT_SYMBOL_GPL(arizona_init_dai);
1281 static irqreturn_t arizona_fll_clock_ok(int irq, void *data)
1283 struct arizona_fll *fll = data;
1285 arizona_fll_dbg(fll, "clock OK\n");
1298 { 0, 64000, 4, 16 },
1299 { 64000, 128000, 3, 8 },
1300 { 128000, 256000, 2, 4 },
1301 { 256000, 1000000, 1, 2 },
1302 { 1000000, 13500000, 0, 1 },
1311 { 256000, 1000000, 2 },
1312 { 1000000, 13500000, 4 },
1315 struct arizona_fll_cfg {
1325 static int arizona_calc_fll(struct arizona_fll *fll,
1326 struct arizona_fll_cfg *cfg,
1330 unsigned int target, div, gcd_fll;
1333 arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, Fout);
1335 /* Fref must be <=13.5MHz */
1338 while ((Fref / div) > 13500000) {
1343 arizona_fll_err(fll,
1344 "Can't scale %dMHz in to <=13.5MHz\n",
1350 /* Apply the division for our remaining calculations */
1353 /* Fvco should be over the targt; don't check the upper bound */
1355 while (Fout * div < 90000000 * fll->vco_mult) {
1358 arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
1363 target = Fout * div / fll->vco_mult;
1366 arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
1368 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1369 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1370 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1371 cfg->fratio = fll_fratios[i].fratio;
1372 ratio = fll_fratios[i].ratio;
1376 if (i == ARRAY_SIZE(fll_fratios)) {
1377 arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n",
1382 for (i = 0; i < ARRAY_SIZE(fll_gains); i++) {
1383 if (fll_gains[i].min <= Fref && Fref <= fll_gains[i].max) {
1384 cfg->gain = fll_gains[i].gain;
1388 if (i == ARRAY_SIZE(fll_gains)) {
1389 arizona_fll_err(fll, "Unable to find gain for Fref=%uHz\n",
1394 cfg->n = target / (ratio * Fref);
1396 if (target % (ratio * Fref)) {
1397 gcd_fll = gcd(target, ratio * Fref);
1398 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
1400 cfg->theta = (target - (cfg->n * ratio * Fref))
1402 cfg->lambda = (ratio * Fref) / gcd_fll;
1408 /* Round down to 16bit range with cost of accuracy lost.
1409 * Denominator must be bigger than numerator so we only
1412 while (cfg->lambda >= (1 << 16)) {
1417 arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n",
1418 cfg->n, cfg->theta, cfg->lambda);
1419 arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
1420 cfg->fratio, cfg->fratio, cfg->outdiv, cfg->refdiv);
1421 arizona_fll_dbg(fll, "GAIN=%d\n", cfg->gain);
1427 static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
1428 struct arizona_fll_cfg *cfg, int source,
1431 regmap_update_bits(arizona->regmap, base + 3,
1432 ARIZONA_FLL1_THETA_MASK, cfg->theta);
1433 regmap_update_bits(arizona->regmap, base + 4,
1434 ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
1435 regmap_update_bits(arizona->regmap, base + 5,
1436 ARIZONA_FLL1_FRATIO_MASK,
1437 cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
1438 regmap_update_bits(arizona->regmap, base + 6,
1439 ARIZONA_FLL1_CLK_REF_DIV_MASK |
1440 ARIZONA_FLL1_CLK_REF_SRC_MASK,
1441 cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
1442 source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
1445 regmap_update_bits(arizona->regmap, base + 0x7,
1446 ARIZONA_FLL1_GAIN_MASK,
1447 cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
1449 regmap_update_bits(arizona->regmap, base + 0x9,
1450 ARIZONA_FLL1_GAIN_MASK,
1451 cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
1453 regmap_update_bits(arizona->regmap, base + 2,
1454 ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
1455 ARIZONA_FLL1_CTRL_UPD | cfg->n);
1458 static bool arizona_is_enabled_fll(struct arizona_fll *fll)
1460 struct arizona *arizona = fll->arizona;
1464 ret = regmap_read(arizona->regmap, fll->base + 1, ®);
1466 arizona_fll_err(fll, "Failed to read current state: %d\n",
1471 return reg & ARIZONA_FLL1_ENA;
1474 static void arizona_enable_fll(struct arizona_fll *fll,
1475 struct arizona_fll_cfg *ref,
1476 struct arizona_fll_cfg *sync)
1478 struct arizona *arizona = fll->arizona;
1480 bool use_sync = false;
1483 * If we have both REFCLK and SYNCCLK then enable both,
1484 * otherwise apply the SYNCCLK settings to REFCLK.
1486 if (fll->ref_src >= 0 && fll->ref_freq &&
1487 fll->ref_src != fll->sync_src) {
1488 regmap_update_bits(arizona->regmap, fll->base + 5,
1489 ARIZONA_FLL1_OUTDIV_MASK,
1490 ref->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
1492 arizona_apply_fll(arizona, fll->base, ref, fll->ref_src,
1494 if (fll->sync_src >= 0) {
1495 arizona_apply_fll(arizona, fll->base + 0x10, sync,
1496 fll->sync_src, true);
1499 } else if (fll->sync_src >= 0) {
1500 regmap_update_bits(arizona->regmap, fll->base + 5,
1501 ARIZONA_FLL1_OUTDIV_MASK,
1502 sync->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
1504 arizona_apply_fll(arizona, fll->base, sync,
1505 fll->sync_src, false);
1507 regmap_update_bits(arizona->regmap, fll->base + 0x11,
1508 ARIZONA_FLL1_SYNC_ENA, 0);
1510 arizona_fll_err(fll, "No clocks provided\n");
1515 * Increase the bandwidth if we're not using a low frequency
1518 if (use_sync && fll->sync_freq > 100000)
1519 regmap_update_bits(arizona->regmap, fll->base + 0x17,
1520 ARIZONA_FLL1_SYNC_BW, 0);
1522 regmap_update_bits(arizona->regmap, fll->base + 0x17,
1523 ARIZONA_FLL1_SYNC_BW, ARIZONA_FLL1_SYNC_BW);
1525 if (!arizona_is_enabled_fll(fll))
1526 pm_runtime_get(arizona->dev);
1528 /* Clear any pending completions */
1529 try_wait_for_completion(&fll->ok);
1531 regmap_update_bits(arizona->regmap, fll->base + 1,
1532 ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
1534 regmap_update_bits(arizona->regmap, fll->base + 0x11,
1535 ARIZONA_FLL1_SYNC_ENA,
1536 ARIZONA_FLL1_SYNC_ENA);
1538 ret = wait_for_completion_timeout(&fll->ok,
1539 msecs_to_jiffies(250));
1541 arizona_fll_warn(fll, "Timed out waiting for lock\n");
1544 static void arizona_disable_fll(struct arizona_fll *fll)
1546 struct arizona *arizona = fll->arizona;
1549 regmap_update_bits_check(arizona->regmap, fll->base + 1,
1550 ARIZONA_FLL1_ENA, 0, &change);
1551 regmap_update_bits(arizona->regmap, fll->base + 0x11,
1552 ARIZONA_FLL1_SYNC_ENA, 0);
1555 pm_runtime_put_autosuspend(arizona->dev);
1558 int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
1559 unsigned int Fref, unsigned int Fout)
1561 struct arizona_fll_cfg ref, sync;
1564 if (fll->ref_src == source && fll->ref_freq == Fref)
1569 ret = arizona_calc_fll(fll, &ref, Fref, fll->fout);
1574 if (fll->sync_src >= 0) {
1575 ret = arizona_calc_fll(fll, &sync, fll->sync_freq,
1582 fll->ref_src = source;
1583 fll->ref_freq = Fref;
1585 if (fll->fout && Fref > 0) {
1586 arizona_enable_fll(fll, &ref, &sync);
1591 EXPORT_SYMBOL_GPL(arizona_set_fll_refclk);
1593 int arizona_set_fll(struct arizona_fll *fll, int source,
1594 unsigned int Fref, unsigned int Fout)
1596 struct arizona_fll_cfg ref, sync;
1599 if (fll->sync_src == source &&
1600 fll->sync_freq == Fref && fll->fout == Fout)
1604 if (fll->ref_src >= 0) {
1605 ret = arizona_calc_fll(fll, &ref, fll->ref_freq,
1611 ret = arizona_calc_fll(fll, &sync, Fref, Fout);
1616 fll->sync_src = source;
1617 fll->sync_freq = Fref;
1621 arizona_enable_fll(fll, &ref, &sync);
1623 arizona_disable_fll(fll);
1628 EXPORT_SYMBOL_GPL(arizona_set_fll);
1630 int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
1631 int ok_irq, struct arizona_fll *fll)
1636 init_completion(&fll->ok);
1640 fll->arizona = arizona;
1641 fll->sync_src = ARIZONA_FLL_SRC_NONE;
1643 /* Configure default refclk to 32kHz if we have one */
1644 regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
1645 switch (val & ARIZONA_CLK_32K_SRC_MASK) {
1646 case ARIZONA_CLK_SRC_MCLK1:
1647 case ARIZONA_CLK_SRC_MCLK2:
1648 fll->ref_src = val & ARIZONA_CLK_32K_SRC_MASK;
1651 fll->ref_src = ARIZONA_FLL_SRC_NONE;
1653 fll->ref_freq = 32768;
1655 snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id);
1656 snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
1657 "FLL%d clock OK", id);
1659 ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name,
1660 arizona_fll_clock_ok, fll);
1662 dev_err(arizona->dev, "Failed to get FLL%d clock OK IRQ: %d\n",
1666 regmap_update_bits(arizona->regmap, fll->base + 1,
1667 ARIZONA_FLL1_FREERUN, 0);
1671 EXPORT_SYMBOL_GPL(arizona_init_fll);
1674 * arizona_set_output_mode - Set the mode of the specified output
1676 * @codec: Device to configure
1677 * @output: Output number
1678 * @diff: True to set the output to differential mode
1680 * Some systems use external analogue switches to connect more
1681 * analogue devices to the CODEC than are supported by the device. In
1682 * some systems this requires changing the switched output from single
1683 * ended to differential mode dynamically at runtime, an operation
1684 * supported using this function.
1686 * Most systems have a single static configuration and should use
1687 * platform data instead.
1689 int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff)
1691 unsigned int reg, val;
1693 if (output < 1 || output > 6)
1696 reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
1699 val = ARIZONA_OUT1_MONO;
1703 return snd_soc_update_bits(codec, reg, ARIZONA_OUT1_MONO, val);
1705 EXPORT_SYMBOL_GPL(arizona_set_output_mode);
1707 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
1708 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1709 MODULE_LICENSE("GPL");