2 * Cirrus Logic CS42448/CS42888 Audio CODEC Digital Audio Interface (DAI) driver
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
6 * Author: Nicolin Chen <Guangyu.Chen@freescale.com>
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/tlv.h>
25 #define CS42XX8_NUM_SUPPLIES 4
26 static const char *const cs42xx8_supply_names[CS42XX8_NUM_SUPPLIES] = {
33 #define CS42XX8_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
34 SNDRV_PCM_FMTBIT_S20_3LE | \
35 SNDRV_PCM_FMTBIT_S24_LE | \
36 SNDRV_PCM_FMTBIT_S32_LE)
38 /* codec private data */
40 struct regulator_bulk_data supplies[CS42XX8_NUM_SUPPLIES];
41 const struct cs42xx8_driver_data *drvdata;
42 struct regmap *regmap;
49 /* -127.5dB to 0dB with step of 0.5dB */
50 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
51 /* -64dB to 24dB with step of 0.5dB */
52 static const DECLARE_TLV_DB_SCALE(adc_tlv, -6400, 50, 0);
54 static const char *const cs42xx8_adc_single[] = { "Differential", "Single-Ended" };
55 static const char *const cs42xx8_szc[] = { "Immediate Change", "Zero Cross",
56 "Soft Ramp", "Soft Ramp on Zero Cross" };
58 static const struct soc_enum adc1_single_enum =
59 SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 4, 2, cs42xx8_adc_single);
60 static const struct soc_enum adc2_single_enum =
61 SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 3, 2, cs42xx8_adc_single);
62 static const struct soc_enum adc3_single_enum =
63 SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 2, 2, cs42xx8_adc_single);
64 static const struct soc_enum dac_szc_enum =
65 SOC_ENUM_SINGLE(CS42XX8_TXCTL, 5, 4, cs42xx8_szc);
66 static const struct soc_enum adc_szc_enum =
67 SOC_ENUM_SINGLE(CS42XX8_TXCTL, 0, 4, cs42xx8_szc);
69 static const struct snd_kcontrol_new cs42xx8_snd_controls[] = {
70 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", CS42XX8_VOLAOUT1,
71 CS42XX8_VOLAOUT2, 0, 0xff, 1, dac_tlv),
72 SOC_DOUBLE_R_TLV("DAC2 Playback Volume", CS42XX8_VOLAOUT3,
73 CS42XX8_VOLAOUT4, 0, 0xff, 1, dac_tlv),
74 SOC_DOUBLE_R_TLV("DAC3 Playback Volume", CS42XX8_VOLAOUT5,
75 CS42XX8_VOLAOUT6, 0, 0xff, 1, dac_tlv),
76 SOC_DOUBLE_R_TLV("DAC4 Playback Volume", CS42XX8_VOLAOUT7,
77 CS42XX8_VOLAOUT8, 0, 0xff, 1, dac_tlv),
78 SOC_DOUBLE_R_S_TLV("ADC1 Capture Volume", CS42XX8_VOLAIN1,
79 CS42XX8_VOLAIN2, 0, -0x80, 0x30, 7, 0, adc_tlv),
80 SOC_DOUBLE_R_S_TLV("ADC2 Capture Volume", CS42XX8_VOLAIN3,
81 CS42XX8_VOLAIN4, 0, -0x80, 0x30, 7, 0, adc_tlv),
82 SOC_DOUBLE("DAC1 Invert Switch", CS42XX8_DACINV, 0, 1, 1, 0),
83 SOC_DOUBLE("DAC2 Invert Switch", CS42XX8_DACINV, 2, 3, 1, 0),
84 SOC_DOUBLE("DAC3 Invert Switch", CS42XX8_DACINV, 4, 5, 1, 0),
85 SOC_DOUBLE("DAC4 Invert Switch", CS42XX8_DACINV, 6, 7, 1, 0),
86 SOC_DOUBLE("ADC1 Invert Switch", CS42XX8_ADCINV, 0, 1, 1, 0),
87 SOC_DOUBLE("ADC2 Invert Switch", CS42XX8_ADCINV, 2, 3, 1, 0),
88 SOC_SINGLE("ADC High-Pass Filter Switch", CS42XX8_ADCCTL, 7, 1, 1),
89 SOC_SINGLE("DAC De-emphasis Switch", CS42XX8_ADCCTL, 5, 1, 0),
90 SOC_ENUM("ADC1 Single Ended Mode Switch", adc1_single_enum),
91 SOC_ENUM("ADC2 Single Ended Mode Switch", adc2_single_enum),
92 SOC_SINGLE("DAC Single Volume Control Switch", CS42XX8_TXCTL, 7, 1, 0),
93 SOC_ENUM("DAC Soft Ramp & Zero Cross Control Switch", dac_szc_enum),
94 SOC_SINGLE("DAC Auto Mute Switch", CS42XX8_TXCTL, 4, 1, 0),
95 SOC_SINGLE("Mute ADC Serial Port Switch", CS42XX8_TXCTL, 3, 1, 0),
96 SOC_SINGLE("ADC Single Volume Control Switch", CS42XX8_TXCTL, 2, 1, 0),
97 SOC_ENUM("ADC Soft Ramp & Zero Cross Control Switch", adc_szc_enum),
100 static const struct snd_kcontrol_new cs42xx8_adc3_snd_controls[] = {
101 SOC_DOUBLE_R_S_TLV("ADC3 Capture Volume", CS42XX8_VOLAIN5,
102 CS42XX8_VOLAIN6, 0, -0x80, 0x30, 7, 0, adc_tlv),
103 SOC_DOUBLE("ADC3 Invert Switch", CS42XX8_ADCINV, 4, 5, 1, 0),
104 SOC_ENUM("ADC3 Single Ended Mode Switch", adc3_single_enum),
107 static const struct snd_soc_dapm_widget cs42xx8_dapm_widgets[] = {
108 SND_SOC_DAPM_DAC("DAC1", "Playback", CS42XX8_PWRCTL, 1, 1),
109 SND_SOC_DAPM_DAC("DAC2", "Playback", CS42XX8_PWRCTL, 2, 1),
110 SND_SOC_DAPM_DAC("DAC3", "Playback", CS42XX8_PWRCTL, 3, 1),
111 SND_SOC_DAPM_DAC("DAC4", "Playback", CS42XX8_PWRCTL, 4, 1),
113 SND_SOC_DAPM_OUTPUT("AOUT1L"),
114 SND_SOC_DAPM_OUTPUT("AOUT1R"),
115 SND_SOC_DAPM_OUTPUT("AOUT2L"),
116 SND_SOC_DAPM_OUTPUT("AOUT2R"),
117 SND_SOC_DAPM_OUTPUT("AOUT3L"),
118 SND_SOC_DAPM_OUTPUT("AOUT3R"),
119 SND_SOC_DAPM_OUTPUT("AOUT4L"),
120 SND_SOC_DAPM_OUTPUT("AOUT4R"),
122 SND_SOC_DAPM_ADC("ADC1", "Capture", CS42XX8_PWRCTL, 5, 1),
123 SND_SOC_DAPM_ADC("ADC2", "Capture", CS42XX8_PWRCTL, 6, 1),
125 SND_SOC_DAPM_INPUT("AIN1L"),
126 SND_SOC_DAPM_INPUT("AIN1R"),
127 SND_SOC_DAPM_INPUT("AIN2L"),
128 SND_SOC_DAPM_INPUT("AIN2R"),
130 SND_SOC_DAPM_SUPPLY("PWR", CS42XX8_PWRCTL, 0, 1, NULL, 0),
133 static const struct snd_soc_dapm_widget cs42xx8_adc3_dapm_widgets[] = {
134 SND_SOC_DAPM_ADC("ADC3", "Capture", CS42XX8_PWRCTL, 7, 1),
136 SND_SOC_DAPM_INPUT("AIN3L"),
137 SND_SOC_DAPM_INPUT("AIN3R"),
140 static const struct snd_soc_dapm_route cs42xx8_dapm_routes[] = {
142 { "AOUT1L", NULL, "DAC1" },
143 { "AOUT1R", NULL, "DAC1" },
144 { "DAC1", NULL, "PWR" },
146 { "AOUT2L", NULL, "DAC2" },
147 { "AOUT2R", NULL, "DAC2" },
148 { "DAC2", NULL, "PWR" },
150 { "AOUT3L", NULL, "DAC3" },
151 { "AOUT3R", NULL, "DAC3" },
152 { "DAC3", NULL, "PWR" },
154 { "AOUT4L", NULL, "DAC4" },
155 { "AOUT4R", NULL, "DAC4" },
156 { "DAC4", NULL, "PWR" },
159 { "ADC1", NULL, "AIN1L" },
160 { "ADC1", NULL, "AIN1R" },
161 { "ADC1", NULL, "PWR" },
163 { "ADC2", NULL, "AIN2L" },
164 { "ADC2", NULL, "AIN2R" },
165 { "ADC2", NULL, "PWR" },
168 static const struct snd_soc_dapm_route cs42xx8_adc3_dapm_routes[] = {
170 { "ADC3", NULL, "AIN3L" },
171 { "ADC3", NULL, "AIN3R" },
172 { "ADC3", NULL, "PWR" },
175 struct cs42xx8_ratios {
181 static const struct cs42xx8_ratios cs42xx8_ratios[] = {
182 { 64, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_256(4) },
183 { 96, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_384(4) },
184 { 128, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_512(4) },
185 { 192, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_768(4) },
186 { 256, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_256(1) },
187 { 384, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_384(1) },
188 { 512, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_512(1) },
189 { 768, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_768(1) },
190 { 1024, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_1024(1) }
193 static int cs42xx8_set_dai_sysclk(struct snd_soc_dai *codec_dai,
194 int clk_id, unsigned int freq, int dir)
196 struct snd_soc_codec *codec = codec_dai->codec;
197 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
199 cs42xx8->sysclk = freq;
204 static int cs42xx8_set_dai_fmt(struct snd_soc_dai *codec_dai,
207 struct snd_soc_codec *codec = codec_dai->codec;
208 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
212 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
213 case SND_SOC_DAIFMT_LEFT_J:
214 val = CS42XX8_INTF_DAC_DIF_LEFTJ | CS42XX8_INTF_ADC_DIF_LEFTJ;
216 case SND_SOC_DAIFMT_I2S:
217 val = CS42XX8_INTF_DAC_DIF_I2S | CS42XX8_INTF_ADC_DIF_I2S;
219 case SND_SOC_DAIFMT_RIGHT_J:
220 val = CS42XX8_INTF_DAC_DIF_RIGHTJ | CS42XX8_INTF_ADC_DIF_RIGHTJ;
223 dev_err(codec->dev, "unsupported dai format\n");
227 regmap_update_bits(cs42xx8->regmap, CS42XX8_INTF,
228 CS42XX8_INTF_DAC_DIF_MASK |
229 CS42XX8_INTF_ADC_DIF_MASK, val);
231 /* Set master/slave audio interface */
232 switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
233 case SND_SOC_DAIFMT_CBS_CFS:
234 cs42xx8->slave_mode = true;
236 case SND_SOC_DAIFMT_CBM_CFM:
237 cs42xx8->slave_mode = false;
240 dev_err(codec->dev, "unsupported master/slave mode\n");
247 static int cs42xx8_hw_params(struct snd_pcm_substream *substream,
248 struct snd_pcm_hw_params *params,
249 struct snd_soc_dai *dai)
251 struct snd_soc_pcm_runtime *rtd = substream->private_data;
252 struct snd_soc_codec *codec = rtd->codec;
253 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
254 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
255 u32 ratio = cs42xx8->sysclk / params_rate(params);
256 u32 i, fm, val, mask;
258 for (i = 0; i < ARRAY_SIZE(cs42xx8_ratios); i++) {
259 if (cs42xx8_ratios[i].ratio == ratio)
263 if (i == ARRAY_SIZE(cs42xx8_ratios)) {
264 dev_err(codec->dev, "unsupported sysclk ratio\n");
268 mask = CS42XX8_FUNCMOD_MFREQ_MASK;
269 val = cs42xx8_ratios[i].mclk;
271 fm = cs42xx8->slave_mode ? CS42XX8_FM_AUTO : cs42xx8_ratios[i].speed;
273 regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD,
274 CS42XX8_FUNCMOD_xC_FM_MASK(tx) | mask,
275 CS42XX8_FUNCMOD_xC_FM(tx, fm) | val);
280 static int cs42xx8_digital_mute(struct snd_soc_dai *dai, int mute)
282 struct snd_soc_codec *codec = dai->codec;
283 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
285 regmap_update_bits(cs42xx8->regmap, CS42XX8_DACMUTE,
286 CS42XX8_DACMUTE_ALL, mute ? CS42XX8_DACMUTE_ALL : 0);
291 static const struct snd_soc_dai_ops cs42xx8_dai_ops = {
292 .set_fmt = cs42xx8_set_dai_fmt,
293 .set_sysclk = cs42xx8_set_dai_sysclk,
294 .hw_params = cs42xx8_hw_params,
295 .digital_mute = cs42xx8_digital_mute,
298 static struct snd_soc_dai_driver cs42xx8_dai = {
300 .stream_name = "Playback",
303 .rates = SNDRV_PCM_RATE_8000_192000,
304 .formats = CS42XX8_FORMATS,
307 .stream_name = "Capture",
309 .rates = SNDRV_PCM_RATE_8000_192000,
310 .formats = CS42XX8_FORMATS,
312 .ops = &cs42xx8_dai_ops,
315 static const struct reg_default cs42xx8_reg[] = {
316 { 0x01, 0x01 }, /* Chip I.D. and Revision Register */
317 { 0x02, 0x00 }, /* Power Control */
318 { 0x03, 0xF0 }, /* Functional Mode */
319 { 0x04, 0x46 }, /* Interface Formats */
320 { 0x05, 0x00 }, /* ADC Control & DAC De-Emphasis */
321 { 0x06, 0x10 }, /* Transition Control */
322 { 0x07, 0x00 }, /* DAC Channel Mute */
323 { 0x08, 0x00 }, /* Volume Control AOUT1 */
324 { 0x09, 0x00 }, /* Volume Control AOUT2 */
325 { 0x0a, 0x00 }, /* Volume Control AOUT3 */
326 { 0x0b, 0x00 }, /* Volume Control AOUT4 */
327 { 0x0c, 0x00 }, /* Volume Control AOUT5 */
328 { 0x0d, 0x00 }, /* Volume Control AOUT6 */
329 { 0x0e, 0x00 }, /* Volume Control AOUT7 */
330 { 0x0f, 0x00 }, /* Volume Control AOUT8 */
331 { 0x10, 0x00 }, /* DAC Channel Invert */
332 { 0x11, 0x00 }, /* Volume Control AIN1 */
333 { 0x12, 0x00 }, /* Volume Control AIN2 */
334 { 0x13, 0x00 }, /* Volume Control AIN3 */
335 { 0x14, 0x00 }, /* Volume Control AIN4 */
336 { 0x15, 0x00 }, /* Volume Control AIN5 */
337 { 0x16, 0x00 }, /* Volume Control AIN6 */
338 { 0x17, 0x00 }, /* ADC Channel Invert */
339 { 0x18, 0x00 }, /* Status Control */
340 { 0x1a, 0x00 }, /* Status Mask */
341 { 0x1b, 0x00 }, /* MUTEC Pin Control */
344 static bool cs42xx8_volatile_register(struct device *dev, unsigned int reg)
354 static bool cs42xx8_writeable_register(struct device *dev, unsigned int reg)
365 const struct regmap_config cs42xx8_regmap_config = {
369 .max_register = CS42XX8_LASTREG,
370 .reg_defaults = cs42xx8_reg,
371 .num_reg_defaults = ARRAY_SIZE(cs42xx8_reg),
372 .volatile_reg = cs42xx8_volatile_register,
373 .writeable_reg = cs42xx8_writeable_register,
374 .cache_type = REGCACHE_RBTREE,
376 EXPORT_SYMBOL_GPL(cs42xx8_regmap_config);
378 static int cs42xx8_codec_probe(struct snd_soc_codec *codec)
380 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
381 struct snd_soc_dapm_context *dapm = &codec->dapm;
383 switch (cs42xx8->drvdata->num_adcs) {
385 snd_soc_add_codec_controls(codec, cs42xx8_adc3_snd_controls,
386 ARRAY_SIZE(cs42xx8_adc3_snd_controls));
387 snd_soc_dapm_new_controls(dapm, cs42xx8_adc3_dapm_widgets,
388 ARRAY_SIZE(cs42xx8_adc3_dapm_widgets));
389 snd_soc_dapm_add_routes(dapm, cs42xx8_adc3_dapm_routes,
390 ARRAY_SIZE(cs42xx8_adc3_dapm_routes));
396 /* Mute all DAC channels */
397 regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE, CS42XX8_DACMUTE_ALL);
402 static const struct snd_soc_codec_driver cs42xx8_driver = {
403 .probe = cs42xx8_codec_probe,
404 .idle_bias_off = true,
406 .controls = cs42xx8_snd_controls,
407 .num_controls = ARRAY_SIZE(cs42xx8_snd_controls),
408 .dapm_widgets = cs42xx8_dapm_widgets,
409 .num_dapm_widgets = ARRAY_SIZE(cs42xx8_dapm_widgets),
410 .dapm_routes = cs42xx8_dapm_routes,
411 .num_dapm_routes = ARRAY_SIZE(cs42xx8_dapm_routes),
414 const struct cs42xx8_driver_data cs42448_data = {
418 EXPORT_SYMBOL_GPL(cs42448_data);
420 const struct cs42xx8_driver_data cs42888_data = {
424 EXPORT_SYMBOL_GPL(cs42888_data);
426 const struct of_device_id cs42xx8_of_match[] = {
427 { .compatible = "cirrus,cs42448", .data = &cs42448_data, },
428 { .compatible = "cirrus,cs42888", .data = &cs42888_data, },
431 MODULE_DEVICE_TABLE(of, cs42xx8_of_match);
432 EXPORT_SYMBOL_GPL(cs42xx8_of_match);
434 int cs42xx8_probe(struct device *dev, struct regmap *regmap)
436 const struct of_device_id *of_id = of_match_device(cs42xx8_of_match, dev);
437 struct cs42xx8_priv *cs42xx8;
440 cs42xx8 = devm_kzalloc(dev, sizeof(*cs42xx8), GFP_KERNEL);
444 dev_set_drvdata(dev, cs42xx8);
447 cs42xx8->drvdata = of_id->data;
449 if (!cs42xx8->drvdata) {
450 dev_err(dev, "failed to find driver data\n");
454 cs42xx8->clk = devm_clk_get(dev, "mclk");
455 if (IS_ERR(cs42xx8->clk)) {
456 dev_err(dev, "failed to get the clock: %ld\n",
457 PTR_ERR(cs42xx8->clk));
461 cs42xx8->sysclk = clk_get_rate(cs42xx8->clk);
463 for (i = 0; i < ARRAY_SIZE(cs42xx8->supplies); i++)
464 cs42xx8->supplies[i].supply = cs42xx8_supply_names[i];
466 ret = devm_regulator_bulk_get(dev,
467 ARRAY_SIZE(cs42xx8->supplies), cs42xx8->supplies);
469 dev_err(dev, "failed to request supplies: %d\n", ret);
473 ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies),
476 dev_err(dev, "failed to enable supplies: %d\n", ret);
480 /* Make sure hardware reset done */
483 cs42xx8->regmap = regmap;
484 if (IS_ERR(cs42xx8->regmap)) {
485 ret = PTR_ERR(cs42xx8->regmap);
486 dev_err(dev, "failed to allocate regmap: %d\n", ret);
491 * We haven't marked the chip revision as volatile due to
492 * sharing a register with the right input volume; explicitly
493 * bypass the cache to read it.
495 regcache_cache_bypass(cs42xx8->regmap, true);
497 /* Validate the chip ID */
498 ret = regmap_read(cs42xx8->regmap, CS42XX8_CHIPID, &val);
500 dev_err(dev, "failed to get device ID, ret = %d", ret);
504 /* The top four bits of the chip ID should be 0000 */
505 if (((val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4) != 0x00) {
506 dev_err(dev, "unmatched chip ID: %d\n",
507 (val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4);
512 dev_info(dev, "found device, revision %X\n",
513 val & CS42XX8_CHIPID_REV_ID_MASK);
515 regcache_cache_bypass(cs42xx8->regmap, false);
517 cs42xx8_dai.name = cs42xx8->drvdata->name;
519 /* Each adc supports stereo input */
520 cs42xx8_dai.capture.channels_max = cs42xx8->drvdata->num_adcs * 2;
522 ret = snd_soc_register_codec(dev, &cs42xx8_driver, &cs42xx8_dai, 1);
524 dev_err(dev, "failed to register codec:%d\n", ret);
528 regcache_cache_only(cs42xx8->regmap, true);
531 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
536 EXPORT_SYMBOL_GPL(cs42xx8_probe);
538 #ifdef CONFIG_PM_RUNTIME
539 static int cs42xx8_runtime_resume(struct device *dev)
541 struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev);
544 ret = clk_prepare_enable(cs42xx8->clk);
546 dev_err(dev, "failed to enable mclk: %d\n", ret);
550 ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies),
553 dev_err(dev, "failed to enable supplies: %d\n", ret);
557 /* Make sure hardware reset done */
560 regcache_cache_only(cs42xx8->regmap, false);
562 ret = regcache_sync(cs42xx8->regmap);
564 dev_err(dev, "failed to sync regmap: %d\n", ret);
571 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
574 clk_disable_unprepare(cs42xx8->clk);
579 static int cs42xx8_runtime_suspend(struct device *dev)
581 struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev);
583 regcache_cache_only(cs42xx8->regmap, true);
585 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
588 clk_disable_unprepare(cs42xx8->clk);
594 const struct dev_pm_ops cs42xx8_pm = {
595 SET_RUNTIME_PM_OPS(cs42xx8_runtime_suspend, cs42xx8_runtime_resume, NULL)
597 EXPORT_SYMBOL_GPL(cs42xx8_pm);
599 MODULE_DESCRIPTION("Cirrus Logic CS42448/CS42888 ALSA SoC Codec Driver");
600 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
601 MODULE_LICENSE("GPL");