2 * Cirrus Logic CS42448/CS42888 Audio CODEC Digital Audio Interface (DAI) driver
4 * Copyright (C) 2014 Freescale Semiconductor, Inc.
6 * Author: Nicolin Chen <Guangyu.Chen@freescale.com>
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/tlv.h>
25 #define CS42XX8_NUM_SUPPLIES 4
26 static const char *const cs42xx8_supply_names[CS42XX8_NUM_SUPPLIES] = {
33 #define CS42XX8_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
34 SNDRV_PCM_FMTBIT_S20_3LE | \
35 SNDRV_PCM_FMTBIT_S24_LE | \
36 SNDRV_PCM_FMTBIT_S32_LE)
38 /* codec private data */
40 struct regulator_bulk_data supplies[CS42XX8_NUM_SUPPLIES];
41 const struct cs42xx8_driver_data *drvdata;
42 struct regmap *regmap;
50 /* -127.5dB to 0dB with step of 0.5dB */
51 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
52 /* -64dB to 24dB with step of 0.5dB */
53 static const DECLARE_TLV_DB_SCALE(adc_tlv, -6400, 50, 0);
55 static const char *const cs42xx8_adc_single[] = { "Differential", "Single-Ended" };
56 static const char *const cs42xx8_szc[] = { "Immediate Change", "Zero Cross",
57 "Soft Ramp", "Soft Ramp on Zero Cross" };
59 static const struct soc_enum adc1_single_enum =
60 SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 4, 2, cs42xx8_adc_single);
61 static const struct soc_enum adc2_single_enum =
62 SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 3, 2, cs42xx8_adc_single);
63 static const struct soc_enum adc3_single_enum =
64 SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 2, 2, cs42xx8_adc_single);
65 static const struct soc_enum dac_szc_enum =
66 SOC_ENUM_SINGLE(CS42XX8_TXCTL, 5, 4, cs42xx8_szc);
67 static const struct soc_enum adc_szc_enum =
68 SOC_ENUM_SINGLE(CS42XX8_TXCTL, 0, 4, cs42xx8_szc);
70 static const struct snd_kcontrol_new cs42xx8_snd_controls[] = {
71 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", CS42XX8_VOLAOUT1,
72 CS42XX8_VOLAOUT2, 0, 0xff, 1, dac_tlv),
73 SOC_DOUBLE_R_TLV("DAC2 Playback Volume", CS42XX8_VOLAOUT3,
74 CS42XX8_VOLAOUT4, 0, 0xff, 1, dac_tlv),
75 SOC_DOUBLE_R_TLV("DAC3 Playback Volume", CS42XX8_VOLAOUT5,
76 CS42XX8_VOLAOUT6, 0, 0xff, 1, dac_tlv),
77 SOC_DOUBLE_R_TLV("DAC4 Playback Volume", CS42XX8_VOLAOUT7,
78 CS42XX8_VOLAOUT8, 0, 0xff, 1, dac_tlv),
79 SOC_DOUBLE_R_S_TLV("ADC1 Capture Volume", CS42XX8_VOLAIN1,
80 CS42XX8_VOLAIN2, 0, -0x80, 0x30, 7, 0, adc_tlv),
81 SOC_DOUBLE_R_S_TLV("ADC2 Capture Volume", CS42XX8_VOLAIN3,
82 CS42XX8_VOLAIN4, 0, -0x80, 0x30, 7, 0, adc_tlv),
83 SOC_DOUBLE("DAC1 Invert Switch", CS42XX8_DACINV, 0, 1, 1, 0),
84 SOC_DOUBLE("DAC2 Invert Switch", CS42XX8_DACINV, 2, 3, 1, 0),
85 SOC_DOUBLE("DAC3 Invert Switch", CS42XX8_DACINV, 4, 5, 1, 0),
86 SOC_DOUBLE("DAC4 Invert Switch", CS42XX8_DACINV, 6, 7, 1, 0),
87 SOC_DOUBLE("ADC1 Invert Switch", CS42XX8_ADCINV, 0, 1, 1, 0),
88 SOC_DOUBLE("ADC2 Invert Switch", CS42XX8_ADCINV, 2, 3, 1, 0),
89 SOC_SINGLE("ADC High-Pass Filter Switch", CS42XX8_ADCCTL, 7, 1, 1),
90 SOC_SINGLE("DAC De-emphasis Switch", CS42XX8_ADCCTL, 5, 1, 0),
91 SOC_ENUM("ADC1 Single Ended Mode Switch", adc1_single_enum),
92 SOC_ENUM("ADC2 Single Ended Mode Switch", adc2_single_enum),
93 SOC_SINGLE("DAC Single Volume Control Switch", CS42XX8_TXCTL, 7, 1, 0),
94 SOC_ENUM("DAC Soft Ramp & Zero Cross Control Switch", dac_szc_enum),
95 SOC_SINGLE("DAC Auto Mute Switch", CS42XX8_TXCTL, 4, 1, 0),
96 SOC_SINGLE("Mute ADC Serial Port Switch", CS42XX8_TXCTL, 3, 1, 0),
97 SOC_SINGLE("ADC Single Volume Control Switch", CS42XX8_TXCTL, 2, 1, 0),
98 SOC_ENUM("ADC Soft Ramp & Zero Cross Control Switch", adc_szc_enum),
101 static const struct snd_kcontrol_new cs42xx8_adc3_snd_controls[] = {
102 SOC_DOUBLE_R_S_TLV("ADC3 Capture Volume", CS42XX8_VOLAIN5,
103 CS42XX8_VOLAIN6, 0, -0x80, 0x30, 7, 0, adc_tlv),
104 SOC_DOUBLE("ADC3 Invert Switch", CS42XX8_ADCINV, 4, 5, 1, 0),
105 SOC_ENUM("ADC3 Single Ended Mode Switch", adc3_single_enum),
108 static const struct snd_soc_dapm_widget cs42xx8_dapm_widgets[] = {
109 SND_SOC_DAPM_DAC("DAC1", "Playback", CS42XX8_PWRCTL, 1, 1),
110 SND_SOC_DAPM_DAC("DAC2", "Playback", CS42XX8_PWRCTL, 2, 1),
111 SND_SOC_DAPM_DAC("DAC3", "Playback", CS42XX8_PWRCTL, 3, 1),
112 SND_SOC_DAPM_DAC("DAC4", "Playback", CS42XX8_PWRCTL, 4, 1),
114 SND_SOC_DAPM_OUTPUT("AOUT1L"),
115 SND_SOC_DAPM_OUTPUT("AOUT1R"),
116 SND_SOC_DAPM_OUTPUT("AOUT2L"),
117 SND_SOC_DAPM_OUTPUT("AOUT2R"),
118 SND_SOC_DAPM_OUTPUT("AOUT3L"),
119 SND_SOC_DAPM_OUTPUT("AOUT3R"),
120 SND_SOC_DAPM_OUTPUT("AOUT4L"),
121 SND_SOC_DAPM_OUTPUT("AOUT4R"),
123 SND_SOC_DAPM_ADC("ADC1", "Capture", CS42XX8_PWRCTL, 5, 1),
124 SND_SOC_DAPM_ADC("ADC2", "Capture", CS42XX8_PWRCTL, 6, 1),
126 SND_SOC_DAPM_INPUT("AIN1L"),
127 SND_SOC_DAPM_INPUT("AIN1R"),
128 SND_SOC_DAPM_INPUT("AIN2L"),
129 SND_SOC_DAPM_INPUT("AIN2R"),
131 SND_SOC_DAPM_SUPPLY("PWR", CS42XX8_PWRCTL, 0, 1, NULL, 0),
134 static const struct snd_soc_dapm_widget cs42xx8_adc3_dapm_widgets[] = {
135 SND_SOC_DAPM_ADC("ADC3", "Capture", CS42XX8_PWRCTL, 7, 1),
137 SND_SOC_DAPM_INPUT("AIN3L"),
138 SND_SOC_DAPM_INPUT("AIN3R"),
141 static const struct snd_soc_dapm_route cs42xx8_dapm_routes[] = {
143 { "AOUT1L", NULL, "DAC1" },
144 { "AOUT1R", NULL, "DAC1" },
145 { "DAC1", NULL, "PWR" },
147 { "AOUT2L", NULL, "DAC2" },
148 { "AOUT2R", NULL, "DAC2" },
149 { "DAC2", NULL, "PWR" },
151 { "AOUT3L", NULL, "DAC3" },
152 { "AOUT3R", NULL, "DAC3" },
153 { "DAC3", NULL, "PWR" },
155 { "AOUT4L", NULL, "DAC4" },
156 { "AOUT4R", NULL, "DAC4" },
157 { "DAC4", NULL, "PWR" },
160 { "ADC1", NULL, "AIN1L" },
161 { "ADC1", NULL, "AIN1R" },
162 { "ADC1", NULL, "PWR" },
164 { "ADC2", NULL, "AIN2L" },
165 { "ADC2", NULL, "AIN2R" },
166 { "ADC2", NULL, "PWR" },
169 static const struct snd_soc_dapm_route cs42xx8_adc3_dapm_routes[] = {
171 { "ADC3", NULL, "AIN3L" },
172 { "ADC3", NULL, "AIN3R" },
173 { "ADC3", NULL, "PWR" },
176 struct cs42xx8_ratios {
182 static const struct cs42xx8_ratios cs42xx8_ratios[] = {
183 { 64, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_256(4) },
184 { 96, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_384(4) },
185 { 128, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_512(4) },
186 { 192, CS42XX8_FM_QUAD, CS42XX8_FUNCMOD_MFREQ_768(4) },
187 { 256, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_256(1) },
188 { 384, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_384(1) },
189 { 512, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_512(1) },
190 { 768, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_768(1) },
191 { 1024, CS42XX8_FM_SINGLE, CS42XX8_FUNCMOD_MFREQ_1024(1) }
194 static int cs42xx8_set_dai_sysclk(struct snd_soc_dai *codec_dai,
195 int clk_id, unsigned int freq, int dir)
197 struct snd_soc_codec *codec = codec_dai->codec;
198 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
200 cs42xx8->sysclk = freq;
205 static int cs42xx8_set_dai_fmt(struct snd_soc_dai *codec_dai,
208 struct snd_soc_codec *codec = codec_dai->codec;
209 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
213 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
214 case SND_SOC_DAIFMT_LEFT_J:
215 val = CS42XX8_INTF_DAC_DIF_LEFTJ | CS42XX8_INTF_ADC_DIF_LEFTJ;
217 case SND_SOC_DAIFMT_I2S:
218 val = CS42XX8_INTF_DAC_DIF_I2S | CS42XX8_INTF_ADC_DIF_I2S;
220 case SND_SOC_DAIFMT_RIGHT_J:
221 val = CS42XX8_INTF_DAC_DIF_RIGHTJ | CS42XX8_INTF_ADC_DIF_RIGHTJ;
223 case SND_SOC_DAIFMT_DSP_A:
224 val = CS42XX8_INTF_DAC_DIF_TDM | CS42XX8_INTF_ADC_DIF_TDM;
227 dev_err(codec->dev, "unsupported dai format\n");
231 regmap_update_bits(cs42xx8->regmap, CS42XX8_INTF,
232 CS42XX8_INTF_DAC_DIF_MASK |
233 CS42XX8_INTF_ADC_DIF_MASK, val);
235 /* Set master/slave audio interface */
236 switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
237 case SND_SOC_DAIFMT_CBS_CFS:
238 cs42xx8->slave_mode = true;
240 case SND_SOC_DAIFMT_CBM_CFM:
241 cs42xx8->slave_mode = false;
244 dev_err(codec->dev, "unsupported master/slave mode\n");
251 static int cs42xx8_hw_params(struct snd_pcm_substream *substream,
252 struct snd_pcm_hw_params *params,
253 struct snd_soc_dai *dai)
255 struct snd_soc_codec *codec = dai->codec;
256 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
257 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
258 u32 ratio = cs42xx8->sysclk / params_rate(params);
259 u32 i, fm, val, mask;
262 cs42xx8->tx_channels = params_channels(params);
264 for (i = 0; i < ARRAY_SIZE(cs42xx8_ratios); i++) {
265 if (cs42xx8_ratios[i].ratio == ratio)
269 if (i == ARRAY_SIZE(cs42xx8_ratios)) {
270 dev_err(codec->dev, "unsupported sysclk ratio\n");
274 mask = CS42XX8_FUNCMOD_MFREQ_MASK;
275 val = cs42xx8_ratios[i].mclk;
277 fm = cs42xx8->slave_mode ? CS42XX8_FM_AUTO : cs42xx8_ratios[i].speed;
279 regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD,
280 CS42XX8_FUNCMOD_xC_FM_MASK(tx) | mask,
281 CS42XX8_FUNCMOD_xC_FM(tx, fm) | val);
286 static int cs42xx8_digital_mute(struct snd_soc_dai *dai, int mute)
288 struct snd_soc_codec *codec = dai->codec;
289 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
290 u8 dac_unmute = cs42xx8->tx_channels ?
291 ~((0x1 << cs42xx8->tx_channels) - 1) : 0;
293 regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE,
294 mute ? CS42XX8_DACMUTE_ALL : dac_unmute);
299 static const struct snd_soc_dai_ops cs42xx8_dai_ops = {
300 .set_fmt = cs42xx8_set_dai_fmt,
301 .set_sysclk = cs42xx8_set_dai_sysclk,
302 .hw_params = cs42xx8_hw_params,
303 .digital_mute = cs42xx8_digital_mute,
306 static struct snd_soc_dai_driver cs42xx8_dai = {
308 .stream_name = "Playback",
311 .rates = SNDRV_PCM_RATE_8000_192000,
312 .formats = CS42XX8_FORMATS,
315 .stream_name = "Capture",
317 .rates = SNDRV_PCM_RATE_8000_192000,
318 .formats = CS42XX8_FORMATS,
320 .ops = &cs42xx8_dai_ops,
323 static const struct reg_default cs42xx8_reg[] = {
324 { 0x01, 0x01 }, /* Chip I.D. and Revision Register */
325 { 0x02, 0x00 }, /* Power Control */
326 { 0x03, 0xF0 }, /* Functional Mode */
327 { 0x04, 0x46 }, /* Interface Formats */
328 { 0x05, 0x00 }, /* ADC Control & DAC De-Emphasis */
329 { 0x06, 0x10 }, /* Transition Control */
330 { 0x07, 0x00 }, /* DAC Channel Mute */
331 { 0x08, 0x00 }, /* Volume Control AOUT1 */
332 { 0x09, 0x00 }, /* Volume Control AOUT2 */
333 { 0x0a, 0x00 }, /* Volume Control AOUT3 */
334 { 0x0b, 0x00 }, /* Volume Control AOUT4 */
335 { 0x0c, 0x00 }, /* Volume Control AOUT5 */
336 { 0x0d, 0x00 }, /* Volume Control AOUT6 */
337 { 0x0e, 0x00 }, /* Volume Control AOUT7 */
338 { 0x0f, 0x00 }, /* Volume Control AOUT8 */
339 { 0x10, 0x00 }, /* DAC Channel Invert */
340 { 0x11, 0x00 }, /* Volume Control AIN1 */
341 { 0x12, 0x00 }, /* Volume Control AIN2 */
342 { 0x13, 0x00 }, /* Volume Control AIN3 */
343 { 0x14, 0x00 }, /* Volume Control AIN4 */
344 { 0x15, 0x00 }, /* Volume Control AIN5 */
345 { 0x16, 0x00 }, /* Volume Control AIN6 */
346 { 0x17, 0x00 }, /* ADC Channel Invert */
347 { 0x18, 0x00 }, /* Status Control */
348 { 0x1a, 0x00 }, /* Status Mask */
349 { 0x1b, 0x00 }, /* MUTEC Pin Control */
352 static bool cs42xx8_volatile_register(struct device *dev, unsigned int reg)
362 static bool cs42xx8_writeable_register(struct device *dev, unsigned int reg)
373 const struct regmap_config cs42xx8_regmap_config = {
377 .max_register = CS42XX8_LASTREG,
378 .reg_defaults = cs42xx8_reg,
379 .num_reg_defaults = ARRAY_SIZE(cs42xx8_reg),
380 .volatile_reg = cs42xx8_volatile_register,
381 .writeable_reg = cs42xx8_writeable_register,
382 .cache_type = REGCACHE_RBTREE,
384 EXPORT_SYMBOL_GPL(cs42xx8_regmap_config);
386 static int cs42xx8_codec_probe(struct snd_soc_codec *codec)
388 struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
389 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
391 switch (cs42xx8->drvdata->num_adcs) {
393 snd_soc_add_codec_controls(codec, cs42xx8_adc3_snd_controls,
394 ARRAY_SIZE(cs42xx8_adc3_snd_controls));
395 snd_soc_dapm_new_controls(dapm, cs42xx8_adc3_dapm_widgets,
396 ARRAY_SIZE(cs42xx8_adc3_dapm_widgets));
397 snd_soc_dapm_add_routes(dapm, cs42xx8_adc3_dapm_routes,
398 ARRAY_SIZE(cs42xx8_adc3_dapm_routes));
404 /* Mute all DAC channels */
405 regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE, CS42XX8_DACMUTE_ALL);
410 static const struct snd_soc_codec_driver cs42xx8_driver = {
411 .probe = cs42xx8_codec_probe,
412 .idle_bias_off = true,
414 .component_driver = {
415 .controls = cs42xx8_snd_controls,
416 .num_controls = ARRAY_SIZE(cs42xx8_snd_controls),
417 .dapm_widgets = cs42xx8_dapm_widgets,
418 .num_dapm_widgets = ARRAY_SIZE(cs42xx8_dapm_widgets),
419 .dapm_routes = cs42xx8_dapm_routes,
420 .num_dapm_routes = ARRAY_SIZE(cs42xx8_dapm_routes),
424 const struct cs42xx8_driver_data cs42448_data = {
428 EXPORT_SYMBOL_GPL(cs42448_data);
430 const struct cs42xx8_driver_data cs42888_data = {
434 EXPORT_SYMBOL_GPL(cs42888_data);
436 const struct of_device_id cs42xx8_of_match[] = {
437 { .compatible = "cirrus,cs42448", .data = &cs42448_data, },
438 { .compatible = "cirrus,cs42888", .data = &cs42888_data, },
441 MODULE_DEVICE_TABLE(of, cs42xx8_of_match);
442 EXPORT_SYMBOL_GPL(cs42xx8_of_match);
444 int cs42xx8_probe(struct device *dev, struct regmap *regmap)
446 const struct of_device_id *of_id;
447 struct cs42xx8_priv *cs42xx8;
450 if (IS_ERR(regmap)) {
451 ret = PTR_ERR(regmap);
452 dev_err(dev, "failed to allocate regmap: %d\n", ret);
456 cs42xx8 = devm_kzalloc(dev, sizeof(*cs42xx8), GFP_KERNEL);
460 cs42xx8->regmap = regmap;
461 dev_set_drvdata(dev, cs42xx8);
463 of_id = of_match_device(cs42xx8_of_match, dev);
465 cs42xx8->drvdata = of_id->data;
467 if (!cs42xx8->drvdata) {
468 dev_err(dev, "failed to find driver data\n");
472 cs42xx8->clk = devm_clk_get(dev, "mclk");
473 if (IS_ERR(cs42xx8->clk)) {
474 dev_err(dev, "failed to get the clock: %ld\n",
475 PTR_ERR(cs42xx8->clk));
479 cs42xx8->sysclk = clk_get_rate(cs42xx8->clk);
481 for (i = 0; i < ARRAY_SIZE(cs42xx8->supplies); i++)
482 cs42xx8->supplies[i].supply = cs42xx8_supply_names[i];
484 ret = devm_regulator_bulk_get(dev,
485 ARRAY_SIZE(cs42xx8->supplies), cs42xx8->supplies);
487 dev_err(dev, "failed to request supplies: %d\n", ret);
491 ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies),
494 dev_err(dev, "failed to enable supplies: %d\n", ret);
498 /* Make sure hardware reset done */
502 * We haven't marked the chip revision as volatile due to
503 * sharing a register with the right input volume; explicitly
504 * bypass the cache to read it.
506 regcache_cache_bypass(cs42xx8->regmap, true);
508 /* Validate the chip ID */
509 ret = regmap_read(cs42xx8->regmap, CS42XX8_CHIPID, &val);
511 dev_err(dev, "failed to get device ID, ret = %d", ret);
515 /* The top four bits of the chip ID should be 0000 */
516 if (((val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4) != 0x00) {
517 dev_err(dev, "unmatched chip ID: %d\n",
518 (val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4);
523 dev_info(dev, "found device, revision %X\n",
524 val & CS42XX8_CHIPID_REV_ID_MASK);
526 regcache_cache_bypass(cs42xx8->regmap, false);
528 cs42xx8_dai.name = cs42xx8->drvdata->name;
530 /* Each adc supports stereo input */
531 cs42xx8_dai.capture.channels_max = cs42xx8->drvdata->num_adcs * 2;
533 ret = snd_soc_register_codec(dev, &cs42xx8_driver, &cs42xx8_dai, 1);
535 dev_err(dev, "failed to register codec:%d\n", ret);
539 regcache_cache_only(cs42xx8->regmap, true);
542 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
547 EXPORT_SYMBOL_GPL(cs42xx8_probe);
550 static int cs42xx8_runtime_resume(struct device *dev)
552 struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev);
555 ret = clk_prepare_enable(cs42xx8->clk);
557 dev_err(dev, "failed to enable mclk: %d\n", ret);
561 ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies),
564 dev_err(dev, "failed to enable supplies: %d\n", ret);
568 /* Make sure hardware reset done */
571 regcache_cache_only(cs42xx8->regmap, false);
573 ret = regcache_sync(cs42xx8->regmap);
575 dev_err(dev, "failed to sync regmap: %d\n", ret);
582 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
585 clk_disable_unprepare(cs42xx8->clk);
590 static int cs42xx8_runtime_suspend(struct device *dev)
592 struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev);
594 regcache_cache_only(cs42xx8->regmap, true);
596 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
599 clk_disable_unprepare(cs42xx8->clk);
605 const struct dev_pm_ops cs42xx8_pm = {
606 SET_RUNTIME_PM_OPS(cs42xx8_runtime_suspend, cs42xx8_runtime_resume, NULL)
608 EXPORT_SYMBOL_GPL(cs42xx8_pm);
610 MODULE_DESCRIPTION("Cirrus Logic CS42448/CS42888 ALSA SoC Codec Driver");
611 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
612 MODULE_LICENSE("GPL");