1 #include <linux/delay.h>
3 #include <linux/interrupt.h>
4 #include <linux/module.h>
5 #include <linux/regulator/consumer.h>
6 #include <linux/types.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include <linux/mfd/syscon.h>
15 #include <sound/soc.h>
16 #include <sound/soc-dapm.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/tlv.h>
21 #include "msm8x16-wcd.h"
22 #include "msm8x16_wcd_registers.h"
24 #define MSM8X16_WCD_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
25 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
26 #define MSM8X16_WCD_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
27 SNDRV_PCM_FMTBIT_S24_LE)
29 #define TOMBAK_VERSION_1_0 0
30 #define TOMBAK_IS_1_0(ver) \
31 ((ver == TOMBAK_VERSION_1_0) ? 1 : 0)
33 #define HPHL_PA_DISABLE (0x01 << 1)
34 #define HPHR_PA_DISABLE (0x01 << 2)
35 #define EAR_PA_DISABLE (0x01 << 3)
36 #define SPKR_PA_DISABLE (0x01 << 4)
38 #define MICBIAS_DEFAULT_VAL 1800000
39 #define MICBIAS_MIN_VAL 1600000
40 #define MICBIAS_STEP_SIZE 50000
42 #define DEFAULT_BOOST_VOLTAGE 5000
43 #define MIN_BOOST_VOLTAGE 4000
44 #define MAX_BOOST_VOLTAGE 5550
45 #define BOOST_VOLTAGE_STEP 50
47 #define VOLTAGE_CONVERTER(value, min_value, step_size)\
48 ((value - min_value)/step_size);
56 static unsigned long rx_digital_gain_reg[] = {
57 MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL,
58 MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL,
59 MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL,
62 static unsigned long tx_digital_gain_reg[] = {
63 MSM8X16_WCD_A_CDC_TX1_VOL_CTL_GAIN,
64 MSM8X16_WCD_A_CDC_TX2_VOL_CTL_GAIN,
68 struct regmap *analog_map;
69 struct regmap *digital_map;
70 unsigned int analog_base;
76 bool ear_pa_boost_set;
80 struct regulator *vddio;
81 struct regulator *vdd_pa;
82 struct regulator *vdd_px;
83 struct regulator *vdd_cp;
84 struct regulator *vdd_mic_bias;
87 static int msm8x16_wcd_volatile(struct snd_soc_codec *codec, unsigned int reg)
89 return msm8x16_wcd_reg_readonly[reg];
92 static int msm8x16_wcd_readable(struct snd_soc_codec *ssc, unsigned int reg)
94 return msm8x16_wcd_reg_readable[reg];
97 static int __msm8x16_wcd_reg_write(struct snd_soc_codec *codec,
98 unsigned short reg, u8 val)
101 struct wcd_chip *chip = dev_get_drvdata(codec->dev);
103 if (MSM8X16_WCD_IS_TOMBAK_REG(reg)) {
104 ret = regmap_write(chip->analog_map,
105 chip->analog_base + reg, val);
106 } else if (MSM8X16_WCD_IS_DIGITAL_REG(reg)) {
107 u32 temp = val & 0x000000FF;
108 u16 offset = (reg ^ 0x0200) & 0x0FFF;
110 ret = regmap_write(chip->digital_map, offset, temp);
116 static int msm8x16_wcd_write(struct snd_soc_codec *codec, unsigned int reg,
119 if (reg == SND_SOC_NOPM)
122 BUG_ON(reg > MSM8X16_WCD_MAX_REGISTER);
123 if (!msm8x16_wcd_volatile(codec, reg))
124 msm8x16_wcd_reset_reg_defaults[reg] = value;
126 return __msm8x16_wcd_reg_write(codec, reg, (u8)value);
129 static int __msm8x16_wcd_reg_read(struct snd_soc_codec *codec,
134 struct wcd_chip *chip = dev_get_drvdata(codec->dev);
136 if (MSM8X16_WCD_IS_TOMBAK_REG(reg)) {
137 ret = regmap_read(chip->analog_map,
138 chip->analog_base + reg, &temp);
139 } else if (MSM8X16_WCD_IS_DIGITAL_REG(reg)) {
141 u16 offset = (reg ^ 0x0200) & 0x0FFF;
143 ret = regmap_read(chip->digital_map, offset, &val);
149 "%s: codec read failed for reg 0x%x\n",
154 dev_dbg(codec->dev, "Read 0x%02x from 0x%x\n", temp, reg);
159 static unsigned int msm8x16_wcd_read(struct snd_soc_codec *codec,
164 if (reg == SND_SOC_NOPM)
167 BUG_ON(reg > MSM8X16_WCD_MAX_REGISTER);
169 if (!msm8x16_wcd_volatile(codec, reg) &&
170 msm8x16_wcd_readable(codec, reg) &&
171 reg < codec->driver->reg_cache_size) {
172 return msm8x16_wcd_reset_reg_defaults[reg];
175 val = __msm8x16_wcd_reg_read(codec, reg);
180 static const struct msm8x16_wcd_reg_mask_val msm8x16_wcd_reg_defaults[] = {
181 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x03),
182 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT, 0x82),
183 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL, 0xE1),
186 static const struct msm8x16_wcd_reg_mask_val msm8x16_wcd_reg_defaults_2_0[] = {
187 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL3, 0x0F),
188 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_TX_1_2_OPAMP_BIAS, 0x4B),
189 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_NCP_FBCTRL, 0x28),
190 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL, 0x69),
191 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DRV_DBG, 0x01),
192 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL, 0x5F),
193 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SLOPE_COMP_IP_ZERO, 0x88),
194 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3, 0x0F),
195 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT, 0x82),
196 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x03),
197 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL, 0xE1),
200 static int msm8x16_wcd_bringup(struct snd_soc_codec *codec)
202 snd_soc_write(codec, MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL4, 0x01);
203 snd_soc_write(codec, MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL4, 0x01);
207 static const struct msm8x16_wcd_reg_mask_val
208 msm8x16_wcd_codec_reg_init_val[] = {
210 /* Initialize current threshold to 350MA
211 * number of wait and run cycles to 4096
213 {MSM8X16_WCD_A_ANALOG_RX_COM_OCP_CTL, 0xFF, 0xD1},
214 {MSM8X16_WCD_A_ANALOG_RX_COM_OCP_COUNT, 0xFF, 0xFF},
217 static void msm8x16_wcd_codec_init_reg(struct snd_soc_codec *codec)
221 for (i = 0; i < ARRAY_SIZE(msm8x16_wcd_codec_reg_init_val); i++)
222 snd_soc_update_bits(codec,
223 msm8x16_wcd_codec_reg_init_val[i].reg,
224 msm8x16_wcd_codec_reg_init_val[i].mask,
225 msm8x16_wcd_codec_reg_init_val[i].val);
228 static void msm8x16_wcd_update_reg_defaults(struct snd_soc_codec *codec)
231 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
233 if (TOMBAK_IS_1_0(msm8x16_wcd->pmic_rev)) {
234 for (i = 0; i < ARRAY_SIZE(msm8x16_wcd_reg_defaults); i++)
235 snd_soc_write(codec, msm8x16_wcd_reg_defaults[i].reg,
236 msm8x16_wcd_reg_defaults[i].val);
238 for (i = 0; i < ARRAY_SIZE(msm8x16_wcd_reg_defaults_2_0); i++)
240 msm8x16_wcd_reg_defaults_2_0[i].reg,
241 msm8x16_wcd_reg_defaults_2_0[i].val);
245 static int msm8x16_wcd_device_up(struct snd_soc_codec *codec)
249 dev_dbg(codec->dev, "%s: device up!\n", __func__);
250 msm8x16_wcd_bringup(codec);
252 for (reg = 0; reg < ARRAY_SIZE(msm8x16_wcd_reset_reg_defaults); reg++)
253 if (msm8x16_wcd_reg_readable[reg])
254 msm8x16_wcd_write(codec,
255 reg, msm8x16_wcd_reset_reg_defaults[reg]);
257 /* delay is required to make sure sound card state updated */
258 usleep_range(5000, 5100);
260 msm8x16_wcd_codec_init_reg(codec);
261 msm8x16_wcd_update_reg_defaults(codec);
266 static int msm8x16_wcd_codec_enable_clock_block(struct snd_soc_codec *codec,
269 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
270 unsigned long mclk_rate;
273 snd_soc_update_bits(codec,
274 MSM8X16_WCD_A_CDC_CLK_MCLK_CTL, 0x01, 0x01);
275 snd_soc_update_bits(codec,
276 MSM8X16_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x03);
277 snd_soc_update_bits(codec,
278 MSM8X16_WCD_A_ANALOG_MASTER_BIAS_CTL, 0x30, 0x30);
279 snd_soc_update_bits(codec,
280 MSM8X16_WCD_A_DIGITAL_CDC_RST_CTL, 0x80, 0x80);
281 snd_soc_update_bits(codec,
282 MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x0C);
284 mclk_rate = clk_get_rate(msm8x16_wcd->mclk);
286 if (mclk_rate == 12288000)
287 snd_soc_update_bits(codec,
288 MSM8X16_WCD_A_CDC_TOP_CTL, 0x01, 0x00);
289 else if (mclk_rate == 9600000)
290 snd_soc_update_bits(codec,
291 MSM8X16_WCD_A_CDC_TOP_CTL, 0x01, 0x01);
293 snd_soc_update_bits(codec,
294 MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x00);
295 snd_soc_update_bits(codec,
296 MSM8X16_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x00);
302 #define MICBIAS_EXT_BYP_CAP 0x00
303 #define MICBIAS_NO_EXT_BYP_CAP 0x01
305 static void msm8x16_wcd_configure_cap(struct snd_soc_codec *codec,
306 bool micbias1, bool micbias2)
309 // struct msm8916_asoc_mach_data *pdata = NULL;
310 //FIXME should come from DT
311 int micbias1_cap_mode = MICBIAS_EXT_BYP_CAP, micbias2_cap_mode = MICBIAS_NO_EXT_BYP_CAP;
313 //pdata = snd_soc_card_get_drvdata(codec->card);
315 pr_debug("\n %s: micbias1 %x micbias2 = %d\n", __func__, micbias1,
317 if (micbias1 && micbias2) {
318 if ((micbias1_cap_mode
319 == MICBIAS_EXT_BYP_CAP) ||
321 == MICBIAS_EXT_BYP_CAP))
322 snd_soc_update_bits(codec,
323 MSM8X16_WCD_A_ANALOG_MICB_1_EN,
324 0x40, (MICBIAS_EXT_BYP_CAP << 6));
326 snd_soc_update_bits(codec,
327 MSM8X16_WCD_A_ANALOG_MICB_1_EN,
328 0x40, (MICBIAS_NO_EXT_BYP_CAP << 6));
329 } else if (micbias2) {
330 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_MICB_1_EN,
331 0x40, (micbias2_cap_mode << 6));
332 } else if (micbias1) {
333 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_MICB_1_EN,
334 0x40, (micbias1_cap_mode << 6));
336 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_MICB_1_EN,
341 static int msm8x16_wcd_codec_probe(struct snd_soc_codec *codec)
343 struct wcd_chip *chip = dev_get_drvdata(codec->dev);
346 snd_soc_codec_set_drvdata(codec, chip);
347 chip->pmic_rev = snd_soc_read(codec, MSM8X16_WCD_A_DIGITAL_REVISION1);
348 dev_info(codec->dev, "%s :PMIC REV: %d", __func__,
351 chip->codec_version = snd_soc_read(codec,
352 MSM8X16_WCD_A_DIGITAL_PERPH_SUBTYPE);
353 dev_info(codec->dev, "%s :CODEC Version: %d", __func__,
354 chip->codec_version);
356 msm8x16_wcd_device_up(codec);
358 /* Set initial cap mode */
359 msm8x16_wcd_configure_cap(codec, false, false);
361 regulator_set_voltage(chip->vddio, 1800000, 1800000);
362 err = regulator_enable(chip->vddio);
364 dev_err(codec->dev, "failed to enable VDD regulator\n");
367 regulator_set_voltage(chip->vdd_pa, 1800000, 2200000);
368 err = regulator_enable(chip->vdd_pa);
370 dev_err(codec->dev, "failed to enable VDD regulator\n");
374 regulator_set_voltage(chip->vdd_mic_bias, 3075000, 3075000);
375 err = regulator_enable(chip->vdd_mic_bias);
377 dev_err(codec->dev, "failed to enable micbias regulator\n");
380 msm8x16_wcd_codec_enable_clock_block(codec, 1);
385 static int msm8x16_wcd_startup(struct snd_pcm_substream *substream,
386 struct snd_soc_dai *dai)
388 dev_dbg(dai->codec->dev, "%s(): substream = %s stream = %d\n",
390 substream->name, substream->stream);
394 static void msm8x16_wcd_shutdown(struct snd_pcm_substream *substream,
395 struct snd_soc_dai *dai)
397 dev_dbg(dai->codec->dev,
398 "%s(): substream = %s stream = %d\n", __func__,
399 substream->name, substream->stream);
402 static int msm8x16_wcd_set_interpolator_rate(struct snd_soc_dai *dai,
403 u8 rx_fs_rate_reg_val, u32 sample_rate)
408 static int msm8x16_wcd_set_decimator_rate(struct snd_soc_dai *dai,
409 u8 tx_fs_rate_reg_val, u32 sample_rate)
415 static int msm8x16_wcd_hw_params(struct snd_pcm_substream *substream,
416 struct snd_pcm_hw_params *params,
417 struct snd_soc_dai *dai)
419 u8 tx_fs_rate, rx_fs_rate;
422 dev_err(dai->codec->dev,
423 "%s: dai_name = %s DAI-ID %x rate %d num_ch %d format %d\n",
424 __func__, dai->name, dai->id, params_rate(params),
425 params_channels(params), params_format(params));
427 switch (params_rate(params)) {
453 dev_err(dai->codec->dev,
454 "%s: Invalid sampling rate %d\n", __func__,
455 params_rate(params));
459 switch (substream->stream) {
460 case SNDRV_PCM_STREAM_CAPTURE:
461 snd_soc_update_bits(dai->codec,
462 MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL, 0x07, tx_fs_rate);
463 ret = msm8x16_wcd_set_decimator_rate(dai, tx_fs_rate,
464 params_rate(params));
466 dev_err(dai->codec->dev,
467 "%s: set decimator rate failed %d\n", __func__,
472 case SNDRV_PCM_STREAM_PLAYBACK:
473 ret = msm8x16_wcd_set_interpolator_rate(dai, rx_fs_rate,
474 params_rate(params));
476 dev_err(dai->codec->dev,
477 "%s: set decimator rate failed %d\n", __func__,
483 dev_err(dai->codec->dev,
484 "%s: Invalid stream type %d\n", __func__,
489 switch (params_format(params)) {
490 case SNDRV_PCM_FORMAT_S16_LE:
491 snd_soc_update_bits(dai->codec,
492 MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL, 0x20, 0x20);
493 snd_soc_update_bits(dai->codec,
494 MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL, 0x20, 0x20);
496 case SNDRV_PCM_FORMAT_S24_LE:
497 snd_soc_update_bits(dai->codec,
498 MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL, 0x20, 0x00);
499 snd_soc_update_bits(dai->codec,
500 MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL, 0x20, 0x00);
503 dev_err(dai->dev, "%s: wrong format selected\n",
511 static int msm8x16_wcd_set_dai_sysclk(struct snd_soc_dai *dai,
512 int clk_id, unsigned int freq, int dir)
514 dev_dbg(dai->codec->dev, "%s\n", __func__);
518 static int msm8x16_wcd_set_channel_map(struct snd_soc_dai *dai,
519 unsigned int tx_num, unsigned int *tx_slot,
520 unsigned int rx_num, unsigned int *rx_slot)
523 dev_dbg(dai->codec->dev, "%s\n", __func__);
527 static int msm8x16_wcd_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
529 dev_dbg(dai->codec->dev, "%s\n", __func__);
534 static struct snd_soc_dai_ops msm8x16_wcd_dai_ops = {
535 .startup = msm8x16_wcd_startup,
536 .shutdown = msm8x16_wcd_shutdown,
537 .hw_params = msm8x16_wcd_hw_params,
538 .set_sysclk = msm8x16_wcd_set_dai_sysclk,
539 .set_fmt = msm8x16_wcd_set_dai_fmt,
540 .set_channel_map = msm8x16_wcd_set_channel_map,
543 static struct snd_soc_dai_driver msm8x16_wcd_codec_dai[] = {
545 .name = "msm8x16_wcd_i2s_rx1",
548 .stream_name = "AIF1 Playback",
549 .rates = MSM8X16_WCD_RATES,
550 .formats = MSM8X16_WCD_FORMATS,
556 .ops = &msm8x16_wcd_dai_ops,
559 .name = "msm8x16_wcd_i2s_tx1",
562 .stream_name = "AIF1 Capture",
563 .rates = MSM8X16_WCD_RATES,
564 .formats = MSM8X16_WCD_FORMATS,
570 .ops = &msm8x16_wcd_dai_ops,
574 static int msm8x16_wcd_codec_remove(struct snd_soc_codec *codec)
580 static int msm8x16_wcd_spk_boost_get(struct snd_kcontrol *kcontrol,
581 struct snd_ctl_elem_value *ucontrol)
583 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
584 struct wcd_chip *msm8x16_wcd = dev_get_drvdata(codec->dev);
586 if (msm8x16_wcd->spk_boost_set == false) {
587 ucontrol->value.integer.value[0] = 0;
588 } else if (msm8x16_wcd->spk_boost_set == true) {
589 ucontrol->value.integer.value[0] = 1;
591 dev_err(codec->dev, "%s: ERROR: Unsupported Speaker Boost = %d\n",
592 __func__, msm8x16_wcd->spk_boost_set);
596 dev_dbg(codec->dev, "%s: msm8x16_wcd->spk_boost_set = %d\n", __func__,
597 msm8x16_wcd->spk_boost_set);
601 static int msm8x16_wcd_spk_boost_set(struct snd_kcontrol *kcontrol,
602 struct snd_ctl_elem_value *ucontrol)
604 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
605 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
607 switch (ucontrol->value.integer.value[0]) {
609 msm8x16_wcd->spk_boost_set = false;
612 msm8x16_wcd->spk_boost_set = true;
617 dev_dbg(codec->dev, "%s: msm8x16_wcd->spk_boost_set = %d\n",
618 __func__, msm8x16_wcd->spk_boost_set);
622 static const char * const hph_text[] = {
626 static const struct soc_enum hph_enum =
627 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(hph_text), hph_text);
629 static const struct snd_kcontrol_new hphl_mux[] = {
630 SOC_DAPM_ENUM("HPHL", hph_enum)
633 static const struct snd_kcontrol_new hphr_mux[] = {
634 SOC_DAPM_ENUM("HPHR", hph_enum)
637 static const struct snd_kcontrol_new spkr_switch[] = {
638 SOC_DAPM_SINGLE("Switch",
639 MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 7, 1, 0)
642 static void msm8x16_wcd_codec_enable_adc_block(struct snd_soc_codec *codec,
645 //struct msm8x16_wcd_priv *wcd8x16 = snd_soc_codec_get_drvdata(codec);
647 dev_dbg(codec->dev, "%s %d\n", __func__, enable);
650 //wcd8x16->adc_count++;
651 snd_soc_update_bits(codec,
652 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL,
654 snd_soc_update_bits(codec,
655 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
658 //wcd8x16->adc_count--;
659 //if (!wcd8x16->adc_count) {
660 snd_soc_update_bits(codec,
661 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
663 snd_soc_update_bits(codec,
664 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL,
670 static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
671 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
673 static const char * const rx_mix1_text[] = {
674 "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3"
677 static const char * const rx_mix2_text[] = {
678 "ZERO", "IIR1", "IIR2"
681 static const char * const dec_mux_text[] = {
682 "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2"
685 static const char * const adc2_mux_text[] = {
686 "ZERO", "INP2", "INP3"
689 static const char * const rdac2_mux_text[] = {
693 static const char * const iir_inp1_text[] = {
694 "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3"
697 static const char * const iir1_inp1_text[] = {
698 "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3"
701 static const struct soc_enum adc2_enum =
702 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
705 static const struct soc_enum rx_mix1_inp1_chain_enum =
706 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL,
709 static const struct soc_enum rx_mix1_inp2_chain_enum =
710 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL,
713 static const struct soc_enum rx_mix1_inp3_chain_enum =
714 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B2_CTL,
717 static const struct soc_enum rx_mix2_inp1_chain_enum =
718 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B3_CTL,
722 static const struct soc_enum rx2_mix1_inp1_chain_enum =
723 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL,
726 static const struct soc_enum rx2_mix1_inp2_chain_enum =
727 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL,
730 static const struct soc_enum rx2_mix1_inp3_chain_enum =
731 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL,
735 static const struct soc_enum rx2_mix2_inp1_chain_enum =
736 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B3_CTL,
740 static const struct soc_enum rx3_mix1_inp1_chain_enum =
741 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL,
744 static const struct soc_enum rx3_mix1_inp2_chain_enum =
745 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL,
749 static const struct soc_enum dec1_mux_enum =
750 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_TX_B1_CTL,
753 static const struct soc_enum dec2_mux_enum =
754 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_TX_B1_CTL,
757 static const struct soc_enum rdac2_mux_enum =
758 SOC_ENUM_SINGLE(MSM8X16_WCD_A_DIGITAL_CDC_CONN_HPHR_DAC_CTL,
759 0, 3, rdac2_mux_text);
761 static const struct soc_enum iir1_inp1_mux_enum =
762 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_EQ1_B1_CTL,
763 0, 6, iir_inp1_text);
765 static const struct soc_enum iir2_inp1_mux_enum =
766 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_EQ2_B1_CTL,
767 0, 6, iir_inp1_text);
768 static const struct snd_kcontrol_new iir2_inp1_mux =
769 SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum);
771 static const struct soc_enum rx3_mix1_inp3_chain_enum =
772 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL,
774 static const struct snd_kcontrol_new rx_mix1_inp1_mux =
775 SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum);
777 static const struct snd_kcontrol_new dec1_mux =
778 SOC_DAPM_ENUM("DEC1 MUX Mux", dec1_mux_enum);
780 static const struct snd_kcontrol_new dec2_mux =
781 SOC_DAPM_ENUM("DEC2 MUX Mux", dec2_mux_enum);
783 static const struct snd_kcontrol_new rdac2_mux =
784 SOC_DAPM_ENUM("RDAC2 MUX Mux", rdac2_mux_enum);
786 static const struct snd_kcontrol_new iir1_inp1_mux =
787 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
789 static const struct snd_kcontrol_new rx_mix1_inp2_mux =
790 SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum);
792 static const struct snd_kcontrol_new rx_mix1_inp3_mux =
793 SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum);
795 static const struct snd_kcontrol_new rx2_mix1_inp1_mux =
796 SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum);
798 static const struct snd_kcontrol_new rx2_mix1_inp2_mux =
799 SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum);
801 static const struct snd_kcontrol_new rx2_mix1_inp3_mux =
802 SOC_DAPM_ENUM("RX2 MIX1 INP3 Mux", rx2_mix1_inp3_chain_enum);
804 static const struct snd_kcontrol_new rx3_mix1_inp1_mux =
805 SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum);
807 static const struct snd_kcontrol_new rx3_mix1_inp2_mux =
808 SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum);
810 static const struct snd_kcontrol_new rx3_mix1_inp3_mux =
811 SOC_DAPM_ENUM("RX3 MIX1 INP3 Mux", rx3_mix1_inp3_chain_enum);
813 static const struct snd_kcontrol_new rx1_mix2_inp1_mux =
814 SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum);
816 static const struct snd_kcontrol_new rx2_mix2_inp1_mux =
817 SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
819 static const struct snd_kcontrol_new tx_adc2_mux =
820 SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
822 static const char * const msm8x16_wcd_loopback_mode_ctrl_text[] = {
823 "DISABLE", "ENABLE"};
824 static const struct soc_enum msm8x16_wcd_loopback_mode_ctl_enum[] = {
825 SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_loopback_mode_ctrl_text),
828 static int msm8x16_wcd_codec_enable_on_demand_supply(
829 struct snd_soc_dapm_widget *w,
830 struct snd_kcontrol *kcontrol, int event)
833 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
834 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
837 case SND_SOC_DAPM_PRE_PMU:
838 ret = regulator_enable(msm8x16_wcd->vdd_mic_bias);
840 dev_err(codec->dev, "%s: Failed to enable vdd micbias\n",
843 case SND_SOC_DAPM_POST_PMD:
844 ret = regulator_disable(msm8x16_wcd->vdd_mic_bias);
846 dev_err(codec->dev, "%s: Failed to disable vdd-micbias\n",
856 static const char * const msm8x16_wcd_ear_pa_boost_ctrl_text[] = {
857 "DISABLE", "ENABLE"};
858 static const struct soc_enum msm8x16_wcd_ear_pa_boost_ctl_enum[] = {
859 SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_ear_pa_boost_ctrl_text),
862 static const char * const msm8x16_wcd_ear_pa_gain_text[] = {
863 "POS_6_DB", "POS_1P5_DB"};
864 static const struct soc_enum msm8x16_wcd_ear_pa_gain_enum[] = {
865 SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_ear_pa_gain_text),
868 static const char * const msm8x16_wcd_spk_boost_ctrl_text[] = {
869 "DISABLE", "ENABLE"};
870 static const struct soc_enum msm8x16_wcd_spk_boost_ctl_enum[] = {
871 SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_spk_boost_ctrl_text),
874 /*cut of frequency for high pass filter*/
875 static const char * const cf_text[] = {
876 "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz"
879 static const struct soc_enum cf_dec1_enum =
880 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_TX1_MUX_CTL, 4, 3, cf_text);
882 static const struct soc_enum cf_dec2_enum =
883 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_TX2_MUX_CTL, 4, 3, cf_text);
885 static const struct soc_enum cf_rxmix1_enum =
886 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_RX1_B4_CTL, 0, 3, cf_text);
888 static const struct soc_enum cf_rxmix2_enum =
889 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_RX2_B4_CTL, 0, 3, cf_text);
891 static const struct soc_enum cf_rxmix3_enum =
892 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_RX3_B4_CTL, 0, 3, cf_text);
894 static const struct snd_kcontrol_new msm8x16_wcd_snd_controls[] = {
896 SOC_ENUM_EXT("Speaker Boost", msm8x16_wcd_spk_boost_ctl_enum[0],
897 msm8x16_wcd_spk_boost_get, msm8x16_wcd_spk_boost_set),
899 SOC_SINGLE_TLV("ADC1 Volume", MSM8X16_WCD_A_ANALOG_TX_1_EN, 3,
901 SOC_SINGLE_TLV("ADC2 Volume", MSM8X16_WCD_A_ANALOG_TX_2_EN, 3,
903 SOC_SINGLE_TLV("ADC3 Volume", MSM8X16_WCD_A_ANALOG_TX_3_EN, 3,
906 SOC_SINGLE_SX_TLV("RX1 Digital Volume",
907 MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL,
908 0, -84, 40, digital_gain),
909 SOC_SINGLE_SX_TLV("RX2 Digital Volume",
910 MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL,
911 0, -84, 40, digital_gain),
912 SOC_SINGLE_SX_TLV("RX3 Digital Volume",
913 MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL,
914 0, -84, 40, digital_gain),
916 SOC_SINGLE("RX1 HPF Switch",
917 MSM8X16_WCD_A_CDC_RX1_B5_CTL, 2, 1, 0),
918 SOC_SINGLE("RX2 HPF Switch",
919 MSM8X16_WCD_A_CDC_RX2_B5_CTL, 2, 1, 0),
920 SOC_SINGLE("RX3 HPF Switch",
921 MSM8X16_WCD_A_CDC_RX3_B5_CTL, 2, 1, 0),
923 SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum),
924 SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum),
925 SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum),
928 static const struct snd_kcontrol_new ear_pa_switch[] = {
929 SOC_DAPM_SINGLE("Switch",
930 MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 5, 1, 0)
933 static int msm8x16_wcd_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
934 struct snd_kcontrol *kcontrol, int event)
936 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
937 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
940 case SND_SOC_DAPM_PRE_PMU:
942 "%s: Sleeping 20ms after select EAR PA\n",
944 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
947 case SND_SOC_DAPM_POST_PMU:
949 "%s: Sleeping 20ms after enabling EAR PA\n",
951 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
953 usleep_range(7000, 7100);
954 snd_soc_update_bits(codec,
955 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
957 case SND_SOC_DAPM_PRE_PMD:
958 snd_soc_update_bits(codec,
959 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x01);
961 msm8x16_wcd->mute_mask |= EAR_PA_DISABLE;
963 case SND_SOC_DAPM_POST_PMD:
965 "%s: Sleeping 7ms after disabling EAR PA\n",
967 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
969 usleep_range(7000, 7100);
971 * Reset pa select bit from ear to hph after ear pa
972 * is disabled to reduce ear turn off pop
974 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
981 static int msm8x16_wcd_codec_enable_adc(struct snd_soc_dapm_widget *w,
982 struct snd_kcontrol *kcontrol, int event)
984 //struct snd_soc_codec *codec = w->codec;
985 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
989 dev_dbg(codec->dev, "%s %d\n", __func__, event);
991 adc_reg = MSM8X16_WCD_A_ANALOG_TX_1_2_TEST_CTL_2;
993 if (w->reg == MSM8X16_WCD_A_ANALOG_TX_1_EN)
995 else if ((w->reg == MSM8X16_WCD_A_ANALOG_TX_2_EN) ||
996 (w->reg == MSM8X16_WCD_A_ANALOG_TX_3_EN))
999 dev_err(codec->dev, "%s: Error, invalid adc register\n",
1005 case SND_SOC_DAPM_PRE_PMU:
1006 msm8x16_wcd_codec_enable_adc_block(codec, 1);
1007 if (w->reg == MSM8X16_WCD_A_ANALOG_TX_2_EN)
1008 snd_soc_update_bits(codec,
1009 MSM8X16_WCD_A_ANALOG_MICB_1_CTL, 0x02, 0x02);
1011 * Add delay of 10 ms to give sufficient time for the voltage
1012 * to shoot up and settle so that the txfe init does not
1013 * happen when the input voltage is changing too much.
1015 usleep_range(10000, 10010);
1016 snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift,
1017 1 << init_bit_shift);
1018 if (w->reg == MSM8X16_WCD_A_ANALOG_TX_1_EN)
1019 snd_soc_update_bits(codec,
1020 MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX1_CTL,
1022 else if ((w->reg == MSM8X16_WCD_A_ANALOG_TX_2_EN) ||
1023 (w->reg == MSM8X16_WCD_A_ANALOG_TX_3_EN))
1024 snd_soc_update_bits(codec,
1025 MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX2_CTL,
1027 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1029 case SND_SOC_DAPM_POST_PMU:
1031 * Add delay of 12 ms before deasserting the init
1032 * to reduce the tx pop
1034 usleep_range(12000, 12010);
1035 snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00);
1036 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1038 case SND_SOC_DAPM_POST_PMD:
1039 msm8x16_wcd_codec_enable_adc_block(codec, 0);
1040 if (w->reg == MSM8X16_WCD_A_ANALOG_TX_2_EN)
1041 snd_soc_update_bits(codec,
1042 MSM8X16_WCD_A_ANALOG_MICB_1_CTL, 0x02, 0x00);
1043 if (w->reg == MSM8X16_WCD_A_ANALOG_TX_1_EN)
1044 snd_soc_update_bits(codec,
1045 MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX1_CTL,
1047 else if ((w->reg == MSM8X16_WCD_A_ANALOG_TX_2_EN) ||
1048 (w->reg == MSM8X16_WCD_A_ANALOG_TX_3_EN))
1049 snd_soc_update_bits(codec,
1050 MSM8X16_WCD_A_DIGITAL_CDC_CONN_TX2_CTL,
1058 static int msm8x16_wcd_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
1059 struct snd_kcontrol *kcontrol, int event)
1061 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1062 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1065 case SND_SOC_DAPM_PRE_PMU:
1066 snd_soc_update_bits(codec,
1067 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
1068 snd_soc_update_bits(codec,
1069 MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x01);
1070 if (!msm8x16_wcd->spk_boost_set)
1071 snd_soc_update_bits(codec,
1072 MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x10);
1073 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1074 snd_soc_update_bits(codec,
1075 MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0xE0);
1076 if (!TOMBAK_IS_1_0(msm8x16_wcd->pmic_rev))
1077 snd_soc_update_bits(codec,
1078 MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 0x01, 0x01);
1080 case SND_SOC_DAPM_POST_PMU:
1081 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1082 if (msm8x16_wcd->spk_boost_set)
1083 snd_soc_update_bits(codec,
1084 MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL, 0xEF, 0xEF);
1086 snd_soc_update_bits(codec,
1087 MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x00);
1088 snd_soc_update_bits(codec,
1089 MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0x01, 0x00);
1090 snd_soc_update_bits(codec, w->reg, 0x80, 0x80);
1092 case SND_SOC_DAPM_PRE_PMD:
1093 snd_soc_update_bits(codec,
1094 MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0x01, 0x01);
1096 msm8x16_wcd->mute_mask |= SPKR_PA_DISABLE;
1097 snd_soc_update_bits(codec, w->reg, 0x80, 0x00);
1098 if (msm8x16_wcd->spk_boost_set)
1099 snd_soc_update_bits(codec,
1100 MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL, 0xEF, 0x00);
1102 snd_soc_update_bits(codec,
1103 MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x00);
1105 case SND_SOC_DAPM_POST_PMD:
1106 snd_soc_update_bits(codec,
1107 MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0x00);
1108 if (!TOMBAK_IS_1_0(msm8x16_wcd->pmic_rev))
1109 snd_soc_update_bits(codec,
1110 MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 0x01, 0x00);
1111 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1112 snd_soc_update_bits(codec,
1113 MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x00);
1114 snd_soc_update_bits(codec,
1115 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
1121 static void msm8x16_wcd_micbias_2_enable(struct snd_soc_codec *codec, bool on)
1124 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_MICB_1_CTL,
1126 snd_soc_write(codec, MSM8X16_WCD_A_ANALOG_MICB_1_VAL,
1129 * Special headset needs MICBIAS as 2.7V so wait for
1130 * 50 msec for the MICBIAS to reach 2.7 volts.
1133 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_MICB_1_CTL,
1138 static s32 g_dmic_clk_cnt;
1139 static int msm8x16_wcd_codec_enable_dmic(struct snd_soc_dapm_widget *w,
1140 struct snd_kcontrol *kcontrol, int event)
1142 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1148 char *dec_num = strpbrk(w->name, "12");
1150 if (dec_num == NULL) {
1151 dev_err(codec->dev, "%s: Invalid DMIC\n", __func__);
1155 ret = kstrtouint(dec_num, 10, &dmic);
1158 "%s: Invalid DMIC line on the codec\n", __func__);
1166 dmic_clk_cnt = &g_dmic_clk_cnt;
1167 dmic_clk_reg = MSM8X16_WCD_A_CDC_CLK_DMIC_B1_CTL;
1169 "%s() event %d DMIC%d dmic_1_2_clk_cnt %d\n",
1170 __func__, event, dmic, *dmic_clk_cnt);
1173 dev_err(codec->dev, "%s: Invalid DMIC Selection\n", __func__);
1178 case SND_SOC_DAPM_PRE_PMU:
1180 if (*dmic_clk_cnt == 1) {
1181 snd_soc_update_bits(codec, dmic_clk_reg,
1183 snd_soc_update_bits(codec, dmic_clk_reg,
1184 dmic_clk_en, dmic_clk_en);
1187 snd_soc_update_bits(codec,
1188 MSM8X16_WCD_A_CDC_TX1_DMIC_CTL, 0x07, 0x01);
1190 snd_soc_update_bits(codec,
1191 MSM8X16_WCD_A_CDC_TX2_DMIC_CTL, 0x07, 0x01);
1193 case SND_SOC_DAPM_POST_PMD:
1195 if (*dmic_clk_cnt == 0)
1196 snd_soc_update_bits(codec, dmic_clk_reg,
1203 static int msm8x16_wcd_codec_enable_micbias(struct snd_soc_dapm_widget *w,
1204 struct snd_kcontrol *kcontrol, int event)
1206 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1207 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1209 char *internal1_text = "Internal1";
1210 char *internal2_text = "Internal2";
1211 char *internal3_text = "Internal3";
1212 char *external2_text = "External2";
1213 char *external_text = "External";
1217 case MSM8X16_WCD_A_ANALOG_MICB_1_EN:
1218 case MSM8X16_WCD_A_ANALOG_MICB_2_EN:
1219 micb_int_reg = MSM8X16_WCD_A_ANALOG_MICB_1_INT_RBIAS;
1223 "%s: Error, invalid micbias register 0x%x\n",
1228 micbias2 = (snd_soc_read(codec, MSM8X16_WCD_A_ANALOG_MICB_2_EN) & 0x80);
1231 case SND_SOC_DAPM_PRE_PMU:
1232 if (strnstr(w->name, internal1_text, 30)) {
1233 snd_soc_update_bits(codec, micb_int_reg, 0x80, 0x80);
1234 } else if (strnstr(w->name, internal2_text, 30)) {
1235 snd_soc_update_bits(codec, micb_int_reg, 0x10, 0x10);
1236 snd_soc_update_bits(codec, w->reg, 0x60, 0x00);
1237 } else if (strnstr(w->name, internal3_text, 30)) {
1238 snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x2);
1240 if (!strnstr(w->name, external_text, 30))
1241 snd_soc_update_bits(codec,
1242 MSM8X16_WCD_A_ANALOG_MICB_1_EN, 0x05, 0x04);
1243 if (w->reg == MSM8X16_WCD_A_ANALOG_MICB_1_EN)
1244 msm8x16_wcd_configure_cap(codec, true, micbias2);
1247 case SND_SOC_DAPM_POST_PMU:
1248 usleep_range(20000, 20100);
1249 if (strnstr(w->name, internal1_text, 30)) {
1250 snd_soc_update_bits(codec, micb_int_reg, 0x40, 0x40);
1251 } else if (strnstr(w->name, internal2_text, 30)) {
1252 snd_soc_update_bits(codec, micb_int_reg, 0x08, 0x08);
1253 msm8x16_wcd_micbias_2_enable(codec, true);
1255 msm8x16_wcd_configure_cap(codec, false, true);
1256 regmap_write(msm8x16_wcd->analog_map, 0xf144, 0x95);
1257 } else if (strnstr(w->name, internal3_text, 30)) {
1258 snd_soc_update_bits(codec, micb_int_reg, 0x01, 0x01);
1259 } else if (strnstr(w->name, external2_text, 30)) {
1260 msm8x16_wcd_micbias_2_enable(codec, true);
1263 case SND_SOC_DAPM_POST_PMD:
1264 if (strnstr(w->name, internal1_text, 30)) {
1265 snd_soc_update_bits(codec, micb_int_reg, 0xC0, 0x40);
1266 } else if (strnstr(w->name, internal2_text, 30)) {
1267 msm8x16_wcd_micbias_2_enable(codec, false);
1268 } else if (strnstr(w->name, internal3_text, 30)) {
1269 snd_soc_update_bits(codec, micb_int_reg, 0x2, 0x0);
1270 } else if (strnstr(w->name, external2_text, 30)) {
1272 * send micbias turn off event to mbhc driver and then
1273 * break, as no need to set MICB_1_EN register.
1275 msm8x16_wcd_micbias_2_enable(codec, false);
1278 if (w->reg == MSM8X16_WCD_A_ANALOG_MICB_1_EN)
1279 msm8x16_wcd_configure_cap(codec, false, micbias2);
1286 #define TX_MUX_CTL_CUT_OFF_FREQ_MASK 0x30
1287 #define CF_MIN_3DB_4HZ 0x0
1288 #define CF_MIN_3DB_75HZ 0x1
1289 #define CF_MIN_3DB_150HZ 0x2
1291 static int msm8x16_wcd_codec_enable_dec(struct snd_soc_dapm_widget *w,
1292 struct snd_kcontrol *kcontrol, int event)
1294 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1295 unsigned int decimator;
1296 char *dec_name = NULL;
1297 char *widget_name = NULL;
1300 u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
1301 u8 dec_hpf_cut_of_freq;
1304 dev_dbg(codec->dev, "%s %d\n", __func__, event);
1306 widget_name = kstrndup(w->name, 15, GFP_KERNEL);
1311 dec_name = strsep(&widget_name, " ");
1315 "%s: Invalid decimator = %s\n", __func__, w->name);
1320 dec_num = strpbrk(dec_name, "12");
1321 if (dec_num == NULL) {
1322 dev_err(codec->dev, "%s: Invalid Decimator\n", __func__);
1327 ret = kstrtouint(dec_num, 10, &decimator);
1330 "%s: Invalid decimator = %s\n", __func__, dec_name);
1336 "%s(): widget = %s dec_name = %s decimator = %u\n", __func__,
1337 w->name, dec_name, decimator);
1339 if (w->reg == MSM8X16_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL) {
1340 dec_reset_reg = MSM8X16_WCD_A_CDC_CLK_TX_RESET_B1_CTL;
1343 dev_err(codec->dev, "%s: Error, incorrect dec\n", __func__);
1348 tx_vol_ctl_reg = MSM8X16_WCD_A_CDC_TX1_VOL_CTL_CFG +
1349 32 * (decimator - 1);
1350 tx_mux_ctl_reg = MSM8X16_WCD_A_CDC_TX1_MUX_CTL +
1351 32 * (decimator - 1);
1354 case SND_SOC_DAPM_PRE_PMU:
1355 /* Enableable TX digital mute */
1356 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
1357 dec_hpf_cut_of_freq = snd_soc_read(codec, tx_mux_ctl_reg);
1358 dec_hpf_cut_of_freq = (dec_hpf_cut_of_freq & 0x30) >> 4;
1359 if ((dec_hpf_cut_of_freq != CF_MIN_3DB_150HZ)) {
1361 /* set cut of freq to CF_MIN_3DB_150HZ (0x1); */
1362 snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30,
1363 CF_MIN_3DB_150HZ << 4);
1365 snd_soc_update_bits(codec,
1366 MSM8X16_WCD_A_ANALOG_TX_1_2_TXFE_CLKDIV,
1370 case SND_SOC_DAPM_POST_PMU:
1372 snd_soc_update_bits(codec, tx_mux_ctl_reg , 0x08, 0x00);
1373 /* apply the digital gain after the decimator is enabled*/
1374 if ((w->shift) < ARRAY_SIZE(tx_digital_gain_reg))
1375 snd_soc_write(codec,
1376 tx_digital_gain_reg[w->shift + offset],
1378 tx_digital_gain_reg[w->shift + offset])
1380 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00);
1382 case SND_SOC_DAPM_PRE_PMD:
1383 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01);
1385 snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08);
1387 case SND_SOC_DAPM_POST_PMD:
1388 snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift,
1390 snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, 0x0);
1391 snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08);
1392 snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00);
1401 static int msm8x16_wcd_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
1402 struct snd_kcontrol *kcontrol,
1405 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1406 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1409 case SND_SOC_DAPM_POST_PMU:
1410 /* apply the digital gain after the interpolator is enabled*/
1411 if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg))
1412 snd_soc_write(codec,
1413 rx_digital_gain_reg[w->shift],
1415 rx_digital_gain_reg[w->shift])
1418 case SND_SOC_DAPM_POST_PMD:
1419 snd_soc_update_bits(codec,
1420 MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL,
1421 1 << w->shift, 1 << w->shift);
1422 snd_soc_update_bits(codec,
1423 MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL,
1424 1 << w->shift, 0x0);
1426 * disable the mute enabled during the PMD of this device
1428 if (msm8x16_wcd->mute_mask & HPHL_PA_DISABLE) {
1429 pr_debug("disabling HPHL mute\n");
1430 snd_soc_update_bits(codec,
1431 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
1432 msm8x16_wcd->mute_mask &= ~(HPHL_PA_DISABLE);
1434 if (msm8x16_wcd->mute_mask & HPHR_PA_DISABLE) {
1435 pr_debug("disabling HPHR mute\n");
1436 snd_soc_update_bits(codec,
1437 MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0x01, 0x00);
1438 msm8x16_wcd->mute_mask &= ~(HPHR_PA_DISABLE);
1440 if (msm8x16_wcd->mute_mask & SPKR_PA_DISABLE) {
1441 pr_debug("disabling SPKR mute\n");
1442 snd_soc_update_bits(codec,
1443 MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0x01, 0x00);
1444 msm8x16_wcd->mute_mask &= ~(SPKR_PA_DISABLE);
1446 if (msm8x16_wcd->mute_mask & EAR_PA_DISABLE) {
1447 pr_debug("disabling EAR mute\n");
1448 snd_soc_update_bits(codec,
1449 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
1450 msm8x16_wcd->mute_mask &= ~(EAR_PA_DISABLE);
1456 static int msm8x16_wcd_codec_enable_dig_clk(struct snd_soc_dapm_widget *w,
1457 struct snd_kcontrol *kcontrol, int event)
1459 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1460 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1463 case SND_SOC_DAPM_PRE_PMU:
1465 snd_soc_update_bits(codec, w->reg, 0x80, 0x80);
1466 if (msm8x16_wcd->spk_boost_set) {
1467 snd_soc_update_bits(codec,
1468 MSM8X16_WCD_A_ANALOG_SEC_ACCESS,
1470 snd_soc_update_bits(codec,
1471 MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3,
1473 snd_soc_update_bits(codec,
1474 MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT,
1476 snd_soc_update_bits(codec,
1477 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1479 snd_soc_update_bits(codec,
1480 MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
1482 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1483 snd_soc_update_bits(codec,
1484 MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT,
1486 } else if (msm8x16_wcd->ear_pa_boost_set) {
1487 snd_soc_update_bits(codec,
1488 MSM8X16_WCD_A_ANALOG_SEC_ACCESS,
1490 snd_soc_update_bits(codec,
1491 MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3,
1493 snd_soc_update_bits(codec,
1494 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1496 snd_soc_update_bits(codec,
1497 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1499 snd_soc_update_bits(codec,
1500 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1502 snd_soc_update_bits(codec,
1503 MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
1506 snd_soc_update_bits(codec, w->reg, 1<<w->shift,
1510 case SND_SOC_DAPM_POST_PMD:
1511 if (msm8x16_wcd->spk_boost_set) {
1512 snd_soc_update_bits(codec,
1513 MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
1515 snd_soc_update_bits(codec,
1516 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1518 } else if (msm8x16_wcd->ear_pa_boost_set) {
1519 snd_soc_update_bits(codec,
1520 MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
1522 snd_soc_update_bits(codec,
1523 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1525 snd_soc_update_bits(codec,
1526 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1528 snd_soc_update_bits(codec,
1529 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1532 snd_soc_update_bits(codec, w->reg, 1<<w->shift, 0x00);
1539 static int msm8x16_wcd_codec_enable_rx_chain(struct snd_soc_dapm_widget *w,
1540 struct snd_kcontrol *kcontrol, int event)
1542 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1545 case SND_SOC_DAPM_POST_PMU:
1546 snd_soc_update_bits(codec,
1547 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1550 "%s: PMU:Sleeping 20ms after disabling mute\n",
1553 case SND_SOC_DAPM_POST_PMD:
1554 snd_soc_update_bits(codec,
1555 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1558 "%s: PMD:Sleeping 20ms after disabling mute\n",
1560 snd_soc_update_bits(codec, w->reg,
1561 1 << w->shift, 0x00);
1568 static int msm8x16_wcd_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
1569 struct snd_kcontrol *kcontrol, int event)
1571 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1572 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1575 case SND_SOC_DAPM_PRE_PMU:
1576 msm8x16_wcd->rx_bias_count++;
1577 if (msm8x16_wcd->rx_bias_count == 1)
1578 snd_soc_update_bits(codec,
1579 MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC,
1582 case SND_SOC_DAPM_POST_PMD:
1583 msm8x16_wcd->rx_bias_count--;
1584 if (msm8x16_wcd->rx_bias_count == 0)
1585 snd_soc_update_bits(codec,
1586 MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC,
1590 dev_dbg(codec->dev, "%s rx_bias_count = %d\n",
1591 __func__, msm8x16_wcd->rx_bias_count);
1595 static int msm8x16_wcd_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
1596 struct snd_kcontrol *kcontrol, int event)
1598 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1599 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1602 case SND_SOC_DAPM_PRE_PMU:
1603 if (!(strcmp(w->name, "EAR CP")))
1604 snd_soc_update_bits(codec,
1605 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1608 snd_soc_update_bits(codec,
1609 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1612 case SND_SOC_DAPM_POST_PMU:
1613 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1615 case SND_SOC_DAPM_POST_PMD:
1616 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1617 if (!(strcmp(w->name, "EAR CP")))
1618 snd_soc_update_bits(codec,
1619 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1622 snd_soc_update_bits(codec,
1623 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1625 if (msm8x16_wcd->rx_bias_count == 0)
1626 snd_soc_update_bits(codec,
1627 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1629 dev_dbg(codec->dev, "%s: rx_bias_count = %d\n",
1630 __func__, msm8x16_wcd->rx_bias_count);
1637 static int msm8x16_wcd_hphl_dac_event(struct snd_soc_dapm_widget *w,
1638 struct snd_kcontrol *kcontrol, int event)
1640 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1643 case SND_SOC_DAPM_PRE_PMU:
1644 snd_soc_update_bits(codec,
1645 MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x02);
1646 snd_soc_update_bits(codec,
1647 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
1648 snd_soc_update_bits(codec,
1649 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
1651 case SND_SOC_DAPM_POST_PMU:
1652 snd_soc_update_bits(codec,
1653 MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x00);
1655 case SND_SOC_DAPM_POST_PMD:
1656 snd_soc_update_bits(codec,
1657 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
1658 snd_soc_update_bits(codec,
1659 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
1665 static int msm8x16_wcd_hph_pa_event(struct snd_soc_dapm_widget *w,
1666 struct snd_kcontrol *kcontrol, int event)
1668 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1669 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1672 case SND_SOC_DAPM_PRE_PMU:
1673 if (w->shift == 5) {
1674 snd_soc_update_bits(codec,
1675 MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST, 0x04, 0x04);
1676 } else if (w->shift == 4) {
1677 snd_soc_update_bits(codec,
1678 MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST, 0x04, 0x04);
1680 snd_soc_update_bits(codec,
1681 MSM8X16_WCD_A_ANALOG_NCP_FBCTRL, 0x20, 0x20);
1684 case SND_SOC_DAPM_POST_PMU:
1685 usleep_range(4000, 4100);
1687 snd_soc_update_bits(codec,
1688 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
1689 else if (w->shift == 4)
1690 snd_soc_update_bits(codec,
1691 MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0x01, 0x00);
1692 usleep_range(10000, 10100);
1695 case SND_SOC_DAPM_PRE_PMD:
1696 if (w->shift == 5) {
1697 snd_soc_update_bits(codec,
1698 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x01);
1700 msm8x16_wcd->mute_mask |= HPHL_PA_DISABLE;
1701 } else if (w->shift == 4) {
1702 snd_soc_update_bits(codec,
1703 MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0x01, 0x01);
1705 msm8x16_wcd->mute_mask |= HPHR_PA_DISABLE;
1708 case SND_SOC_DAPM_POST_PMD:
1709 if (w->shift == 5) {
1710 snd_soc_update_bits(codec,
1711 MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST, 0x04, 0x00);
1713 } else if (w->shift == 4) {
1714 snd_soc_update_bits(codec,
1715 MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST, 0x04, 0x00);
1717 usleep_range(4000, 4100);
1719 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1720 snd_soc_update_bits(codec,
1721 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
1723 "%s: sleep 10 ms after %s PA disable.\n", __func__,
1725 usleep_range(10000, 10100);
1731 static const struct snd_soc_dapm_route audio_map[] = {
1732 {"RX_I2S_CLK", NULL, "CDC_CONN"},
1733 {"I2S RX1", NULL, "RX_I2S_CLK"},
1734 {"I2S RX2", NULL, "RX_I2S_CLK"},
1735 {"I2S RX3", NULL, "RX_I2S_CLK"},
1737 {"I2S TX1", NULL, "TX_I2S_CLK"},
1738 {"I2S TX2", NULL, "TX_I2S_CLK"},
1740 {"I2S TX1", NULL, "DEC1 MUX"},
1741 {"I2S TX2", NULL, "DEC2 MUX"},
1743 /* RDAC Connections */
1744 {"HPHR DAC", NULL, "RDAC2 MUX"},
1745 {"RDAC2 MUX", "RX1", "RX1 CHAIN"},
1746 {"RDAC2 MUX", "RX2", "RX2 CHAIN"},
1748 /* Earpiece (RX MIX1) */
1749 {"EAR", NULL, "EAR_S"},
1750 {"EAR_S", "Switch", "EAR PA"},
1751 {"EAR PA", NULL, "RX_BIAS"},
1752 {"EAR PA", NULL, "HPHL DAC"},
1753 {"EAR PA", NULL, "HPHR DAC"},
1754 {"EAR PA", NULL, "EAR CP"},
1756 /* Headset (RX MIX1 and RX MIX2) */
1757 {"HEADPHONE", NULL, "HPHL PA"},
1758 {"HEADPHONE", NULL, "HPHR PA"},
1760 {"HPHL PA", NULL, "HPHL"},
1761 {"HPHR PA", NULL, "HPHR"},
1762 {"HPHL", "Switch", "HPHL DAC"},
1763 {"HPHR", "Switch", "HPHR DAC"},
1764 {"HPHL PA", NULL, "CP"},
1765 {"HPHL PA", NULL, "RX_BIAS"},
1766 {"HPHR PA", NULL, "CP"},
1767 {"HPHR PA", NULL, "RX_BIAS"},
1768 {"HPHL DAC", NULL, "RX1 CHAIN"},
1770 {"SPK_OUT", NULL, "SPK PA"},
1771 {"SPK PA", NULL, "SPK_RX_BIAS"},
1772 {"SPK PA", NULL, "SPK DAC"},
1773 {"SPK DAC", "Switch", "RX3 CHAIN"},
1774 {"SPK DAC", NULL, "VDD_SPKDRV"},
1776 {"RX1 CHAIN", NULL, "RX1 CLK"},
1777 {"RX2 CHAIN", NULL, "RX2 CLK"},
1778 {"RX3 CHAIN", NULL, "RX3 CLK"},
1779 {"RX1 CHAIN", NULL, "RX1 MIX2"},
1780 {"RX2 CHAIN", NULL, "RX2 MIX2"},
1781 {"RX3 CHAIN", NULL, "RX3 MIX1"},
1783 {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
1784 {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
1785 {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
1786 {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
1787 {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
1788 {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
1789 {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
1790 {"RX1 MIX2", NULL, "RX1 MIX1"},
1791 {"RX1 MIX2", NULL, "RX1 MIX2 INP1"},
1792 {"RX2 MIX2", NULL, "RX2 MIX1"},
1793 {"RX2 MIX2", NULL, "RX2 MIX2 INP1"},
1795 {"RX1 MIX1 INP1", "RX1", "I2S RX1"},
1796 {"RX1 MIX1 INP1", "RX2", "I2S RX2"},
1797 {"RX1 MIX1 INP1", "RX3", "I2S RX3"},
1798 {"RX1 MIX1 INP1", "IIR1", "IIR1"},
1799 {"RX1 MIX1 INP1", "IIR2", "IIR2"},
1800 {"RX1 MIX1 INP2", "RX1", "I2S RX1"},
1801 {"RX1 MIX1 INP2", "RX2", "I2S RX2"},
1802 {"RX1 MIX1 INP2", "RX3", "I2S RX3"},
1803 {"RX1 MIX1 INP2", "IIR1", "IIR1"},
1804 {"RX1 MIX1 INP2", "IIR2", "IIR2"},
1805 {"RX1 MIX1 INP3", "RX1", "I2S RX1"},
1806 {"RX1 MIX1 INP3", "RX2", "I2S RX2"},
1807 {"RX1 MIX1 INP3", "RX3", "I2S RX3"},
1809 {"RX2 MIX1 INP1", "RX1", "I2S RX1"},
1810 {"RX2 MIX1 INP1", "RX2", "I2S RX2"},
1811 {"RX2 MIX1 INP1", "RX3", "I2S RX3"},
1812 {"RX2 MIX1 INP1", "IIR1", "IIR1"},
1813 {"RX2 MIX1 INP1", "IIR2", "IIR2"},
1814 {"RX2 MIX1 INP2", "RX1", "I2S RX1"},
1815 {"RX2 MIX1 INP2", "RX2", "I2S RX2"},
1816 {"RX2 MIX1 INP2", "RX3", "I2S RX3"},
1817 {"RX2 MIX1 INP2", "IIR1", "IIR1"},
1818 {"RX2 MIX1 INP2", "IIR2", "IIR2"},
1820 {"RX3 MIX1 INP1", "RX1", "I2S RX1"},
1821 {"RX3 MIX1 INP1", "RX2", "I2S RX2"},
1822 {"RX3 MIX1 INP1", "RX3", "I2S RX3"},
1823 {"RX3 MIX1 INP1", "IIR1", "IIR1"},
1824 {"RX3 MIX1 INP1", "IIR2", "IIR2"},
1825 {"RX3 MIX1 INP2", "RX1", "I2S RX1"},
1826 {"RX3 MIX1 INP2", "RX2", "I2S RX2"},
1827 {"RX3 MIX1 INP2", "RX3", "I2S RX3"},
1828 {"RX3 MIX1 INP2", "IIR1", "IIR1"},
1829 {"RX3 MIX1 INP2", "IIR2", "IIR2"},
1831 {"RX1 MIX2 INP1", "IIR1", "IIR1"},
1832 {"RX2 MIX2 INP1", "IIR1", "IIR1"},
1833 {"RX1 MIX2 INP1", "IIR2", "IIR2"},
1834 {"RX2 MIX2 INP1", "IIR2", "IIR2"},
1836 /* Decimator Inputs */
1837 {"DEC1 MUX", "DMIC1", "DMIC1"},
1838 {"DEC1 MUX", "DMIC2", "DMIC2"},
1839 {"DEC1 MUX", "ADC1", "ADC1"},
1840 {"DEC1 MUX", "ADC2", "ADC2"},
1841 {"DEC1 MUX", "ADC3", "ADC3"},
1842 {"DEC1 MUX", NULL, "CDC_CONN"},
1844 {"DEC2 MUX", "DMIC1", "DMIC1"},
1845 {"DEC2 MUX", "DMIC2", "DMIC2"},
1846 {"DEC2 MUX", "ADC1", "ADC1"},
1847 {"DEC2 MUX", "ADC2", "ADC2"},
1848 {"DEC2 MUX", "ADC3", "ADC3"},
1849 {"DEC2 MUX", NULL, "CDC_CONN"},
1851 /* ADC Connections */
1852 {"ADC2", NULL, "ADC2 MUX"},
1853 {"ADC3", NULL, "ADC2 MUX"},
1854 {"ADC2 MUX", "INP2", "ADC2_INP2"},
1855 {"ADC2 MUX", "INP3", "ADC2_INP3"},
1857 {"ADC1", NULL, "AMIC1"},
1858 {"ADC2_INP2", NULL, "AMIC2"},
1859 {"ADC2_INP3", NULL, "AMIC3"},
1861 /* TODO: Fix this */
1862 {"IIR1", NULL, "IIR1 INP1 MUX"},
1863 {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
1864 {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
1865 {"IIR2", NULL, "IIR2 INP1 MUX"},
1866 {"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"},
1867 {"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"},
1868 {"MIC BIAS Internal1", NULL, "INT_LDO_H"},
1869 {"MIC BIAS Internal2", NULL, "INT_LDO_H"},
1870 {"MIC BIAS External", NULL, "INT_LDO_H"},
1871 {"MIC BIAS External2", NULL, "INT_LDO_H"},
1872 {"MIC BIAS Internal1", NULL, "MICBIAS_REGULATOR"},
1873 {"MIC BIAS Internal2", NULL, "MICBIAS_REGULATOR"},
1874 {"MIC BIAS External", NULL, "MICBIAS_REGULATOR"},
1875 {"MIC BIAS External2", NULL, "MICBIAS_REGULATOR"},
1878 static int msm8x16_wcd_hphr_dac_event(struct snd_soc_dapm_widget *w,
1879 struct snd_kcontrol *kcontrol, int event)
1881 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1884 case SND_SOC_DAPM_PRE_PMU:
1885 snd_soc_update_bits(codec,
1886 MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x02);
1887 snd_soc_update_bits(codec,
1888 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
1889 snd_soc_update_bits(codec,
1890 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
1892 case SND_SOC_DAPM_POST_PMU:
1893 snd_soc_update_bits(codec,
1894 MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x00);
1896 case SND_SOC_DAPM_POST_PMD:
1897 snd_soc_update_bits(codec,
1898 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
1899 snd_soc_update_bits(codec,
1900 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x00);
1906 static const struct snd_soc_dapm_widget msm8x16_wcd_dapm_widgets[] = {
1908 SND_SOC_DAPM_OUTPUT("EAR"),
1910 SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM,
1911 0, 0, NULL, 0, msm8x16_wcd_codec_enable_ear_pa,
1912 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1913 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1914 SND_SOC_DAPM_MIXER("EAR_S", SND_SOC_NOPM, 0, 0,
1915 ear_pa_switch, ARRAY_SIZE(ear_pa_switch)),
1917 SND_SOC_DAPM_AIF_IN("I2S RX1", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1919 SND_SOC_DAPM_AIF_IN("I2S RX2", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1921 SND_SOC_DAPM_AIF_IN("I2S RX3", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1923 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
1925 SND_SOC_DAPM_OUTPUT("HEADPHONE"),
1926 SND_SOC_DAPM_PGA_E("HPHL PA", MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN,
1928 msm8x16_wcd_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
1929 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
1930 SND_SOC_DAPM_POST_PMD),
1932 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, hphl_mux),
1934 SND_SOC_DAPM_MIXER_E("HPHL DAC",
1935 MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
1936 0, msm8x16_wcd_hphl_dac_event,
1937 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1938 SND_SOC_DAPM_POST_PMD),
1940 SND_SOC_DAPM_PGA_E("HPHR PA", MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN,
1942 msm8x16_wcd_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
1943 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
1944 SND_SOC_DAPM_POST_PMD),
1945 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, hphr_mux),
1947 SND_SOC_DAPM_MIXER_E("HPHR DAC",
1948 MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
1949 0, msm8x16_wcd_hphr_dac_event,
1950 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1951 SND_SOC_DAPM_POST_PMD),
1953 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
1954 spkr_switch, ARRAY_SIZE(spkr_switch)),
1957 SND_SOC_DAPM_OUTPUT("SPK_OUT"),
1959 SND_SOC_DAPM_PGA_E("SPK PA", MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL,
1960 6, 0, NULL, 0, msm8x16_wcd_codec_enable_spk_pa,
1961 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1962 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1964 SND_SOC_DAPM_MIXER_E("RX1 MIX1",
1965 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL, 0,
1966 msm8x16_wcd_codec_enable_interpolator,
1967 SND_SOC_DAPM_PRE_REG|
1968 SND_SOC_DAPM_POST_PMU |
1969 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD|
1970 SND_SOC_DAPM_POST_PMD),
1972 SND_SOC_DAPM_MIXER_E("RX2 MIX1",
1973 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL, 0,
1974 msm8x16_wcd_codec_enable_interpolator,
1975 SND_SOC_DAPM_PRE_REG|
1976 SND_SOC_DAPM_POST_PMU |
1977 SND_SOC_DAPM_POST_PMD),
1979 SND_SOC_DAPM_MIXER_E("RX1 MIX2",
1980 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
1981 0, msm8x16_wcd_codec_enable_interpolator,
1982 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1983 SND_SOC_DAPM_MIXER_E("RX2 MIX2",
1984 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
1985 0, msm8x16_wcd_codec_enable_interpolator,
1986 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1987 SND_SOC_DAPM_MIXER_E("RX3 MIX1",
1988 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
1989 0, msm8x16_wcd_codec_enable_interpolator,
1990 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1992 SND_SOC_DAPM_SUPPLY("RX1 CLK", MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1994 SND_SOC_DAPM_SUPPLY("RX2 CLK", MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1996 SND_SOC_DAPM_SUPPLY("RX3 CLK", MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1997 2, 0, msm8x16_wcd_codec_enable_dig_clk, SND_SOC_DAPM_PRE_PMU |
1998 SND_SOC_DAPM_POST_PMD),
1999 SND_SOC_DAPM_MIXER_E("RX1 CHAIN", MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0, 0,
2001 msm8x16_wcd_codec_enable_rx_chain,
2002 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2003 SND_SOC_DAPM_MIXER_E("RX2 CHAIN", MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0, 0,
2005 msm8x16_wcd_codec_enable_rx_chain,
2006 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2007 SND_SOC_DAPM_MIXER_E("RX3 CHAIN", MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0, 0,
2009 msm8x16_wcd_codec_enable_rx_chain,
2010 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2012 SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
2014 SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
2016 SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
2019 SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
2020 &rx2_mix1_inp1_mux),
2021 SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
2022 &rx2_mix1_inp2_mux),
2023 SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0,
2024 &rx2_mix1_inp3_mux),
2026 SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
2027 &rx3_mix1_inp1_mux),
2028 SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
2029 &rx3_mix1_inp2_mux),
2030 SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0,
2031 &rx3_mix1_inp3_mux),
2033 SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
2034 &rx1_mix2_inp1_mux),
2035 SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
2036 &rx2_mix2_inp1_mux),
2038 SND_SOC_DAPM_SUPPLY("MICBIAS_REGULATOR", SND_SOC_NOPM,
2039 ON_DEMAND_MICBIAS, 0,
2040 msm8x16_wcd_codec_enable_on_demand_supply,
2041 SND_SOC_DAPM_PRE_PMU |
2042 SND_SOC_DAPM_POST_PMD),
2044 SND_SOC_DAPM_SUPPLY("CP", MSM8X16_WCD_A_ANALOG_NCP_EN, 0, 0,
2045 msm8x16_wcd_codec_enable_charge_pump, SND_SOC_DAPM_PRE_PMU |
2046 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2048 SND_SOC_DAPM_SUPPLY("EAR CP", MSM8X16_WCD_A_ANALOG_NCP_EN, 4, 0,
2049 msm8x16_wcd_codec_enable_charge_pump, SND_SOC_DAPM_PRE_PMU |
2050 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2052 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM,
2053 0, 0, msm8x16_wcd_codec_enable_rx_bias,
2054 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2056 SND_SOC_DAPM_SUPPLY("SPK_RX_BIAS", SND_SOC_NOPM, 0, 0,
2057 msm8x16_wcd_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
2058 SND_SOC_DAPM_POST_PMD),
2062 SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, MSM8X16_WCD_A_CDC_CLK_OTHR_CTL,
2065 SND_SOC_DAPM_INPUT("AMIC1"),
2066 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1",
2067 MSM8X16_WCD_A_ANALOG_MICB_1_EN, 7, 0,
2068 msm8x16_wcd_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
2069 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2070 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2",
2071 MSM8X16_WCD_A_ANALOG_MICB_2_EN, 7, 0,
2072 msm8x16_wcd_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
2073 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2074 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal3",
2075 MSM8X16_WCD_A_ANALOG_MICB_1_EN, 7, 0,
2076 msm8x16_wcd_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
2077 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2078 SND_SOC_DAPM_ADC_E("ADC1", NULL, MSM8X16_WCD_A_ANALOG_TX_1_EN, 7, 0,
2079 msm8x16_wcd_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
2080 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2081 SND_SOC_DAPM_ADC_E("ADC2_INP2",
2082 NULL, MSM8X16_WCD_A_ANALOG_TX_2_EN, 7, 0,
2083 msm8x16_wcd_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
2084 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2085 SND_SOC_DAPM_ADC_E("ADC2_INP3",
2086 NULL, MSM8X16_WCD_A_ANALOG_TX_3_EN, 7, 0,
2087 msm8x16_wcd_codec_enable_adc, SND_SOC_DAPM_PRE_PMU |
2088 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2090 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2091 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2093 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0,
2096 SND_SOC_DAPM_SUPPLY("MIC BIAS External",
2097 MSM8X16_WCD_A_ANALOG_MICB_1_EN, 7, 0,
2098 msm8x16_wcd_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
2099 SND_SOC_DAPM_POST_PMD),
2101 SND_SOC_DAPM_SUPPLY("MIC BIAS External2",
2102 MSM8X16_WCD_A_ANALOG_MICB_2_EN, 7, 0,
2103 msm8x16_wcd_codec_enable_micbias, SND_SOC_DAPM_POST_PMU |
2104 SND_SOC_DAPM_POST_PMD),
2107 SND_SOC_DAPM_INPUT("AMIC3"),
2109 SND_SOC_DAPM_MUX_E("DEC1 MUX",
2110 MSM8X16_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
2111 &dec1_mux, msm8x16_wcd_codec_enable_dec,
2112 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2113 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2115 SND_SOC_DAPM_MUX_E("DEC2 MUX",
2116 MSM8X16_WCD_A_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
2117 &dec2_mux, msm8x16_wcd_codec_enable_dec,
2118 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2119 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2121 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
2123 SND_SOC_DAPM_INPUT("AMIC2"),
2125 SND_SOC_DAPM_AIF_OUT("I2S TX1", "AIF1 Capture", 0, SND_SOC_NOPM,
2127 SND_SOC_DAPM_AIF_OUT("I2S TX2", "AIF1 Capture", 0, SND_SOC_NOPM,
2129 SND_SOC_DAPM_AIF_OUT("I2S TX3", "AIF1 Capture", 0, SND_SOC_NOPM,
2133 /* Digital Mic Inputs */
2134 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
2135 msm8x16_wcd_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
2136 SND_SOC_DAPM_POST_PMD),
2138 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
2139 msm8x16_wcd_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
2140 SND_SOC_DAPM_POST_PMD),
2143 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
2144 SND_SOC_DAPM_PGA("IIR1",
2145 MSM8X16_WCD_A_CDC_CLK_SD_CTL, 0, 0, NULL, 0),
2147 SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux),
2148 SND_SOC_DAPM_PGA("IIR2",
2149 MSM8X16_WCD_A_CDC_CLK_SD_CTL, 1, 0, NULL, 0),
2151 SND_SOC_DAPM_SUPPLY("RX_I2S_CLK",
2152 MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL, 4, 0, NULL, 0),
2153 SND_SOC_DAPM_SUPPLY("TX_I2S_CLK",
2154 MSM8X16_WCD_A_CDC_CLK_TX_I2S_CTL, 4, 0,
2158 static struct snd_soc_codec_driver msm8x16_wcd_codec = {
2159 .probe = msm8x16_wcd_codec_probe,
2160 .remove = msm8x16_wcd_codec_remove,
2161 .read = msm8x16_wcd_read,
2162 .write = msm8x16_wcd_write,
2163 .reg_cache_size = MSM8X16_WCD_CACHE_SIZE,
2164 .reg_cache_default = msm8x16_wcd_reset_reg_defaults,
2166 .controls = msm8x16_wcd_snd_controls,
2167 .num_controls = ARRAY_SIZE(msm8x16_wcd_snd_controls),
2168 .dapm_widgets = msm8x16_wcd_dapm_widgets,
2169 .num_dapm_widgets = ARRAY_SIZE(msm8x16_wcd_dapm_widgets),
2170 .dapm_routes = audio_map,
2171 .num_dapm_routes = ARRAY_SIZE(audio_map),
2174 static int msm8x16_wcd_codec_parse_dt(struct platform_device *pdev,
2175 struct wcd_chip *chip)
2177 struct device *dev = &pdev->dev;
2178 struct device_node *np = dev->of_node;
2182 ret = of_property_read_u32_array(np, "reg", res, 2);
2186 chip->analog_base = res[0];
2188 chip->digital_map = syscon_regmap_lookup_by_phandle(np, "digital");
2189 if (IS_ERR(chip->digital_map))
2190 return PTR_ERR(chip->digital_map);
2192 chip->vddio = devm_regulator_get(dev, "vddio");
2193 if (IS_ERR(chip->vddio)) {
2194 dev_err(dev, "Failed to get vdd supply\n");
2195 return PTR_ERR(chip->vddio);
2198 chip->vdd_pa = devm_regulator_get(dev, "vdd-pa");
2199 if (IS_ERR(chip->vdd_pa)) {
2200 dev_err(dev, "Failed to get vdd supply\n");
2201 return PTR_ERR(chip->vdd_pa);
2204 chip->vdd_mic_bias = devm_regulator_get(dev, "vdd-mic-bias");
2205 if (IS_ERR(chip->vdd_mic_bias)) {
2206 dev_err(dev, "Failed to get vdd micbias supply\n");
2207 return PTR_ERR(chip->vdd_mic_bias);
2210 chip->mclk = devm_clk_get(dev, "mclk");
2215 static int wcd_probe(struct platform_device *pdev)
2217 struct wcd_chip *chip;
2218 struct device *dev = &pdev->dev;
2221 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
2225 chip->analog_map = dev_get_regmap(dev->parent, NULL);
2226 if (!chip->analog_map)
2229 ret = msm8x16_wcd_codec_parse_dt(pdev, chip);
2230 if (IS_ERR_VALUE(ret))
2233 clk_set_rate(chip->mclk, 9600000);
2234 clk_prepare_enable(chip->mclk);
2236 dev_set_drvdata(dev, chip);
2238 return snd_soc_register_codec(dev, &msm8x16_wcd_codec,
2239 msm8x16_wcd_codec_dai,
2240 ARRAY_SIZE(msm8x16_wcd_codec_dai));
2243 static int wcd_remove(struct platform_device *pdev)
2245 snd_soc_unregister_codec(&pdev->dev);
2250 static const struct of_device_id wcd_match_table[] = {
2251 { .compatible = "qcom,apq8016-wcd-codec" },
2252 { .compatible = "qcom,msm8x16-wcd-codec" },
2255 MODULE_DEVICE_TABLE(of, wcd_match_table);
2257 static struct platform_driver wcd_driver = {
2259 .name = "msm8x16-wcd-codec",
2260 .of_match_table = wcd_match_table,
2263 .remove = wcd_remove,
2265 module_platform_driver(wcd_driver);
2267 MODULE_ALIAS("platform:spmi-wcd-codec");
2268 MODULE_DESCRIPTION("SPMI PMIC WCD codec driver");
2269 MODULE_LICENSE("GPL v2");