1 #include <linux/delay.h>
3 #include <linux/interrupt.h>
4 #include <linux/module.h>
5 #include <linux/regulator/consumer.h>
6 #include <linux/types.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include <linux/mfd/syscon.h>
15 #include <sound/soc.h>
16 #include <sound/soc-dapm.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/tlv.h>
21 #include "msm8x16-wcd.h"
22 #include "msm8x16_wcd_registers.h"
24 #define MSM8X16_WCD_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
25 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
26 #define MSM8X16_WCD_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
27 SNDRV_PCM_FMTBIT_S24_LE)
30 #define TOMBAK_VERSION_1_0 0
31 #define TOMBAK_IS_1_0(ver) \
32 ((ver == TOMBAK_VERSION_1_0) ? 1 : 0)
34 #define HPHL_PA_DISABLE (0x01 << 1)
35 #define HPHR_PA_DISABLE (0x01 << 2)
36 #define EAR_PA_DISABLE (0x01 << 3)
37 #define SPKR_PA_DISABLE (0x01 << 4)
45 static unsigned long rx_digital_gain_reg[] = {
46 MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL,
47 MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL,
48 MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL,
52 struct regmap *analog_map;
53 struct regmap *digital_map;
54 unsigned int analog_base;
60 bool ear_pa_boost_set;
64 struct regulator *vddio;
65 struct regulator *vdd_pa;
66 struct regulator *vdd_px;
67 struct regulator *vdd_cp;
71 static int msm8x16_wcd_volatile(struct snd_soc_codec *codec, unsigned int reg)
73 return msm8x16_wcd_reg_readonly[reg];
76 static int msm8x16_wcd_readable(struct snd_soc_codec *ssc, unsigned int reg)
78 return msm8x16_wcd_reg_readable[reg];
81 static int __msm8x16_wcd_reg_write(struct snd_soc_codec *codec,
82 unsigned short reg, u8 val)
85 struct wcd_chip *chip = dev_get_drvdata(codec->dev);
87 if (MSM8X16_WCD_IS_TOMBAK_REG(reg)) {
88 ret = regmap_write(chip->analog_map,
89 chip->analog_base + reg, val);
90 } else if (MSM8X16_WCD_IS_DIGITAL_REG(reg)) {
91 u32 temp = val & 0x000000FF;
92 u16 offset = (reg ^ 0x0200) & 0x0FFF;
94 ret = regmap_write(chip->digital_map, offset, temp);
100 static int msm8x16_wcd_write(struct snd_soc_codec *codec, unsigned int reg,
103 if (reg == SND_SOC_NOPM)
106 BUG_ON(reg > MSM8X16_WCD_MAX_REGISTER);
107 if (!msm8x16_wcd_volatile(codec, reg))
108 msm8x16_wcd_reset_reg_defaults[reg] = value;
110 return __msm8x16_wcd_reg_write(codec, reg, (u8)value);
113 static int __msm8x16_wcd_reg_read(struct snd_soc_codec *codec,
118 struct wcd_chip *chip = dev_get_drvdata(codec->dev);
120 if (MSM8X16_WCD_IS_TOMBAK_REG(reg)) {
121 ret = regmap_read(chip->analog_map,
122 chip->analog_base + reg, &temp);
123 } else if (MSM8X16_WCD_IS_DIGITAL_REG(reg)) {
125 u16 offset = (reg ^ 0x0200) & 0x0FFF;
127 ret = regmap_read(chip->digital_map, offset, &val);
133 "%s: codec read failed for reg 0x%x\n",
138 dev_dbg(codec->dev, "Read 0x%02x from 0x%x\n", temp, reg);
144 static unsigned int msm8x16_wcd_read(struct snd_soc_codec *codec,
149 if (reg == SND_SOC_NOPM)
152 BUG_ON(reg > MSM8X16_WCD_MAX_REGISTER);
154 if (!msm8x16_wcd_volatile(codec, reg) &&
155 msm8x16_wcd_readable(codec, reg) &&
156 reg < codec->driver->reg_cache_size) {
157 return msm8x16_wcd_reset_reg_defaults[reg];
160 val = __msm8x16_wcd_reg_read(codec, reg);
165 static const struct msm8x16_wcd_reg_mask_val msm8x16_wcd_reg_defaults[] = {
166 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x03),
167 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT, 0x82),
168 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL, 0xE1),
171 static const struct msm8x16_wcd_reg_mask_val msm8x16_wcd_reg_defaults_2_0[] = {
172 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL3, 0x0F),
173 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_TX_1_2_OPAMP_BIAS, 0x4B),
174 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_NCP_FBCTRL, 0x28),
175 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL, 0x69),
176 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DRV_DBG, 0x01),
177 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL, 0x5F),
178 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SLOPE_COMP_IP_ZERO, 0x88),
179 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3, 0x0F),
180 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT, 0x82),
181 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x03),
182 MSM8X16_WCD_REG_VAL(MSM8X16_WCD_A_ANALOG_SPKR_OCP_CTL, 0xE1),
185 static int msm8x16_wcd_bringup(struct snd_soc_codec *codec)
187 snd_soc_write(codec, MSM8X16_WCD_A_DIGITAL_PERPH_RESET_CTL4, 0x01);
188 snd_soc_write(codec, MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL4, 0x01);
192 static const struct msm8x16_wcd_reg_mask_val
193 msm8x16_wcd_codec_reg_init_val[] = {
195 /* Initialize current threshold to 350MA
196 * number of wait and run cycles to 4096
198 {MSM8X16_WCD_A_ANALOG_RX_COM_OCP_CTL, 0xFF, 0xD1},
199 {MSM8X16_WCD_A_ANALOG_RX_COM_OCP_COUNT, 0xFF, 0xFF},
202 static void msm8x16_wcd_codec_init_reg(struct snd_soc_codec *codec)
206 for (i = 0; i < ARRAY_SIZE(msm8x16_wcd_codec_reg_init_val); i++)
207 snd_soc_update_bits(codec,
208 msm8x16_wcd_codec_reg_init_val[i].reg,
209 msm8x16_wcd_codec_reg_init_val[i].mask,
210 msm8x16_wcd_codec_reg_init_val[i].val);
213 static void msm8x16_wcd_update_reg_defaults(struct snd_soc_codec *codec)
216 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
218 if (TOMBAK_IS_1_0(msm8x16_wcd->pmic_rev)) {
219 for (i = 0; i < ARRAY_SIZE(msm8x16_wcd_reg_defaults); i++)
220 snd_soc_write(codec, msm8x16_wcd_reg_defaults[i].reg,
221 msm8x16_wcd_reg_defaults[i].val);
223 for (i = 0; i < ARRAY_SIZE(msm8x16_wcd_reg_defaults_2_0); i++)
225 msm8x16_wcd_reg_defaults_2_0[i].reg,
226 msm8x16_wcd_reg_defaults_2_0[i].val);
230 static int msm8x16_wcd_device_up(struct snd_soc_codec *codec)
234 dev_dbg(codec->dev, "%s: device up!\n", __func__);
235 msm8x16_wcd_bringup(codec);
237 for (reg = 0; reg < ARRAY_SIZE(msm8x16_wcd_reset_reg_defaults); reg++)
238 if (msm8x16_wcd_reg_readable[reg])
239 msm8x16_wcd_write(codec,
240 reg, msm8x16_wcd_reset_reg_defaults[reg]);
242 /* delay is required to make sure sound card state updated */
243 usleep_range(5000, 5100);
245 msm8x16_wcd_codec_init_reg(codec);
246 msm8x16_wcd_update_reg_defaults(codec);
252 static int msm8x16_wcd_codec_enable_clock_block(struct snd_soc_codec *codec,
255 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
256 unsigned long mclk_rate;
259 snd_soc_update_bits(codec,
260 MSM8X16_WCD_A_CDC_CLK_MCLK_CTL, 0x01, 0x01);
261 snd_soc_update_bits(codec,
262 MSM8X16_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x03);
263 snd_soc_update_bits(codec,
264 MSM8X16_WCD_A_ANALOG_MASTER_BIAS_CTL, 0x30, 0x30);
265 snd_soc_update_bits(codec,
266 MSM8X16_WCD_A_DIGITAL_CDC_RST_CTL, 0x80, 0x80);
267 snd_soc_update_bits(codec,
268 MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x0C);
270 mclk_rate = clk_get_rate(msm8x16_wcd->mclk);
272 if (mclk_rate == 12288000)
273 snd_soc_update_bits(codec,
274 MSM8X16_WCD_A_CDC_TOP_CTL, 0x01, 0x00);
275 else if (mclk_rate == 9600000)
276 snd_soc_update_bits(codec,
277 MSM8X16_WCD_A_CDC_TOP_CTL, 0x01, 0x01);
279 snd_soc_update_bits(codec,
280 MSM8X16_WCD_A_DIGITAL_CDC_TOP_CLK_CTL, 0x0C, 0x00);
281 snd_soc_update_bits(codec,
282 MSM8X16_WCD_A_CDC_CLK_PDM_CTL, 0x03, 0x00);
288 static int msm8x16_wcd_codec_probe(struct snd_soc_codec *codec)
290 struct wcd_chip *chip = dev_get_drvdata(codec->dev);
293 snd_soc_codec_set_drvdata(codec, chip);
294 chip->pmic_rev = snd_soc_read(codec, MSM8X16_WCD_A_DIGITAL_REVISION1);
295 dev_info(codec->dev, "%s :PMIC REV: %d", __func__,
298 chip->codec_version = snd_soc_read(codec,
299 MSM8X16_WCD_A_DIGITAL_PERPH_SUBTYPE);
300 dev_info(codec->dev, "%s :CODEC Version: %d", __func__,
301 chip->codec_version);
303 msm8x16_wcd_device_up(codec);
305 err = regulator_enable(chip->vddio);
307 dev_err(codec->dev, "failed to enable VDD regulator\n");
311 err = regulator_enable(chip->vdd_pa);
313 dev_err(codec->dev, "failed to enable VDD regulator\n");
317 msm8x16_wcd_codec_enable_clock_block(codec, 1);
322 static int msm8x16_wcd_startup(struct snd_pcm_substream *substream,
323 struct snd_soc_dai *dai)
325 dev_dbg(dai->codec->dev, "%s(): substream = %s stream = %d\n",
327 substream->name, substream->stream);
331 static void msm8x16_wcd_shutdown(struct snd_pcm_substream *substream,
332 struct snd_soc_dai *dai)
334 dev_dbg(dai->codec->dev,
335 "%s(): substream = %s stream = %d\n", __func__,
336 substream->name, substream->stream);
339 static int msm8x16_wcd_set_interpolator_rate(struct snd_soc_dai *dai,
340 u8 rx_fs_rate_reg_val, u32 sample_rate)
345 static int msm8x16_wcd_set_decimator_rate(struct snd_soc_dai *dai,
346 u8 tx_fs_rate_reg_val, u32 sample_rate)
351 static int msm8x16_wcd_hw_params(struct snd_pcm_substream *substream,
352 struct snd_pcm_hw_params *params,
353 struct snd_soc_dai *dai)
355 u8 tx_fs_rate, rx_fs_rate;
358 dev_dbg(dai->codec->dev,
359 "%s: dai_name = %s DAI-ID %x rate %d num_ch %d format %d\n",
360 __func__, dai->name, dai->id, params_rate(params),
361 params_channels(params), params_format(params));
363 switch (params_rate(params)) {
389 dev_err(dai->codec->dev,
390 "%s: Invalid sampling rate %d\n", __func__,
391 params_rate(params));
395 switch (substream->stream) {
396 case SNDRV_PCM_STREAM_CAPTURE:
397 ret = msm8x16_wcd_set_decimator_rate(dai, tx_fs_rate,
398 params_rate(params));
400 dev_err(dai->codec->dev,
401 "%s: set decimator rate failed %d\n", __func__,
406 case SNDRV_PCM_STREAM_PLAYBACK:
407 ret = msm8x16_wcd_set_interpolator_rate(dai, rx_fs_rate,
408 params_rate(params));
410 dev_err(dai->codec->dev,
411 "%s: set decimator rate failed %d\n", __func__,
417 dev_err(dai->codec->dev,
418 "%s: Invalid stream type %d\n", __func__,
423 switch (params_format(params)) {
424 case SNDRV_PCM_FORMAT_S16_LE:
425 snd_soc_update_bits(dai->codec,
426 MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL, 0x20, 0x20);
428 case SNDRV_PCM_FORMAT_S24_LE:
429 snd_soc_update_bits(dai->codec,
430 MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL, 0x20, 0x00);
433 dev_err(dai->dev, "%s: wrong format selected\n",
441 static int msm8x16_wcd_set_dai_sysclk(struct snd_soc_dai *dai,
442 int clk_id, unsigned int freq, int dir)
444 dev_dbg(dai->codec->dev, "%s\n", __func__);
448 static int msm8x16_wcd_set_channel_map(struct snd_soc_dai *dai,
449 unsigned int tx_num, unsigned int *tx_slot,
450 unsigned int rx_num, unsigned int *rx_slot)
453 dev_dbg(dai->codec->dev, "%s\n", __func__);
457 static int msm8x16_wcd_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
459 dev_dbg(dai->codec->dev, "%s\n", __func__);
464 static struct snd_soc_dai_ops msm8x16_wcd_dai_ops = {
465 .startup = msm8x16_wcd_startup,
466 .shutdown = msm8x16_wcd_shutdown,
467 .hw_params = msm8x16_wcd_hw_params,
468 .set_sysclk = msm8x16_wcd_set_dai_sysclk,
469 .set_fmt = msm8x16_wcd_set_dai_fmt,
470 .set_channel_map = msm8x16_wcd_set_channel_map,
473 static struct snd_soc_dai_driver msm8x16_wcd_codec_dai[] = {
475 .name = "msm8x16_wcd_i2s_rx1",
478 .stream_name = "AIF1 Playback",
479 .rates = MSM8X16_WCD_RATES,
480 .formats = MSM8X16_WCD_FORMATS,
486 .ops = &msm8x16_wcd_dai_ops,
489 .name = "msm8x16_wcd_i2s_tx1",
492 .stream_name = "AIF1 Capture",
493 .rates = MSM8X16_WCD_RATES,
494 .formats = MSM8X16_WCD_FORMATS,
500 .ops = &msm8x16_wcd_dai_ops,
504 static int msm8x16_wcd_codec_remove(struct snd_soc_codec *codec)
511 static int msm8x16_wcd_spk_boost_get(struct snd_kcontrol *kcontrol,
512 struct snd_ctl_elem_value *ucontrol)
514 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
515 struct wcd_chip *msm8x16_wcd = dev_get_drvdata(codec->dev);
517 if (msm8x16_wcd->spk_boost_set == false) {
518 ucontrol->value.integer.value[0] = 0;
519 } else if (msm8x16_wcd->spk_boost_set == true) {
520 ucontrol->value.integer.value[0] = 1;
522 dev_err(codec->dev, "%s: ERROR: Unsupported Speaker Boost = %d\n",
523 __func__, msm8x16_wcd->spk_boost_set);
527 dev_dbg(codec->dev, "%s: msm8x16_wcd->spk_boost_set = %d\n", __func__,
528 msm8x16_wcd->spk_boost_set);
532 static int msm8x16_wcd_spk_boost_set(struct snd_kcontrol *kcontrol,
533 struct snd_ctl_elem_value *ucontrol)
535 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
536 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
539 switch (ucontrol->value.integer.value[0]) {
541 msm8x16_wcd->spk_boost_set = false;
544 msm8x16_wcd->spk_boost_set = true;
549 dev_dbg(codec->dev, "%s: msm8x16_wcd->spk_boost_set = %d\n",
550 __func__, msm8x16_wcd->spk_boost_set);
554 static const char * const hph_text[] = {
558 static const struct soc_enum hph_enum =
559 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(hph_text), hph_text);
562 static const struct snd_kcontrol_new hphl_mux[] = {
563 SOC_DAPM_ENUM("HPHL", hph_enum)
566 static const struct snd_kcontrol_new hphr_mux[] = {
567 SOC_DAPM_ENUM("HPHR", hph_enum)
570 static const struct snd_kcontrol_new spkr_switch[] = {
571 SOC_DAPM_SINGLE("Switch",
572 MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 7, 1, 0)
575 static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
576 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
578 static const struct snd_soc_dapm_route audio_map[] = {
579 {"RX_I2S_CLK", NULL, "CDC_CONN"},
580 {"I2S RX1", NULL, "RX_I2S_CLK"},
581 {"I2S RX2", NULL, "RX_I2S_CLK"},
582 {"I2S RX3", NULL, "RX_I2S_CLK"},
584 {"I2S TX1", NULL, "TX_I2S_CLK"},
585 {"I2S TX2", NULL, "TX_I2S_CLK"},
587 {"I2S TX1", NULL, "DEC1 MUX"},
588 {"I2S TX2", NULL, "DEC2 MUX"},
590 /* RDAC Connections */
591 {"HPHR DAC", NULL, "RDAC2 MUX"},
592 {"RDAC2 MUX", "RX1", "RX1 CHAIN"},
593 {"RDAC2 MUX", "RX2", "RX2 CHAIN"},
595 /* Earpiece (RX MIX1) */
596 {"EAR", NULL, "EAR_S"},
597 {"EAR_S", "Switch", "EAR PA"},
598 {"EAR PA", NULL, "RX_BIAS"},
599 {"EAR PA", NULL, "HPHL DAC"},
600 {"EAR PA", NULL, "HPHR DAC"},
601 {"EAR PA", NULL, "EAR CP"},
603 /* Headset (RX MIX1 and RX MIX2) */
604 {"HEADPHONE", NULL, "HPHL PA"},
605 {"HEADPHONE", NULL, "HPHR PA"},
608 {"HPHL PA", NULL, "HPHL"},
609 {"HPHR PA", NULL, "HPHR"},
610 {"HPHL", "Switch", "HPHL DAC"},
611 {"HPHR", "Switch", "HPHR DAC"},
612 {"HPHL PA", NULL, "CP"},
613 {"HPHL PA", NULL, "RX_BIAS"},
614 {"HPHR PA", NULL, "CP"},
615 {"HPHR PA", NULL, "RX_BIAS"},
616 {"HPHL DAC", NULL, "RX1 CHAIN"},
618 {"SPK_OUT", NULL, "SPK PA"},
619 {"SPK PA", NULL, "SPK_RX_BIAS"},
620 {"SPK PA", NULL, "SPK DAC"},
621 {"SPK DAC", "Switch", "RX3 CHAIN"},
623 {"RX1 CHAIN", NULL, "RX1 CLK"},
624 {"RX2 CHAIN", NULL, "RX2 CLK"},
625 {"RX3 CHAIN", NULL, "RX3 CLK"},
626 {"RX1 CHAIN", NULL, "RX1 MIX2"},
627 {"RX2 CHAIN", NULL, "RX2 MIX2"},
628 {"RX1 CHAIN", NULL, "RX1 MIX1"},
629 {"RX2 CHAIN", NULL, "RX2 MIX1"},
630 {"RX3 CHAIN", NULL, "RX3 MIX1"},
632 {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
633 {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
634 {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
636 {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
637 {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
639 {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
640 {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
642 {"RX1 MIX2", NULL, "RX1 MIX2 INP1"},
643 {"RX2 MIX2", NULL, "RX2 MIX2 INP1"},
645 {"RX1 MIX1 INP1", "RX1", "I2S RX1"},
646 {"RX1 MIX1 INP1", "RX2", "I2S RX2"},
647 {"RX1 MIX1 INP1", "RX3", "I2S RX3"},
648 {"RX1 MIX1 INP1", "IIR1", "IIR1"},
649 {"RX1 MIX1 INP2", "RX1", "I2S RX1"},
650 {"RX1 MIX1 INP2", "RX2", "I2S RX2"},
651 {"RX1 MIX1 INP2", "RX3", "I2S RX3"},
652 {"RX1 MIX1 INP2", "IIR1", "IIR1"},
653 {"RX1 MIX1 INP3", "RX1", "I2S RX1"},
654 {"RX1 MIX1 INP3", "RX2", "I2S RX2"},
655 {"RX1 MIX1 INP3", "RX3", "I2S RX3"},
657 {"RX2 MIX1 INP1", "RX1", "I2S RX1"},
658 {"RX2 MIX1 INP1", "RX2", "I2S RX2"},
659 {"RX2 MIX1 INP1", "RX3", "I2S RX3"},
660 {"RX2 MIX1 INP1", "IIR1", "IIR1"},
661 {"RX2 MIX1 INP2", "RX1", "I2S RX1"},
662 {"RX2 MIX1 INP2", "RX2", "I2S RX2"},
663 {"RX2 MIX1 INP2", "RX3", "I2S RX3"},
664 {"RX2 MIX1 INP2", "IIR1", "IIR1"},
666 {"RX3 MIX1 INP1", "RX1", "I2S RX1"},
667 {"RX3 MIX1 INP1", "RX2", "I2S RX2"},
668 {"RX3 MIX1 INP1", "RX3", "I2S RX3"},
669 {"RX3 MIX1 INP1", "IIR1", "IIR1"},
670 {"RX3 MIX1 INP2", "RX1", "I2S RX1"},
671 {"RX3 MIX1 INP2", "RX2", "I2S RX2"},
672 {"RX3 MIX1 INP2", "RX3", "I2S RX3"},
673 {"RX3 MIX1 INP2", "IIR1", "IIR1"},
675 {"RX1 MIX2 INP1", "IIR1", "IIR1"},
676 {"RX2 MIX2 INP1", "IIR1", "IIR1"},
678 /* Decimator Inputs */
679 {"DEC1 MUX", "DMIC1", "DMIC1"},
680 {"DEC1 MUX", "DMIC2", "DMIC2"},
681 {"DEC1 MUX", "ADC1", "ADC1"},
682 {"DEC1 MUX", "ADC2", "ADC2"},
683 {"DEC1 MUX", "ADC3", "ADC3"},
684 {"DEC1 MUX", NULL, "CDC_CONN"},
686 {"DEC2 MUX", "DMIC1", "DMIC1"},
687 {"DEC2 MUX", "DMIC2", "DMIC2"},
688 {"DEC2 MUX", "ADC1", "ADC1"},
689 {"DEC2 MUX", "ADC2", "ADC2"},
690 {"DEC2 MUX", "ADC3", "ADC3"},
691 {"DEC2 MUX", NULL, "CDC_CONN"},
693 /* ADC Connections */
694 {"ADC2", NULL, "ADC2 MUX"},
695 {"ADC3", NULL, "ADC2 MUX"},
696 {"ADC2 MUX", "INP2", "ADC2_INP2"},
697 {"ADC2 MUX", "INP3", "ADC2_INP3"},
699 {"ADC1", NULL, "AMIC1"},
700 {"ADC2_INP2", NULL, "AMIC2"},
701 {"ADC2_INP3", NULL, "AMIC3"},
704 {"IIR1", NULL, "IIR1 INP1 MUX"},
705 {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
706 {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
707 {"MIC BIAS Internal1", NULL, "INT_LDO_H"},
708 {"MIC BIAS Internal2", NULL, "INT_LDO_H"},
709 {"MIC BIAS External", NULL, "INT_LDO_H"},
710 {"MIC BIAS External2", NULL, "INT_LDO_H"},
711 {"MIC BIAS Internal1", NULL, "MICBIAS_REGULATOR"},
712 {"MIC BIAS Internal2", NULL, "MICBIAS_REGULATOR"},
713 {"MIC BIAS External", NULL, "MICBIAS_REGULATOR"},
714 {"MIC BIAS External2", NULL, "MICBIAS_REGULATOR"},
717 static const char * const rx_mix1_text[] = {
718 "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3"
721 static const char * const rx_mix2_text[] = {
722 "ZERO", "IIR1", "IIR2"
725 static const char * const dec_mux_text[] = {
726 "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2"
729 static const char * const adc2_mux_text[] = {
730 "ZERO", "INP2", "INP3"
733 static const char * const rdac2_mux_text[] = {
737 static const char * const iir1_inp1_text[] = {
738 "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3"
742 static const struct soc_enum rx_mix1_inp1_chain_enum =
743 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL,
746 static const struct soc_enum rx_mix1_inp2_chain_enum =
747 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B1_CTL,
750 static const struct soc_enum rx_mix1_inp3_chain_enum =
751 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B2_CTL,
754 static const struct soc_enum rx_mix2_inp1_chain_enum =
755 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX1_B3_CTL,
759 static const struct soc_enum rx2_mix1_inp1_chain_enum =
760 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL,
763 static const struct soc_enum rx2_mix1_inp2_chain_enum =
764 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL,
767 static const struct soc_enum rx2_mix1_inp3_chain_enum =
768 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B1_CTL,
772 static const struct soc_enum rx2_mix2_inp1_chain_enum =
773 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX2_B3_CTL,
777 static const struct soc_enum rx3_mix1_inp1_chain_enum =
778 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL,
781 static const struct soc_enum rx3_mix1_inp2_chain_enum =
782 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL,
785 static const struct soc_enum rdac2_mux_enum =
786 SOC_ENUM_SINGLE(MSM8X16_WCD_A_DIGITAL_CDC_CONN_HPHR_DAC_CTL,
787 0, 3, rdac2_mux_text);
789 static const struct soc_enum rx3_mix1_inp3_chain_enum =
790 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_CONN_RX3_B1_CTL,
792 static const struct snd_kcontrol_new rx_mix1_inp1_mux =
793 SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum);
795 static const struct snd_kcontrol_new rdac2_mux =
796 SOC_DAPM_ENUM("RDAC2 MUX Mux", rdac2_mux_enum);
798 static const struct snd_kcontrol_new rx_mix1_inp2_mux =
799 SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum);
801 static const struct snd_kcontrol_new rx_mix1_inp3_mux =
802 SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum);
804 static const struct snd_kcontrol_new rx2_mix1_inp1_mux =
805 SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum);
807 static const struct snd_kcontrol_new rx2_mix1_inp2_mux =
808 SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum);
810 static const struct snd_kcontrol_new rx2_mix1_inp3_mux =
811 SOC_DAPM_ENUM("RX2 MIX1 INP3 Mux", rx2_mix1_inp3_chain_enum);
813 static const struct snd_kcontrol_new rx3_mix1_inp1_mux =
814 SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum);
816 static const struct snd_kcontrol_new rx3_mix1_inp2_mux =
817 SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum);
819 static const struct snd_kcontrol_new rx3_mix1_inp3_mux =
820 SOC_DAPM_ENUM("RX3 MIX1 INP3 Mux", rx3_mix1_inp3_chain_enum);
822 static const struct snd_kcontrol_new rx1_mix2_inp1_mux =
823 SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum);
825 static const struct snd_kcontrol_new rx2_mix2_inp1_mux =
826 SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
828 static const char * const msm8x16_wcd_loopback_mode_ctrl_text[] = {
829 "DISABLE", "ENABLE"};
831 static const struct soc_enum msm8x16_wcd_loopback_mode_ctl_enum[] = {
832 SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_loopback_mode_ctrl_text),
835 static const char * const msm8x16_wcd_ear_pa_boost_ctrl_text[] = {
836 "DISABLE", "ENABLE"};
837 static const struct soc_enum msm8x16_wcd_ear_pa_boost_ctl_enum[] = {
838 SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_ear_pa_boost_ctrl_text),
841 static const char * const msm8x16_wcd_ear_pa_gain_text[] = {
842 "POS_6_DB", "POS_1P5_DB"};
843 static const struct soc_enum msm8x16_wcd_ear_pa_gain_enum[] = {
844 SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_ear_pa_gain_text),
847 static const char * const msm8x16_wcd_spk_boost_ctrl_text[] = {
848 "DISABLE", "ENABLE"};
849 static const struct soc_enum msm8x16_wcd_spk_boost_ctl_enum[] = {
850 SOC_ENUM_SINGLE_EXT(2, msm8x16_wcd_spk_boost_ctrl_text),
853 /*cut of frequency for high pass filter*/
854 static const char * const cf_text[] = {
855 "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz"
858 static const struct soc_enum cf_dec1_enum =
859 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_TX1_MUX_CTL, 4, 3, cf_text);
861 static const struct soc_enum cf_dec2_enum =
862 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_TX2_MUX_CTL, 4, 3, cf_text);
864 static const struct soc_enum cf_rxmix1_enum =
865 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_RX1_B4_CTL, 0, 3, cf_text);
867 static const struct soc_enum cf_rxmix2_enum =
868 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_RX2_B4_CTL, 0, 3, cf_text);
870 static const struct soc_enum cf_rxmix3_enum =
871 SOC_ENUM_SINGLE(MSM8X16_WCD_A_CDC_RX3_B4_CTL, 0, 3, cf_text);
873 static const struct snd_kcontrol_new msm8x16_wcd_snd_controls[] = {
875 SOC_ENUM_EXT("Speaker Boost", msm8x16_wcd_spk_boost_ctl_enum[0],
876 msm8x16_wcd_spk_boost_get, msm8x16_wcd_spk_boost_set),
878 SOC_SINGLE_TLV("ADC1 Volume", MSM8X16_WCD_A_ANALOG_TX_1_EN, 3,
880 SOC_SINGLE_TLV("ADC2 Volume", MSM8X16_WCD_A_ANALOG_TX_2_EN, 3,
882 SOC_SINGLE_TLV("ADC3 Volume", MSM8X16_WCD_A_ANALOG_TX_3_EN, 3,
885 SOC_SINGLE_SX_TLV("RX1 Digital Volume",
886 MSM8X16_WCD_A_CDC_RX1_VOL_CTL_B2_CTL,
887 0, -84, 40, digital_gain),
888 SOC_SINGLE_SX_TLV("RX2 Digital Volume",
889 MSM8X16_WCD_A_CDC_RX2_VOL_CTL_B2_CTL,
890 0, -84, 40, digital_gain),
891 SOC_SINGLE_SX_TLV("RX3 Digital Volume",
892 MSM8X16_WCD_A_CDC_RX3_VOL_CTL_B2_CTL,
893 0, -84, 40, digital_gain),
895 SOC_SINGLE("RX1 HPF Switch",
896 MSM8X16_WCD_A_CDC_RX1_B5_CTL, 2, 1, 0),
897 SOC_SINGLE("RX2 HPF Switch",
898 MSM8X16_WCD_A_CDC_RX2_B5_CTL, 2, 1, 0),
899 SOC_SINGLE("RX3 HPF Switch",
900 MSM8X16_WCD_A_CDC_RX3_B5_CTL, 2, 1, 0),
902 SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum),
903 SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum),
904 SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum),
908 static const struct snd_kcontrol_new ear_pa_switch[] = {
909 SOC_DAPM_SINGLE("Switch",
910 MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 5, 1, 0)
913 static int msm8x16_wcd_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
914 struct snd_kcontrol *kcontrol, int event)
916 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
917 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
920 case SND_SOC_DAPM_PRE_PMU:
922 "%s: Sleeping 20ms after select EAR PA\n",
924 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
927 case SND_SOC_DAPM_POST_PMU:
929 "%s: Sleeping 20ms after enabling EAR PA\n",
931 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
933 usleep_range(7000, 7100);
934 snd_soc_update_bits(codec,
935 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
937 case SND_SOC_DAPM_PRE_PMD:
938 snd_soc_update_bits(codec,
939 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x01);
941 msm8x16_wcd->mute_mask |= EAR_PA_DISABLE;
943 case SND_SOC_DAPM_POST_PMD:
945 "%s: Sleeping 7ms after disabling EAR PA\n",
947 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
949 usleep_range(7000, 7100);
951 * Reset pa select bit from ear to hph after ear pa
952 * is disabled to reduce ear turn off pop
954 snd_soc_update_bits(codec, MSM8X16_WCD_A_ANALOG_RX_EAR_CTL,
962 static int msm8x16_wcd_codec_enable_spk_pa(struct snd_soc_dapm_widget *w,
963 struct snd_kcontrol *kcontrol, int event)
965 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
966 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
969 case SND_SOC_DAPM_PRE_PMU:
970 snd_soc_update_bits(codec,
971 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x10);
972 snd_soc_update_bits(codec,
973 MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x01);
974 if (!msm8x16_wcd->spk_boost_set)
975 snd_soc_update_bits(codec,
976 MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x10);
977 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
978 snd_soc_update_bits(codec,
979 MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0xE0);
980 if (!TOMBAK_IS_1_0(msm8x16_wcd->pmic_rev))
981 snd_soc_update_bits(codec,
982 MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 0x01, 0x01);
984 case SND_SOC_DAPM_POST_PMU:
985 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
986 if (msm8x16_wcd->spk_boost_set)
987 snd_soc_update_bits(codec,
988 MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL, 0xEF, 0xEF);
990 snd_soc_update_bits(codec,
991 MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x00);
992 snd_soc_update_bits(codec,
993 MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0x01, 0x00);
994 snd_soc_update_bits(codec, w->reg, 0x80, 0x80);
996 case SND_SOC_DAPM_PRE_PMD:
997 snd_soc_update_bits(codec,
998 MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0x01, 0x01);
1000 msm8x16_wcd->mute_mask |= SPKR_PA_DISABLE;
1001 snd_soc_update_bits(codec, w->reg, 0x80, 0x00);
1002 if (msm8x16_wcd->spk_boost_set)
1003 snd_soc_update_bits(codec,
1004 MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL, 0xEF, 0x00);
1006 snd_soc_update_bits(codec,
1007 MSM8X16_WCD_A_ANALOG_SPKR_DAC_CTL, 0x10, 0x00);
1009 case SND_SOC_DAPM_POST_PMD:
1010 snd_soc_update_bits(codec,
1011 MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0xE0, 0x00);
1012 if (!TOMBAK_IS_1_0(msm8x16_wcd->pmic_rev))
1013 snd_soc_update_bits(codec,
1014 MSM8X16_WCD_A_ANALOG_RX_EAR_CTL, 0x01, 0x00);
1015 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1016 snd_soc_update_bits(codec,
1017 MSM8X16_WCD_A_ANALOG_SPKR_PWRSTG_CTL, 0x01, 0x00);
1018 snd_soc_update_bits(codec,
1019 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x10, 0x00);
1025 static int msm8x16_wcd_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
1026 struct snd_kcontrol *kcontrol,
1029 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1030 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1033 case SND_SOC_DAPM_POST_PMU:
1034 /* apply the digital gain after the interpolator is enabled*/
1035 if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg))
1036 snd_soc_write(codec,
1037 rx_digital_gain_reg[w->shift],
1039 rx_digital_gain_reg[w->shift])
1042 case SND_SOC_DAPM_POST_PMD:
1043 snd_soc_update_bits(codec,
1044 MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL,
1045 1 << w->shift, 1 << w->shift);
1046 snd_soc_update_bits(codec,
1047 MSM8X16_WCD_A_CDC_CLK_RX_RESET_CTL,
1048 1 << w->shift, 0x0);
1050 * disable the mute enabled during the PMD of this device
1052 if (msm8x16_wcd->mute_mask & HPHL_PA_DISABLE) {
1053 pr_debug("disabling HPHL mute\n");
1054 snd_soc_update_bits(codec,
1055 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
1056 msm8x16_wcd->mute_mask &= ~(HPHL_PA_DISABLE);
1058 if (msm8x16_wcd->mute_mask & HPHR_PA_DISABLE) {
1059 pr_debug("disabling HPHR mute\n");
1060 snd_soc_update_bits(codec,
1061 MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0x01, 0x00);
1062 msm8x16_wcd->mute_mask &= ~(HPHR_PA_DISABLE);
1064 if (msm8x16_wcd->mute_mask & SPKR_PA_DISABLE) {
1065 pr_debug("disabling SPKR mute\n");
1066 snd_soc_update_bits(codec,
1067 MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0x01, 0x00);
1068 msm8x16_wcd->mute_mask &= ~(SPKR_PA_DISABLE);
1070 if (msm8x16_wcd->mute_mask & EAR_PA_DISABLE) {
1071 pr_debug("disabling EAR mute\n");
1072 snd_soc_update_bits(codec,
1073 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
1074 msm8x16_wcd->mute_mask &= ~(EAR_PA_DISABLE);
1080 static int msm8x16_wcd_codec_enable_dig_clk(struct snd_soc_dapm_widget *w,
1081 struct snd_kcontrol *kcontrol, int event)
1083 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1084 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1087 case SND_SOC_DAPM_PRE_PMU:
1089 snd_soc_update_bits(codec, w->reg, 0x80, 0x80);
1090 if (msm8x16_wcd->spk_boost_set) {
1091 snd_soc_update_bits(codec,
1092 MSM8X16_WCD_A_ANALOG_SEC_ACCESS,
1094 snd_soc_update_bits(codec,
1095 MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3,
1097 snd_soc_update_bits(codec,
1098 MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT,
1100 snd_soc_update_bits(codec,
1101 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1103 snd_soc_update_bits(codec,
1104 MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
1106 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1107 snd_soc_update_bits(codec,
1108 MSM8X16_WCD_A_ANALOG_CURRENT_LIMIT,
1110 } else if (msm8x16_wcd->ear_pa_boost_set) {
1111 snd_soc_update_bits(codec,
1112 MSM8X16_WCD_A_ANALOG_SEC_ACCESS,
1114 snd_soc_update_bits(codec,
1115 MSM8X16_WCD_A_ANALOG_PERPH_RESET_CTL3,
1117 snd_soc_update_bits(codec,
1118 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1120 snd_soc_update_bits(codec,
1121 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1123 snd_soc_update_bits(codec,
1124 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1126 snd_soc_update_bits(codec,
1127 MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
1130 snd_soc_update_bits(codec, w->reg, 1<<w->shift,
1134 case SND_SOC_DAPM_POST_PMD:
1135 if (msm8x16_wcd->spk_boost_set) {
1136 snd_soc_update_bits(codec,
1137 MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
1139 snd_soc_update_bits(codec,
1140 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1142 } else if (msm8x16_wcd->ear_pa_boost_set) {
1143 snd_soc_update_bits(codec,
1144 MSM8X16_WCD_A_ANALOG_BOOST_EN_CTL,
1146 snd_soc_update_bits(codec,
1147 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1149 snd_soc_update_bits(codec,
1150 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1152 snd_soc_update_bits(codec,
1153 MSM8X16_WCD_A_ANALOG_BYPASS_MODE,
1156 snd_soc_update_bits(codec, w->reg, 1<<w->shift, 0x00);
1163 static int msm8x16_wcd_codec_enable_rx_chain(struct snd_soc_dapm_widget *w,
1164 struct snd_kcontrol *kcontrol, int event)
1166 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1169 case SND_SOC_DAPM_POST_PMU:
1170 snd_soc_update_bits(codec,
1171 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1174 "%s: PMU:Sleeping 20ms after disabling mute\n",
1177 case SND_SOC_DAPM_POST_PMD:
1178 snd_soc_update_bits(codec,
1179 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1182 "%s: PMD:Sleeping 20ms after disabling mute\n",
1184 snd_soc_update_bits(codec, w->reg,
1185 1 << w->shift, 0x00);
1192 static int msm8x16_wcd_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
1193 struct snd_kcontrol *kcontrol, int event)
1195 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1196 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1200 case SND_SOC_DAPM_PRE_PMU:
1201 msm8x16_wcd->rx_bias_count++;
1202 if (msm8x16_wcd->rx_bias_count == 1)
1203 snd_soc_update_bits(codec,
1204 MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC,
1207 case SND_SOC_DAPM_POST_PMD:
1208 msm8x16_wcd->rx_bias_count--;
1209 if (msm8x16_wcd->rx_bias_count == 0)
1210 snd_soc_update_bits(codec,
1211 MSM8X16_WCD_A_ANALOG_RX_COM_BIAS_DAC,
1215 dev_dbg(codec->dev, "%s rx_bias_count = %d\n",
1216 __func__, msm8x16_wcd->rx_bias_count);
1220 static int msm8x16_wcd_codec_enable_charge_pump(struct snd_soc_dapm_widget *w,
1221 struct snd_kcontrol *kcontrol, int event)
1223 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1224 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1227 case SND_SOC_DAPM_PRE_PMU:
1228 if (!(strcmp(w->name, "EAR CP")))
1229 snd_soc_update_bits(codec,
1230 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1233 snd_soc_update_bits(codec,
1234 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1237 case SND_SOC_DAPM_POST_PMU:
1238 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1240 case SND_SOC_DAPM_POST_PMD:
1241 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1242 if (!(strcmp(w->name, "EAR CP")))
1243 snd_soc_update_bits(codec,
1244 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1247 snd_soc_update_bits(codec,
1248 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1250 if (msm8x16_wcd->rx_bias_count == 0)
1251 snd_soc_update_bits(codec,
1252 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1254 dev_dbg(codec->dev, "%s: rx_bias_count = %d\n",
1255 __func__, msm8x16_wcd->rx_bias_count);
1262 static int msm8x16_wcd_hphl_dac_event(struct snd_soc_dapm_widget *w,
1263 struct snd_kcontrol *kcontrol, int event)
1265 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1268 case SND_SOC_DAPM_PRE_PMU:
1269 snd_soc_update_bits(codec,
1270 MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x02);
1271 snd_soc_update_bits(codec,
1272 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x01);
1273 snd_soc_update_bits(codec,
1274 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x02);
1276 case SND_SOC_DAPM_POST_PMU:
1277 snd_soc_update_bits(codec,
1278 MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x02, 0x00);
1280 case SND_SOC_DAPM_POST_PMD:
1281 snd_soc_update_bits(codec,
1282 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x02, 0x00);
1283 snd_soc_update_bits(codec,
1284 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00);
1290 static int msm8x16_wcd_hph_pa_event(struct snd_soc_dapm_widget *w,
1291 struct snd_kcontrol *kcontrol, int event)
1293 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1294 struct wcd_chip *msm8x16_wcd = snd_soc_codec_get_drvdata(codec);
1297 case SND_SOC_DAPM_PRE_PMU:
1298 if (w->shift == 5) {
1299 snd_soc_update_bits(codec,
1300 MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST, 0x04, 0x04);
1301 } else if (w->shift == 4) {
1302 snd_soc_update_bits(codec,
1303 MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST, 0x04, 0x04);
1305 snd_soc_update_bits(codec,
1306 MSM8X16_WCD_A_ANALOG_NCP_FBCTRL, 0x20, 0x20);
1309 case SND_SOC_DAPM_POST_PMU:
1310 usleep_range(4000, 4100);
1312 snd_soc_update_bits(codec,
1313 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x00);
1314 else if (w->shift == 4)
1315 snd_soc_update_bits(codec,
1316 MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0x01, 0x00);
1317 usleep_range(10000, 10100);
1320 case SND_SOC_DAPM_PRE_PMD:
1321 if (w->shift == 5) {
1322 snd_soc_update_bits(codec,
1323 MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0x01, 0x01);
1325 msm8x16_wcd->mute_mask |= HPHL_PA_DISABLE;
1326 } else if (w->shift == 4) {
1327 snd_soc_update_bits(codec,
1328 MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0x01, 0x01);
1330 msm8x16_wcd->mute_mask |= HPHR_PA_DISABLE;
1333 case SND_SOC_DAPM_POST_PMD:
1334 if (w->shift == 5) {
1335 snd_soc_update_bits(codec,
1336 MSM8X16_WCD_A_ANALOG_RX_HPH_L_TEST, 0x04, 0x00);
1338 } else if (w->shift == 4) {
1339 snd_soc_update_bits(codec,
1340 MSM8X16_WCD_A_ANALOG_RX_HPH_R_TEST, 0x04, 0x00);
1342 usleep_range(4000, 4100);
1344 usleep_range(CODEC_DELAY_1_MS, CODEC_DELAY_1_1_MS);
1345 snd_soc_update_bits(codec,
1346 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x40, 0x40);
1348 "%s: sleep 10 ms after %s PA disable.\n", __func__,
1350 usleep_range(10000, 10100);
1356 static int msm8x16_wcd_hphr_dac_event(struct snd_soc_dapm_widget *w,
1357 struct snd_kcontrol *kcontrol, int event)
1359 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1363 case SND_SOC_DAPM_PRE_PMU:
1364 snd_soc_update_bits(codec,
1365 MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x02);
1366 snd_soc_update_bits(codec,
1367 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x02);
1368 snd_soc_update_bits(codec,
1369 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x01);
1371 case SND_SOC_DAPM_POST_PMU:
1372 snd_soc_update_bits(codec,
1373 MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x02, 0x00);
1375 case SND_SOC_DAPM_POST_PMD:
1376 snd_soc_update_bits(codec,
1377 MSM8X16_WCD_A_DIGITAL_CDC_ANA_CLK_CTL, 0x01, 0x00);
1378 snd_soc_update_bits(codec,
1379 MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL, 0x02, 0x00);
1385 static const struct snd_soc_dapm_widget msm8x16_wcd_dapm_widgets[] = {
1387 SND_SOC_DAPM_OUTPUT("EAR"),
1389 SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM,
1390 0, 0, NULL, 0, msm8x16_wcd_codec_enable_ear_pa,
1391 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1392 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1393 SND_SOC_DAPM_MIXER("EAR_S", SND_SOC_NOPM, 0, 0,
1394 ear_pa_switch, ARRAY_SIZE(ear_pa_switch)),
1396 SND_SOC_DAPM_AIF_IN("I2S RX1", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1398 SND_SOC_DAPM_AIF_IN("I2S RX2", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1400 SND_SOC_DAPM_AIF_IN("I2S RX3", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1402 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0),
1404 SND_SOC_DAPM_OUTPUT("HEADPHONE"),
1405 SND_SOC_DAPM_PGA_E("HPHL PA", MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN,
1407 msm8x16_wcd_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
1408 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
1409 SND_SOC_DAPM_POST_PMD),
1411 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, hphl_mux),
1413 SND_SOC_DAPM_MIXER_E("HPHL DAC",
1414 MSM8X16_WCD_A_ANALOG_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL,
1415 0, msm8x16_wcd_hphl_dac_event,
1416 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1417 SND_SOC_DAPM_POST_PMD),
1419 SND_SOC_DAPM_PGA_E("HPHR PA", MSM8X16_WCD_A_ANALOG_RX_HPH_CNP_EN,
1421 msm8x16_wcd_hph_pa_event, SND_SOC_DAPM_PRE_PMU |
1422 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
1423 SND_SOC_DAPM_POST_PMD),
1424 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, hphr_mux),
1426 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0,
1427 spkr_switch, ARRAY_SIZE(spkr_switch)),
1429 SND_SOC_DAPM_MIXER_E("HPHR DAC",
1430 MSM8X16_WCD_A_ANALOG_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL,
1431 0, msm8x16_wcd_hphr_dac_event,
1432 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1433 SND_SOC_DAPM_POST_PMD),
1435 SND_SOC_DAPM_OUTPUT("SPK_OUT"),
1437 SND_SOC_DAPM_PGA_E("SPK PA", MSM8X16_WCD_A_ANALOG_SPKR_DRV_CTL,
1438 6, 0, NULL, 0, msm8x16_wcd_codec_enable_spk_pa,
1439 SND_SOC_DAPM_PRE_REG|
1440 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1441 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1443 SND_SOC_DAPM_MIXER_E("RX1 MIX1",
1444 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL, 0,
1445 msm8x16_wcd_codec_enable_interpolator,
1446 SND_SOC_DAPM_PRE_REG|
1447 SND_SOC_DAPM_POST_PMU |
1448 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD|
1449 SND_SOC_DAPM_POST_PMD),
1451 SND_SOC_DAPM_MIXER_E("RX2 MIX1",
1452 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL, 0,
1453 msm8x16_wcd_codec_enable_interpolator,
1454 SND_SOC_DAPM_PRE_REG|
1455 SND_SOC_DAPM_POST_PMU |
1456 SND_SOC_DAPM_POST_PMD),
1458 SND_SOC_DAPM_MIXER_E("RX1 MIX2",
1459 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
1460 0, msm8x16_wcd_codec_enable_interpolator,
1461 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1462 SND_SOC_DAPM_MIXER_E("RX2 MIX2",
1463 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
1464 0, msm8x16_wcd_codec_enable_interpolator,
1465 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1466 SND_SOC_DAPM_MIXER_E("RX3 MIX1",
1467 MSM8X16_WCD_A_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
1468 0, msm8x16_wcd_codec_enable_interpolator,
1469 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1471 SND_SOC_DAPM_SUPPLY("RX1 CLK", MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1473 SND_SOC_DAPM_SUPPLY("RX2 CLK", MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1475 SND_SOC_DAPM_SUPPLY("RX3 CLK", MSM8X16_WCD_A_DIGITAL_CDC_DIG_CLK_CTL,
1476 2, 0, msm8x16_wcd_codec_enable_dig_clk, SND_SOC_DAPM_PRE_PMU |
1477 SND_SOC_DAPM_POST_PMD),
1478 SND_SOC_DAPM_MIXER_E("RX1 CHAIN", MSM8X16_WCD_A_CDC_RX1_B6_CTL, 0, 0,
1480 msm8x16_wcd_codec_enable_rx_chain,
1481 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1482 SND_SOC_DAPM_MIXER_E("RX2 CHAIN", MSM8X16_WCD_A_CDC_RX2_B6_CTL, 0, 0,
1484 msm8x16_wcd_codec_enable_rx_chain,
1485 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1486 SND_SOC_DAPM_MIXER_E("RX3 CHAIN", MSM8X16_WCD_A_CDC_RX3_B6_CTL, 0, 0,
1488 msm8x16_wcd_codec_enable_rx_chain,
1489 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1491 SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
1493 SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
1495 SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
1498 SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
1499 &rx2_mix1_inp1_mux),
1500 SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
1501 &rx2_mix1_inp2_mux),
1502 SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0,
1503 &rx2_mix1_inp3_mux),
1505 SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
1506 &rx3_mix1_inp1_mux),
1507 SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
1508 &rx3_mix1_inp2_mux),
1509 SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0,
1510 &rx3_mix1_inp3_mux),
1512 SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
1513 &rx1_mix2_inp1_mux),
1514 SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
1515 &rx2_mix2_inp1_mux),
1516 SND_SOC_DAPM_SUPPLY("CP", MSM8X16_WCD_A_ANALOG_NCP_EN, 0, 0,
1517 msm8x16_wcd_codec_enable_charge_pump, SND_SOC_DAPM_PRE_PMU |
1518 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1520 SND_SOC_DAPM_SUPPLY("EAR CP", MSM8X16_WCD_A_ANALOG_NCP_EN, 4, 0,
1521 msm8x16_wcd_codec_enable_charge_pump, SND_SOC_DAPM_PRE_PMU |
1522 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1524 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM,
1525 0, 0, msm8x16_wcd_codec_enable_rx_bias,
1526 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1528 SND_SOC_DAPM_SUPPLY("SPK_RX_BIAS",
1530 msm8x16_wcd_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
1531 SND_SOC_DAPM_POST_PMD),
1532 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux),
1533 SND_SOC_DAPM_SUPPLY("RX_I2S_CLK",
1534 MSM8X16_WCD_A_CDC_CLK_RX_I2S_CTL, 4, 0, NULL, 0),
1538 static struct snd_soc_codec_driver msm8x16_wcd_codec = {
1539 .probe = msm8x16_wcd_codec_probe,
1540 .remove = msm8x16_wcd_codec_remove,
1541 .read = msm8x16_wcd_read,
1542 .write = msm8x16_wcd_write,
1543 .reg_cache_size = MSM8X16_WCD_CACHE_SIZE,
1544 .reg_cache_default = msm8x16_wcd_reset_reg_defaults,
1546 .controls = msm8x16_wcd_snd_controls,
1547 .num_controls = ARRAY_SIZE(msm8x16_wcd_snd_controls),
1548 .dapm_widgets = msm8x16_wcd_dapm_widgets,
1549 .num_dapm_widgets = ARRAY_SIZE(msm8x16_wcd_dapm_widgets),
1550 .dapm_routes = audio_map,
1551 .num_dapm_routes = ARRAY_SIZE(audio_map),
1554 static int msm8x16_wcd_codec_parse_dt(struct platform_device *pdev,
1555 struct wcd_chip *chip)
1557 struct device *dev = &pdev->dev;
1558 struct device_node *np = dev->of_node;
1562 ret = of_property_read_u32_array(np, "reg", res, 2);
1566 chip->analog_base = res[0];
1568 chip->digital_map = syscon_regmap_lookup_by_phandle(np, "digital");
1569 if (IS_ERR(chip->digital_map))
1570 return PTR_ERR(chip->digital_map);
1572 chip->vddio = devm_regulator_get(dev, "vddio");
1573 if (IS_ERR(chip->vddio)) {
1574 dev_err(dev, "Failed to get vdd supply\n");
1575 return PTR_ERR(chip->vddio);
1578 chip->vdd_pa = devm_regulator_get(dev, "vdd-pa");
1579 if (IS_ERR(chip->vdd_pa)) {
1580 dev_err(dev, "Failed to get vdd supply\n");
1581 return PTR_ERR(chip->vdd_pa);
1584 chip->mclk = devm_clk_get(dev, "mclk");
1589 static int wcd_probe(struct platform_device *pdev)
1591 struct wcd_chip *chip;
1592 struct device *dev = &pdev->dev;
1594 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
1598 chip->analog_map = dev_get_regmap(dev->parent, NULL);
1599 if (!chip->analog_map)
1602 msm8x16_wcd_codec_parse_dt(pdev, chip);
1603 clk_set_rate(chip->mclk, 9600000);
1604 clk_prepare_enable(chip->mclk);
1606 dev_set_drvdata(dev, chip);
1608 return snd_soc_register_codec(dev, &msm8x16_wcd_codec,
1609 msm8x16_wcd_codec_dai,
1610 ARRAY_SIZE(msm8x16_wcd_codec_dai));
1613 static int wcd_remove(struct platform_device *pdev)
1618 static const struct of_device_id wcd_match_table[] = {
1619 { .compatible = "qcom,apq8016-wcd-codec" },
1622 MODULE_DEVICE_TABLE(of, wcd_match_table);
1624 static struct platform_driver wcd_driver = {
1626 .name = "spmi-wcd-codec",
1627 .of_match_table = wcd_match_table,
1630 .remove = wcd_remove,
1632 module_platform_driver(wcd_driver);
1634 MODULE_ALIAS("platform:spmi-wcd-codec");
1635 MODULE_DESCRIPTION("SPMI PMIC WCD codec driver");
1636 MODULE_LICENSE("GPL v2");