2 * PCM3168A codec driver
4 * Copyright (C) 2015 Imagination Technologies Ltd.
6 * Author: Damien Horsley <Damien.Horsley@imgtec.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/tlv.h>
25 #define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
26 SNDRV_PCM_FMTBIT_S24_3LE | \
27 SNDRV_PCM_FMTBIT_S24_LE | \
28 SNDRV_PCM_FMTBIT_S32_LE)
30 #define PCM3168A_FMT_I2S 0x0
31 #define PCM3168A_FMT_LEFT_J 0x1
32 #define PCM3168A_FMT_RIGHT_J 0x2
33 #define PCM3168A_FMT_RIGHT_J_16 0x3
34 #define PCM3168A_FMT_DSP_A 0x4
35 #define PCM3168A_FMT_DSP_B 0x5
36 #define PCM3168A_FMT_DSP_MASK 0x4
38 #define PCM3168A_NUM_SUPPLIES 6
39 static const char *const pcm3168a_supply_names[PCM3168A_NUM_SUPPLIES] = {
48 struct pcm3168a_priv {
49 struct regulator_bulk_data supplies[PCM3168A_NUM_SUPPLIES];
50 struct regmap *regmap;
59 static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" };
61 static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT,
62 PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off);
63 static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT,
64 PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off);
65 static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT,
66 PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off);
67 static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT,
68 PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off);
70 static const char *const pcm3168a_volume_type[] = {
71 "Individual", "Master + Individual" };
73 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF,
74 PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type);
76 static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" };
78 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF,
79 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult);
81 static const char *const pcm3168a_demp[] = {
82 "Disabled", "48khz", "44.1khz", "32khz" };
84 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF,
85 PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp);
87 static const char *const pcm3168a_zf_func[] = {
88 "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND",
89 "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" };
91 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF,
92 PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func);
94 static const char *const pcm3168a_pol[] = { "Active High", "Active Low" };
96 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF,
97 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol);
99 static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" };
101 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD,
103 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD,
105 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD,
108 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF,
109 PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type);
111 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF,
112 PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult);
114 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF,
115 PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol);
117 /* -100db to 0db, register values 0-54 cause mute */
118 static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1);
120 /* -100db to 20db, register values 0-14 cause mute */
121 static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1);
123 static const struct snd_kcontrol_new pcm3168a_snd_controls[] = {
124 SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT,
125 PCM3168A_DAC_PSMDA_SHIFT, 1, 1),
126 SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off),
127 SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off),
128 SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off),
129 SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off),
130 SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0),
131 SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0),
132 SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0),
133 SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0),
134 SOC_DOUBLE_STS("DAC1 Zero Flag", PCM3168A_DAC_ZERO, 0, 1, 1, 0),
135 SOC_DOUBLE_STS("DAC2 Zero Flag", PCM3168A_DAC_ZERO, 2, 3, 1, 0),
136 SOC_DOUBLE_STS("DAC3 Zero Flag", PCM3168A_DAC_ZERO, 4, 5, 1, 0),
137 SOC_DOUBLE_STS("DAC4 Zero Flag", PCM3168A_DAC_ZERO, 6, 7, 1, 0),
138 SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type),
139 SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult),
140 SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp),
141 SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func),
142 SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol),
143 SOC_SINGLE_RANGE_TLV("Master Playback Volume",
144 PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0,
146 SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume",
147 PCM3168A_DAC_VOL_CHAN_START,
148 PCM3168A_DAC_VOL_CHAN_START + 1,
149 0, 54, 255, 0, pcm3168a_dac_tlv),
150 SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume",
151 PCM3168A_DAC_VOL_CHAN_START + 2,
152 PCM3168A_DAC_VOL_CHAN_START + 3,
153 0, 54, 255, 0, pcm3168a_dac_tlv),
154 SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume",
155 PCM3168A_DAC_VOL_CHAN_START + 4,
156 PCM3168A_DAC_VOL_CHAN_START + 5,
157 0, 54, 255, 0, pcm3168a_dac_tlv),
158 SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume",
159 PCM3168A_DAC_VOL_CHAN_START + 6,
160 PCM3168A_DAC_VOL_CHAN_START + 7,
161 0, 54, 255, 0, pcm3168a_dac_tlv),
162 SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
163 PCM3168A_ADC_BYP_SHIFT, 1, 1),
164 SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
165 PCM3168A_ADC_BYP_SHIFT + 1, 1, 1),
166 SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
167 PCM3168A_ADC_BYP_SHIFT + 2, 1, 1),
168 SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con),
169 SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con),
170 SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con),
171 SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0),
172 SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0),
173 SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0),
174 SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0),
175 SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0),
176 SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0),
177 SOC_DOUBLE_STS("ADC1 Overflow Flag", PCM3168A_ADC_OV, 0, 1, 1, 0),
178 SOC_DOUBLE_STS("ADC2 Overflow Flag", PCM3168A_ADC_OV, 2, 3, 1, 0),
179 SOC_DOUBLE_STS("ADC3 Overflow Flag", PCM3168A_ADC_OV, 4, 5, 1, 0),
180 SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type),
181 SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult),
182 SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol),
183 SOC_SINGLE_RANGE_TLV("Master Capture Volume",
184 PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0,
186 SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume",
187 PCM3168A_ADC_VOL_CHAN_START,
188 PCM3168A_ADC_VOL_CHAN_START + 1,
189 0, 14, 255, 0, pcm3168a_adc_tlv),
190 SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume",
191 PCM3168A_ADC_VOL_CHAN_START + 2,
192 PCM3168A_ADC_VOL_CHAN_START + 3,
193 0, 14, 255, 0, pcm3168a_adc_tlv),
194 SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume",
195 PCM3168A_ADC_VOL_CHAN_START + 4,
196 PCM3168A_ADC_VOL_CHAN_START + 5,
197 0, 14, 255, 0, pcm3168a_adc_tlv)
200 static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = {
201 SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT,
202 PCM3168A_DAC_OPEDA_SHIFT, 1),
203 SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT,
204 PCM3168A_DAC_OPEDA_SHIFT + 1, 1),
205 SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT,
206 PCM3168A_DAC_OPEDA_SHIFT + 2, 1),
207 SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT,
208 PCM3168A_DAC_OPEDA_SHIFT + 3, 1),
210 SND_SOC_DAPM_OUTPUT("AOUT1L"),
211 SND_SOC_DAPM_OUTPUT("AOUT1R"),
212 SND_SOC_DAPM_OUTPUT("AOUT2L"),
213 SND_SOC_DAPM_OUTPUT("AOUT2R"),
214 SND_SOC_DAPM_OUTPUT("AOUT3L"),
215 SND_SOC_DAPM_OUTPUT("AOUT3R"),
216 SND_SOC_DAPM_OUTPUT("AOUT4L"),
217 SND_SOC_DAPM_OUTPUT("AOUT4R"),
219 SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB,
220 PCM3168A_ADC_PSVAD_SHIFT, 1),
221 SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB,
222 PCM3168A_ADC_PSVAD_SHIFT + 1, 1),
223 SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB,
224 PCM3168A_ADC_PSVAD_SHIFT + 2, 1),
226 SND_SOC_DAPM_INPUT("AIN1L"),
227 SND_SOC_DAPM_INPUT("AIN1R"),
228 SND_SOC_DAPM_INPUT("AIN2L"),
229 SND_SOC_DAPM_INPUT("AIN2R"),
230 SND_SOC_DAPM_INPUT("AIN3L"),
231 SND_SOC_DAPM_INPUT("AIN3R")
234 static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = {
236 { "AOUT1L", NULL, "DAC1" },
237 { "AOUT1R", NULL, "DAC1" },
239 { "AOUT2L", NULL, "DAC2" },
240 { "AOUT2R", NULL, "DAC2" },
242 { "AOUT3L", NULL, "DAC3" },
243 { "AOUT3R", NULL, "DAC3" },
245 { "AOUT4L", NULL, "DAC4" },
246 { "AOUT4R", NULL, "DAC4" },
249 { "ADC1", NULL, "AIN1L" },
250 { "ADC1", NULL, "AIN1R" },
252 { "ADC2", NULL, "AIN2L" },
253 { "ADC2", NULL, "AIN2R" },
255 { "ADC3", NULL, "AIN3L" },
256 { "ADC3", NULL, "AIN3R" }
259 static unsigned int pcm3168a_scki_ratios[] = {
268 #define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios)
269 #define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2)
271 #define PCM1368A_MAX_SYSCLK 36864000
273 static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a)
277 ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0);
281 /* Internal reset is de-asserted after 3846 SCKI cycles */
282 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk));
284 return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE,
285 PCM3168A_MRST_MASK | PCM3168A_SRST_MASK);
288 static int pcm3168a_digital_mute(struct snd_soc_dai *dai, int mute)
290 struct snd_soc_codec *codec = dai->codec;
291 struct pcm3168a_priv *pcm3168a = snd_soc_codec_get_drvdata(codec);
293 regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0);
298 static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai,
299 int clk_id, unsigned int freq, int dir)
301 struct pcm3168a_priv *pcm3168a = snd_soc_codec_get_drvdata(dai->codec);
303 if (freq > PCM1368A_MAX_SYSCLK)
306 pcm3168a->sysclk = freq;
311 static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai,
312 unsigned int format, bool dac)
314 struct snd_soc_codec *codec = dai->codec;
315 struct pcm3168a_priv *pcm3168a = snd_soc_codec_get_drvdata(codec);
316 u32 fmt, reg, mask, shift;
319 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
320 case SND_SOC_DAIFMT_LEFT_J:
321 fmt = PCM3168A_FMT_LEFT_J;
323 case SND_SOC_DAIFMT_I2S:
324 fmt = PCM3168A_FMT_I2S;
326 case SND_SOC_DAIFMT_RIGHT_J:
327 fmt = PCM3168A_FMT_RIGHT_J;
329 case SND_SOC_DAIFMT_DSP_A:
330 fmt = PCM3168A_FMT_DSP_A;
332 case SND_SOC_DAIFMT_DSP_B:
333 fmt = PCM3168A_FMT_DSP_B;
336 dev_err(codec->dev, "unsupported dai format\n");
340 switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
341 case SND_SOC_DAIFMT_CBS_CFS:
344 case SND_SOC_DAIFMT_CBM_CFM:
348 dev_err(codec->dev, "unsupported master/slave mode\n");
352 switch (format & SND_SOC_DAIFMT_INV_MASK) {
353 case SND_SOC_DAIFMT_NB_NF:
360 reg = PCM3168A_DAC_PWR_MST_FMT;
361 mask = PCM3168A_DAC_FMT_MASK;
362 shift = PCM3168A_DAC_FMT_SHIFT;
363 pcm3168a->dac_master_mode = master_mode;
364 pcm3168a->dac_fmt = fmt;
366 reg = PCM3168A_ADC_MST_FMT;
367 mask = PCM3168A_ADC_FMTAD_MASK;
368 shift = PCM3168A_ADC_FMTAD_SHIFT;
369 pcm3168a->adc_master_mode = master_mode;
370 pcm3168a->adc_fmt = fmt;
373 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift);
378 static int pcm3168a_set_dai_fmt_dac(struct snd_soc_dai *dai,
381 return pcm3168a_set_dai_fmt(dai, format, true);
384 static int pcm3168a_set_dai_fmt_adc(struct snd_soc_dai *dai,
387 return pcm3168a_set_dai_fmt(dai, format, false);
390 static int pcm3168a_hw_params(struct snd_pcm_substream *substream,
391 struct snd_pcm_hw_params *params,
392 struct snd_soc_dai *dai)
394 struct snd_soc_codec *codec = dai->codec;
395 struct pcm3168a_priv *pcm3168a = snd_soc_codec_get_drvdata(codec);
396 bool tx, master_mode;
397 u32 val, mask, shift, reg;
398 unsigned int rate, channels, fmt, ratio, max_ratio;
399 int i, min_frame_size;
400 snd_pcm_format_t format;
402 rate = params_rate(params);
403 format = params_format(params);
404 channels = params_channels(params);
406 ratio = pcm3168a->sysclk / rate;
408 tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
410 max_ratio = PCM3168A_NUM_SCKI_RATIOS_DAC;
411 reg = PCM3168A_DAC_PWR_MST_FMT;
412 mask = PCM3168A_DAC_MSDA_MASK;
413 shift = PCM3168A_DAC_MSDA_SHIFT;
414 master_mode = pcm3168a->dac_master_mode;
415 fmt = pcm3168a->dac_fmt;
417 max_ratio = PCM3168A_NUM_SCKI_RATIOS_ADC;
418 reg = PCM3168A_ADC_MST_FMT;
419 mask = PCM3168A_ADC_MSAD_MASK;
420 shift = PCM3168A_ADC_MSAD_SHIFT;
421 master_mode = pcm3168a->adc_master_mode;
422 fmt = pcm3168a->adc_fmt;
425 for (i = 0; i < max_ratio; i++) {
426 if (pcm3168a_scki_ratios[i] == ratio)
430 if (i == max_ratio) {
431 dev_err(codec->dev, "unsupported sysclk ratio\n");
435 min_frame_size = params_width(params) * 2;
436 switch (min_frame_size) {
438 if (master_mode || (fmt != PCM3168A_FMT_RIGHT_J)) {
439 dev_err(codec->dev, "32-bit frames are supported only for slave mode using right justified\n");
442 fmt = PCM3168A_FMT_RIGHT_J_16;
445 if (master_mode || (fmt & PCM3168A_FMT_DSP_MASK)) {
446 dev_err(codec->dev, "48-bit frames not supported in master mode, or slave mode using DSP\n");
453 dev_err(codec->dev, "unsupported frame size: %d\n", min_frame_size);
458 val = ((i + 1) << shift);
462 regmap_update_bits(pcm3168a->regmap, reg, mask, val);
465 mask = PCM3168A_DAC_FMT_MASK;
466 shift = PCM3168A_DAC_FMT_SHIFT;
468 mask = PCM3168A_ADC_FMTAD_MASK;
469 shift = PCM3168A_ADC_FMTAD_SHIFT;
472 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift);
477 static const struct snd_soc_dai_ops pcm3168a_dac_dai_ops = {
478 .set_fmt = pcm3168a_set_dai_fmt_dac,
479 .set_sysclk = pcm3168a_set_dai_sysclk,
480 .hw_params = pcm3168a_hw_params,
481 .digital_mute = pcm3168a_digital_mute
484 static const struct snd_soc_dai_ops pcm3168a_adc_dai_ops = {
485 .set_fmt = pcm3168a_set_dai_fmt_adc,
486 .set_sysclk = pcm3168a_set_dai_sysclk,
487 .hw_params = pcm3168a_hw_params
490 static struct snd_soc_dai_driver pcm3168a_dais[] = {
492 .name = "pcm3168a-dac",
494 .stream_name = "Playback",
497 .rates = SNDRV_PCM_RATE_8000_192000,
498 .formats = PCM3168A_FORMATS
500 .ops = &pcm3168a_dac_dai_ops
503 .name = "pcm3168a-adc",
505 .stream_name = "Capture",
508 .rates = SNDRV_PCM_RATE_8000_96000,
509 .formats = PCM3168A_FORMATS
511 .ops = &pcm3168a_adc_dai_ops
515 static const struct reg_default pcm3168a_reg_default[] = {
516 { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK },
517 { PCM3168A_DAC_PWR_MST_FMT, 0x00 },
518 { PCM3168A_DAC_OP_FLT, 0x00 },
519 { PCM3168A_DAC_INV, 0x00 },
520 { PCM3168A_DAC_MUTE, 0x00 },
521 { PCM3168A_DAC_ZERO, 0x00 },
522 { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 },
523 { PCM3168A_DAC_VOL_MASTER, 0xff },
524 { PCM3168A_DAC_VOL_CHAN_START, 0xff },
525 { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff },
526 { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff },
527 { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff },
528 { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff },
529 { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff },
530 { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff },
531 { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff },
532 { PCM3168A_ADC_SMODE, 0x00 },
533 { PCM3168A_ADC_MST_FMT, 0x00 },
534 { PCM3168A_ADC_PWR_HPFB, 0x00 },
535 { PCM3168A_ADC_SEAD, 0x00 },
536 { PCM3168A_ADC_INV, 0x00 },
537 { PCM3168A_ADC_MUTE, 0x00 },
538 { PCM3168A_ADC_OV, 0x00 },
539 { PCM3168A_ADC_ATT_OVF, 0x00 },
540 { PCM3168A_ADC_VOL_MASTER, 0xd3 },
541 { PCM3168A_ADC_VOL_CHAN_START, 0xd3 },
542 { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 },
543 { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 },
544 { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 },
545 { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 },
546 { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 }
549 static bool pcm3168a_readable_register(struct device *dev, unsigned int reg)
551 if (reg >= PCM3168A_RST_SMODE)
557 static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg)
560 case PCM3168A_DAC_ZERO:
561 case PCM3168A_ADC_OV:
568 static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg)
570 if (reg < PCM3168A_RST_SMODE)
574 case PCM3168A_DAC_ZERO:
575 case PCM3168A_ADC_OV:
582 const struct regmap_config pcm3168a_regmap = {
586 .max_register = PCM3168A_ADC_VOL_CHAN_START + 5,
587 .reg_defaults = pcm3168a_reg_default,
588 .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default),
589 .readable_reg = pcm3168a_readable_register,
590 .volatile_reg = pcm3168a_volatile_register,
591 .writeable_reg = pcm3168a_writeable_register,
592 .cache_type = REGCACHE_FLAT
594 EXPORT_SYMBOL_GPL(pcm3168a_regmap);
596 static const struct snd_soc_codec_driver pcm3168a_driver = {
597 .idle_bias_off = true,
598 .controls = pcm3168a_snd_controls,
599 .num_controls = ARRAY_SIZE(pcm3168a_snd_controls),
600 .dapm_widgets = pcm3168a_dapm_widgets,
601 .num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets),
602 .dapm_routes = pcm3168a_dapm_routes,
603 .num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes)
606 int pcm3168a_probe(struct device *dev, struct regmap *regmap)
608 struct pcm3168a_priv *pcm3168a;
611 pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL);
612 if (pcm3168a == NULL)
615 dev_set_drvdata(dev, pcm3168a);
617 pcm3168a->scki = devm_clk_get(dev, "scki");
618 if (IS_ERR(pcm3168a->scki)) {
619 ret = PTR_ERR(pcm3168a->scki);
620 if (ret != -EPROBE_DEFER)
621 dev_err(dev, "failed to acquire clock 'scki': %d\n", ret);
625 ret = clk_prepare_enable(pcm3168a->scki);
627 dev_err(dev, "Failed to enable mclk: %d\n", ret);
631 pcm3168a->sysclk = clk_get_rate(pcm3168a->scki);
633 for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++)
634 pcm3168a->supplies[i].supply = pcm3168a_supply_names[i];
636 ret = devm_regulator_bulk_get(dev,
637 ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies);
639 if (ret != -EPROBE_DEFER)
640 dev_err(dev, "failed to request supplies: %d\n", ret);
644 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
647 dev_err(dev, "failed to enable supplies: %d\n", ret);
651 pcm3168a->regmap = regmap;
652 if (IS_ERR(pcm3168a->regmap)) {
653 ret = PTR_ERR(pcm3168a->regmap);
654 dev_err(dev, "failed to allocate regmap: %d\n", ret);
658 ret = pcm3168a_reset(pcm3168a);
660 dev_err(dev, "Failed to reset device: %d\n", ret);
664 pm_runtime_set_active(dev);
665 pm_runtime_enable(dev);
666 pm_runtime_idle(dev);
668 ret = snd_soc_register_codec(dev, &pcm3168a_driver, pcm3168a_dais,
669 ARRAY_SIZE(pcm3168a_dais));
671 dev_err(dev, "failed to register codec: %d\n", ret);
678 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
681 clk_disable_unprepare(pcm3168a->scki);
685 EXPORT_SYMBOL_GPL(pcm3168a_probe);
687 void pcm3168a_remove(struct device *dev)
689 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
691 snd_soc_unregister_codec(dev);
692 pm_runtime_disable(dev);
693 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
695 clk_disable_unprepare(pcm3168a->scki);
697 EXPORT_SYMBOL_GPL(pcm3168a_remove);
700 static int pcm3168a_rt_resume(struct device *dev)
702 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
705 ret = clk_prepare_enable(pcm3168a->scki);
707 dev_err(dev, "Failed to enable mclk: %d\n", ret);
711 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
714 dev_err(dev, "Failed to enable supplies: %d\n", ret);
718 ret = pcm3168a_reset(pcm3168a);
720 dev_err(dev, "Failed to reset device: %d\n", ret);
724 regcache_cache_only(pcm3168a->regmap, false);
726 regcache_mark_dirty(pcm3168a->regmap);
728 ret = regcache_sync(pcm3168a->regmap);
730 dev_err(dev, "Failed to sync regmap: %d\n", ret);
737 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
740 clk_disable_unprepare(pcm3168a->scki);
745 static int pcm3168a_rt_suspend(struct device *dev)
747 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
749 regcache_cache_only(pcm3168a->regmap, true);
751 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
754 clk_disable_unprepare(pcm3168a->scki);
760 const struct dev_pm_ops pcm3168a_pm_ops = {
761 SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL)
763 EXPORT_SYMBOL_GPL(pcm3168a_pm_ops);
765 MODULE_DESCRIPTION("PCM3168A codec driver");
766 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
767 MODULE_LICENSE("GPL v2");