2 * rt5663.c -- RT5668/RT5663 ALSA SoC audio codec driver
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Jack Yu <jack.yu@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
16 #include <linux/i2c.h>
17 #include <linux/platform_device.h>
18 #include <linux/spi/spi.h>
19 #include <linux/acpi.h>
20 #include <linux/workqueue.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
33 #define RT5668_DEVICE_ID 0x6451
34 #define RT5663_DEVICE_ID 0x6406
42 struct snd_soc_codec *codec;
43 struct regmap *regmap;
44 struct delayed_work jack_detect_work;
45 struct snd_soc_jack *hs_jack;
46 struct timer_list btn_check_timer;
60 static const struct reg_default rt5668_reg[] = {
462 static const struct reg_default rt5663_reg[] = {
720 static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
724 case RT5663_SIL_DET_CTL:
725 case RT5663_HP_IMP_GAIN_2:
726 case RT5663_AD_DA_MIXER:
727 case RT5663_FRAC_DIV_2:
728 case RT5663_MICBIAS_1:
729 case RT5663_ASRC_11_2:
730 case RT5663_ADC_EQ_1:
731 case RT5663_INT_ST_1:
732 case RT5663_INT_ST_2:
733 case RT5663_GPIO_STA:
734 case RT5663_SIN_GEN_1:
735 case RT5663_IL_CMD_1:
736 case RT5663_IL_CMD_5:
737 case RT5663_IL_CMD_PWRSAV1:
738 case RT5663_EM_JACK_TYPE_1:
739 case RT5663_EM_JACK_TYPE_2:
740 case RT5663_EM_JACK_TYPE_3:
741 case RT5663_JD_CTRL2:
742 case RT5663_VENDOR_ID:
743 case RT5663_VENDOR_ID_1:
744 case RT5663_VENDOR_ID_2:
745 case RT5663_PLL_INT_REG:
746 case RT5663_SOFT_RAMP:
747 case RT5663_STO_DRE_1:
748 case RT5663_STO_DRE_5:
749 case RT5663_STO_DRE_6:
750 case RT5663_STO_DRE_7:
751 case RT5663_MIC_DECRO_1:
752 case RT5663_MIC_DECRO_4:
753 case RT5663_HP_IMP_SEN_1:
754 case RT5663_HP_IMP_SEN_3:
755 case RT5663_HP_IMP_SEN_4:
756 case RT5663_HP_IMP_SEN_5:
757 case RT5663_HP_CALIB_1_1:
758 case RT5663_HP_CALIB_9:
759 case RT5663_HP_CALIB_ST1:
760 case RT5663_HP_CALIB_ST2:
761 case RT5663_HP_CALIB_ST3:
762 case RT5663_HP_CALIB_ST4:
763 case RT5663_HP_CALIB_ST5:
764 case RT5663_HP_CALIB_ST6:
765 case RT5663_HP_CALIB_ST7:
766 case RT5663_HP_CALIB_ST8:
767 case RT5663_HP_CALIB_ST9:
775 static bool rt5663_readable_register(struct device *dev, unsigned int reg)
779 case RT5663_HP_OUT_EN:
780 case RT5663_HP_LCH_DRE:
781 case RT5663_HP_RCH_DRE:
782 case RT5663_CALIB_BST:
784 case RT5663_SIL_DET_CTL:
785 case RT5663_PWR_SAV_SILDET:
786 case RT5663_SIDETONE_CTL:
787 case RT5663_STO1_DAC_DIG_VOL:
788 case RT5663_STO1_ADC_DIG_VOL:
789 case RT5663_STO1_BOOST:
790 case RT5663_HP_IMP_GAIN_1:
791 case RT5663_HP_IMP_GAIN_2:
792 case RT5663_STO1_ADC_MIXER:
793 case RT5663_AD_DA_MIXER:
794 case RT5663_STO_DAC_MIXER:
795 case RT5663_DIG_SIDE_MIXER:
796 case RT5663_BYPASS_STO_DAC:
797 case RT5663_CALIB_REC_MIX:
798 case RT5663_PWR_DIG_1:
799 case RT5663_PWR_DIG_2:
800 case RT5663_PWR_ANLG_1:
801 case RT5663_PWR_ANLG_2:
802 case RT5663_PWR_ANLG_3:
803 case RT5663_PWR_MIXER:
804 case RT5663_SIG_CLK_DET:
805 case RT5663_PRE_DIV_GATING_1:
806 case RT5663_PRE_DIV_GATING_2:
807 case RT5663_I2S1_SDP:
808 case RT5663_ADDA_CLK_1:
809 case RT5663_ADDA_RST:
810 case RT5663_FRAC_DIV_1:
811 case RT5663_FRAC_DIV_2:
823 case RT5663_DUMMY_REG:
830 case RT5663_HP_CHARGE_PUMP_1:
831 case RT5663_HP_CHARGE_PUMP_2:
832 case RT5663_MICBIAS_1:
834 case RT5663_ASRC_11_2:
835 case RT5663_DUMMY_REG_2:
836 case RT5663_REC_PATH_GAIN:
837 case RT5663_AUTO_1MRC_CLK:
838 case RT5663_ADC_EQ_1:
839 case RT5663_ADC_EQ_2:
845 case RT5663_INT_ST_1:
846 case RT5663_INT_ST_2:
849 case RT5663_GPIO_STA:
850 case RT5663_SIN_GEN_1:
851 case RT5663_SIN_GEN_2:
852 case RT5663_SIN_GEN_3:
853 case RT5663_SOF_VOL_ZC1:
854 case RT5663_IL_CMD_1:
855 case RT5663_IL_CMD_2:
856 case RT5663_IL_CMD_3:
857 case RT5663_IL_CMD_4:
858 case RT5663_IL_CMD_5:
859 case RT5663_IL_CMD_6:
860 case RT5663_IL_CMD_7:
861 case RT5663_IL_CMD_8:
862 case RT5663_IL_CMD_PWRSAV1:
863 case RT5663_IL_CMD_PWRSAV2:
864 case RT5663_EM_JACK_TYPE_1:
865 case RT5663_EM_JACK_TYPE_2:
866 case RT5663_EM_JACK_TYPE_3:
867 case RT5663_EM_JACK_TYPE_4:
868 case RT5663_EM_JACK_TYPE_5:
869 case RT5663_EM_JACK_TYPE_6:
870 case RT5663_STO1_HPF_ADJ1:
871 case RT5663_STO1_HPF_ADJ2:
872 case RT5663_FAST_OFF_MICBIAS:
873 case RT5663_JD_CTRL1:
874 case RT5663_JD_CTRL2:
875 case RT5663_DIG_MISC:
876 case RT5663_VENDOR_ID:
877 case RT5663_VENDOR_ID_1:
878 case RT5663_VENDOR_ID_2:
879 case RT5663_DIG_VOL_ZCD:
880 case RT5663_ANA_BIAS_CUR_1:
881 case RT5663_ANA_BIAS_CUR_2:
882 case RT5663_ANA_BIAS_CUR_3:
883 case RT5663_ANA_BIAS_CUR_4:
884 case RT5663_ANA_BIAS_CUR_5:
885 case RT5663_ANA_BIAS_CUR_6:
886 case RT5663_BIAS_CUR_5:
887 case RT5663_BIAS_CUR_6:
888 case RT5663_BIAS_CUR_7:
889 case RT5663_BIAS_CUR_8:
890 case RT5663_DACREF_LDO:
891 case RT5663_DUMMY_REG_3:
892 case RT5663_BIAS_CUR_9:
893 case RT5663_DUMMY_REG_4:
894 case RT5663_VREFADJ_OP:
895 case RT5663_VREF_RECMIX:
896 case RT5663_CHARGE_PUMP_1:
897 case RT5663_CHARGE_PUMP_1_2:
898 case RT5663_CHARGE_PUMP_1_3:
899 case RT5663_CHARGE_PUMP_2:
900 case RT5663_DIG_IN_PIN1:
901 case RT5663_PAD_DRV_CTL:
902 case RT5663_PLL_INT_REG:
903 case RT5663_CHOP_DAC_L:
904 case RT5663_CHOP_ADC:
905 case RT5663_CALIB_ADC:
906 case RT5663_CHOP_DAC_R:
907 case RT5663_DUMMY_CTL_DACLR:
908 case RT5663_DUMMY_REG_5:
909 case RT5663_SOFT_RAMP:
910 case RT5663_TEST_MODE_1:
911 case RT5663_TEST_MODE_2:
912 case RT5663_TEST_MODE_3:
913 case RT5663_STO_DRE_1:
914 case RT5663_STO_DRE_2:
915 case RT5663_STO_DRE_3:
916 case RT5663_STO_DRE_4:
917 case RT5663_STO_DRE_5:
918 case RT5663_STO_DRE_6:
919 case RT5663_STO_DRE_7:
920 case RT5663_STO_DRE_8:
921 case RT5663_STO_DRE_9:
922 case RT5663_STO_DRE_10:
923 case RT5663_MIC_DECRO_1:
924 case RT5663_MIC_DECRO_2:
925 case RT5663_MIC_DECRO_3:
926 case RT5663_MIC_DECRO_4:
927 case RT5663_MIC_DECRO_5:
928 case RT5663_MIC_DECRO_6:
929 case RT5663_HP_DECRO_1:
930 case RT5663_HP_DECRO_2:
931 case RT5663_HP_DECRO_3:
932 case RT5663_HP_DECRO_4:
933 case RT5663_HP_DECOUP:
934 case RT5663_HP_IMP_SEN_MAP8:
935 case RT5663_HP_IMP_SEN_MAP9:
936 case RT5663_HP_IMP_SEN_MAP10:
937 case RT5663_HP_IMP_SEN_MAP11:
938 case RT5663_HP_IMP_SEN_1:
939 case RT5663_HP_IMP_SEN_2:
940 case RT5663_HP_IMP_SEN_3:
941 case RT5663_HP_IMP_SEN_4:
942 case RT5663_HP_IMP_SEN_5:
943 case RT5663_HP_IMP_SEN_6:
944 case RT5663_HP_IMP_SEN_7:
945 case RT5663_HP_IMP_SEN_8:
946 case RT5663_HP_IMP_SEN_9:
947 case RT5663_HP_IMP_SEN_10:
948 case RT5663_HP_IMP_SEN_11:
949 case RT5663_HP_IMP_SEN_12:
950 case RT5663_HP_IMP_SEN_13:
951 case RT5663_HP_IMP_SEN_14:
952 case RT5663_HP_IMP_SEN_15:
953 case RT5663_HP_IMP_SEN_16:
954 case RT5663_HP_IMP_SEN_17:
955 case RT5663_HP_IMP_SEN_18:
956 case RT5663_HP_IMP_SEN_19:
957 case RT5663_HP_IMPSEN_DIG5:
958 case RT5663_HP_IMPSEN_MAP1:
959 case RT5663_HP_IMPSEN_MAP2:
960 case RT5663_HP_IMPSEN_MAP3:
961 case RT5663_HP_IMPSEN_MAP4:
962 case RT5663_HP_IMPSEN_MAP5:
963 case RT5663_HP_IMPSEN_MAP7:
964 case RT5663_HP_LOGIC_1:
965 case RT5663_HP_LOGIC_2:
966 case RT5663_HP_CALIB_1:
967 case RT5663_HP_CALIB_1_1:
968 case RT5663_HP_CALIB_2:
969 case RT5663_HP_CALIB_3:
970 case RT5663_HP_CALIB_4:
971 case RT5663_HP_CALIB_5:
972 case RT5663_HP_CALIB_5_1:
973 case RT5663_HP_CALIB_6:
974 case RT5663_HP_CALIB_7:
975 case RT5663_HP_CALIB_9:
976 case RT5663_HP_CALIB_10:
977 case RT5663_HP_CALIB_11:
978 case RT5663_HP_CALIB_ST1:
979 case RT5663_HP_CALIB_ST2:
980 case RT5663_HP_CALIB_ST3:
981 case RT5663_HP_CALIB_ST4:
982 case RT5663_HP_CALIB_ST5:
983 case RT5663_HP_CALIB_ST6:
984 case RT5663_HP_CALIB_ST7:
985 case RT5663_HP_CALIB_ST8:
986 case RT5663_HP_CALIB_ST9:
987 case RT5663_HP_AMP_DET:
988 case RT5663_DUMMY_REG_6:
997 case RT5663_ADC_LCH_LPF1_A1:
998 case RT5663_ADC_RCH_LPF1_A1:
999 case RT5663_ADC_LCH_LPF1_H0:
1000 case RT5663_ADC_RCH_LPF1_H0:
1001 case RT5663_ADC_LCH_BPF1_A1:
1002 case RT5663_ADC_RCH_BPF1_A1:
1003 case RT5663_ADC_LCH_BPF1_A2:
1004 case RT5663_ADC_RCH_BPF1_A2:
1005 case RT5663_ADC_LCH_BPF1_H0:
1006 case RT5663_ADC_RCH_BPF1_H0:
1007 case RT5663_ADC_LCH_BPF2_A1:
1008 case RT5663_ADC_RCH_BPF2_A1:
1009 case RT5663_ADC_LCH_BPF2_A2:
1010 case RT5663_ADC_RCH_BPF2_A2:
1011 case RT5663_ADC_LCH_BPF2_H0:
1012 case RT5663_ADC_RCH_BPF2_H0:
1013 case RT5663_ADC_LCH_BPF3_A1:
1014 case RT5663_ADC_RCH_BPF3_A1:
1015 case RT5663_ADC_LCH_BPF3_A2:
1016 case RT5663_ADC_RCH_BPF3_A2:
1017 case RT5663_ADC_LCH_BPF3_H0:
1018 case RT5663_ADC_RCH_BPF3_H0:
1019 case RT5663_ADC_LCH_BPF4_A1:
1020 case RT5663_ADC_RCH_BPF4_A1:
1021 case RT5663_ADC_LCH_BPF4_A2:
1022 case RT5663_ADC_RCH_BPF4_A2:
1023 case RT5663_ADC_LCH_BPF4_H0:
1024 case RT5663_ADC_RCH_BPF4_H0:
1025 case RT5663_ADC_LCH_HPF1_A1:
1026 case RT5663_ADC_RCH_HPF1_A1:
1027 case RT5663_ADC_LCH_HPF1_H0:
1028 case RT5663_ADC_RCH_HPF1_H0:
1029 case RT5663_ADC_EQ_PRE_VOL_L:
1030 case RT5663_ADC_EQ_PRE_VOL_R:
1031 case RT5663_ADC_EQ_POST_VOL_L:
1032 case RT5663_ADC_EQ_POST_VOL_R:
1039 static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
1043 case RT5668_CBJ_TYPE_2:
1044 case RT5668_PDM_OUT_CTL:
1045 case RT5668_PDM_I2C_DATA_CTL1:
1046 case RT5668_PDM_I2C_DATA_CTL4:
1047 case RT5668_ALC_BK_GAIN:
1049 case RT5663_MICBIAS_1:
1050 case RT5663_ADC_EQ_1:
1051 case RT5663_INT_ST_1:
1052 case RT5668_GPIO_STA:
1053 case RT5663_IL_CMD_1:
1054 case RT5663_IL_CMD_5:
1055 case RT5668_A_JD_CTRL:
1056 case RT5663_JD_CTRL2:
1057 case RT5663_VENDOR_ID:
1058 case RT5663_VENDOR_ID_1:
1059 case RT5663_VENDOR_ID_2:
1060 case RT5663_STO_DRE_1:
1061 case RT5663_STO_DRE_5:
1062 case RT5663_STO_DRE_6:
1063 case RT5663_STO_DRE_7:
1064 case RT5668_MONO_DYNA_6:
1065 case RT5668_STO1_SIL_DET:
1066 case RT5668_MONOL_SIL_DET:
1067 case RT5668_MONOR_SIL_DET:
1068 case RT5668_STO2_DAC_SIL:
1069 case RT5668_MONO_AMP_CAL_ST1:
1070 case RT5668_MONO_AMP_CAL_ST2:
1071 case RT5668_MONO_AMP_CAL_ST3:
1072 case RT5668_MONO_AMP_CAL_ST4:
1073 case RT5663_HP_IMP_SEN_2:
1074 case RT5663_HP_IMP_SEN_3:
1075 case RT5663_HP_IMP_SEN_4:
1076 case RT5663_HP_IMP_SEN_10:
1077 case RT5663_HP_CALIB_1:
1078 case RT5663_HP_CALIB_10:
1079 case RT5663_HP_CALIB_ST1:
1080 case RT5663_HP_CALIB_ST4:
1081 case RT5663_HP_CALIB_ST5:
1082 case RT5663_HP_CALIB_ST6:
1083 case RT5663_HP_CALIB_ST7:
1084 case RT5663_HP_CALIB_ST8:
1085 case RT5663_HP_CALIB_ST9:
1086 case RT5668_HP_CALIB_ST10:
1087 case RT5668_HP_CALIB_ST11:
1094 static bool rt5668_readable_register(struct device *dev, unsigned int reg)
1097 case RT5668_LOUT_CTRL:
1098 case RT5668_HP_AMP_2:
1099 case RT5668_MONO_OUT:
1100 case RT5668_MONO_GAIN:
1101 case RT5668_AEC_BST:
1102 case RT5668_IN1_IN2:
1103 case RT5668_IN3_IN4:
1104 case RT5668_INL1_INR1:
1105 case RT5668_CBJ_TYPE_2:
1106 case RT5668_CBJ_TYPE_3:
1107 case RT5668_CBJ_TYPE_4:
1108 case RT5668_CBJ_TYPE_5:
1109 case RT5668_CBJ_TYPE_8:
1110 case RT5668_DAC3_DIG_VOL:
1111 case RT5668_DAC3_CTRL:
1112 case RT5668_MONO_ADC_DIG_VOL:
1113 case RT5668_STO2_ADC_DIG_VOL:
1114 case RT5668_MONO_ADC_BST_GAIN:
1115 case RT5668_STO2_ADC_BST_GAIN:
1116 case RT5668_SIDETONE_CTRL:
1117 case RT5668_MONO1_ADC_MIXER:
1118 case RT5668_STO2_ADC_MIXER:
1119 case RT5668_MONO_DAC_MIXER:
1120 case RT5668_DAC2_SRC_CTRL:
1121 case RT5668_IF_3_4_DATA_CTL:
1122 case RT5668_IF_5_DATA_CTL:
1123 case RT5668_PDM_OUT_CTL:
1124 case RT5668_PDM_I2C_DATA_CTL1:
1125 case RT5668_PDM_I2C_DATA_CTL2:
1126 case RT5668_PDM_I2C_DATA_CTL3:
1127 case RT5668_PDM_I2C_DATA_CTL4:
1128 case RT5668_RECMIX1_NEW:
1129 case RT5668_RECMIX1L_0:
1130 case RT5668_RECMIX1L:
1131 case RT5668_RECMIX1R_0:
1132 case RT5668_RECMIX1R:
1133 case RT5668_RECMIX2_NEW:
1134 case RT5668_RECMIX2_L_2:
1135 case RT5668_RECMIX2_R:
1136 case RT5668_RECMIX2_R_2:
1137 case RT5668_CALIB_REC_LR:
1138 case RT5668_ALC_BK_GAIN:
1139 case RT5668_MONOMIX_GAIN:
1140 case RT5668_MONOMIX_IN_GAIN:
1141 case RT5668_OUT_MIXL_GAIN:
1142 case RT5668_OUT_LMIX_IN_GAIN:
1143 case RT5668_OUT_RMIX_IN_GAIN:
1144 case RT5668_OUT_RMIX_IN_GAIN1:
1145 case RT5668_LOUT_MIXER_CTRL:
1146 case RT5668_PWR_VOL:
1147 case RT5668_ADCDAC_RST:
1148 case RT5668_I2S34_SDP:
1149 case RT5668_I2S5_SDP:
1157 case RT5668_PLL_TRK_13:
1158 case RT5668_I2S_M_CLK_CTL:
1159 case RT5668_FDIV_I2S34_M_CLK:
1160 case RT5668_FDIV_I2S34_M_CLK2:
1161 case RT5668_FDIV_I2S5_M_CLK:
1162 case RT5668_FDIV_I2S5_M_CLK2:
1166 case RT5668_GPIO_STA:
1167 case RT5668_HP_AMP_DET1:
1168 case RT5668_HP_AMP_DET2:
1169 case RT5668_HP_AMP_DET3:
1170 case RT5668_MID_BD_HP_AMP:
1171 case RT5668_LOW_BD_HP_AMP:
1172 case RT5668_SOF_VOL_ZC2:
1173 case RT5668_ADC_STO2_ADJ1:
1174 case RT5668_ADC_STO2_ADJ2:
1175 case RT5668_A_JD_CTRL:
1176 case RT5668_JD1_TRES_CTRL:
1177 case RT5668_JD2_TRES_CTRL:
1178 case RT5668_JD_CTRL2:
1179 case RT5668_DUM_REG_2:
1180 case RT5668_DUM_REG_3:
1181 case RT5663_VENDOR_ID:
1182 case RT5663_VENDOR_ID_1:
1183 case RT5663_VENDOR_ID_2:
1184 case RT5668_DACADC_DIG_VOL2:
1185 case RT5668_DIG_IN_PIN2:
1186 case RT5668_PAD_DRV_CTL1:
1187 case RT5668_SOF_RAM_DEPOP:
1188 case RT5668_VOL_TEST:
1189 case RT5668_TEST_MODE_3:
1190 case RT5668_TEST_MODE_4:
1191 case RT5663_STO_DRE_9:
1192 case RT5668_MONO_DYNA_1:
1193 case RT5668_MONO_DYNA_2:
1194 case RT5668_MONO_DYNA_3:
1195 case RT5668_MONO_DYNA_4:
1196 case RT5668_MONO_DYNA_5:
1197 case RT5668_MONO_DYNA_6:
1198 case RT5668_STO1_SIL_DET:
1199 case RT5668_MONOL_SIL_DET:
1200 case RT5668_MONOR_SIL_DET:
1201 case RT5668_STO2_DAC_SIL:
1202 case RT5668_PWR_SAV_CTL1:
1203 case RT5668_PWR_SAV_CTL2:
1204 case RT5668_PWR_SAV_CTL3:
1205 case RT5668_PWR_SAV_CTL4:
1206 case RT5668_PWR_SAV_CTL5:
1207 case RT5668_PWR_SAV_CTL6:
1208 case RT5668_MONO_AMP_CAL1:
1209 case RT5668_MONO_AMP_CAL2:
1210 case RT5668_MONO_AMP_CAL3:
1211 case RT5668_MONO_AMP_CAL4:
1212 case RT5668_MONO_AMP_CAL5:
1213 case RT5668_MONO_AMP_CAL6:
1214 case RT5668_MONO_AMP_CAL7:
1215 case RT5668_MONO_AMP_CAL_ST1:
1216 case RT5668_MONO_AMP_CAL_ST2:
1217 case RT5668_MONO_AMP_CAL_ST3:
1218 case RT5668_MONO_AMP_CAL_ST4:
1219 case RT5668_MONO_AMP_CAL_ST5:
1220 case RT5668_HP_IMP_SEN_13:
1221 case RT5668_HP_IMP_SEN_14:
1222 case RT5668_HP_IMP_SEN_6:
1223 case RT5668_HP_IMP_SEN_7:
1224 case RT5668_HP_IMP_SEN_8:
1225 case RT5668_HP_IMP_SEN_9:
1226 case RT5668_HP_IMP_SEN_10:
1227 case RT5668_HP_LOGIC_3:
1228 case RT5668_HP_CALIB_ST10:
1229 case RT5668_HP_CALIB_ST11:
1230 case RT5668_PRO_REG_TBL_4:
1231 case RT5668_PRO_REG_TBL_5:
1232 case RT5668_PRO_REG_TBL_6:
1233 case RT5668_PRO_REG_TBL_7:
1234 case RT5668_PRO_REG_TBL_8:
1235 case RT5668_PRO_REG_TBL_9:
1236 case RT5668_SAR_ADC_INL_1:
1237 case RT5668_SAR_ADC_INL_2:
1238 case RT5668_SAR_ADC_INL_3:
1239 case RT5668_SAR_ADC_INL_4:
1240 case RT5668_SAR_ADC_INL_5:
1241 case RT5668_SAR_ADC_INL_6:
1242 case RT5668_SAR_ADC_INL_7:
1243 case RT5668_SAR_ADC_INL_8:
1244 case RT5668_SAR_ADC_INL_9:
1245 case RT5668_SAR_ADC_INL_10:
1246 case RT5668_SAR_ADC_INL_11:
1247 case RT5668_SAR_ADC_INL_12:
1248 case RT5668_DRC_CTRL_1:
1249 case RT5668_DRC1_CTRL_2:
1250 case RT5668_DRC1_CTRL_3:
1251 case RT5668_DRC1_CTRL_4:
1252 case RT5668_DRC1_CTRL_5:
1253 case RT5668_DRC1_CTRL_6:
1254 case RT5668_DRC1_HD_CTRL_1:
1255 case RT5668_DRC1_HD_CTRL_2:
1256 case RT5668_DRC1_PRI_REG_1:
1257 case RT5668_DRC1_PRI_REG_2:
1258 case RT5668_DRC1_PRI_REG_3:
1259 case RT5668_DRC1_PRI_REG_4:
1260 case RT5668_DRC1_PRI_REG_5:
1261 case RT5668_DRC1_PRI_REG_6:
1262 case RT5668_DRC1_PRI_REG_7:
1263 case RT5668_DRC1_PRI_REG_8:
1264 case RT5668_ALC_PGA_CTL_1:
1265 case RT5668_ALC_PGA_CTL_2:
1266 case RT5668_ALC_PGA_CTL_3:
1267 case RT5668_ALC_PGA_CTL_4:
1268 case RT5668_ALC_PGA_CTL_5:
1269 case RT5668_ALC_PGA_CTL_6:
1270 case RT5668_ALC_PGA_CTL_7:
1271 case RT5668_ALC_PGA_CTL_8:
1272 case RT5668_ALC_PGA_REG_1:
1273 case RT5668_ALC_PGA_REG_2:
1274 case RT5668_ALC_PGA_REG_3:
1275 case RT5668_ADC_EQ_RECOV_1:
1276 case RT5668_ADC_EQ_RECOV_2:
1277 case RT5668_ADC_EQ_RECOV_3:
1278 case RT5668_ADC_EQ_RECOV_4:
1279 case RT5668_ADC_EQ_RECOV_5:
1280 case RT5668_ADC_EQ_RECOV_6:
1281 case RT5668_ADC_EQ_RECOV_7:
1282 case RT5668_ADC_EQ_RECOV_8:
1283 case RT5668_ADC_EQ_RECOV_9:
1284 case RT5668_ADC_EQ_RECOV_10:
1285 case RT5668_ADC_EQ_RECOV_11:
1286 case RT5668_ADC_EQ_RECOV_12:
1287 case RT5668_ADC_EQ_RECOV_13:
1288 case RT5668_VID_HIDDEN:
1289 case RT5668_VID_CUSTOMER:
1290 case RT5668_SCAN_MODE:
1291 case RT5668_I2C_BYPA:
1294 case RT5663_DEPOP_3:
1295 case RT5663_ASRC_11_2:
1296 case RT5663_INT_ST_2:
1297 case RT5663_GPIO_STA:
1298 case RT5663_SIN_GEN_1:
1299 case RT5663_SIN_GEN_2:
1300 case RT5663_SIN_GEN_3:
1301 case RT5663_IL_CMD_PWRSAV1:
1302 case RT5663_IL_CMD_PWRSAV2:
1303 case RT5663_EM_JACK_TYPE_1:
1304 case RT5663_EM_JACK_TYPE_2:
1305 case RT5663_EM_JACK_TYPE_3:
1306 case RT5663_EM_JACK_TYPE_4:
1307 case RT5663_FAST_OFF_MICBIAS:
1308 case RT5663_ANA_BIAS_CUR_1:
1309 case RT5663_ANA_BIAS_CUR_2:
1310 case RT5663_BIAS_CUR_9:
1311 case RT5663_DUMMY_REG_4:
1312 case RT5663_VREF_RECMIX:
1313 case RT5663_CHARGE_PUMP_1_2:
1314 case RT5663_CHARGE_PUMP_1_3:
1315 case RT5663_CHARGE_PUMP_2:
1316 case RT5663_CHOP_DAC_R:
1317 case RT5663_DUMMY_CTL_DACLR:
1318 case RT5663_DUMMY_REG_5:
1319 case RT5663_SOFT_RAMP:
1320 case RT5663_TEST_MODE_1:
1321 case RT5663_STO_DRE_10:
1322 case RT5663_MIC_DECRO_1:
1323 case RT5663_MIC_DECRO_2:
1324 case RT5663_MIC_DECRO_3:
1325 case RT5663_MIC_DECRO_4:
1326 case RT5663_MIC_DECRO_5:
1327 case RT5663_MIC_DECRO_6:
1328 case RT5663_HP_DECRO_1:
1329 case RT5663_HP_DECRO_2:
1330 case RT5663_HP_DECRO_3:
1331 case RT5663_HP_DECRO_4:
1332 case RT5663_HP_DECOUP:
1333 case RT5663_HP_IMPSEN_MAP4:
1334 case RT5663_HP_IMPSEN_MAP5:
1335 case RT5663_HP_IMPSEN_MAP7:
1336 case RT5663_HP_CALIB_1:
1342 return rt5663_readable_register(dev, reg);
1346 static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1347 static const DECLARE_TLV_DB_SCALE(rt5668_hp_vol_tlv, -2250, 150, 0);
1348 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1349 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1351 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
1352 static const DECLARE_TLV_DB_RANGE(in_bst_tlv,
1353 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
1354 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
1355 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
1356 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
1357 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
1358 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
1359 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
1362 /* Interface data select */
1363 static const char * const rt5663_if1_adc_data_select[] = {
1364 "L/R", "R/L", "L/L", "R/R"
1367 static SOC_ENUM_SINGLE_DECL(rt5663_if1_adc_enum, RT5663_TDM_2,
1368 RT5663_DATA_SWAP_ADCDAT1_SHIFT, rt5663_if1_adc_data_select);
1370 static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
1373 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1376 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1377 RT5668_EN_4BTN_INL_MASK, RT5668_EN_4BTN_INL_EN);
1378 /* reset in-line command */
1379 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1380 RT5668_RESET_4BTN_INL_MASK,
1381 RT5668_RESET_4BTN_INL_RESET);
1382 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1383 RT5668_RESET_4BTN_INL_MASK,
1384 RT5668_RESET_4BTN_INL_NOR);
1385 switch (rt5663->codec_type) {
1386 case CODEC_TYPE_RT5668:
1387 snd_soc_update_bits(codec, RT5663_IRQ_3,
1388 RT5668_EN_IRQ_INLINE_MASK,
1389 RT5668_EN_IRQ_INLINE_NOR);
1391 case CODEC_TYPE_RT5663:
1392 snd_soc_update_bits(codec, RT5663_IRQ_2,
1393 RT5663_EN_IRQ_INLINE_MASK,
1394 RT5663_EN_IRQ_INLINE_NOR);
1397 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1400 switch (rt5663->codec_type) {
1401 case CODEC_TYPE_RT5668:
1402 snd_soc_update_bits(codec, RT5663_IRQ_3,
1403 RT5668_EN_IRQ_INLINE_MASK,
1404 RT5668_EN_IRQ_INLINE_BYP);
1406 case CODEC_TYPE_RT5663:
1407 snd_soc_update_bits(codec, RT5663_IRQ_2,
1408 RT5663_EN_IRQ_INLINE_MASK,
1409 RT5663_EN_IRQ_INLINE_BYP);
1412 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1414 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1415 RT5668_EN_4BTN_INL_MASK, RT5668_EN_4BTN_INL_DIS);
1416 /* reset in-line command */
1417 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1418 RT5668_RESET_4BTN_INL_MASK,
1419 RT5668_RESET_4BTN_INL_RESET);
1420 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1421 RT5668_RESET_4BTN_INL_MASK,
1422 RT5668_RESET_4BTN_INL_NOR);
1427 * rt5668_jack_detect - Detect headset.
1428 * @codec: SoC audio codec device.
1429 * @jack_insert: Jack insert or not.
1431 * Detect whether is headset or not when jack inserted.
1433 * Returns detect status.
1436 static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1438 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1439 struct rt5663_priv *rt5668 = snd_soc_codec_get_drvdata(codec);
1440 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1442 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1444 snd_soc_write(codec, RT5668_CBJ_TYPE_2, 0x8040);
1445 snd_soc_write(codec, RT5668_CBJ_TYPE_3, 0x1484);
1447 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1448 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
1449 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
1450 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1451 snd_soc_dapm_sync(dapm);
1452 snd_soc_update_bits(codec, RT5663_RC_CLK,
1453 RT5668_DIG_1M_CLK_MASK, RT5668_DIG_1M_CLK_EN);
1454 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8);
1457 msleep(sleep_time[i]);
1458 val = snd_soc_read(codec, RT5668_CBJ_TYPE_2) & 0x0003;
1459 if (val == 0x1 || val == 0x2 || val == 0x3)
1461 dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n",
1462 __func__, val, sleep_time[i]);
1465 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
1469 rt5668->jack_type = SND_JACK_HEADSET;
1470 rt5663_enable_push_button_irq(codec, true);
1473 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1474 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1475 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1476 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1477 snd_soc_dapm_sync(dapm);
1478 rt5668->jack_type = SND_JACK_HEADPHONE;
1482 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0);
1484 if (rt5668->jack_type == SND_JACK_HEADSET) {
1485 rt5663_enable_push_button_irq(codec, false);
1486 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1487 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
1488 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1489 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1490 snd_soc_dapm_sync(dapm);
1492 rt5668->jack_type = 0;
1495 dev_dbg(codec->dev, "jack_type = %d\n", rt5668->jack_type);
1496 return rt5668->jack_type;
1500 * rt5663_jack_detect - Detect headset.
1501 * @codec: SoC audio codec device.
1502 * @jack_insert: Jack insert or not.
1504 * Detect whether is headset or not when jack inserted.
1506 * Returns detect status.
1508 static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1510 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1511 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1513 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1516 snd_soc_update_bits(codec, RT5663_DIG_MISC,
1517 RT5668_DIG_GATE_CTRL_MASK, RT5668_DIG_GATE_CTRL_EN);
1518 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
1519 RT5663_SI_HP_MASK | RT5668_OSW_HP_L_MASK |
1520 RT5668_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1521 RT5668_OSW_HP_L_DIS | RT5668_OSW_HP_R_DIS);
1522 snd_soc_update_bits(codec, RT5663_DUMMY_1,
1523 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1524 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
1525 RT5663_HPA_CPL_BIAS_1 | RT5663_HPA_CPR_BIAS_1);
1526 snd_soc_update_bits(codec, RT5663_CBJ_1,
1527 RT5663_INBUF_CBJ_BST1_MASK | RT5663_CBJ_SENSE_BST1_MASK,
1528 RT5663_INBUF_CBJ_BST1_ON | RT5663_CBJ_SENSE_BST1_L);
1529 snd_soc_update_bits(codec, RT5663_IL_CMD_2,
1530 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1531 /* BST1 power on for JD */
1532 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
1533 RT5668_PWR_BST1_MASK, RT5668_PWR_BST1_ON);
1534 snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1,
1535 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1536 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1537 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1538 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
1539 RT5668_PWR_MB_MASK | RT5668_LDO1_DVO_MASK |
1540 RT5668_AMP_HP_MASK, RT5668_PWR_MB |
1541 RT5668_LDO1_DVO_0_9V | RT5668_AMP_HP_3X);
1542 snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK,
1543 RT5668_IRQ_POW_SAV_MASK, RT5668_IRQ_POW_SAV_EN);
1544 snd_soc_update_bits(codec, RT5663_IRQ_1,
1545 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
1547 msleep(sleep_time[i]);
1548 val = snd_soc_read(codec, RT5663_EM_JACK_TYPE_2) &
1551 if (val == 0x1 || val == 0x2 || val == 0x3)
1553 dev_dbg(codec->dev, "%s: MX-00e7 val=%x sleep %d\n",
1554 __func__, val, sleep_time[i]);
1556 dev_dbg(codec->dev, "%s val = %d\n", __func__, val);
1560 rt5663->jack_type = SND_JACK_HEADSET;
1561 rt5663_enable_push_button_irq(codec, true);
1564 rt5663->jack_type = SND_JACK_HEADPHONE;
1568 if (rt5663->jack_type == SND_JACK_HEADSET)
1569 rt5663_enable_push_button_irq(codec, false);
1570 rt5663->jack_type = 0;
1573 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1574 return rt5663->jack_type;
1577 static int rt5663_button_detect(struct snd_soc_codec *codec)
1581 val = snd_soc_read(codec, RT5663_IL_CMD_5);
1582 dev_dbg(codec->dev, "%s: val=0x%x\n", __func__, val);
1583 btn_type = val & 0xfff0;
1584 snd_soc_write(codec, RT5663_IL_CMD_5, val);
1589 static irqreturn_t rt5663_irq(int irq, void *data)
1591 struct rt5663_priv *rt5663 = data;
1593 dev_dbg(rt5663->codec->dev, "%s IRQ queue work\n", __func__);
1595 queue_delayed_work(system_wq, &rt5663->jack_detect_work,
1596 msecs_to_jiffies(250));
1601 int rt5663_set_jack_detect(struct snd_soc_codec *codec,
1602 struct snd_soc_jack *hs_jack)
1604 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1606 rt5663->hs_jack = hs_jack;
1608 rt5663_irq(0, rt5663);
1612 EXPORT_SYMBOL_GPL(rt5663_set_jack_detect);
1614 static bool rt5663_check_jd_status(struct snd_soc_codec *codec)
1616 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1617 int val = snd_soc_read(codec, RT5663_INT_ST_1);
1619 dev_dbg(codec->dev, "%s val=%x\n", __func__, val);
1622 switch (rt5663->codec_type) {
1623 case CODEC_TYPE_RT5668:
1624 return !(val & 0x2000);
1625 case CODEC_TYPE_RT5663:
1626 return !(val & 0x1000);
1628 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1634 static void rt5663_jack_detect_work(struct work_struct *work)
1636 struct rt5663_priv *rt5663 =
1637 container_of(work, struct rt5663_priv, jack_detect_work.work);
1638 struct snd_soc_codec *codec = rt5663->codec;
1639 int btn_type, report = 0;
1644 if (rt5663_check_jd_status(codec)) {
1646 if (rt5663->jack_type == 0) {
1647 /* jack was out, report jack type */
1648 switch (rt5663->codec_type) {
1649 case CODEC_TYPE_RT5668:
1650 report = rt5668_jack_detect(rt5663->codec, 1);
1652 case CODEC_TYPE_RT5663:
1653 report = rt5663_jack_detect(rt5663->codec, 1);
1656 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1659 /* jack is already in, report button event */
1660 report = SND_JACK_HEADSET;
1661 btn_type = rt5663_button_detect(rt5663->codec);
1663 * rt5663 can report three kinds of button behavior,
1664 * one click, double click and hold. However,
1665 * currently we will report button pressed/released
1666 * event. So all the three button behaviors are
1667 * treated as button pressed.
1673 report |= SND_JACK_BTN_0;
1678 report |= SND_JACK_BTN_1;
1683 report |= SND_JACK_BTN_2;
1688 report |= SND_JACK_BTN_3;
1690 case 0x0000: /* unpressed */
1694 dev_err(rt5663->codec->dev,
1695 "Unexpected button code 0x%04x\n",
1699 /* button release or spurious interrput*/
1701 report = rt5663->jack_type;
1705 switch (rt5663->codec_type) {
1706 case CODEC_TYPE_RT5668:
1707 report = rt5668_jack_detect(rt5663->codec, 0);
1709 case CODEC_TYPE_RT5663:
1710 report = rt5663_jack_detect(rt5663->codec, 0);
1713 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1716 dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report);
1717 snd_soc_jack_report(rt5663->hs_jack, report, SND_JACK_HEADSET |
1718 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1719 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1722 static const struct snd_kcontrol_new rt5663_snd_controls[] = {
1723 /* DAC Digital Volume */
1724 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
1725 RT5668_DAC_L1_VOL_SHIFT + 1, RT5668_DAC_R1_VOL_SHIFT + 1,
1726 87, 0, dac_vol_tlv),
1727 /* ADC Digital Volume Control */
1728 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
1729 RT5668_ADC_L_MUTE_SHIFT, RT5668_ADC_R_MUTE_SHIFT, 1, 1),
1730 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
1731 RT5668_ADC_L_VOL_SHIFT + 1, RT5668_ADC_R_VOL_SHIFT + 1,
1732 63, 0, adc_vol_tlv),
1735 static const struct snd_kcontrol_new rt5668_specific_controls[] = {
1736 /* Headphone Output Volume */
1737 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
1738 RT5663_HP_RCH_DRE, RT5668_GAIN_HP_SHIFT, 15, 1,
1740 /* Mic Boost Volume */
1741 SOC_SINGLE_TLV("IN1 Capture Volume", RT5668_AEC_BST,
1742 RT5668_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
1745 static const struct snd_kcontrol_new rt5663_specific_controls[] = {
1746 /* Headphone Output Volume */
1747 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_STO_DRE_9,
1748 RT5663_STO_DRE_10, RT5663_DRE_GAIN_HP_SHIFT, 23, 1,
1750 /* Mic Boost Volume*/
1751 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_CBJ_2,
1752 RT5663_GAIN_BST1_SHIFT, 8, 0, in_bst_tlv),
1753 /* Data Swap for Slot0/1 in ADCDAT1 */
1754 SOC_ENUM("IF1 ADC Data Swap", rt5663_if1_adc_enum),
1757 static int rt5663_is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1758 struct snd_soc_dapm_widget *sink)
1761 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1763 val = snd_soc_read(codec, RT5663_GLB_CLK);
1764 val &= RT5663_SCLK_SRC_MASK;
1765 if (val == RT5663_SCLK_SRC_PLL1)
1771 static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
1772 struct snd_soc_dapm_widget *sink)
1774 unsigned int reg, shift, val;
1775 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1776 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1778 if (rt5663->codec_type == CODEC_TYPE_RT5668) {
1780 case RT5668_ADC_STO1_ASRC_SHIFT:
1781 reg = RT5668_ASRC_3;
1782 shift = RT5668_AD_STO1_TRACK_SHIFT;
1784 case RT5668_DAC_STO1_ASRC_SHIFT:
1785 reg = RT5663_ASRC_2;
1786 shift = RT5668_DA_STO1_TRACK_SHIFT;
1793 case RT5663_ADC_STO1_ASRC_SHIFT:
1794 reg = RT5663_ASRC_2;
1795 shift = RT5663_AD_STO1_TRACK_SHIFT;
1797 case RT5663_DAC_STO1_ASRC_SHIFT:
1798 reg = RT5663_ASRC_2;
1799 shift = RT5663_DA_STO1_TRACK_SHIFT;
1806 val = (snd_soc_read(codec, reg) >> shift) & 0x7;
1814 static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
1815 struct snd_soc_dapm_widget *sink)
1817 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
1818 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1819 int da_asrc_en, ad_asrc_en;
1821 da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1822 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
1823 switch (rt5663->codec_type) {
1824 case CODEC_TYPE_RT5668:
1825 ad_asrc_en = (snd_soc_read(codec, RT5668_ASRC_3) &
1826 RT5668_AD_STO1_TRACK_MASK) ? 1 : 0;
1828 case CODEC_TYPE_RT5663:
1829 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1830 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
1833 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1837 if (da_asrc_en || ad_asrc_en)
1838 if (rt5663->sysclk > rt5663->lrck * 384)
1841 dev_err(codec->dev, "sysclk < 384 x fs, disable i2s asrc\n");
1847 * rt5663_sel_asrc_clk_src - select ASRC clock source for a set of filters
1848 * @codec: SoC audio codec device.
1849 * @filter_mask: mask of filters.
1850 * @clk_src: clock source
1852 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5668 can
1853 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1854 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1855 * ASRC function will track i2s clock and generate a corresponding system clock
1856 * for codec. This function provides an API to select the clock source for a
1857 * set of filters specified by the mask. And the codec driver will turn on ASRC
1858 * for these filters if ASRC is selected as their clock source.
1860 int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1861 unsigned int filter_mask, unsigned int clk_src)
1863 struct rt5663_priv *rt5668 = snd_soc_codec_get_drvdata(codec);
1864 unsigned int asrc2_mask = 0;
1865 unsigned int asrc2_value = 0;
1866 unsigned int asrc3_mask = 0;
1867 unsigned int asrc3_value = 0;
1870 case RT5663_CLK_SEL_SYS:
1871 case RT5663_CLK_SEL_I2S1_ASRC:
1878 if (filter_mask & RT5663_DA_STEREO_FILTER) {
1879 asrc2_mask |= RT5668_DA_STO1_TRACK_MASK;
1880 asrc2_value |= clk_src << RT5668_DA_STO1_TRACK_SHIFT;
1883 if (filter_mask & RT5663_AD_STEREO_FILTER) {
1884 switch (rt5668->codec_type) {
1885 case CODEC_TYPE_RT5668:
1886 asrc3_mask |= RT5668_AD_STO1_TRACK_MASK;
1887 asrc3_value |= clk_src << RT5668_AD_STO1_TRACK_SHIFT;
1889 case CODEC_TYPE_RT5663:
1890 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
1891 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
1894 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
1899 snd_soc_update_bits(codec, RT5663_ASRC_2, asrc2_mask,
1903 snd_soc_update_bits(codec, RT5668_ASRC_3, asrc3_mask,
1908 EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
1911 static const struct snd_kcontrol_new rt5668_recmix1l[] = {
1912 SOC_DAPM_SINGLE("BST2 Switch", RT5668_RECMIX1L,
1913 RT5668_RECMIX1L_BST2_SHIFT, 1, 1),
1914 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5668_RECMIX1L,
1915 RT5668_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
1918 static const struct snd_kcontrol_new rt5668_recmix1r[] = {
1919 SOC_DAPM_SINGLE("BST2 Switch", RT5668_RECMIX1R,
1920 RT5668_RECMIX1R_BST2_SHIFT, 1, 1),
1924 static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
1925 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
1926 RT5668_M_STO1_ADC_L1_SHIFT, 1, 1),
1927 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
1928 RT5668_M_STO1_ADC_L2_SHIFT, 1, 1),
1931 static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = {
1932 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
1933 RT5668_M_STO1_ADC_R1_SHIFT, 1, 1),
1934 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
1935 RT5668_M_STO1_ADC_R2_SHIFT, 1, 1),
1938 static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
1939 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
1940 RT5668_M_ADCMIX_L_SHIFT, 1, 1),
1941 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
1942 RT5668_M_DAC1_L_SHIFT, 1, 1),
1945 static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
1946 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
1947 RT5668_M_ADCMIX_R_SHIFT, 1, 1),
1948 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
1949 RT5668_M_DAC1_R_SHIFT, 1, 1),
1952 static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
1953 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
1954 RT5668_M_DAC_L1_STO_L_SHIFT, 1, 1),
1955 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
1956 RT5668_M_DAC_R1_STO_L_SHIFT, 1, 1),
1959 static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
1960 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
1961 RT5668_M_DAC_L1_STO_R_SHIFT, 1, 1),
1962 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
1963 RT5668_M_DAC_R1_STO_R_SHIFT, 1, 1),
1967 static const struct snd_kcontrol_new rt5668_hpo_switch =
1968 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_AMP_2,
1969 RT5668_EN_DAC_HPO_SHIFT, 1, 0);
1971 /* Stereo ADC source */
1972 static const char * const rt5668_sto1_adc_src[] = {
1976 static SOC_ENUM_SINGLE_DECL(rt5668_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
1977 RT5668_STO1_ADC_L_SRC_SHIFT, rt5668_sto1_adc_src);
1979 static const struct snd_kcontrol_new rt5668_sto1_adcl_mux =
1980 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5668_sto1_adcl_enum);
1982 static SOC_ENUM_SINGLE_DECL(rt5668_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
1983 RT5668_STO1_ADC_R_SRC_SHIFT, rt5668_sto1_adc_src);
1985 static const struct snd_kcontrol_new rt5668_sto1_adcr_mux =
1986 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5668_sto1_adcr_enum);
1988 /* RT5663: Analog DACL1 input source */
1989 static const char * const rt5663_alg_dacl_src[] = {
1990 "DAC L", "STO DAC MIXL"
1993 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacl_enum, RT5663_BYPASS_STO_DAC,
1994 RT5663_DACL1_SRC_SHIFT, rt5663_alg_dacl_src);
1996 static const struct snd_kcontrol_new rt5663_alg_dacl_mux =
1997 SOC_DAPM_ENUM("DAC L Mux", rt5663_alg_dacl_enum);
1999 /* RT5663: Analog DACR1 input source */
2000 static const char * const rt5663_alg_dacr_src[] = {
2001 "DAC R", "STO DAC MIXR"
2004 static SOC_ENUM_SINGLE_DECL(rt5663_alg_dacr_enum, RT5663_BYPASS_STO_DAC,
2005 RT5663_DACR1_SRC_SHIFT, rt5663_alg_dacr_src);
2007 static const struct snd_kcontrol_new rt5663_alg_dacr_mux =
2008 SOC_DAPM_ENUM("DAC R Mux", rt5663_alg_dacr_enum);
2010 static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2011 struct snd_kcontrol *kcontrol, int event)
2013 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2014 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2017 case SND_SOC_DAPM_POST_PMU:
2018 if (rt5663->codec_type == CODEC_TYPE_RT5668) {
2019 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2020 RT5668_SEL_PM_HP_SHIFT, RT5668_SEL_PM_HP_HIGH);
2021 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
2022 RT5668_HP_SIG_SRC1_MASK,
2023 RT5668_HP_SIG_SRC1_SILENCE);
2025 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
2026 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
2028 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030,
2030 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2031 RT5668_OVCD_HP_MASK, RT5668_OVCD_HP_DIS);
2032 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2033 snd_soc_write(codec, RT5663_HP_BIAS, 0xabba);
2034 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
2035 snd_soc_write(codec, RT5663_ANA_BIAS_CUR_1, 0x7766);
2036 snd_soc_write(codec, RT5663_HP_BIAS, 0xafaa);
2037 snd_soc_write(codec, RT5663_CHARGE_PUMP_2, 0x7777);
2038 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000,
2043 case SND_SOC_DAPM_PRE_PMD:
2044 if (rt5663->codec_type == CODEC_TYPE_RT5668) {
2045 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
2046 RT5668_HP_SIG_SRC1_MASK,
2047 RT5668_HP_SIG_SRC1_REG);
2049 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
2050 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2051 RT5668_OVCD_HP_MASK, RT5668_OVCD_HP_EN);
2052 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0);
2053 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
2065 static int rt5668_bst2_power(struct snd_soc_dapm_widget *w,
2066 struct snd_kcontrol *kcontrol, int event)
2068 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2071 case SND_SOC_DAPM_POST_PMU:
2072 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
2073 RT5668_PWR_BST2_MASK | RT5668_PWR_BST2_OP_MASK,
2074 RT5668_PWR_BST2 | RT5668_PWR_BST2_OP);
2077 case SND_SOC_DAPM_PRE_PMD:
2078 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
2079 RT5668_PWR_BST2_MASK | RT5668_PWR_BST2_OP_MASK, 0);
2089 static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2090 struct snd_kcontrol *kcontrol, int event)
2092 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2095 case SND_SOC_DAPM_POST_PMU:
2096 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0xff00);
2097 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0xfffc);
2100 case SND_SOC_DAPM_PRE_PMD:
2101 snd_soc_write(codec, RT5663_PRE_DIV_GATING_1, 0x0000);
2102 snd_soc_write(codec, RT5663_PRE_DIV_GATING_2, 0x0000);
2112 static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2113 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5668_PWR_PLL_SHIFT, 0,
2117 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
2118 RT5668_PWR_MB1_SHIFT, 0),
2119 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
2120 RT5668_PWR_MB2_SHIFT, 0),
2123 SND_SOC_DAPM_INPUT("IN1P"),
2124 SND_SOC_DAPM_INPUT("IN1N"),
2126 /* REC Mixer Power */
2127 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
2128 RT5668_PWR_RECMIX1_SHIFT, 0, NULL, 0),
2131 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2132 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
2133 RT5668_PWR_ADC_L1_SHIFT, 0, NULL, 0),
2134 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
2135 RT5668_CKGEN_ADCC_SHIFT, 0, NULL, 0),
2138 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
2139 0, 0, rt5663_sto1_adc_l_mix,
2140 ARRAY_SIZE(rt5663_sto1_adc_l_mix)),
2142 /* ADC Filter Power */
2143 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
2144 RT5668_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
2146 /* Digital Interface */
2147 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5668_PWR_I2S1_SHIFT, 0,
2149 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2150 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2151 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2152 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2153 SND_SOC_DAPM_PGA("IF ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2155 /* Audio Interface */
2156 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
2157 SND_SOC_DAPM_AIF_OUT("AIFTX", "AIF Capture", 0, SND_SOC_NOPM, 0, 0),
2159 /* DAC mixer before sound effect */
2160 SND_SOC_DAPM_MIXER("ADDA MIXL", SND_SOC_NOPM, 0, 0, rt5663_adda_l_mix,
2161 ARRAY_SIZE(rt5663_adda_l_mix)),
2162 SND_SOC_DAPM_MIXER("ADDA MIXR", SND_SOC_NOPM, 0, 0, rt5663_adda_r_mix,
2163 ARRAY_SIZE(rt5663_adda_r_mix)),
2164 SND_SOC_DAPM_PGA("DAC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2165 SND_SOC_DAPM_PGA("DAC R1", SND_SOC_NOPM, 0, 0, NULL, 0),
2168 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
2169 RT5668_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
2170 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2171 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2172 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
2173 rt5663_sto1_dac_r_mix, ARRAY_SIZE(rt5663_sto1_dac_r_mix)),
2176 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
2177 RT5668_PWR_DAC_L1_SHIFT, 0, NULL, 0),
2178 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
2179 RT5668_PWR_DAC_R1_SHIFT, 0, NULL, 0),
2180 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2181 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2184 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5663_hp_event,
2185 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2188 SND_SOC_DAPM_OUTPUT("HPOL"),
2189 SND_SOC_DAPM_OUTPUT("HPOR"),
2192 static const struct snd_soc_dapm_widget rt5668_specific_dapm_widgets[] = {
2193 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
2194 RT5668_PWR_LDO2_SHIFT, 0, NULL, 0),
2195 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5668_PWR_VOL,
2196 RT5668_PWR_MIC_DET_SHIFT, 0, NULL, 0),
2197 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
2198 RT5668_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2201 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2202 RT5668_I2S1_ASRC_SHIFT, 0, NULL, 0),
2203 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2204 RT5668_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2205 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2206 RT5668_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2209 SND_SOC_DAPM_INPUT("IN2P"),
2210 SND_SOC_DAPM_INPUT("IN2N"),
2213 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2214 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
2215 RT5668_PWR_CBJ_SHIFT, 0, NULL, 0),
2216 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2217 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
2218 rt5668_bst2_power, SND_SOC_DAPM_PRE_PMD |
2219 SND_SOC_DAPM_POST_PMU),
2222 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_recmix1l,
2223 ARRAY_SIZE(rt5668_recmix1l)),
2224 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5668_recmix1r,
2225 ARRAY_SIZE(rt5668_recmix1r)),
2226 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
2227 RT5668_PWR_RECMIX2_SHIFT, 0, NULL, 0),
2230 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2231 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
2232 RT5668_PWR_ADC_R1_SHIFT, 0, NULL, 0),
2235 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
2236 RT5668_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
2237 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
2238 RT5668_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
2239 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
2240 RT5668_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
2241 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
2242 RT5668_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
2244 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2245 &rt5668_sto1_adcl_mux),
2246 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2247 &rt5668_sto1_adcr_mux),
2250 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2251 rt5668_sto1_adc_r_mix, ARRAY_SIZE(rt5668_sto1_adc_r_mix)),
2253 /* Analog DAC Clock */
2254 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
2255 RT5668_CKGEN_DAC1_SHIFT, 0, NULL, 0),
2258 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
2259 &rt5668_hpo_switch),
2262 static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2263 /* System Clock Pre Divider Gating */
2264 SND_SOC_DAPM_SUPPLY("Pre Div Power", SND_SOC_NOPM, 0, 0,
2265 rt5663_pre_div_power, SND_SOC_DAPM_POST_PMU |
2266 SND_SOC_DAPM_PRE_PMD),
2269 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
2270 RT5668_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2273 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2274 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2275 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2276 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2277 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2278 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2281 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM, 0, 0, NULL, 0),
2284 SND_SOC_DAPM_PGA("STO1 ADC L1", SND_SOC_NOPM, 0, 0, NULL, 0),
2285 SND_SOC_DAPM_PGA("STO1 ADC L2", SND_SOC_NOPM, 0, 0, NULL, 0),
2287 /* Analog DAC source */
2288 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacl_mux),
2289 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0, &rt5663_alg_dacr_mux),
2292 static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2294 { "I2S", NULL, "PLL", rt5663_is_sys_clk_from_pll },
2297 { "STO1 ADC Filter", NULL, "ADC ASRC", rt5663_is_using_asrc },
2298 { "STO1 DAC Filter", NULL, "DAC ASRC", rt5663_is_using_asrc },
2299 { "I2S", NULL, "I2S ASRC", rt5663_i2s_use_asrc },
2301 { "ADC L", NULL, "ADC L Power" },
2302 { "ADC L", NULL, "ADC Clock" },
2304 { "STO1 ADC L2", NULL, "STO1 DAC MIXL" },
2306 { "STO1 ADC MIXL", "ADC1 Switch", "STO1 ADC L1" },
2307 { "STO1 ADC MIXL", "ADC2 Switch", "STO1 ADC L2" },
2308 { "STO1 ADC MIXL", NULL, "STO1 ADC Filter" },
2310 { "IF1 ADC1", NULL, "STO1 ADC MIXL" },
2311 { "IF ADC", NULL, "IF1 ADC1" },
2312 { "AIFTX", NULL, "IF ADC" },
2313 { "AIFTX", NULL, "I2S" },
2315 { "AIFRX", NULL, "I2S" },
2316 { "IF DAC", NULL, "AIFRX" },
2317 { "IF1 DAC1 L", NULL, "IF DAC" },
2318 { "IF1 DAC1 R", NULL, "IF DAC" },
2320 { "ADDA MIXL", "ADC L Switch", "STO1 ADC MIXL" },
2321 { "ADDA MIXL", "DAC L Switch", "IF1 DAC1 L" },
2322 { "ADDA MIXL", NULL, "STO1 DAC Filter" },
2323 { "ADDA MIXL", NULL, "STO1 DAC L Power" },
2324 { "ADDA MIXR", "DAC R Switch", "IF1 DAC1 R" },
2325 { "ADDA MIXR", NULL, "STO1 DAC Filter" },
2326 { "ADDA MIXR", NULL, "STO1 DAC R Power" },
2328 { "DAC L1", NULL, "ADDA MIXL" },
2329 { "DAC R1", NULL, "ADDA MIXR" },
2331 { "STO1 DAC MIXL", "DAC L Switch", "DAC L1" },
2332 { "STO1 DAC MIXL", "DAC R Switch", "DAC R1" },
2333 { "STO1 DAC MIXL", NULL, "STO1 DAC L Power" },
2334 { "STO1 DAC MIXL", NULL, "STO1 DAC Filter" },
2335 { "STO1 DAC MIXR", "DAC R Switch", "DAC R1" },
2336 { "STO1 DAC MIXR", "DAC L Switch", "DAC L1" },
2337 { "STO1 DAC MIXR", NULL, "STO1 DAC R Power" },
2338 { "STO1 DAC MIXR", NULL, "STO1 DAC Filter" },
2340 { "HP Amp", NULL, "DAC L" },
2341 { "HP Amp", NULL, "DAC R" },
2344 static const struct snd_soc_dapm_route rt5668_specific_dapm_routes[] = {
2345 { "MICBIAS1", NULL, "LDO2" },
2346 { "MICBIAS2", NULL, "LDO2" },
2348 { "BST1 CBJ", NULL, "IN1P" },
2349 { "BST1 CBJ", NULL, "IN1N" },
2350 { "BST1 CBJ", NULL, "CBJ Power" },
2352 { "BST2", NULL, "IN2P" },
2353 { "BST2", NULL, "IN2N" },
2354 { "BST2", NULL, "BST2 Power" },
2356 { "RECMIX1L", "BST2 Switch", "BST2" },
2357 { "RECMIX1L", "BST1 CBJ Switch", "BST1 CBJ" },
2358 { "RECMIX1L", NULL, "RECMIX1L Power" },
2359 { "RECMIX1R", "BST2 Switch", "BST2" },
2360 { "RECMIX1R", NULL, "RECMIX1R Power" },
2362 { "ADC L", NULL, "RECMIX1L" },
2363 { "ADC R", NULL, "RECMIX1R" },
2364 { "ADC R", NULL, "ADC R Power" },
2365 { "ADC R", NULL, "ADC Clock" },
2367 { "STO1 ADC L Mux", "ADC L", "ADC L" },
2368 { "STO1 ADC L Mux", "ADC R", "ADC R" },
2369 { "STO1 ADC L1", NULL, "STO1 ADC L Mux" },
2371 { "STO1 ADC R Mux", "ADC L", "ADC L" },
2372 { "STO1 ADC R Mux", "ADC R", "ADC R" },
2373 { "STO1 ADC R1", NULL, "STO1 ADC R Mux" },
2374 { "STO1 ADC R2", NULL, "STO1 DAC MIXR" },
2376 { "STO1 ADC MIXR", "ADC1 Switch", "STO1 ADC R1" },
2377 { "STO1 ADC MIXR", "ADC2 Switch", "STO1 ADC R2" },
2378 { "STO1 ADC MIXR", NULL, "STO1 ADC Filter" },
2380 { "IF1 ADC1", NULL, "STO1 ADC MIXR" },
2382 { "ADDA MIXR", "ADC R Switch", "STO1 ADC MIXR" },
2384 { "DAC L", NULL, "STO1 DAC MIXL" },
2385 { "DAC L", NULL, "LDO DAC" },
2386 { "DAC L", NULL, "DAC Clock" },
2387 { "DAC R", NULL, "STO1 DAC MIXR" },
2388 { "DAC R", NULL, "LDO DAC" },
2389 { "DAC R", NULL, "DAC Clock" },
2391 { "HPO Playback", "Switch", "HP Amp" },
2392 { "HPOL", NULL, "HPO Playback" },
2393 { "HPOR", NULL, "HPO Playback" },
2396 static const struct snd_soc_dapm_route rt5663_specific_dapm_routes[] = {
2397 { "I2S", NULL, "Pre Div Power" },
2399 { "BST1", NULL, "IN1P" },
2400 { "BST1", NULL, "IN1N" },
2401 { "BST1", NULL, "RECMIX1L Power" },
2403 { "ADC L", NULL, "BST1" },
2405 { "STO1 ADC L1", NULL, "ADC L" },
2407 { "DAC L Mux", "DAC L", "DAC L1" },
2408 { "DAC L Mux", "STO DAC MIXL", "STO1 DAC MIXL" },
2409 { "DAC R Mux", "DAC R", "DAC R1"},
2410 { "DAC R Mux", "STO DAC MIXR", "STO1 DAC MIXR" },
2412 { "DAC L", NULL, "DAC L Mux" },
2413 { "DAC R", NULL, "DAC R Mux" },
2415 { "HPOL", NULL, "HP Amp" },
2416 { "HPOR", NULL, "HP Amp" },
2419 static int rt5663_hw_params(struct snd_pcm_substream *substream,
2420 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2422 struct snd_soc_codec *codec = dai->codec;
2423 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2424 unsigned int val_len = 0;
2427 rt5663->lrck = params_rate(params);
2429 dev_dbg(dai->dev, "bclk is %dHz and sysclk is %dHz\n",
2430 rt5663->lrck, rt5663->sysclk);
2432 pre_div = rl6231_get_clk_info(rt5663->sysclk, rt5663->lrck);
2434 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
2435 rt5663->lrck, dai->id);
2439 dev_dbg(dai->dev, "pre_div is %d for iis %d\n", pre_div, dai->id);
2441 switch (params_width(params)) {
2443 val_len = RT5668_I2S_DL_8;
2446 val_len = RT5668_I2S_DL_16;
2449 val_len = RT5668_I2S_DL_20;
2452 val_len = RT5668_I2S_DL_24;
2458 snd_soc_update_bits(codec, RT5663_I2S1_SDP,
2459 RT5668_I2S_DL_MASK, val_len);
2461 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1,
2462 RT5668_I2S_PD1_MASK, pre_div << RT5668_I2S_PD1_SHIFT);
2467 static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2469 struct snd_soc_codec *codec = dai->codec;
2470 unsigned int reg_val = 0;
2472 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2473 case SND_SOC_DAIFMT_CBM_CFM:
2475 case SND_SOC_DAIFMT_CBS_CFS:
2476 reg_val |= RT5668_I2S_MS_S;
2482 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2483 case SND_SOC_DAIFMT_NB_NF:
2485 case SND_SOC_DAIFMT_IB_NF:
2486 reg_val |= RT5668_I2S_BP_INV;
2492 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2493 case SND_SOC_DAIFMT_I2S:
2495 case SND_SOC_DAIFMT_LEFT_J:
2496 reg_val |= RT5668_I2S_DF_LEFT;
2498 case SND_SOC_DAIFMT_DSP_A:
2499 reg_val |= RT5668_I2S_DF_PCM_A;
2501 case SND_SOC_DAIFMT_DSP_B:
2502 reg_val |= RT5668_I2S_DF_PCM_B;
2508 snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5668_I2S_MS_MASK |
2509 RT5668_I2S_BP_MASK | RT5668_I2S_DF_MASK, reg_val);
2514 static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2515 unsigned int freq, int dir)
2517 struct snd_soc_codec *codec = dai->codec;
2518 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2519 unsigned int reg_val = 0;
2521 if (freq == rt5663->sysclk && clk_id == rt5663->sysclk_src)
2525 case RT5663_SCLK_S_MCLK:
2526 reg_val |= RT5663_SCLK_SRC_MCLK;
2528 case RT5663_SCLK_S_PLL1:
2529 reg_val |= RT5663_SCLK_SRC_PLL1;
2531 case RT5663_SCLK_S_RCCLK:
2532 reg_val |= RT5663_SCLK_SRC_RCCLK;
2535 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2538 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5668_SCLK_SRC_MASK,
2540 rt5663->sysclk = freq;
2541 rt5663->sysclk_src = clk_id;
2543 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n",
2549 static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2550 unsigned int freq_in, unsigned int freq_out)
2552 struct snd_soc_codec *codec = dai->codec;
2553 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2554 struct rl6231_pll_code pll_code;
2556 int mask, shift, val;
2558 if (source == rt5663->pll_src && freq_in == rt5663->pll_in &&
2559 freq_out == rt5663->pll_out)
2562 if (!freq_in || !freq_out) {
2563 dev_dbg(codec->dev, "PLL disabled\n");
2566 rt5663->pll_out = 0;
2567 snd_soc_update_bits(codec, RT5663_GLB_CLK,
2568 RT5663_SCLK_SRC_MASK, RT5663_SCLK_SRC_MCLK);
2572 switch (rt5663->codec_type) {
2573 case CODEC_TYPE_RT5668:
2574 mask = RT5668_PLL1_SRC_MASK;
2575 shift = RT5668_PLL1_SRC_SHIFT;
2577 case CODEC_TYPE_RT5663:
2578 mask = RT5663_PLL1_SRC_MASK;
2579 shift = RT5663_PLL1_SRC_SHIFT;
2582 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
2587 case RT5663_PLL1_S_MCLK:
2590 case RT5663_PLL1_S_BCLK1:
2594 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2597 snd_soc_update_bits(codec, RT5663_GLB_CLK, mask, (val << shift));
2599 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2601 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2605 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", pll_code.m_bp,
2606 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
2609 snd_soc_write(codec, RT5663_PLL_1,
2610 pll_code.n_code << RT5668_PLL_N_SHIFT | pll_code.k_code);
2611 snd_soc_write(codec, RT5663_PLL_2,
2612 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SHIFT |
2613 pll_code.m_bp << RT5668_PLL_M_BP_SHIFT);
2615 rt5663->pll_in = freq_in;
2616 rt5663->pll_out = freq_out;
2617 rt5663->pll_src = source;
2622 static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2623 unsigned int rx_mask, int slots, int slot_width)
2625 struct snd_soc_codec *codec = dai->codec;
2626 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2627 unsigned int val = 0, reg;
2629 if (rx_mask || tx_mask)
2630 val |= RT5668_TDM_MODE_TDM;
2634 val |= RT5668_TDM_IN_CH_4;
2635 val |= RT5668_TDM_OUT_CH_4;
2638 val |= RT5668_TDM_IN_CH_6;
2639 val |= RT5668_TDM_OUT_CH_6;
2642 val |= RT5668_TDM_IN_CH_8;
2643 val |= RT5668_TDM_OUT_CH_8;
2651 switch (slot_width) {
2653 val |= RT5668_TDM_IN_LEN_20;
2654 val |= RT5668_TDM_OUT_LEN_20;
2657 val |= RT5668_TDM_IN_LEN_24;
2658 val |= RT5668_TDM_OUT_LEN_24;
2661 val |= RT5668_TDM_IN_LEN_32;
2662 val |= RT5668_TDM_OUT_LEN_32;
2670 switch (rt5663->codec_type) {
2671 case CODEC_TYPE_RT5668:
2674 case CODEC_TYPE_RT5663:
2678 dev_err(codec->dev, "Unknown CODEC_TYPE\n");
2682 snd_soc_update_bits(codec, reg, RT5668_TDM_MODE_MASK |
2683 RT5668_TDM_IN_CH_MASK | RT5668_TDM_OUT_CH_MASK |
2684 RT5668_TDM_IN_LEN_MASK | RT5668_TDM_OUT_LEN_MASK, val);
2689 static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2691 struct snd_soc_codec *codec = dai->codec;
2692 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2695 dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio);
2697 if (rt5663->codec_type == CODEC_TYPE_RT5668)
2704 snd_soc_update_bits(codec, reg,
2705 RT5663_TDM_LENGTN_MASK,
2706 RT5663_TDM_LENGTN_16);
2709 snd_soc_update_bits(codec, reg,
2710 RT5663_TDM_LENGTN_MASK,
2711 RT5663_TDM_LENGTN_20);
2714 snd_soc_update_bits(codec, reg,
2715 RT5663_TDM_LENGTN_MASK,
2716 RT5663_TDM_LENGTN_24);
2719 snd_soc_update_bits(codec, reg,
2720 RT5663_TDM_LENGTN_MASK,
2721 RT5663_TDM_LENGTN_32);
2724 dev_err(codec->dev, "Invalid ratio!\n");
2731 static int rt5663_set_bias_level(struct snd_soc_codec *codec,
2732 enum snd_soc_bias_level level)
2734 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2737 case SND_SOC_BIAS_ON:
2738 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
2739 RT5668_PWR_FV1_MASK | RT5668_PWR_FV2_MASK,
2740 RT5668_PWR_FV1 | RT5668_PWR_FV2);
2743 case SND_SOC_BIAS_PREPARE:
2744 if (rt5663->codec_type == CODEC_TYPE_RT5668) {
2745 snd_soc_update_bits(codec, RT5663_DIG_MISC,
2746 RT5668_DIG_GATE_CTRL_MASK,
2747 RT5668_DIG_GATE_CTRL_EN);
2748 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
2749 RT5668_EN_ANA_CLK_DET_MASK |
2750 RT5668_PWR_CLK_DET_MASK,
2751 RT5668_EN_ANA_CLK_DET_AUTO |
2752 RT5668_PWR_CLK_DET_EN);
2756 case SND_SOC_BIAS_STANDBY:
2757 if (rt5663->codec_type == CODEC_TYPE_RT5668)
2758 snd_soc_update_bits(codec, RT5663_DIG_MISC,
2759 RT5668_DIG_GATE_CTRL_MASK,
2760 RT5668_DIG_GATE_CTRL_DIS);
2761 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
2762 RT5668_PWR_VREF1_MASK | RT5668_PWR_VREF2_MASK |
2763 RT5668_PWR_FV1_MASK | RT5668_PWR_FV2_MASK |
2764 RT5668_PWR_MB_MASK, RT5668_PWR_VREF1 |
2765 RT5668_PWR_VREF2 | RT5668_PWR_MB);
2766 usleep_range(10000, 10005);
2767 if (rt5663->codec_type == CODEC_TYPE_RT5668) {
2768 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
2769 RT5668_EN_ANA_CLK_DET_MASK |
2770 RT5668_PWR_CLK_DET_MASK,
2771 RT5668_EN_ANA_CLK_DET_DIS |
2772 RT5668_PWR_CLK_DET_DIS);
2776 case SND_SOC_BIAS_OFF:
2777 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
2778 RT5668_PWR_VREF1_MASK | RT5668_PWR_VREF2_MASK |
2779 RT5668_PWR_FV1 | RT5668_PWR_FV2, 0x0);
2789 static int rt5663_probe(struct snd_soc_codec *codec)
2791 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
2792 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2794 rt5663->codec = codec;
2796 switch (rt5663->codec_type) {
2797 case CODEC_TYPE_RT5668:
2798 snd_soc_dapm_new_controls(dapm,
2799 rt5668_specific_dapm_widgets,
2800 ARRAY_SIZE(rt5668_specific_dapm_widgets));
2801 snd_soc_dapm_add_routes(dapm,
2802 rt5668_specific_dapm_routes,
2803 ARRAY_SIZE(rt5668_specific_dapm_routes));
2804 snd_soc_add_codec_controls(codec, rt5668_specific_controls,
2805 ARRAY_SIZE(rt5668_specific_controls));
2807 case CODEC_TYPE_RT5663:
2808 snd_soc_dapm_new_controls(dapm,
2809 rt5663_specific_dapm_widgets,
2810 ARRAY_SIZE(rt5663_specific_dapm_widgets));
2811 snd_soc_dapm_add_routes(dapm,
2812 rt5663_specific_dapm_routes,
2813 ARRAY_SIZE(rt5663_specific_dapm_routes));
2814 snd_soc_add_codec_controls(codec, rt5663_specific_controls,
2815 ARRAY_SIZE(rt5663_specific_controls));
2822 static int rt5663_remove(struct snd_soc_codec *codec)
2824 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2826 regmap_write(rt5663->regmap, RT5663_RESET, 0);
2832 static int rt5663_suspend(struct snd_soc_codec *codec)
2834 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2836 regcache_cache_only(rt5663->regmap, true);
2837 regcache_mark_dirty(rt5663->regmap);
2842 static int rt5663_resume(struct snd_soc_codec *codec)
2844 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
2846 regcache_cache_only(rt5663->regmap, false);
2847 regcache_sync(rt5663->regmap);
2852 #define rt5663_suspend NULL
2853 #define rt5663_resume NULL
2856 #define RT5663_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2857 #define RT5663_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2858 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2860 static struct snd_soc_dai_ops rt5663_aif_dai_ops = {
2861 .hw_params = rt5663_hw_params,
2862 .set_fmt = rt5663_set_dai_fmt,
2863 .set_sysclk = rt5663_set_dai_sysclk,
2864 .set_pll = rt5663_set_dai_pll,
2865 .set_tdm_slot = rt5663_set_tdm_slot,
2866 .set_bclk_ratio = rt5663_set_bclk_ratio,
2869 static struct snd_soc_dai_driver rt5663_dai[] = {
2871 .name = "rt5663-aif",
2874 .stream_name = "AIF Playback",
2877 .rates = RT5663_STEREO_RATES,
2878 .formats = RT5663_FORMATS,
2881 .stream_name = "AIF Capture",
2884 .rates = RT5663_STEREO_RATES,
2885 .formats = RT5663_FORMATS,
2887 .ops = &rt5663_aif_dai_ops,
2891 static struct snd_soc_codec_driver soc_codec_dev_rt5663 = {
2892 .probe = rt5663_probe,
2893 .remove = rt5663_remove,
2894 .suspend = rt5663_suspend,
2895 .resume = rt5663_resume,
2896 .set_bias_level = rt5663_set_bias_level,
2897 .idle_bias_off = true,
2898 .component_driver = {
2899 .controls = rt5663_snd_controls,
2900 .num_controls = ARRAY_SIZE(rt5663_snd_controls),
2901 .dapm_widgets = rt5663_dapm_widgets,
2902 .num_dapm_widgets = ARRAY_SIZE(rt5663_dapm_widgets),
2903 .dapm_routes = rt5663_dapm_routes,
2904 .num_dapm_routes = ARRAY_SIZE(rt5663_dapm_routes),
2908 static const struct regmap_config rt5668_regmap = {
2911 .use_single_rw = true,
2912 .max_register = 0x07fa,
2913 .volatile_reg = rt5668_volatile_register,
2914 .readable_reg = rt5668_readable_register,
2915 .cache_type = REGCACHE_RBTREE,
2916 .reg_defaults = rt5668_reg,
2917 .num_reg_defaults = ARRAY_SIZE(rt5668_reg),
2920 static const struct regmap_config rt5663_regmap = {
2923 .use_single_rw = true,
2924 .max_register = 0x03f3,
2925 .volatile_reg = rt5663_volatile_register,
2926 .readable_reg = rt5663_readable_register,
2927 .cache_type = REGCACHE_RBTREE,
2928 .reg_defaults = rt5663_reg,
2929 .num_reg_defaults = ARRAY_SIZE(rt5663_reg),
2932 static const struct regmap_config temp_regmap = {
2936 .use_single_rw = true,
2937 .max_register = 0x03f3,
2938 .cache_type = REGCACHE_NONE,
2941 static const struct i2c_device_id rt5663_i2c_id[] = {
2946 MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
2948 #if defined(CONFIG_OF)
2949 static const struct of_device_id rt5663_of_match[] = {
2950 { .compatible = "realtek,rt5668", },
2951 { .compatible = "realtek,rt5663", },
2954 MODULE_DEVICE_TABLE(of, rt5663_of_match);
2958 static struct acpi_device_id rt5663_acpi_match[] = {
2963 MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
2966 static void rt5668_calibrate(struct rt5663_priv *rt5668)
2968 regmap_write(rt5668->regmap, RT5663_BIAS_CUR_8, 0xa402);
2969 regmap_write(rt5668->regmap, RT5663_PWR_DIG_1, 0x0100);
2970 regmap_write(rt5668->regmap, RT5663_RECMIX, 0x4040);
2971 regmap_write(rt5668->regmap, RT5663_DIG_MISC, 0x0001);
2972 regmap_write(rt5668->regmap, RT5663_RC_CLK, 0x0380);
2973 regmap_write(rt5668->regmap, RT5663_GLB_CLK, 0x8000);
2974 regmap_write(rt5668->regmap, RT5663_ADDA_CLK_1, 0x1000);
2975 regmap_write(rt5668->regmap, RT5663_CHOP_DAC_L, 0x3030);
2976 regmap_write(rt5668->regmap, RT5663_CALIB_ADC, 0x3c05);
2977 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xa23e);
2979 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xf23e);
2980 regmap_write(rt5668->regmap, RT5663_HP_CALIB_2, 0x0321);
2981 regmap_write(rt5668->regmap, RT5663_HP_CALIB_1, 0xfc00);
2985 static void rt5663_calibrate(struct rt5663_priv *rt5668)
2989 regmap_write(rt5668->regmap, RT5663_RC_CLK, 0x0280);
2990 regmap_write(rt5668->regmap, RT5663_GLB_CLK, 0x8000);
2991 regmap_write(rt5668->regmap, RT5663_DIG_MISC, 0x8001);
2992 regmap_write(rt5668->regmap, RT5663_VREF_RECMIX, 0x0032);
2993 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xa2be);
2995 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xf2be);
2996 regmap_write(rt5668->regmap, RT5663_PWR_DIG_2, 0x8400);
2997 regmap_write(rt5668->regmap, RT5663_CHOP_ADC, 0x3000);
2998 regmap_write(rt5668->regmap, RT5663_DEPOP_1, 0x003b);
2999 regmap_write(rt5668->regmap, RT5663_PWR_DIG_1, 0x8df8);
3000 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_2, 0x0003);
3001 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_3, 0x018c);
3002 regmap_write(rt5668->regmap, RT5663_ADDA_CLK_1, 0x1111);
3003 regmap_write(rt5668->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3004 regmap_write(rt5668->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
3005 regmap_write(rt5668->regmap, RT5663_DEPOP_2, 0x3003);
3006 regmap_write(rt5668->regmap, RT5663_DEPOP_1, 0x003b);
3007 regmap_write(rt5668->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
3008 regmap_write(rt5668->regmap, RT5663_HP_CHARGE_PUMP_2, 0x1371);
3009 regmap_write(rt5668->regmap, RT5663_DACREF_LDO, 0x3b0b);
3010 regmap_write(rt5668->regmap, RT5663_STO_DAC_MIXER, 0x2080);
3011 regmap_write(rt5668->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
3012 regmap_write(rt5668->regmap, RT5663_HP_BIAS, 0xabba);
3013 regmap_write(rt5668->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3014 regmap_write(rt5668->regmap, RT5663_HP_OUT_EN, 0x8088);
3015 regmap_write(rt5668->regmap, RT5663_STO_DRE_9, 0x0017);
3016 regmap_write(rt5668->regmap, RT5663_STO_DRE_10, 0x0017);
3017 regmap_write(rt5668->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
3018 regmap_write(rt5668->regmap, RT5663_RECMIX, 0x0005);
3019 regmap_write(rt5668->regmap, RT5663_ADDA_RST, 0xc000);
3020 regmap_write(rt5668->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3021 regmap_write(rt5668->regmap, RT5663_HP_CALIB_2, 0x00c9);
3022 regmap_write(rt5668->regmap, RT5663_DUMMY_1, 0x004c);
3023 regmap_write(rt5668->regmap, RT5663_ANA_BIAS_CUR_1, 0x7766);
3024 regmap_write(rt5668->regmap, RT5663_BIAS_CUR_8, 0x4702);
3026 regmap_write(rt5668->regmap, RT5663_HP_CALIB_1, 0x0069);
3027 regmap_write(rt5668->regmap, RT5663_HP_CALIB_3, 0x06c2);
3028 regmap_write(rt5668->regmap, RT5663_HP_CALIB_1_1, 0x7b00);
3029 regmap_write(rt5668->regmap, RT5663_HP_CALIB_1_1, 0xfb00);
3032 regmap_read(rt5668->regmap, RT5663_HP_CALIB_1_1, &value);
3034 usleep_range(10000, 10005);
3044 static int rt5663_i2c_probe(struct i2c_client *i2c,
3045 const struct i2c_device_id *id)
3047 struct rt5663_priv *rt5663;
3050 struct regmap *regmap;
3052 rt5663 = devm_kzalloc(&i2c->dev, sizeof(struct rt5663_priv),
3058 i2c_set_clientdata(i2c, rt5663);
3060 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3061 if (IS_ERR(regmap)) {
3062 ret = PTR_ERR(regmap);
3063 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3067 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3069 case RT5668_DEVICE_ID:
3070 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap);
3071 rt5663->codec_type = CODEC_TYPE_RT5668;
3073 case RT5663_DEVICE_ID:
3074 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
3075 rt5663->codec_type = CODEC_TYPE_RT5663;
3079 "Device with ID register %#x is not rt5663 or rt5668\n",
3084 if (IS_ERR(rt5663->regmap)) {
3085 ret = PTR_ERR(rt5663->regmap);
3086 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3091 /* reset and calibrate */
3092 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3093 regcache_cache_bypass(rt5663->regmap, true);
3094 switch (rt5663->codec_type) {
3095 case CODEC_TYPE_RT5668:
3096 rt5668_calibrate(rt5663);
3098 case CODEC_TYPE_RT5663:
3099 rt5663_calibrate(rt5663);
3102 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3104 regcache_cache_bypass(rt5663->regmap, false);
3105 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3106 dev_dbg(&i2c->dev, "calibrate done\n");
3109 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5668_GP1_PIN_MASK,
3110 RT5668_GP1_PIN_IRQ);
3111 /* 4btn inline command debounce */
3112 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
3113 RT5668_4BTN_CLK_DEB_MASK, RT5668_4BTN_CLK_DEB_65MS);
3115 switch (rt5663->codec_type) {
3116 case CODEC_TYPE_RT5668:
3117 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3119 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3120 RT5668_IRQ_POW_SAV_MASK | RT5668_IRQ_POW_SAV_JD1_MASK,
3121 RT5668_IRQ_POW_SAV_EN | RT5668_IRQ_POW_SAV_JD1_EN);
3122 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
3123 RT5668_PWR_JD1_MASK, RT5668_PWR_JD1);
3124 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3125 RT5668_EN_CB_JD_MASK, RT5668_EN_CB_JD_EN);
3127 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
3128 RT5668_HP_SIG_SRC1_MASK, RT5668_HP_SIG_SRC1_REG);
3129 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3130 RT5668_VREF_BIAS_MASK | RT5668_CBJ_DET_MASK |
3131 RT5668_DET_TYPE_MASK, RT5668_VREF_BIAS_REG |
3132 RT5668_CBJ_DET_EN | RT5668_DET_TYPE_QFN);
3133 /* Set GPIO4 and GPIO8 as input for combo jack */
3134 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3135 RT5668_GP4_PIN_CONF_MASK, RT5668_GP4_PIN_CONF_INPUT);
3136 regmap_update_bits(rt5663->regmap, RT5668_GPIO_3,
3137 RT5668_GP8_PIN_CONF_MASK, RT5668_GP8_PIN_CONF_INPUT);
3138 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
3139 RT5668_LDO1_DVO_MASK | RT5668_AMP_HP_MASK,
3140 RT5668_LDO1_DVO_0_9V | RT5668_AMP_HP_3X);
3142 case CODEC_TYPE_RT5663:
3143 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
3144 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
3146 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
3147 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3148 RT5663_GP1_PIN_CONF_MASK, RT5663_GP1_PIN_CONF_OUTPUT);
3149 /* DACREF LDO control */
3150 regmap_update_bits(rt5663->regmap, RT5663_DACREF_LDO, 0x3e0e,
3152 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3153 RT5663_RECMIX1_BST1_MASK, RT5663_RECMIX1_BST1_ON);
3154 regmap_update_bits(rt5663->regmap, RT5663_TDM_2,
3155 RT5663_DATA_SWAP_ADCDAT1_MASK,
3156 RT5663_DATA_SWAP_ADCDAT1_LL);
3159 dev_err(&i2c->dev, "%s:Unknown codec type\n", __func__);
3162 INIT_DELAYED_WORK(&rt5663->jack_detect_work, rt5663_jack_detect_work);
3165 ret = request_irq(i2c->irq, rt5663_irq,
3166 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3167 | IRQF_ONESHOT, "rt5663", rt5663);
3169 dev_err(&i2c->dev, "%s Failed to reguest IRQ: %d\n",
3173 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5663,
3174 rt5663_dai, ARRAY_SIZE(rt5663_dai));
3178 free_irq(i2c->irq, rt5663);
3184 static int rt5663_i2c_remove(struct i2c_client *i2c)
3186 struct rt5663_priv *rt5663 = i2c_get_clientdata(i2c);
3189 free_irq(i2c->irq, rt5663);
3191 snd_soc_unregister_codec(&i2c->dev);
3196 static void rt5663_i2c_shutdown(struct i2c_client *client)
3198 struct rt5663_priv *rt5663 = i2c_get_clientdata(client);
3200 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3203 static struct i2c_driver rt5663_i2c_driver = {
3206 .acpi_match_table = ACPI_PTR(rt5663_acpi_match),
3207 .of_match_table = of_match_ptr(rt5663_of_match),
3209 .probe = rt5663_i2c_probe,
3210 .remove = rt5663_i2c_remove,
3211 .shutdown = rt5663_i2c_shutdown,
3212 .id_table = rt5663_i2c_id,
3214 module_i2c_driver(rt5663_i2c_driver);
3216 MODULE_DESCRIPTION("ASoC RT5663 driver");
3217 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
3218 MODULE_LICENSE("GPL v2");