]> git.karo-electronics.de Git - karo-tx-linux.git/blob - sound/soc/codecs/rt5663.h
Merge tag 'gvt-fixes-2017-03-23' of https://github.com/01org/gvt-linux into drm-intel...
[karo-tx-linux.git] / sound / soc / codecs / rt5663.h
1 /*
2  * rt5663.h  --  RT5663 ALSA SoC audio driver
3  *
4  * Copyright 2016 Realtek Microelectronics
5  * Author: Jack Yu <jack.yu@realtek.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #ifndef __RT5663_H__
13 #define __RT5663_H__
14
15 /* Info */
16 #define RT5663_RESET                            0x0000
17 #define RT5663_VENDOR_ID                        0x00fd
18 #define RT5663_VENDOR_ID_1                      0x00fe
19 #define RT5663_VENDOR_ID_2                      0x00ff
20
21 #define RT5663_LOUT_CTRL                        0x0001
22 #define RT5663_HP_AMP_2                         0x0003
23 #define RT5663_MONO_OUT                         0x0004
24 #define RT5663_MONO_GAIN                        0x0007
25
26 #define RT5663_AEC_BST                          0x000b
27 #define RT5663_IN1_IN2                          0x000c
28 #define RT5663_IN3_IN4                          0x000d
29 #define RT5663_INL1_INR1                        0x000f
30 #define RT5663_CBJ_TYPE_2                       0x0011
31 #define RT5663_CBJ_TYPE_3                       0x0012
32 #define RT5663_CBJ_TYPE_4                       0x0013
33 #define RT5663_CBJ_TYPE_5                       0x0014
34 #define RT5663_CBJ_TYPE_8                       0x0017
35
36 /* I/O - ADC/DAC/DMIC */
37 #define RT5663_DAC3_DIG_VOL                     0x001a
38 #define RT5663_DAC3_CTRL                        0x001b
39 #define RT5663_MONO_ADC_DIG_VOL                 0x001d
40 #define RT5663_STO2_ADC_DIG_VOL                 0x001e
41 #define RT5663_MONO_ADC_BST_GAIN                0x0020
42 #define RT5663_STO2_ADC_BST_GAIN                0x0021
43 #define RT5663_SIDETONE_CTRL                    0x0024
44 /* Mixer - D-D */
45 #define RT5663_MONO1_ADC_MIXER                  0x0027
46 #define RT5663_STO2_ADC_MIXER                   0x0028
47 #define RT5663_MONO_DAC_MIXER                   0x002b
48 #define RT5663_DAC2_SRC_CTRL                    0x002e
49 #define RT5663_IF_3_4_DATA_CTL                  0x002f
50 #define RT5663_IF_5_DATA_CTL                    0x0030
51 #define RT5663_PDM_OUT_CTL                      0x0031
52 #define RT5663_PDM_I2C_DATA_CTL1                0x0032
53 #define RT5663_PDM_I2C_DATA_CTL2                0x0033
54 #define RT5663_PDM_I2C_DATA_CTL3                0x0034
55 #define RT5663_PDM_I2C_DATA_CTL4                0x0035
56
57 /*Mixer - Analog*/
58 #define RT5663_RECMIX1_NEW                      0x003a
59 #define RT5663_RECMIX1L_0                       0x003b
60 #define RT5663_RECMIX1L                         0x003c
61 #define RT5663_RECMIX1R_0                       0x003d
62 #define RT5663_RECMIX1R                         0x003e
63 #define RT5663_RECMIX2_NEW                      0x003f
64 #define RT5663_RECMIX2_L_2                      0x0041
65 #define RT5663_RECMIX2_R                        0x0042
66 #define RT5663_RECMIX2_R_2                      0x0043
67 #define RT5663_CALIB_REC_LR                     0x0044
68 #define RT5663_ALC_BK_GAIN                      0x0049
69 #define RT5663_MONOMIX_GAIN                     0x004a
70 #define RT5663_MONOMIX_IN_GAIN                  0x004b
71 #define RT5663_OUT_MIXL_GAIN                    0x004d
72 #define RT5663_OUT_LMIX_IN_GAIN                 0x004e
73 #define RT5663_OUT_RMIX_IN_GAIN                 0x004f
74 #define RT5663_OUT_RMIX_IN_GAIN1                0x0050
75 #define RT5663_LOUT_MIXER_CTRL                  0x0052
76 /* Power */
77 #define RT5663_PWR_VOL                          0x0067
78
79 #define RT5663_ADCDAC_RST                       0x006d
80 /* Format - ADC/DAC */
81 #define RT5663_I2S34_SDP                        0x0071
82 #define RT5663_I2S5_SDP                         0x0072
83
84 /* Function - Analog */
85 #define RT5663_ASRC_3                           0x0085
86 #define RT5663_ASRC_6                           0x0088
87 #define RT5663_ASRC_7                           0x0089
88 #define RT5663_PLL_TRK_13                       0x0099
89 #define RT5663_I2S_M_CLK_CTL                    0x00a0
90 #define RT5663_FDIV_I2S34_M_CLK                 0x00a1
91 #define RT5663_FDIV_I2S34_M_CLK2                0x00a2
92 #define RT5663_FDIV_I2S5_M_CLK                  0x00a3
93 #define RT5663_FDIV_I2S5_M_CLK2                 0x00a4
94
95 /* Function - Digital */
96 #define RT5663_V2_IRQ_4                         0x00b9
97 #define RT5663_GPIO_3                           0x00c2
98 #define RT5663_GPIO_4                           0x00c3
99 #define RT5663_GPIO_STA2                        0x00c4
100 #define RT5663_HP_AMP_DET1                      0x00d0
101 #define RT5663_HP_AMP_DET2                      0x00d1
102 #define RT5663_HP_AMP_DET3                      0x00d2
103 #define RT5663_MID_BD_HP_AMP                    0x00d3
104 #define RT5663_LOW_BD_HP_AMP                    0x00d4
105 #define RT5663_SOF_VOL_ZC2                      0x00da
106 #define RT5663_ADC_STO2_ADJ1                    0x00ee
107 #define RT5663_ADC_STO2_ADJ2                    0x00ef
108 /* General Control */
109 #define RT5663_A_JD_CTRL                        0x00f0
110 #define RT5663_JD1_TRES_CTRL                    0x00f1
111 #define RT5663_JD2_TRES_CTRL                    0x00f2
112 #define RT5663_V2_JD_CTRL2                      0x00f7
113 #define RT5663_DUM_REG_2                        0x00fb
114 #define RT5663_DUM_REG_3                        0x00fc
115
116
117 #define RT5663_DACADC_DIG_VOL2                  0x0101
118 #define RT5663_DIG_IN_PIN2                      0x0133
119 #define RT5663_PAD_DRV_CTL1                     0x0136
120 #define RT5663_SOF_RAM_DEPOP                    0x0138
121 #define RT5663_VOL_TEST                         0x013f
122 #define RT5663_MONO_DYNA_1                      0x0170
123 #define RT5663_MONO_DYNA_2                      0x0171
124 #define RT5663_MONO_DYNA_3                      0x0172
125 #define RT5663_MONO_DYNA_4                      0x0173
126 #define RT5663_MONO_DYNA_5                      0x0174
127 #define RT5663_MONO_DYNA_6                      0x0175
128 #define RT5663_STO1_SIL_DET                     0x0190
129 #define RT5663_MONOL_SIL_DET                    0x0191
130 #define RT5663_MONOR_SIL_DET                    0x0192
131 #define RT5663_STO2_DAC_SIL                     0x0193
132 #define RT5663_PWR_SAV_CTL1                     0x0194
133 #define RT5663_PWR_SAV_CTL2                     0x0195
134 #define RT5663_PWR_SAV_CTL3                     0x0196
135 #define RT5663_PWR_SAV_CTL4                     0x0197
136 #define RT5663_PWR_SAV_CTL5                     0x0198
137 #define RT5663_PWR_SAV_CTL6                     0x0199
138 #define RT5663_MONO_AMP_CAL1                    0x01a0
139 #define RT5663_MONO_AMP_CAL2                    0x01a1
140 #define RT5663_MONO_AMP_CAL3                    0x01a2
141 #define RT5663_MONO_AMP_CAL4                    0x01a3
142 #define RT5663_MONO_AMP_CAL5                    0x01a4
143 #define RT5663_MONO_AMP_CAL6                    0x01a5
144 #define RT5663_MONO_AMP_CAL7                    0x01a6
145 #define RT5663_MONO_AMP_CAL_ST1                 0x01a7
146 #define RT5663_MONO_AMP_CAL_ST2                 0x01a8
147 #define RT5663_MONO_AMP_CAL_ST3                 0x01a9
148 #define RT5663_MONO_AMP_CAL_ST4                 0x01aa
149 #define RT5663_MONO_AMP_CAL_ST5                 0x01ab
150 #define RT5663_V2_HP_IMP_SEN_13                 0x01b9
151 #define RT5663_V2_HP_IMP_SEN_14                 0x01ba
152 #define RT5663_V2_HP_IMP_SEN_6                  0x01bb
153 #define RT5663_V2_HP_IMP_SEN_7                  0x01bc
154 #define RT5663_V2_HP_IMP_SEN_8                  0x01bd
155 #define RT5663_V2_HP_IMP_SEN_9                  0x01be
156 #define RT5663_V2_HP_IMP_SEN_10                 0x01bf
157 #define RT5663_HP_LOGIC_3                       0x01dc
158 #define RT5663_HP_CALIB_ST10                    0x01f3
159 #define RT5663_HP_CALIB_ST11                    0x01f4
160 #define RT5663_PRO_REG_TBL_4                    0x0203
161 #define RT5663_PRO_REG_TBL_5                    0x0204
162 #define RT5663_PRO_REG_TBL_6                    0x0205
163 #define RT5663_PRO_REG_TBL_7                    0x0206
164 #define RT5663_PRO_REG_TBL_8                    0x0207
165 #define RT5663_PRO_REG_TBL_9                    0x0208
166 #define RT5663_SAR_ADC_INL_1                    0x0210
167 #define RT5663_SAR_ADC_INL_2                    0x0211
168 #define RT5663_SAR_ADC_INL_3                    0x0212
169 #define RT5663_SAR_ADC_INL_4                    0x0213
170 #define RT5663_SAR_ADC_INL_5                    0x0214
171 #define RT5663_SAR_ADC_INL_6                    0x0215
172 #define RT5663_SAR_ADC_INL_7                    0x0216
173 #define RT5663_SAR_ADC_INL_8                    0x0217
174 #define RT5663_SAR_ADC_INL_9                    0x0218
175 #define RT5663_SAR_ADC_INL_10                   0x0219
176 #define RT5663_SAR_ADC_INL_11                   0x021a
177 #define RT5663_SAR_ADC_INL_12                   0x021b
178 #define RT5663_DRC_CTRL_1                       0x02ff
179 #define RT5663_DRC1_CTRL_2                      0x0301
180 #define RT5663_DRC1_CTRL_3                      0x0302
181 #define RT5663_DRC1_CTRL_4                      0x0303
182 #define RT5663_DRC1_CTRL_5                      0x0304
183 #define RT5663_DRC1_CTRL_6                      0x0305
184 #define RT5663_DRC1_HD_CTRL_1                   0x0306
185 #define RT5663_DRC1_HD_CTRL_2                   0x0307
186 #define RT5663_DRC1_PRI_REG_1                   0x0310
187 #define RT5663_DRC1_PRI_REG_2                   0x0311
188 #define RT5663_DRC1_PRI_REG_3                   0x0312
189 #define RT5663_DRC1_PRI_REG_4                   0x0313
190 #define RT5663_DRC1_PRI_REG_5                   0x0314
191 #define RT5663_DRC1_PRI_REG_6                   0x0315
192 #define RT5663_DRC1_PRI_REG_7                   0x0316
193 #define RT5663_DRC1_PRI_REG_8                   0x0317
194 #define RT5663_ALC_PGA_CTL_1                    0x0330
195 #define RT5663_ALC_PGA_CTL_2                    0x0331
196 #define RT5663_ALC_PGA_CTL_3                    0x0332
197 #define RT5663_ALC_PGA_CTL_4                    0x0333
198 #define RT5663_ALC_PGA_CTL_5                    0x0334
199 #define RT5663_ALC_PGA_CTL_6                    0x0335
200 #define RT5663_ALC_PGA_CTL_7                    0x0336
201 #define RT5663_ALC_PGA_CTL_8                    0x0337
202 #define RT5663_ALC_PGA_REG_1                    0x0338
203 #define RT5663_ALC_PGA_REG_2                    0x0339
204 #define RT5663_ALC_PGA_REG_3                    0x033a
205 #define RT5663_ADC_EQ_RECOV_1                   0x03c0
206 #define RT5663_ADC_EQ_RECOV_2                   0x03c1
207 #define RT5663_ADC_EQ_RECOV_3                   0x03c2
208 #define RT5663_ADC_EQ_RECOV_4                   0x03c3
209 #define RT5663_ADC_EQ_RECOV_5                   0x03c4
210 #define RT5663_ADC_EQ_RECOV_6                   0x03c5
211 #define RT5663_ADC_EQ_RECOV_7                   0x03c6
212 #define RT5663_ADC_EQ_RECOV_8                   0x03c7
213 #define RT5663_ADC_EQ_RECOV_9                   0x03c8
214 #define RT5663_ADC_EQ_RECOV_10                  0x03c9
215 #define RT5663_ADC_EQ_RECOV_11                  0x03ca
216 #define RT5663_ADC_EQ_RECOV_12                  0x03cb
217 #define RT5663_ADC_EQ_RECOV_13                  0x03cc
218 #define RT5663_VID_HIDDEN                       0x03fe
219 #define RT5663_VID_CUSTOMER                     0x03ff
220 #define RT5663_SCAN_MODE                        0x07f0
221 #define RT5663_I2C_BYPA                         0x07fa
222
223 /* Headphone Amp Control 2 (0x0003) */
224 #define RT5663_EN_DAC_HPO_MASK                  (0x1 << 14)
225 #define RT5663_EN_DAC_HPO_SHIFT                 14
226 #define RT5663_EN_DAC_HPO_DIS                   (0x0 << 14)
227 #define RT5663_EN_DAC_HPO_EN                    (0x1 << 14)
228
229 /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
230 #define RT5663_GAIN_HP                          (0x1f << 8)
231 #define RT5663_GAIN_HP_SHIFT                    8
232
233 /* AEC BST Control (0x000b) */
234 #define RT5663_GAIN_CBJ_MASK                    (0xf << 8)
235 #define RT5663_GAIN_CBJ_SHIFT                   8
236
237 /* IN1 Control / MIC GND REF (0x000c) */
238 #define RT5663_IN1_DF_MASK                      (0x1 << 15)
239 #define RT5663_IN1_DF_SHIFT                     15
240
241 /* Combo Jack and Type Detection Control 1 (0x0010) */
242 #define RT5663_CBJ_DET_MASK                     (0x1 << 15)
243 #define RT5663_CBJ_DET_SHIFT                    15
244 #define RT5663_CBJ_DET_DIS                      (0x0 << 15)
245 #define RT5663_CBJ_DET_EN                       (0x1 << 15)
246 #define RT5663_DET_TYPE_MASK                    (0x1 << 12)
247 #define RT5663_DET_TYPE_SHIFT                   12
248 #define RT5663_DET_TYPE_WLCSP                   (0x0 << 12)
249 #define RT5663_DET_TYPE_QFN                     (0x1 << 12)
250 #define RT5663_VREF_BIAS_MASK                   (0x1 << 6)
251 #define RT5663_VREF_BIAS_SHIFT                  6
252 #define RT5663_VREF_BIAS_FSM                    (0x0 << 6)
253 #define RT5663_VREF_BIAS_REG                    (0x1 << 6)
254
255 /* REC Left Mixer Control 2 (0x003c) */
256 #define RT5663_RECMIX1L_BST1_CBJ                (0x1 << 7)
257 #define RT5663_RECMIX1L_BST1_CBJ_SHIFT          7
258 #define RT5663_RECMIX1L_BST2                    (0x1 << 4)
259 #define RT5663_RECMIX1L_BST2_SHIFT              4
260
261 /* REC Right Mixer Control 2 (0x003e) */
262 #define RT5663_RECMIX1R_BST2                    (0x1 << 4)
263 #define RT5663_RECMIX1R_BST2_SHIFT              4
264
265 /* DAC1 Digital Volume (0x0019) */
266 #define RT5663_DAC_L1_VOL_MASK                  (0xff << 8)
267 #define RT5663_DAC_L1_VOL_SHIFT                 8
268 #define RT5663_DAC_R1_VOL_MASK                  (0xff)
269 #define RT5663_DAC_R1_VOL_SHIFT                 0
270
271 /* ADC Digital Volume Control (0x001c) */
272 #define RT5663_ADC_L_MUTE_MASK                  (0x1 << 15)
273 #define RT5663_ADC_L_MUTE_SHIFT                 15
274 #define RT5663_ADC_L_VOL_MASK                   (0x7f << 8)
275 #define RT5663_ADC_L_VOL_SHIFT                  8
276 #define RT5663_ADC_R_MUTE_MASK                  (0x1 << 7)
277 #define RT5663_ADC_R_MUTE_SHIFT                 7
278 #define RT5663_ADC_R_VOL_MASK                   (0x7f)
279 #define RT5663_ADC_R_VOL_SHIFT                  0
280
281 /* Stereo ADC Mixer Control (0x0026) */
282 #define RT5663_M_STO1_ADC_L1                    (0x1 << 15)
283 #define RT5663_M_STO1_ADC_L1_SHIFT              15
284 #define RT5663_M_STO1_ADC_L2                    (0x1 << 14)
285 #define RT5663_M_STO1_ADC_L2_SHIFT              14
286 #define RT5663_STO1_ADC_L1_SRC                  (0x1 << 13)
287 #define RT5663_STO1_ADC_L1_SRC_SHIFT            13
288 #define RT5663_STO1_ADC_L2_SRC                  (0x1 << 12)
289 #define RT5663_STO1_ADC_L2_SRC_SHIFT            12
290 #define RT5663_STO1_ADC_L_SRC                   (0x3 << 10)
291 #define RT5663_STO1_ADC_L_SRC_SHIFT             10
292 #define RT5663_M_STO1_ADC_R1                    (0x1 << 7)
293 #define RT5663_M_STO1_ADC_R1_SHIFT              7
294 #define RT5663_M_STO1_ADC_R2                    (0x1 << 6)
295 #define RT5663_M_STO1_ADC_R2_SHIFT              6
296 #define RT5663_STO1_ADC_R1_SRC                  (0x1 << 5)
297 #define RT5663_STO1_ADC_R1_SRC_SHIFT            5
298 #define RT5663_STO1_ADC_R2_SRC                  (0x1 << 4)
299 #define RT5663_STO1_ADC_R2_SRC_SHIFT            4
300 #define RT5663_STO1_ADC_R_SRC                   (0x3 << 2)
301 #define RT5663_STO1_ADC_R_SRC_SHIFT             2
302
303 /* ADC Mixer to DAC Mixer Control (0x0029) */
304 #define RT5663_M_ADCMIX_L                       (0x1 << 15)
305 #define RT5663_M_ADCMIX_L_SHIFT                 15
306 #define RT5663_M_DAC1_L                         (0x1 << 14)
307 #define RT5663_M_DAC1_L_SHIFT                   14
308 #define RT5663_M_ADCMIX_R                       (0x1 << 7)
309 #define RT5663_M_ADCMIX_R_SHIFT                 7
310 #define RT5663_M_DAC1_R                         (0x1 << 6)
311 #define RT5663_M_DAC1_R_SHIFT                   6
312
313 /* Stereo DAC Mixer Control (0x002a) */
314 #define RT5663_M_DAC_L1_STO_L                   (0x1 << 15)
315 #define RT5663_M_DAC_L1_STO_L_SHIFT             15
316 #define RT5663_M_DAC_R1_STO_L                   (0x1 << 13)
317 #define RT5663_M_DAC_R1_STO_L_SHIFT             13
318 #define RT5663_M_DAC_L1_STO_R                   (0x1 << 7)
319 #define RT5663_M_DAC_L1_STO_R_SHIFT             7
320 #define RT5663_M_DAC_R1_STO_R                   (0x1 << 5)
321 #define RT5663_M_DAC_R1_STO_R_SHIFT             5
322
323 /* Power Management for Digital 1 (0x0061) */
324 #define RT5663_PWR_I2S1                         (0x1 << 15)
325 #define RT5663_PWR_I2S1_SHIFT                   15
326 #define RT5663_PWR_DAC_L1                       (0x1 << 11)
327 #define RT5663_PWR_DAC_L1_SHIFT                 11
328 #define RT5663_PWR_DAC_R1                       (0x1 << 10)
329 #define RT5663_PWR_DAC_R1_SHIFT                 10
330 #define RT5663_PWR_LDO_DACREF_MASK              (0x1 << 8)
331 #define RT5663_PWR_LDO_DACREF_SHIFT             8
332 #define RT5663_PWR_LDO_DACREF_ON                (0x1 << 8)
333 #define RT5663_PWR_LDO_DACREF_DOWN              (0x0 << 8)
334 #define RT5663_PWR_LDO_SHIFT                    8
335 #define RT5663_PWR_ADC_L1                       (0x1 << 4)
336 #define RT5663_PWR_ADC_L1_SHIFT                 4
337 #define RT5663_PWR_ADC_R1                       (0x1 << 3)
338 #define RT5663_PWR_ADC_R1_SHIFT                 3
339
340 /* Power Management for Digital 2 (0x0062) */
341 #define RT5663_PWR_ADC_S1F                      (0x1 << 15)
342 #define RT5663_PWR_ADC_S1F_SHIFT                15
343 #define RT5663_PWR_DAC_S1F                      (0x1 << 10)
344 #define RT5663_PWR_DAC_S1F_SHIFT                10
345
346 /* Power Management for Analog 1 (0x0063) */
347 #define RT5663_PWR_VREF1                        (0x1 << 15)
348 #define RT5663_PWR_VREF1_MASK                   (0x1 << 15)
349 #define RT5663_PWR_VREF1_SHIFT                  15
350 #define RT5663_PWR_FV1                          (0x1 << 14)
351 #define RT5663_PWR_FV1_MASK                     (0x1 << 14)
352 #define RT5663_PWR_FV1_SHIFT                    14
353 #define RT5663_PWR_VREF2                        (0x1 << 13)
354 #define RT5663_PWR_VREF2_MASK                   (0x1 << 13)
355 #define RT5663_PWR_VREF2_SHIFT                  13
356 #define RT5663_PWR_FV2                          (0x1 << 12)
357 #define RT5663_PWR_FV2_MASK                     (0x1 << 12)
358 #define RT5663_PWR_FV2_SHIFT                    12
359 #define RT5663_PWR_MB                           (0x1 << 9)
360 #define RT5663_PWR_MB_MASK                      (0x1 << 9)
361 #define RT5663_PWR_MB_SHIFT                     9
362 #define RT5663_AMP_HP_MASK                      (0x3 << 2)
363 #define RT5663_AMP_HP_SHIFT                     2
364 #define RT5663_AMP_HP_1X                        (0x0 << 2)
365 #define RT5663_AMP_HP_3X                        (0x1 << 2)
366 #define RT5663_AMP_HP_5X                        (0x3 << 2)
367 #define RT5663_LDO1_DVO_MASK                    (0x3)
368 #define RT5663_LDO1_DVO_SHIFT                   0
369 #define RT5663_LDO1_DVO_0_9V                    (0x0)
370 #define RT5663_LDO1_DVO_1_0V                    (0x1)
371 #define RT5663_LDO1_DVO_1_2V                    (0x2)
372 #define RT5663_LDO1_DVO_1_4V                    (0x3)
373
374 /* Power Management for Analog 2 (0x0064) */
375 #define RT5663_PWR_BST1                         (0x1 << 15)
376 #define RT5663_PWR_BST1_MASK                    (0x1 << 15)
377 #define RT5663_PWR_BST1_SHIFT                   15
378 #define RT5663_PWR_BST1_OFF                     (0x0 << 15)
379 #define RT5663_PWR_BST1_ON                      (0x1 << 15)
380 #define RT5663_PWR_BST2                         (0x1 << 14)
381 #define RT5663_PWR_BST2_MASK                    (0x1 << 14)
382 #define RT5663_PWR_BST2_SHIFT                   14
383 #define RT5663_PWR_MB1                          (0x1 << 11)
384 #define RT5663_PWR_MB1_SHIFT                    11
385 #define RT5663_PWR_MB2                          (0x1 << 10)
386 #define RT5663_PWR_MB2_SHIFT                    10
387 #define RT5663_PWR_BST2_OP                      (0x1 << 6)
388 #define RT5663_PWR_BST2_OP_MASK                 (0x1 << 6)
389 #define RT5663_PWR_BST2_OP_SHIFT                6
390 #define RT5663_PWR_JD1                          (0x1 << 3)
391 #define RT5663_PWR_JD1_MASK                     (0x1 << 3)
392 #define RT5663_PWR_JD1_SHIFT                    3
393 #define RT5663_PWR_JD2                          (0x1 << 2)
394 #define RT5663_PWR_JD2_MASK                     (0x1 << 2)
395 #define RT5663_PWR_JD2_SHIFT                    2
396 #define RT5663_PWR_RECMIX1                      (0x1 << 1)
397 #define RT5663_PWR_RECMIX1_SHIFT                1
398 #define RT5663_PWR_RECMIX2                      (0x1)
399 #define RT5663_PWR_RECMIX2_SHIFT                0
400
401 /* Power Management for Analog 3 (0x0065) */
402 #define RT5663_PWR_CBJ_MASK                     (0x1 << 9)
403 #define RT5663_PWR_CBJ_SHIFT                    9
404 #define RT5663_PWR_CBJ_OFF                      (0x0 << 9)
405 #define RT5663_PWR_CBJ_ON                       (0x1 << 9)
406 #define RT5663_PWR_PLL                          (0x1 << 6)
407 #define RT5663_PWR_PLL_SHIFT                    6
408 #define RT5663_PWR_LDO2                         (0x1 << 2)
409 #define RT5663_PWR_LDO2_SHIFT                   2
410
411 /* Power Management for Volume (0x0067) */
412 #define RT5663_V2_PWR_MIC_DET                   (0x1 << 5)
413 #define RT5663_V2_PWR_MIC_DET_SHIFT             5
414
415 /* MCLK and System Clock Detection Control (0x006b) */
416 #define RT5663_EN_ANA_CLK_DET_MASK              (0x1 << 15)
417 #define RT5663_EN_ANA_CLK_DET_SHIFT             15
418 #define RT5663_EN_ANA_CLK_DET_DIS               (0x0 << 15)
419 #define RT5663_EN_ANA_CLK_DET_AUTO              (0x1 << 15)
420 #define RT5663_PWR_CLK_DET_MASK                 (0x1)
421 #define RT5663_PWR_CLK_DET_SHIFT                0
422 #define RT5663_PWR_CLK_DET_DIS                  (0x0)
423 #define RT5663_PWR_CLK_DET_EN                   (0x1)
424
425 /* I2S1 Audio Serial Data Port Control (0x0070) */
426 #define RT5663_I2S_MS_MASK                      (0x1 << 15)
427 #define RT5663_I2S_MS_SHIFT                     15
428 #define RT5663_I2S_MS_M                         (0x0 << 15)
429 #define RT5663_I2S_MS_S                         (0x1 << 15)
430 #define RT5663_I2S_BP_MASK                      (0x1 << 8)
431 #define RT5663_I2S_BP_SHIFT                     8
432 #define RT5663_I2S_BP_NOR                       (0x0 << 8)
433 #define RT5663_I2S_BP_INV                       (0x1 << 8)
434 #define RT5663_I2S_DL_MASK                      (0x3 << 4)
435 #define RT5663_I2S_DL_SHIFT                     4
436 #define RT5663_I2S_DL_16                        (0x0 << 4)
437 #define RT5663_I2S_DL_20                        (0x1 << 4)
438 #define RT5663_I2S_DL_24                        (0x2 << 4)
439 #define RT5663_I2S_DL_8                         (0x3 << 4)
440 #define RT5663_I2S_DF_MASK                      (0x7)
441 #define RT5663_I2S_DF_SHIFT                     0
442 #define RT5663_I2S_DF_I2S                       (0x0)
443 #define RT5663_I2S_DF_LEFT                      (0x1)
444 #define RT5663_I2S_DF_PCM_A                     (0x2)
445 #define RT5663_I2S_DF_PCM_B                     (0x3)
446 #define RT5663_I2S_DF_PCM_A_N                   (0x6)
447 #define RT5663_I2S_DF_PCM_B_N                   (0x7)
448
449 /* ADC/DAC Clock Control 1 (0x0073) */
450 #define RT5663_I2S_PD1_MASK                     (0x7 << 12)
451 #define RT5663_I2S_PD1_SHIFT                    12
452 #define RT5663_M_I2S_DIV_MASK                   (0x7 << 8)
453 #define RT5663_M_I2S_DIV_SHIFT                  8
454 #define RT5663_CLK_SRC_MASK                     (0x3 << 4)
455 #define RT5663_CLK_SRC_MCLK                     (0x0 << 4)
456 #define RT5663_CLK_SRC_PLL_OUT                  (0x1 << 4)
457 #define RT5663_CLK_SRC_DIV                      (0x2 << 4)
458 #define RT5663_CLK_SRC_RC                       (0x3 << 4)
459 #define RT5663_DAC_OSR_MASK                     (0x3 << 2)
460 #define RT5663_DAC_OSR_SHIFT                    2
461 #define RT5663_DAC_OSR_128                      (0x0 << 2)
462 #define RT5663_DAC_OSR_64                       (0x1 << 2)
463 #define RT5663_DAC_OSR_32                       (0x2 << 2)
464 #define RT5663_ADC_OSR_MASK                     (0x3)
465 #define RT5663_ADC_OSR_SHIFT                    0
466 #define RT5663_ADC_OSR_128                      (0x0)
467 #define RT5663_ADC_OSR_64                       (0x1)
468 #define RT5663_ADC_OSR_32                       (0x2)
469
470 /* TDM1 control 1 (0x0078) */
471 #define RT5663_TDM_MODE_MASK                    (0x1 << 15)
472 #define RT5663_TDM_MODE_SHIFT                   15
473 #define RT5663_TDM_MODE_I2S                     (0x0 << 15)
474 #define RT5663_TDM_MODE_TDM                     (0x1 << 15)
475 #define RT5663_TDM_IN_CH_MASK                   (0x3 << 10)
476 #define RT5663_TDM_IN_CH_SHIFT                  10
477 #define RT5663_TDM_IN_CH_2                      (0x0 << 10)
478 #define RT5663_TDM_IN_CH_4                      (0x1 << 10)
479 #define RT5663_TDM_IN_CH_6                      (0x2 << 10)
480 #define RT5663_TDM_IN_CH_8                      (0x3 << 10)
481 #define RT5663_TDM_OUT_CH_MASK                  (0x3 << 8)
482 #define RT5663_TDM_OUT_CH_SHIFT                 8
483 #define RT5663_TDM_OUT_CH_2                     (0x0 << 8)
484 #define RT5663_TDM_OUT_CH_4                     (0x1 << 8)
485 #define RT5663_TDM_OUT_CH_6                     (0x2 << 8)
486 #define RT5663_TDM_OUT_CH_8                     (0x3 << 8)
487 #define RT5663_TDM_IN_LEN_MASK                  (0x3 << 6)
488 #define RT5663_TDM_IN_LEN_SHIFT                 6
489 #define RT5663_TDM_IN_LEN_16                    (0x0 << 6)
490 #define RT5663_TDM_IN_LEN_20                    (0x1 << 6)
491 #define RT5663_TDM_IN_LEN_24                    (0x2 << 6)
492 #define RT5663_TDM_IN_LEN_32                    (0x3 << 6)
493 #define RT5663_TDM_OUT_LEN_MASK                 (0x3 << 4)
494 #define RT5663_TDM_OUT_LEN_SHIFT                4
495 #define RT5663_TDM_OUT_LEN_16                   (0x0 << 4)
496 #define RT5663_TDM_OUT_LEN_20                   (0x1 << 4)
497 #define RT5663_TDM_OUT_LEN_24                   (0x2 << 4)
498 #define RT5663_TDM_OUT_LEN_32                   (0x3 << 4)
499
500 /* Global Clock Control (0x0080) */
501 #define RT5663_SCLK_SRC_MASK                    (0x3 << 14)
502 #define RT5663_SCLK_SRC_SHIFT                   14
503 #define RT5663_SCLK_SRC_MCLK                    (0x0 << 14)
504 #define RT5663_SCLK_SRC_PLL1                    (0x1 << 14)
505 #define RT5663_SCLK_SRC_RCCLK                   (0x2 << 14)
506 #define RT5663_PLL1_SRC_MASK                    (0x7 << 11)
507 #define RT5663_PLL1_SRC_SHIFT                   11
508 #define RT5663_PLL1_SRC_MCLK                    (0x0 << 11)
509 #define RT5663_PLL1_SRC_BCLK1                   (0x1 << 11)
510 #define RT5663_V2_PLL1_SRC_MASK                 (0x7 << 8)
511 #define RT5663_V2_PLL1_SRC_SHIFT                8
512 #define RT5663_V2_PLL1_SRC_MCLK                 (0x0 << 8)
513 #define RT5663_V2_PLL1_SRC_BCLK1                (0x1 << 8)
514 #define RT5663_PLL1_PD_MASK                     (0x1 << 4)
515 #define RT5663_PLL1_PD_SHIFT                    4
516
517 #define RT5663_PLL_INP_MAX                      40000000
518 #define RT5663_PLL_INP_MIN                      256000
519 /* PLL M/N/K Code Control 1 (0x0081) */
520 #define RT5663_PLL_N_MAX                        0x001ff
521 #define RT5663_PLL_N_MASK                       (RT5663_PLL_N_MAX << 7)
522 #define RT5663_PLL_N_SHIFT                      7
523 #define RT5663_PLL_K_MAX                        0x001f
524 #define RT5663_PLL_K_MASK                       (RT5663_PLL_K_MAX)
525 #define RT5663_PLL_K_SHIFT                      0
526
527 /* PLL M/N/K Code Control 2 (0x0082) */
528 #define RT5663_PLL_M_MAX                        0x00f
529 #define RT5663_PLL_M_MASK                       (RT5663_PLL_M_MAX << 12)
530 #define RT5663_PLL_M_SHIFT                      12
531 #define RT5663_PLL_M_BP                         (0x1 << 11)
532 #define RT5663_PLL_M_BP_SHIFT                   11
533
534 /* PLL tracking mode 1 (0x0083) */
535 #define RT5663_V2_I2S1_ASRC_MASK                        (0x1 << 13)
536 #define RT5663_V2_I2S1_ASRC_SHIFT                       13
537 #define RT5663_V2_DAC_STO1_ASRC_MASK            (0x1 << 12)
538 #define RT5663_V2_DAC_STO1_ASRC_SHIFT           12
539 #define RT5663_V2_ADC_STO1_ASRC_MASK            (0x1 << 4)
540 #define RT5663_V2_ADC_STO1_ASRC_SHIFT           4
541
542 /* PLL tracking mode 2 (0x0084)*/
543 #define RT5663_DA_STO1_TRACK_MASK               (0x7 << 12)
544 #define RT5663_DA_STO1_TRACK_SHIFT              12
545 #define RT5663_DA_STO1_TRACK_SYSCLK             (0x0 << 12)
546 #define RT5663_DA_STO1_TRACK_I2S1               (0x1 << 12)
547
548 /* PLL tracking mode 3 (0x0085)*/
549 #define RT5663_V2_AD_STO1_TRACK_MASK            (0x7 << 12)
550 #define RT5663_V2_AD_STO1_TRACK_SHIFT           12
551 #define RT5663_V2_AD_STO1_TRACK_SYSCLK          (0x0 << 12)
552 #define RT5663_V2_AD_STO1_TRACK_I2S1            (0x1 << 12)
553
554 /* HPOUT Charge pump control 1 (0x0091) */
555 #define RT5663_OSW_HP_L_MASK                    (0x1 << 11)
556 #define RT5663_OSW_HP_L_SHIFT                   11
557 #define RT5663_OSW_HP_L_EN                      (0x1 << 11)
558 #define RT5663_OSW_HP_L_DIS                     (0x0 << 11)
559 #define RT5663_OSW_HP_R_MASK                    (0x1 << 10)
560 #define RT5663_OSW_HP_R_SHIFT                   10
561 #define RT5663_OSW_HP_R_EN                      (0x1 << 10)
562 #define RT5663_OSW_HP_R_DIS                     (0x0 << 10)
563 #define RT5663_SEL_PM_HP_MASK                   (0x3 << 8)
564 #define RT5663_SEL_PM_HP_SHIFT                  8
565 #define RT5663_SEL_PM_HP_0_6                    (0x0 << 8)
566 #define RT5663_SEL_PM_HP_0_9                    (0x1 << 8)
567 #define RT5663_SEL_PM_HP_1_8                    (0x2 << 8)
568 #define RT5663_SEL_PM_HP_HIGH                   (0x3 << 8)
569 #define RT5663_OVCD_HP_MASK                     (0x1 << 2)
570 #define RT5663_OVCD_HP_SHIFT                    2
571 #define RT5663_OVCD_HP_EN                       (0x1 << 2)
572 #define RT5663_OVCD_HP_DIS                      (0x0 << 2)
573
574 /* RC Clock Control (0x0094) */
575 #define RT5663_DIG_25M_CLK_MASK                 (0x1 << 9)
576 #define RT5663_DIG_25M_CLK_SHIFT                9
577 #define RT5663_DIG_25M_CLK_DIS                  (0x0 << 9)
578 #define RT5663_DIG_25M_CLK_EN                   (0x1 << 9)
579 #define RT5663_DIG_1M_CLK_MASK                  (0x1 << 8)
580 #define RT5663_DIG_1M_CLK_SHIFT                 8
581 #define RT5663_DIG_1M_CLK_DIS                   (0x0 << 8)
582 #define RT5663_DIG_1M_CLK_EN                    (0x1 << 8)
583
584 /* Auto Turn On 1M RC CLK (0x009f) */
585 #define RT5663_IRQ_POW_SAV_MASK                 (0x1 << 15)
586 #define RT5663_IRQ_POW_SAV_SHIFT                15
587 #define RT5663_IRQ_POW_SAV_DIS                  (0x0 << 15)
588 #define RT5663_IRQ_POW_SAV_EN                   (0x1 << 15)
589 #define RT5663_IRQ_POW_SAV_JD1_MASK             (0x1 << 14)
590 #define RT5663_IRQ_POW_SAV_JD1_SHIFT            14
591 #define RT5663_IRQ_POW_SAV_JD1_DIS              (0x0 << 14)
592 #define RT5663_IRQ_POW_SAV_JD1_EN               (0x1 << 14)
593
594 /* IRQ Control 1 (0x00b6) */
595 #define RT5663_EN_CB_JD_MASK                    (0x1 << 3)
596 #define RT5663_EN_CB_JD_SHIFT                   3
597 #define RT5663_EN_CB_JD_EN                      (0x1 << 3)
598 #define RT5663_EN_CB_JD_DIS                     (0x0 << 3)
599
600 /* IRQ Control 3 (0x00b8) */
601 #define RT5663_V2_EN_IRQ_INLINE_MASK            (0x1 << 6)
602 #define RT5663_V2_EN_IRQ_INLINE_SHIFT           6
603 #define RT5663_V2_EN_IRQ_INLINE_BYP             (0x0 << 6)
604 #define RT5663_V2_EN_IRQ_INLINE_NOR             (0x1 << 6)
605
606 /* GPIO Control 1 (0x00c0) */
607 #define RT5663_GP1_PIN_MASK                     (0x1 << 15)
608 #define RT5663_GP1_PIN_SHIFT                    15
609 #define RT5663_GP1_PIN_GPIO1                    (0x0 << 15)
610 #define RT5663_GP1_PIN_IRQ                      (0x1 << 15)
611
612 /* GPIO Control 2 (0x00c1) */
613 #define RT5663_GP4_PIN_CONF_MASK                (0x1 << 5)
614 #define RT5663_GP4_PIN_CONF_SHIFT               5
615 #define RT5663_GP4_PIN_CONF_INPUT               (0x0 << 5)
616 #define RT5663_GP4_PIN_CONF_OUTPUT              (0x1 << 5)
617
618 /* GPIO Control 2 (0x00c2) */
619 #define RT5663_GP8_PIN_CONF_MASK                (0x1 << 13)
620 #define RT5663_GP8_PIN_CONF_SHIFT               13
621 #define RT5663_GP8_PIN_CONF_INPUT               (0x0 << 13)
622 #define RT5663_GP8_PIN_CONF_OUTPUT              (0x1 << 13)
623
624 /* 4 Buttons Inline Command Function 1 (0x00df) */
625 #define RT5663_4BTN_CLK_DEB_MASK                (0x3 << 2)
626 #define RT5663_4BTN_CLK_DEB_SHIFT               2
627 #define RT5663_4BTN_CLK_DEB_8MS                 (0x0 << 2)
628 #define RT5663_4BTN_CLK_DEB_16MS                (0x1 << 2)
629 #define RT5663_4BTN_CLK_DEB_32MS                (0x2 << 2)
630 #define RT5663_4BTN_CLK_DEB_65MS                (0x3 << 2)
631
632 /* Inline Command Function 6 (0x00e0) */
633 #define RT5663_EN_4BTN_INL_MASK                 (0x1 << 15)
634 #define RT5663_EN_4BTN_INL_SHIFT                15
635 #define RT5663_EN_4BTN_INL_DIS                  (0x0 << 15)
636 #define RT5663_EN_4BTN_INL_EN                   (0x1 << 15)
637 #define RT5663_RESET_4BTN_INL_MASK              (0x1 << 14)
638 #define RT5663_RESET_4BTN_INL_SHIFT             14
639 #define RT5663_RESET_4BTN_INL_RESET             (0x0 << 14)
640 #define RT5663_RESET_4BTN_INL_NOR               (0x1 << 14)
641
642 /* Digital Misc Control (0x00fa) */
643 #define RT5663_DIG_GATE_CTRL_MASK               0x1
644 #define RT5663_DIG_GATE_CTRL_SHIFT              (0)
645 #define RT5663_DIG_GATE_CTRL_DIS                0x0
646 #define RT5663_DIG_GATE_CTRL_EN                 0x1
647
648 /* Chopper and Clock control for DAC L (0x013a)*/
649 #define RT5663_CKXEN_DAC1_MASK                  (0x1 << 13)
650 #define RT5663_CKXEN_DAC1_SHIFT                 13
651 #define RT5663_CKGEN_DAC1_MASK                  (0x1 << 12)
652 #define RT5663_CKGEN_DAC1_SHIFT                 12
653
654 /* Chopper and Clock control for ADC (0x013b)*/
655 #define RT5663_CKXEN_ADCC_MASK                  (0x1 << 13)
656 #define RT5663_CKXEN_ADCC_SHIFT                 13
657 #define RT5663_CKGEN_ADCC_MASK                  (0x1 << 12)
658 #define RT5663_CKGEN_ADCC_SHIFT                 12
659
660 /* HP Behavior Logic Control 2 (0x01db) */
661 #define RT5663_HP_SIG_SRC1_MASK                 (0x3)
662 #define RT5663_HP_SIG_SRC1_SHIFT                0
663 #define RT5663_HP_SIG_SRC1_HP_DC                (0x0)
664 #define RT5663_HP_SIG_SRC1_HP_CALIB             (0x1)
665 #define RT5663_HP_SIG_SRC1_REG                  (0x2)
666 #define RT5663_HP_SIG_SRC1_SILENCE              (0x3)
667
668 /* RT5663 specific register */
669 #define RT5663_HP_OUT_EN                        0x0002
670 #define RT5663_HP_LCH_DRE                       0x0005
671 #define RT5663_HP_RCH_DRE                       0x0006
672 #define RT5663_CALIB_BST                        0x000a
673 #define RT5663_RECMIX                           0x0010
674 #define RT5663_SIL_DET_CTL                      0x0015
675 #define RT5663_PWR_SAV_SILDET                   0x0016
676 #define RT5663_SIDETONE_CTL                     0x0018
677 #define RT5663_STO1_DAC_DIG_VOL                 0x0019
678 #define RT5663_STO1_ADC_DIG_VOL                 0x001c
679 #define RT5663_STO1_BOOST                       0x001f
680 #define RT5663_HP_IMP_GAIN_1                    0x0022
681 #define RT5663_HP_IMP_GAIN_2                    0x0023
682 #define RT5663_STO1_ADC_MIXER                   0x0026
683 #define RT5663_AD_DA_MIXER                      0x0029
684 #define RT5663_STO_DAC_MIXER                    0x002a
685 #define RT5663_DIG_SIDE_MIXER                   0x002c
686 #define RT5663_BYPASS_STO_DAC                   0x002d
687 #define RT5663_CALIB_REC_MIX                    0x0040
688 #define RT5663_PWR_DIG_1                        0x0061
689 #define RT5663_PWR_DIG_2                        0x0062
690 #define RT5663_PWR_ANLG_1                       0x0063
691 #define RT5663_PWR_ANLG_2                       0x0064
692 #define RT5663_PWR_ANLG_3                       0x0065
693 #define RT5663_PWR_MIXER                        0x0066
694 #define RT5663_SIG_CLK_DET                      0x006b
695 #define RT5663_PRE_DIV_GATING_1                 0x006e
696 #define RT5663_PRE_DIV_GATING_2                 0x006f
697 #define RT5663_I2S1_SDP                         0x0070
698 #define RT5663_ADDA_CLK_1                       0x0073
699 #define RT5663_ADDA_RST                         0x0074
700 #define RT5663_FRAC_DIV_1                       0x0075
701 #define RT5663_FRAC_DIV_2                       0x0076
702 #define RT5663_TDM_1                            0x0077
703 #define RT5663_TDM_2                            0x0078
704 #define RT5663_TDM_3                            0x0079
705 #define RT5663_TDM_4                            0x007a
706 #define RT5663_TDM_5                            0x007b
707 #define RT5663_TDM_6                            0x007c
708 #define RT5663_TDM_7                            0x007d
709 #define RT5663_TDM_8                            0x007e
710 #define RT5663_TDM_9                            0x007f
711 #define RT5663_GLB_CLK                          0x0080
712 #define RT5663_PLL_1                            0x0081
713 #define RT5663_PLL_2                            0x0082
714 #define RT5663_ASRC_1                           0x0083
715 #define RT5663_ASRC_2                           0x0084
716 #define RT5663_ASRC_4                           0x0086
717 #define RT5663_DUMMY_REG                        0x0087
718 #define RT5663_ASRC_8                           0x008a
719 #define RT5663_ASRC_9                           0x008b
720 #define RT5663_ASRC_11                          0x008c
721 #define RT5663_DEPOP_1                          0x008e
722 #define RT5663_DEPOP_2                          0x008f
723 #define RT5663_DEPOP_3                          0x0090
724 #define RT5663_HP_CHARGE_PUMP_1                 0x0091
725 #define RT5663_HP_CHARGE_PUMP_2                 0x0092
726 #define RT5663_MICBIAS_1                        0x0093
727 #define RT5663_RC_CLK                           0x0094
728 #define RT5663_ASRC_11_2                        0x0097
729 #define RT5663_DUMMY_REG_2                      0x0098
730 #define RT5663_REC_PATH_GAIN                    0x009a
731 #define RT5663_AUTO_1MRC_CLK                    0x009f
732 #define RT5663_ADC_EQ_1                         0x00ae
733 #define RT5663_ADC_EQ_2                         0x00af
734 #define RT5663_IRQ_1                            0x00b6
735 #define RT5663_IRQ_2                            0x00b7
736 #define RT5663_IRQ_3                            0x00b8
737 #define RT5663_IRQ_4                            0x00ba
738 #define RT5663_IRQ_5                            0x00bb
739 #define RT5663_INT_ST_1                         0x00be
740 #define RT5663_INT_ST_2                         0x00bf
741 #define RT5663_GPIO_1                           0x00c0
742 #define RT5663_GPIO_2                           0x00c1
743 #define RT5663_GPIO_STA1                        0x00c5
744 #define RT5663_SIN_GEN_1                        0x00cb
745 #define RT5663_SIN_GEN_2                        0x00cc
746 #define RT5663_SIN_GEN_3                        0x00cd
747 #define RT5663_SOF_VOL_ZC1                      0x00d9
748 #define RT5663_IL_CMD_1                         0x00db
749 #define RT5663_IL_CMD_2                         0x00dc
750 #define RT5663_IL_CMD_3                         0x00dd
751 #define RT5663_IL_CMD_4                         0x00de
752 #define RT5663_IL_CMD_5                         0x00df
753 #define RT5663_IL_CMD_6                         0x00e0
754 #define RT5663_IL_CMD_7                         0x00e1
755 #define RT5663_IL_CMD_8                         0x00e2
756 #define RT5663_IL_CMD_PWRSAV1                   0x00e4
757 #define RT5663_IL_CMD_PWRSAV2                   0x00e5
758 #define RT5663_EM_JACK_TYPE_1                   0x00e6
759 #define RT5663_EM_JACK_TYPE_2                   0x00e7
760 #define RT5663_EM_JACK_TYPE_3                   0x00e8
761 #define RT5663_EM_JACK_TYPE_4                   0x00e9
762 #define RT5663_EM_JACK_TYPE_5                   0x00ea
763 #define RT5663_EM_JACK_TYPE_6                   0x00eb
764 #define RT5663_STO1_HPF_ADJ1                    0x00ec
765 #define RT5663_STO1_HPF_ADJ2                    0x00ed
766 #define RT5663_FAST_OFF_MICBIAS                 0x00f4
767 #define RT5663_JD_CTRL1                         0x00f6
768 #define RT5663_JD_CTRL2                         0x00f8
769 #define RT5663_DIG_MISC                         0x00fa
770 #define RT5663_DIG_VOL_ZCD                      0x0100
771 #define RT5663_ANA_BIAS_CUR_1                   0x0108
772 #define RT5663_ANA_BIAS_CUR_2                   0x0109
773 #define RT5663_ANA_BIAS_CUR_3                   0x010a
774 #define RT5663_ANA_BIAS_CUR_4                   0x010b
775 #define RT5663_ANA_BIAS_CUR_5                   0x010c
776 #define RT5663_ANA_BIAS_CUR_6                   0x010d
777 #define RT5663_BIAS_CUR_5                       0x010e
778 #define RT5663_BIAS_CUR_6                       0x010f
779 #define RT5663_BIAS_CUR_7                       0x0110
780 #define RT5663_BIAS_CUR_8                       0x0111
781 #define RT5663_DACREF_LDO                       0x0112
782 #define RT5663_DUMMY_REG_3                      0x0113
783 #define RT5663_BIAS_CUR_9                       0x0114
784 #define RT5663_DUMMY_REG_4                      0x0116
785 #define RT5663_VREFADJ_OP                       0x0117
786 #define RT5663_VREF_RECMIX                      0x0118
787 #define RT5663_CHARGE_PUMP_1                    0x0125
788 #define RT5663_CHARGE_PUMP_1_2                  0x0126
789 #define RT5663_CHARGE_PUMP_1_3                  0x0127
790 #define RT5663_CHARGE_PUMP_2                    0x0128
791 #define RT5663_DIG_IN_PIN1                      0x0132
792 #define RT5663_PAD_DRV_CTL                      0x0137
793 #define RT5663_PLL_INT_REG                      0x0139
794 #define RT5663_CHOP_DAC_L                       0x013a
795 #define RT5663_CHOP_ADC                         0x013b
796 #define RT5663_CALIB_ADC                        0x013c
797 #define RT5663_CHOP_DAC_R                       0x013d
798 #define RT5663_DUMMY_CTL_DACLR                  0x013e
799 #define RT5663_DUMMY_REG_5                      0x0140
800 #define RT5663_SOFT_RAMP                        0x0141
801 #define RT5663_TEST_MODE_1                      0x0144
802 #define RT5663_TEST_MODE_2                      0x0145
803 #define RT5663_TEST_MODE_3                      0x0146
804 #define RT5663_TEST_MODE_4                      0x0147
805 #define RT5663_TEST_MODE_5                      0x0148
806 #define RT5663_STO_DRE_1                        0x0160
807 #define RT5663_STO_DRE_2                        0x0161
808 #define RT5663_STO_DRE_3                        0x0162
809 #define RT5663_STO_DRE_4                        0x0163
810 #define RT5663_STO_DRE_5                        0x0164
811 #define RT5663_STO_DRE_6                        0x0165
812 #define RT5663_STO_DRE_7                        0x0166
813 #define RT5663_STO_DRE_8                        0x0167
814 #define RT5663_STO_DRE_9                        0x0168
815 #define RT5663_STO_DRE_10                       0x0169
816 #define RT5663_MIC_DECRO_1                      0x0180
817 #define RT5663_MIC_DECRO_2                      0x0181
818 #define RT5663_MIC_DECRO_3                      0x0182
819 #define RT5663_MIC_DECRO_4                      0x0183
820 #define RT5663_MIC_DECRO_5                      0x0184
821 #define RT5663_MIC_DECRO_6                      0x0185
822 #define RT5663_HP_DECRO_1                       0x01b0
823 #define RT5663_HP_DECRO_2                       0x01b1
824 #define RT5663_HP_DECRO_3                       0x01b2
825 #define RT5663_HP_DECRO_4                       0x01b3
826 #define RT5663_HP_DECOUP                        0x01b4
827 #define RT5663_HP_IMP_SEN_MAP8                  0x01b5
828 #define RT5663_HP_IMP_SEN_MAP9                  0x01b6
829 #define RT5663_HP_IMP_SEN_MAP10                 0x01b7
830 #define RT5663_HP_IMP_SEN_MAP11                 0x01b8
831 #define RT5663_HP_IMP_SEN_1                     0x01c0
832 #define RT5663_HP_IMP_SEN_2                     0x01c1
833 #define RT5663_HP_IMP_SEN_3                     0x01c2
834 #define RT5663_HP_IMP_SEN_4                     0x01c3
835 #define RT5663_HP_IMP_SEN_5                     0x01c4
836 #define RT5663_HP_IMP_SEN_6                     0x01c5
837 #define RT5663_HP_IMP_SEN_7                     0x01c6
838 #define RT5663_HP_IMP_SEN_8                     0x01c7
839 #define RT5663_HP_IMP_SEN_9                     0x01c8
840 #define RT5663_HP_IMP_SEN_10                    0x01c9
841 #define RT5663_HP_IMP_SEN_11                    0x01ca
842 #define RT5663_HP_IMP_SEN_12                    0x01cb
843 #define RT5663_HP_IMP_SEN_13                    0x01cc
844 #define RT5663_HP_IMP_SEN_14                    0x01cd
845 #define RT5663_HP_IMP_SEN_15                    0x01ce
846 #define RT5663_HP_IMP_SEN_16                    0x01cf
847 #define RT5663_HP_IMP_SEN_17                    0x01d0
848 #define RT5663_HP_IMP_SEN_18                    0x01d1
849 #define RT5663_HP_IMP_SEN_19                    0x01d2
850 #define RT5663_HP_IMPSEN_DIG5                   0x01d3
851 #define RT5663_HP_IMPSEN_MAP1                   0x01d4
852 #define RT5663_HP_IMPSEN_MAP2                   0x01d5
853 #define RT5663_HP_IMPSEN_MAP3                   0x01d6
854 #define RT5663_HP_IMPSEN_MAP4                   0x01d7
855 #define RT5663_HP_IMPSEN_MAP5                   0x01d8
856 #define RT5663_HP_IMPSEN_MAP7                   0x01d9
857 #define RT5663_HP_LOGIC_1                       0x01da
858 #define RT5663_HP_LOGIC_2                       0x01db
859 #define RT5663_HP_CALIB_1                       0x01dd
860 #define RT5663_HP_CALIB_1_1                     0x01de
861 #define RT5663_HP_CALIB_2                       0x01df
862 #define RT5663_HP_CALIB_3                       0x01e0
863 #define RT5663_HP_CALIB_4                       0x01e1
864 #define RT5663_HP_CALIB_5                       0x01e2
865 #define RT5663_HP_CALIB_5_1                     0x01e3
866 #define RT5663_HP_CALIB_6                       0x01e4
867 #define RT5663_HP_CALIB_7                       0x01e5
868 #define RT5663_HP_CALIB_9                       0x01e6
869 #define RT5663_HP_CALIB_10                      0x01e7
870 #define RT5663_HP_CALIB_11                      0x01e8
871 #define RT5663_HP_CALIB_ST1                     0x01ea
872 #define RT5663_HP_CALIB_ST2                     0x01eb
873 #define RT5663_HP_CALIB_ST3                     0x01ec
874 #define RT5663_HP_CALIB_ST4                     0x01ed
875 #define RT5663_HP_CALIB_ST5                     0x01ee
876 #define RT5663_HP_CALIB_ST6                     0x01ef
877 #define RT5663_HP_CALIB_ST7                     0x01f0
878 #define RT5663_HP_CALIB_ST8                     0x01f1
879 #define RT5663_HP_CALIB_ST9                     0x01f2
880 #define RT5663_HP_AMP_DET                       0x0200
881 #define RT5663_DUMMY_REG_6                      0x0201
882 #define RT5663_HP_BIAS                          0x0202
883 #define RT5663_CBJ_1                            0x0250
884 #define RT5663_CBJ_2                            0x0251
885 #define RT5663_CBJ_3                            0x0252
886 #define RT5663_DUMMY_1                          0x02fa
887 #define RT5663_DUMMY_2                          0x02fb
888 #define RT5663_DUMMY_3                          0x02fc
889 #define RT5663_ANA_JD                           0x0300
890 #define RT5663_ADC_LCH_LPF1_A1                  0x03d0
891 #define RT5663_ADC_RCH_LPF1_A1                  0x03d1
892 #define RT5663_ADC_LCH_LPF1_H0                  0x03d2
893 #define RT5663_ADC_RCH_LPF1_H0                  0x03d3
894 #define RT5663_ADC_LCH_BPF1_A1                  0x03d4
895 #define RT5663_ADC_RCH_BPF1_A1                  0x03d5
896 #define RT5663_ADC_LCH_BPF1_A2                  0x03d6
897 #define RT5663_ADC_RCH_BPF1_A2                  0x03d7
898 #define RT5663_ADC_LCH_BPF1_H0                  0x03d8
899 #define RT5663_ADC_RCH_BPF1_H0                  0x03d9
900 #define RT5663_ADC_LCH_BPF2_A1                  0x03da
901 #define RT5663_ADC_RCH_BPF2_A1                  0x03db
902 #define RT5663_ADC_LCH_BPF2_A2                  0x03dc
903 #define RT5663_ADC_RCH_BPF2_A2                  0x03dd
904 #define RT5663_ADC_LCH_BPF2_H0                  0x03de
905 #define RT5663_ADC_RCH_BPF2_H0                  0x03df
906 #define RT5663_ADC_LCH_BPF3_A1                  0x03e0
907 #define RT5663_ADC_RCH_BPF3_A1                  0x03e1
908 #define RT5663_ADC_LCH_BPF3_A2                  0x03e2
909 #define RT5663_ADC_RCH_BPF3_A2                  0x03e3
910 #define RT5663_ADC_LCH_BPF3_H0                  0x03e4
911 #define RT5663_ADC_RCH_BPF3_H0                  0x03e5
912 #define RT5663_ADC_LCH_BPF4_A1                  0x03e6
913 #define RT5663_ADC_RCH_BPF4_A1                  0x03e7
914 #define RT5663_ADC_LCH_BPF4_A2                  0x03e8
915 #define RT5663_ADC_RCH_BPF4_A2                  0x03e9
916 #define RT5663_ADC_LCH_BPF4_H0                  0x03ea
917 #define RT5663_ADC_RCH_BPF4_H0                  0x03eb
918 #define RT5663_ADC_LCH_HPF1_A1                  0x03ec
919 #define RT5663_ADC_RCH_HPF1_A1                  0x03ed
920 #define RT5663_ADC_LCH_HPF1_H0                  0x03ee
921 #define RT5663_ADC_RCH_HPF1_H0                  0x03ef
922 #define RT5663_ADC_EQ_PRE_VOL_L                 0x03f0
923 #define RT5663_ADC_EQ_PRE_VOL_R                 0x03f1
924 #define RT5663_ADC_EQ_POST_VOL_L                0x03f2
925 #define RT5663_ADC_EQ_POST_VOL_R                0x03f3
926
927 /* RECMIX Control (0x0010) */
928 #define RT5663_RECMIX1_BST1_MASK                (0x1)
929 #define RT5663_RECMIX1_BST1_SHIFT               0
930 #define RT5663_RECMIX1_BST1_ON                  (0x0)
931 #define RT5663_RECMIX1_BST1_OFF                 (0x1)
932
933 /* Bypass Stereo1 DAC Mixer Control (0x002d) */
934 #define RT5663_DACL1_SRC_MASK                   (0x1 << 3)
935 #define RT5663_DACL1_SRC_SHIFT                  3
936 #define RT5663_DACR1_SRC_MASK                   (0x1 << 2)
937 #define RT5663_DACR1_SRC_SHIFT                  2
938
939 /* TDM control 2 (0x0078) */
940 #define RT5663_DATA_SWAP_ADCDAT1_MASK           (0x3 << 14)
941 #define RT5663_DATA_SWAP_ADCDAT1_SHIFT          14
942 #define RT5663_DATA_SWAP_ADCDAT1_LR             (0x0 << 14)
943 #define RT5663_DATA_SWAP_ADCDAT1_RL             (0x1 << 14)
944 #define RT5663_DATA_SWAP_ADCDAT1_LL             (0x2 << 14)
945 #define RT5663_DATA_SWAP_ADCDAT1_RR             (0x3 << 14)
946
947 /* TDM control 5 (0x007b) */
948 #define RT5663_TDM_LENGTN_MASK                  (0x3)
949 #define RT5663_TDM_LENGTN_SHIFT                 0
950 #define RT5663_TDM_LENGTN_16                    (0x0)
951 #define RT5663_TDM_LENGTN_20                    (0x1)
952 #define RT5663_TDM_LENGTN_24                    (0x2)
953 #define RT5663_TDM_LENGTN_32                    (0x3)
954
955 /* PLL tracking mode 1 (0x0083) */
956 #define RT5663_I2S1_ASRC_MASK                   (0x1 << 11)
957 #define RT5663_I2S1_ASRC_SHIFT                  11
958 #define RT5663_DAC_STO1_ASRC_MASK               (0x1 << 10)
959 #define RT5663_DAC_STO1_ASRC_SHIFT              10
960 #define RT5663_ADC_STO1_ASRC_MASK               (0x1 << 3)
961 #define RT5663_ADC_STO1_ASRC_SHIFT              3
962
963 /* PLL tracking mode 2 (0x0084)*/
964 #define RT5663_DA_STO1_TRACK_MASK               (0x7 << 12)
965 #define RT5663_DA_STO1_TRACK_SHIFT              12
966 #define RT5663_DA_STO1_TRACK_SYSCLK             (0x0 << 12)
967 #define RT5663_DA_STO1_TRACK_I2S1               (0x1 << 12)
968 #define RT5663_AD_STO1_TRACK_MASK               (0x7)
969 #define RT5663_AD_STO1_TRACK_SHIFT              0
970 #define RT5663_AD_STO1_TRACK_SYSCLK             (0x0)
971 #define RT5663_AD_STO1_TRACK_I2S1               (0x1)
972
973 /* HPOUT Charge pump control 1 (0x0091) */
974 #define RT5663_SI_HP_MASK                       (0x1 << 12)
975 #define RT5663_SI_HP_SHIFT                      12
976 #define RT5663_SI_HP_EN                         (0x1 << 12)
977 #define RT5663_SI_HP_DIS                        (0x0 << 12)
978
979 /* GPIO Control 2 (0x00b6) */
980 #define RT5663_GP1_PIN_CONF_MASK                (0x1 << 2)
981 #define RT5663_GP1_PIN_CONF_SHIFT               2
982 #define RT5663_GP1_PIN_CONF_OUTPUT              (0x1 << 2)
983 #define RT5663_GP1_PIN_CONF_INPUT               (0x0 << 2)
984
985 /* GPIO Control 2 (0x00b7) */
986 #define RT5663_EN_IRQ_INLINE_MASK               (0x1 << 3)
987 #define RT5663_EN_IRQ_INLINE_SHIFT              3
988 #define RT5663_EN_IRQ_INLINE_NOR                (0x1 << 3)
989 #define RT5663_EN_IRQ_INLINE_BYP                (0x0 << 3)
990
991 /* GPIO Control 1 (0x00c0) */
992 #define RT5663_GPIO1_TYPE_MASK                  (0x1 << 15)
993 #define RT5663_GPIO1_TYPE_SHIFT                 15
994 #define RT5663_GPIO1_TYPE_EN                    (0x1 << 15)
995 #define RT5663_GPIO1_TYPE_DIS                   (0x0 << 15)
996
997 /* IRQ Control 1 (0x00c1) */
998 #define RT5663_EN_IRQ_JD1_MASK                  (0x1 << 6)
999 #define RT5663_EN_IRQ_JD1_SHIFT                 6
1000 #define RT5663_EN_IRQ_JD1_EN                    (0x1 << 6)
1001 #define RT5663_EN_IRQ_JD1_DIS                   (0x0 << 6)
1002 #define RT5663_SEL_GPIO1_MASK                   (0x1 << 2)
1003 #define RT5663_SEL_GPIO1_SHIFT                  6
1004 #define RT5663_SEL_GPIO1_EN                     (0x1 << 2)
1005 #define RT5663_SEL_GPIO1_DIS                    (0x0 << 2)
1006
1007 /* Inline Command Function 2 (0x00dc) */
1008 #define RT5663_PWR_MIC_DET_MASK                 (0x1)
1009 #define RT5663_PWR_MIC_DET_SHIFT                0
1010 #define RT5663_PWR_MIC_DET_ON                   (0x1)
1011 #define RT5663_PWR_MIC_DET_OFF                  (0x0)
1012
1013 /* Embeeded Jack and Type Detection Control 1 (0x00e6)*/
1014 #define RT5663_CBJ_DET_MASK                     (0x1 << 15)
1015 #define RT5663_CBJ_DET_SHIFT                    15
1016 #define RT5663_CBJ_DET_DIS                      (0x0 << 15)
1017 #define RT5663_CBJ_DET_EN                       (0x1 << 15)
1018 #define RT5663_EXT_JD_MASK                      (0x1 << 11)
1019 #define RT5663_EXT_JD_SHIFT                     11
1020 #define RT5663_EXT_JD_EN                        (0x1 << 11)
1021 #define RT5663_EXT_JD_DIS                       (0x0 << 11)
1022 #define RT5663_POL_EXT_JD_MASK                  (0x1 << 10)
1023 #define RT5663_POL_EXT_JD_SHIFT                 10
1024 #define RT5663_POL_EXT_JD_EN                    (0x1 << 10)
1025 #define RT5663_POL_EXT_JD_DIS                   (0x0 << 10)
1026
1027 /* DACREF LDO Control (0x0112)*/
1028 #define RT5663_PWR_LDO_DACREFL_MASK             (0x1 << 9)
1029 #define RT5663_PWR_LDO_DACREFL_SHIFT            9
1030 #define RT5663_PWR_LDO_DACREFR_MASK             (0x1 << 1)
1031 #define RT5663_PWR_LDO_DACREFR_SHIFT            1
1032
1033 /* Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/
1034 #define RT5663_DRE_GAIN_HP_MASK                 (0x1f)
1035 #define RT5663_DRE_GAIN_HP_SHIFT                0
1036
1037 /* Combo Jack Control (0x0250) */
1038 #define RT5663_INBUF_CBJ_BST1_MASK              (0x1 << 11)
1039 #define RT5663_INBUF_CBJ_BST1_SHIFT             11
1040 #define RT5663_INBUF_CBJ_BST1_ON                (0x1 << 11)
1041 #define RT5663_INBUF_CBJ_BST1_OFF               (0x0 << 11)
1042 #define RT5663_CBJ_SENSE_BST1_MASK              (0x1 << 10)
1043 #define RT5663_CBJ_SENSE_BST1_SHIFT             10
1044 #define RT5663_CBJ_SENSE_BST1_L                 (0x1 << 10)
1045 #define RT5663_CBJ_SENSE_BST1_R                 (0x0 << 10)
1046
1047 /* Combo Jack Control (0x0251) */
1048 #define RT5663_GAIN_BST1_MASK                   (0xf)
1049 #define RT5663_GAIN_BST1_SHIFT                  0
1050
1051 /* Dummy register 1 (0x02fa) */
1052 #define RT5663_EMB_CLK_MASK                     (0x1 << 9)
1053 #define RT5663_EMB_CLK_SHIFT                    9
1054 #define RT5663_EMB_CLK_EN                       (0x1 << 9)
1055 #define RT5663_EMB_CLK_DIS                      (0x0 << 9)
1056 #define RT5663_HPA_CPL_BIAS_MASK                (0x7 << 6)
1057 #define RT5663_HPA_CPL_BIAS_SHIFT               6
1058 #define RT5663_HPA_CPL_BIAS_0_5                 (0x0 << 6)
1059 #define RT5663_HPA_CPL_BIAS_1                   (0x1 << 6)
1060 #define RT5663_HPA_CPL_BIAS_2                   (0x2 << 6)
1061 #define RT5663_HPA_CPL_BIAS_3                   (0x3 << 6)
1062 #define RT5663_HPA_CPL_BIAS_4_1                 (0x4 << 6)
1063 #define RT5663_HPA_CPL_BIAS_4_2                 (0x5 << 6)
1064 #define RT5663_HPA_CPL_BIAS_6                   (0x6 << 6)
1065 #define RT5663_HPA_CPL_BIAS_8                   (0x7 << 6)
1066 #define RT5663_HPA_CPR_BIAS_MASK                (0x7 << 3)
1067 #define RT5663_HPA_CPR_BIAS_SHIFT               3
1068 #define RT5663_HPA_CPR_BIAS_0_5                 (0x0 << 3)
1069 #define RT5663_HPA_CPR_BIAS_1                   (0x1 << 3)
1070 #define RT5663_HPA_CPR_BIAS_2                   (0x2 << 3)
1071 #define RT5663_HPA_CPR_BIAS_3                   (0x3 << 3)
1072 #define RT5663_HPA_CPR_BIAS_4_1                 (0x4 << 3)
1073 #define RT5663_HPA_CPR_BIAS_4_2                 (0x5 << 3)
1074 #define RT5663_HPA_CPR_BIAS_6                   (0x6 << 3)
1075 #define RT5663_HPA_CPR_BIAS_8                   (0x7 << 3)
1076 #define RT5663_DUMMY_BIAS_MASK                  (0x7)
1077 #define RT5663_DUMMY_BIAS_SHIFT                 0
1078 #define RT5663_DUMMY_BIAS_0_5                   (0x0)
1079 #define RT5663_DUMMY_BIAS_1                     (0x1)
1080 #define RT5663_DUMMY_BIAS_2                     (0x2)
1081 #define RT5663_DUMMY_BIAS_3                     (0x3)
1082 #define RT5663_DUMMY_BIAS_4_1                   (0x4)
1083 #define RT5663_DUMMY_BIAS_4_2                   (0x5)
1084 #define RT5663_DUMMY_BIAS_6                     (0x6)
1085 #define RT5663_DUMMY_BIAS_8                     (0x7)
1086
1087
1088 /* System Clock Source */
1089 enum {
1090         RT5663_SCLK_S_MCLK,
1091         RT5663_SCLK_S_PLL1,
1092         RT5663_SCLK_S_RCCLK,
1093 };
1094
1095 /* PLL1 Source */
1096 enum {
1097         RT5663_PLL1_S_MCLK,
1098         RT5663_PLL1_S_BCLK1,
1099 };
1100
1101 enum {
1102         RT5663_AIF,
1103         RT5663_AIFS,
1104 };
1105
1106 /* asrc clock source */
1107 enum {
1108         RT5663_CLK_SEL_SYS = 0x0,
1109         RT5663_CLK_SEL_I2S1_ASRC = 0x1,
1110 };
1111
1112 /* filter mask */
1113 enum {
1114         RT5663_DA_STEREO_FILTER = 0x1,
1115         RT5663_AD_STEREO_FILTER = 0x2,
1116 };
1117
1118 int rt5663_set_jack_detect(struct snd_soc_codec *codec,
1119         struct snd_soc_jack *hs_jack);
1120 int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1121         unsigned int filter_mask, unsigned int clk_src);
1122
1123 #endif /* __RT5663_H__ */