2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/regmap.h>
19 #include <linux/i2c.h>
20 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
22 #include <linux/gpio.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
34 #define RT5677_DEVICE_ID 0x6327
36 #define RT5677_PR_RANGE_BASE (0xff + 1)
37 #define RT5677_PR_SPACING 0x100
39 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
41 static const struct regmap_range_cfg rt5677_ranges[] = {
44 .range_min = RT5677_PR_BASE,
45 .range_max = RT5677_PR_BASE + 0xfd,
46 .selector_reg = RT5677_PRIV_INDEX,
47 .selector_mask = 0xff,
48 .selector_shift = 0x0,
49 .window_start = RT5677_PRIV_DATA,
54 static const struct reg_default init_list[] = {
55 {RT5677_PR_BASE + 0x3d, 0x364d},
56 {RT5677_PR_BASE + 0x17, 0x4fc0},
57 {RT5677_PR_BASE + 0x13, 0x0312},
58 {RT5677_PR_BASE + 0x1e, 0x0000},
59 {RT5677_PR_BASE + 0x12, 0x0eaa},
60 {RT5677_PR_BASE + 0x14, 0x018a},
62 #define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
64 static const struct reg_default rt5677_reg[] = {
65 {RT5677_RESET , 0x0000},
66 {RT5677_LOUT1 , 0xa800},
67 {RT5677_IN1 , 0x0000},
68 {RT5677_MICBIAS , 0x0000},
69 {RT5677_SLIMBUS_PARAM , 0x0000},
70 {RT5677_SLIMBUS_RX , 0x0000},
71 {RT5677_SLIMBUS_CTRL , 0x0000},
72 {RT5677_SIDETONE_CTRL , 0x000b},
73 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
74 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
75 {RT5677_DAC4_DIG_VOL , 0xafaf},
76 {RT5677_DAC3_DIG_VOL , 0xafaf},
77 {RT5677_DAC1_DIG_VOL , 0xafaf},
78 {RT5677_DAC2_DIG_VOL , 0xafaf},
79 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
80 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
81 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
82 {RT5677_STO1_2_ADC_BST , 0x0000},
83 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
84 {RT5677_ADC_BST_CTRL2 , 0x0000},
85 {RT5677_STO3_4_ADC_BST , 0x0000},
86 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
87 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
88 {RT5677_STO4_ADC_MIXER , 0xd4c0},
89 {RT5677_STO3_ADC_MIXER , 0xd4c0},
90 {RT5677_STO2_ADC_MIXER , 0xd4c0},
91 {RT5677_STO1_ADC_MIXER , 0xd4c0},
92 {RT5677_MONO_ADC_MIXER , 0xd4d1},
93 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
94 {RT5677_STO1_DAC_MIXER , 0xaaaa},
95 {RT5677_MONO_DAC_MIXER , 0xaaaa},
96 {RT5677_DD1_MIXER , 0xaaaa},
97 {RT5677_DD2_MIXER , 0xaaaa},
98 {RT5677_IF3_DATA , 0x0000},
99 {RT5677_IF4_DATA , 0x0000},
100 {RT5677_PDM_OUT_CTRL , 0x8888},
101 {RT5677_PDM_DATA_CTRL1 , 0x0000},
102 {RT5677_PDM_DATA_CTRL2 , 0x0000},
103 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
104 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
105 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
106 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
107 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
108 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
109 {RT5677_TDM1_CTRL1 , 0x0300},
110 {RT5677_TDM1_CTRL2 , 0x0000},
111 {RT5677_TDM1_CTRL3 , 0x4000},
112 {RT5677_TDM1_CTRL4 , 0x0123},
113 {RT5677_TDM1_CTRL5 , 0x4567},
114 {RT5677_TDM2_CTRL1 , 0x0300},
115 {RT5677_TDM2_CTRL2 , 0x0000},
116 {RT5677_TDM2_CTRL3 , 0x4000},
117 {RT5677_TDM2_CTRL4 , 0x0123},
118 {RT5677_TDM2_CTRL5 , 0x4567},
119 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
120 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
121 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
122 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
123 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
124 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
125 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
126 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
127 {RT5677_DMIC_CTRL1 , 0x1505},
128 {RT5677_DMIC_CTRL2 , 0x0055},
129 {RT5677_HAP_GENE_CTRL1 , 0x0111},
130 {RT5677_HAP_GENE_CTRL2 , 0x0064},
131 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
132 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
133 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
134 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
135 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
136 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
137 {RT5677_HAP_GENE_CTRL9 , 0xf000},
138 {RT5677_HAP_GENE_CTRL10 , 0x0000},
139 {RT5677_PWR_DIG1 , 0x0000},
140 {RT5677_PWR_DIG2 , 0x0000},
141 {RT5677_PWR_ANLG1 , 0x0055},
142 {RT5677_PWR_ANLG2 , 0x0000},
143 {RT5677_PWR_DSP1 , 0x0001},
144 {RT5677_PWR_DSP_ST , 0x0000},
145 {RT5677_PWR_DSP2 , 0x0000},
146 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
147 {RT5677_PRIV_INDEX , 0x0000},
148 {RT5677_PRIV_DATA , 0x0000},
149 {RT5677_I2S4_SDP , 0x8000},
150 {RT5677_I2S1_SDP , 0x8000},
151 {RT5677_I2S2_SDP , 0x8000},
152 {RT5677_I2S3_SDP , 0x8000},
153 {RT5677_CLK_TREE_CTRL1 , 0x1111},
154 {RT5677_CLK_TREE_CTRL2 , 0x1111},
155 {RT5677_CLK_TREE_CTRL3 , 0x0000},
156 {RT5677_PLL1_CTRL1 , 0x0000},
157 {RT5677_PLL1_CTRL2 , 0x0000},
158 {RT5677_PLL2_CTRL1 , 0x0c60},
159 {RT5677_PLL2_CTRL2 , 0x2000},
160 {RT5677_GLB_CLK1 , 0x0000},
161 {RT5677_GLB_CLK2 , 0x0000},
162 {RT5677_ASRC_1 , 0x0000},
163 {RT5677_ASRC_2 , 0x0000},
164 {RT5677_ASRC_3 , 0x0000},
165 {RT5677_ASRC_4 , 0x0000},
166 {RT5677_ASRC_5 , 0x0000},
167 {RT5677_ASRC_6 , 0x0000},
168 {RT5677_ASRC_7 , 0x0000},
169 {RT5677_ASRC_8 , 0x0000},
170 {RT5677_ASRC_9 , 0x0000},
171 {RT5677_ASRC_10 , 0x0000},
172 {RT5677_ASRC_11 , 0x0000},
173 {RT5677_ASRC_12 , 0x0008},
174 {RT5677_ASRC_13 , 0x0000},
175 {RT5677_ASRC_14 , 0x0000},
176 {RT5677_ASRC_15 , 0x0000},
177 {RT5677_ASRC_16 , 0x0000},
178 {RT5677_ASRC_17 , 0x0000},
179 {RT5677_ASRC_18 , 0x0000},
180 {RT5677_ASRC_19 , 0x0000},
181 {RT5677_ASRC_20 , 0x0000},
182 {RT5677_ASRC_21 , 0x000c},
183 {RT5677_ASRC_22 , 0x0000},
184 {RT5677_ASRC_23 , 0x0000},
185 {RT5677_VAD_CTRL1 , 0x2184},
186 {RT5677_VAD_CTRL2 , 0x010a},
187 {RT5677_VAD_CTRL3 , 0x0aea},
188 {RT5677_VAD_CTRL4 , 0x000c},
189 {RT5677_VAD_CTRL5 , 0x0000},
190 {RT5677_DSP_INB_CTRL1 , 0x0000},
191 {RT5677_DSP_INB_CTRL2 , 0x0000},
192 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
193 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
194 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
195 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
196 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
197 {RT5677_ADC_EQ_CTRL1 , 0x6000},
198 {RT5677_ADC_EQ_CTRL2 , 0x0000},
199 {RT5677_EQ_CTRL1 , 0xc000},
200 {RT5677_EQ_CTRL2 , 0x0000},
201 {RT5677_EQ_CTRL3 , 0x0000},
202 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
203 {RT5677_JD_CTRL1 , 0x0000},
204 {RT5677_JD_CTRL2 , 0x0000},
205 {RT5677_JD_CTRL3 , 0x0000},
206 {RT5677_IRQ_CTRL1 , 0x0000},
207 {RT5677_IRQ_CTRL2 , 0x0000},
208 {RT5677_GPIO_ST , 0x0000},
209 {RT5677_GPIO_CTRL1 , 0x0000},
210 {RT5677_GPIO_CTRL2 , 0x0000},
211 {RT5677_GPIO_CTRL3 , 0x0000},
212 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
213 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
214 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
215 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
216 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
217 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
218 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
219 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
221 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
222 {RT5677_MB_DRC_CTRL1 , 0x0f20},
223 {RT5677_DRC1_CTRL1 , 0x001f},
224 {RT5677_DRC1_CTRL2 , 0x020c},
225 {RT5677_DRC1_CTRL3 , 0x1f00},
226 {RT5677_DRC1_CTRL4 , 0x0000},
227 {RT5677_DRC1_CTRL5 , 0x0000},
228 {RT5677_DRC1_CTRL6 , 0x0029},
229 {RT5677_DRC2_CTRL1 , 0x001f},
230 {RT5677_DRC2_CTRL2 , 0x020c},
231 {RT5677_DRC2_CTRL3 , 0x1f00},
232 {RT5677_DRC2_CTRL4 , 0x0000},
233 {RT5677_DRC2_CTRL5 , 0x0000},
234 {RT5677_DRC2_CTRL6 , 0x0029},
235 {RT5677_DRC1_HL_CTRL1 , 0x8000},
236 {RT5677_DRC1_HL_CTRL2 , 0x0200},
237 {RT5677_DRC2_HL_CTRL1 , 0x8000},
238 {RT5677_DRC2_HL_CTRL2 , 0x0200},
239 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
240 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
241 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
242 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
243 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
244 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
245 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
246 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
247 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
248 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
249 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
250 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
251 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
252 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
253 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
254 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
255 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
256 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
257 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
258 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
259 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
260 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
261 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
262 {RT5677_DIG_MISC , 0x0000},
263 {RT5677_GEN_CTRL1 , 0x0000},
264 {RT5677_GEN_CTRL2 , 0x0000},
265 {RT5677_VENDOR_ID , 0x0000},
266 {RT5677_VENDOR_ID1 , 0x10ec},
267 {RT5677_VENDOR_ID2 , 0x6327},
270 static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
274 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
275 if (reg >= rt5677_ranges[i].range_min &&
276 reg <= rt5677_ranges[i].range_max) {
283 case RT5677_SLIMBUS_PARAM:
284 case RT5677_PDM_DATA_CTRL1:
285 case RT5677_PDM_DATA_CTRL2:
286 case RT5677_PDM1_DATA_CTRL4:
287 case RT5677_PDM2_DATA_CTRL4:
288 case RT5677_I2C_MASTER_CTRL1:
289 case RT5677_I2C_MASTER_CTRL7:
290 case RT5677_I2C_MASTER_CTRL8:
291 case RT5677_HAP_GENE_CTRL2:
292 case RT5677_PWR_DSP_ST:
293 case RT5677_PRIV_DATA:
294 case RT5677_PLL1_CTRL2:
295 case RT5677_PLL2_CTRL2:
298 case RT5677_VAD_CTRL5:
299 case RT5677_ADC_EQ_CTRL1:
300 case RT5677_EQ_CTRL1:
301 case RT5677_IRQ_CTRL1:
302 case RT5677_IRQ_CTRL2:
304 case RT5677_DSP_INB1_SRC_CTRL4:
305 case RT5677_DSP_INB2_SRC_CTRL4:
306 case RT5677_DSP_INB3_SRC_CTRL4:
307 case RT5677_DSP_OUTB1_SRC_CTRL4:
308 case RT5677_DSP_OUTB2_SRC_CTRL4:
309 case RT5677_VENDOR_ID:
310 case RT5677_VENDOR_ID1:
311 case RT5677_VENDOR_ID2:
318 static bool rt5677_readable_register(struct device *dev, unsigned int reg)
322 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
323 if (reg >= rt5677_ranges[i].range_min &&
324 reg <= rt5677_ranges[i].range_max) {
334 case RT5677_SLIMBUS_PARAM:
335 case RT5677_SLIMBUS_RX:
336 case RT5677_SLIMBUS_CTRL:
337 case RT5677_SIDETONE_CTRL:
338 case RT5677_ANA_DAC1_2_3_SRC:
339 case RT5677_IF_DSP_DAC3_4_MIXER:
340 case RT5677_DAC4_DIG_VOL:
341 case RT5677_DAC3_DIG_VOL:
342 case RT5677_DAC1_DIG_VOL:
343 case RT5677_DAC2_DIG_VOL:
344 case RT5677_IF_DSP_DAC2_MIXER:
345 case RT5677_STO1_ADC_DIG_VOL:
346 case RT5677_MONO_ADC_DIG_VOL:
347 case RT5677_STO1_2_ADC_BST:
348 case RT5677_STO2_ADC_DIG_VOL:
349 case RT5677_ADC_BST_CTRL2:
350 case RT5677_STO3_4_ADC_BST:
351 case RT5677_STO3_ADC_DIG_VOL:
352 case RT5677_STO4_ADC_DIG_VOL:
353 case RT5677_STO4_ADC_MIXER:
354 case RT5677_STO3_ADC_MIXER:
355 case RT5677_STO2_ADC_MIXER:
356 case RT5677_STO1_ADC_MIXER:
357 case RT5677_MONO_ADC_MIXER:
358 case RT5677_ADC_IF_DSP_DAC1_MIXER:
359 case RT5677_STO1_DAC_MIXER:
360 case RT5677_MONO_DAC_MIXER:
361 case RT5677_DD1_MIXER:
362 case RT5677_DD2_MIXER:
363 case RT5677_IF3_DATA:
364 case RT5677_IF4_DATA:
365 case RT5677_PDM_OUT_CTRL:
366 case RT5677_PDM_DATA_CTRL1:
367 case RT5677_PDM_DATA_CTRL2:
368 case RT5677_PDM1_DATA_CTRL2:
369 case RT5677_PDM1_DATA_CTRL3:
370 case RT5677_PDM1_DATA_CTRL4:
371 case RT5677_PDM2_DATA_CTRL2:
372 case RT5677_PDM2_DATA_CTRL3:
373 case RT5677_PDM2_DATA_CTRL4:
374 case RT5677_TDM1_CTRL1:
375 case RT5677_TDM1_CTRL2:
376 case RT5677_TDM1_CTRL3:
377 case RT5677_TDM1_CTRL4:
378 case RT5677_TDM1_CTRL5:
379 case RT5677_TDM2_CTRL1:
380 case RT5677_TDM2_CTRL2:
381 case RT5677_TDM2_CTRL3:
382 case RT5677_TDM2_CTRL4:
383 case RT5677_TDM2_CTRL5:
384 case RT5677_I2C_MASTER_CTRL1:
385 case RT5677_I2C_MASTER_CTRL2:
386 case RT5677_I2C_MASTER_CTRL3:
387 case RT5677_I2C_MASTER_CTRL4:
388 case RT5677_I2C_MASTER_CTRL5:
389 case RT5677_I2C_MASTER_CTRL6:
390 case RT5677_I2C_MASTER_CTRL7:
391 case RT5677_I2C_MASTER_CTRL8:
392 case RT5677_DMIC_CTRL1:
393 case RT5677_DMIC_CTRL2:
394 case RT5677_HAP_GENE_CTRL1:
395 case RT5677_HAP_GENE_CTRL2:
396 case RT5677_HAP_GENE_CTRL3:
397 case RT5677_HAP_GENE_CTRL4:
398 case RT5677_HAP_GENE_CTRL5:
399 case RT5677_HAP_GENE_CTRL6:
400 case RT5677_HAP_GENE_CTRL7:
401 case RT5677_HAP_GENE_CTRL8:
402 case RT5677_HAP_GENE_CTRL9:
403 case RT5677_HAP_GENE_CTRL10:
404 case RT5677_PWR_DIG1:
405 case RT5677_PWR_DIG2:
406 case RT5677_PWR_ANLG1:
407 case RT5677_PWR_ANLG2:
408 case RT5677_PWR_DSP1:
409 case RT5677_PWR_DSP_ST:
410 case RT5677_PWR_DSP2:
411 case RT5677_ADC_DAC_HPF_CTRL1:
412 case RT5677_PRIV_INDEX:
413 case RT5677_PRIV_DATA:
414 case RT5677_I2S4_SDP:
415 case RT5677_I2S1_SDP:
416 case RT5677_I2S2_SDP:
417 case RT5677_I2S3_SDP:
418 case RT5677_CLK_TREE_CTRL1:
419 case RT5677_CLK_TREE_CTRL2:
420 case RT5677_CLK_TREE_CTRL3:
421 case RT5677_PLL1_CTRL1:
422 case RT5677_PLL1_CTRL2:
423 case RT5677_PLL2_CTRL1:
424 case RT5677_PLL2_CTRL2:
425 case RT5677_GLB_CLK1:
426 case RT5677_GLB_CLK2:
450 case RT5677_VAD_CTRL1:
451 case RT5677_VAD_CTRL2:
452 case RT5677_VAD_CTRL3:
453 case RT5677_VAD_CTRL4:
454 case RT5677_VAD_CTRL5:
455 case RT5677_DSP_INB_CTRL1:
456 case RT5677_DSP_INB_CTRL2:
457 case RT5677_DSP_IN_OUTB_CTRL:
458 case RT5677_DSP_OUTB0_1_DIG_VOL:
459 case RT5677_DSP_OUTB2_3_DIG_VOL:
460 case RT5677_DSP_OUTB4_5_DIG_VOL:
461 case RT5677_DSP_OUTB6_7_DIG_VOL:
462 case RT5677_ADC_EQ_CTRL1:
463 case RT5677_ADC_EQ_CTRL2:
464 case RT5677_EQ_CTRL1:
465 case RT5677_EQ_CTRL2:
466 case RT5677_EQ_CTRL3:
467 case RT5677_SOFT_VOL_ZERO_CROSS1:
468 case RT5677_JD_CTRL1:
469 case RT5677_JD_CTRL2:
470 case RT5677_JD_CTRL3:
471 case RT5677_IRQ_CTRL1:
472 case RT5677_IRQ_CTRL2:
474 case RT5677_GPIO_CTRL1:
475 case RT5677_GPIO_CTRL2:
476 case RT5677_GPIO_CTRL3:
477 case RT5677_STO1_ADC_HI_FILTER1:
478 case RT5677_STO1_ADC_HI_FILTER2:
479 case RT5677_MONO_ADC_HI_FILTER1:
480 case RT5677_MONO_ADC_HI_FILTER2:
481 case RT5677_STO2_ADC_HI_FILTER1:
482 case RT5677_STO2_ADC_HI_FILTER2:
483 case RT5677_STO3_ADC_HI_FILTER1:
484 case RT5677_STO3_ADC_HI_FILTER2:
485 case RT5677_STO4_ADC_HI_FILTER1:
486 case RT5677_STO4_ADC_HI_FILTER2:
487 case RT5677_MB_DRC_CTRL1:
488 case RT5677_DRC1_CTRL1:
489 case RT5677_DRC1_CTRL2:
490 case RT5677_DRC1_CTRL3:
491 case RT5677_DRC1_CTRL4:
492 case RT5677_DRC1_CTRL5:
493 case RT5677_DRC1_CTRL6:
494 case RT5677_DRC2_CTRL1:
495 case RT5677_DRC2_CTRL2:
496 case RT5677_DRC2_CTRL3:
497 case RT5677_DRC2_CTRL4:
498 case RT5677_DRC2_CTRL5:
499 case RT5677_DRC2_CTRL6:
500 case RT5677_DRC1_HL_CTRL1:
501 case RT5677_DRC1_HL_CTRL2:
502 case RT5677_DRC2_HL_CTRL1:
503 case RT5677_DRC2_HL_CTRL2:
504 case RT5677_DSP_INB1_SRC_CTRL1:
505 case RT5677_DSP_INB1_SRC_CTRL2:
506 case RT5677_DSP_INB1_SRC_CTRL3:
507 case RT5677_DSP_INB1_SRC_CTRL4:
508 case RT5677_DSP_INB2_SRC_CTRL1:
509 case RT5677_DSP_INB2_SRC_CTRL2:
510 case RT5677_DSP_INB2_SRC_CTRL3:
511 case RT5677_DSP_INB2_SRC_CTRL4:
512 case RT5677_DSP_INB3_SRC_CTRL1:
513 case RT5677_DSP_INB3_SRC_CTRL2:
514 case RT5677_DSP_INB3_SRC_CTRL3:
515 case RT5677_DSP_INB3_SRC_CTRL4:
516 case RT5677_DSP_OUTB1_SRC_CTRL1:
517 case RT5677_DSP_OUTB1_SRC_CTRL2:
518 case RT5677_DSP_OUTB1_SRC_CTRL3:
519 case RT5677_DSP_OUTB1_SRC_CTRL4:
520 case RT5677_DSP_OUTB2_SRC_CTRL1:
521 case RT5677_DSP_OUTB2_SRC_CTRL2:
522 case RT5677_DSP_OUTB2_SRC_CTRL3:
523 case RT5677_DSP_OUTB2_SRC_CTRL4:
524 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
525 case RT5677_DSP_OUTB_45_MIXER_CTRL:
526 case RT5677_DSP_OUTB_67_MIXER_CTRL:
527 case RT5677_DIG_MISC:
528 case RT5677_GEN_CTRL1:
529 case RT5677_GEN_CTRL2:
530 case RT5677_VENDOR_ID:
531 case RT5677_VENDOR_ID1:
532 case RT5677_VENDOR_ID2:
539 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
540 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
541 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
542 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
543 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
545 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
546 static unsigned int bst_tlv[] = {
547 TLV_DB_RANGE_HEAD(7),
548 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
549 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
550 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
551 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
552 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
553 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
554 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
557 static const struct snd_kcontrol_new rt5677_snd_controls[] = {
559 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
560 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
561 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
562 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
563 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
564 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
566 /* DAC Digital Volume */
567 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
568 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
569 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
570 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
571 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
572 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
573 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
574 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
576 /* IN1/IN2 Control */
577 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
578 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
580 /* ADC Digital Volume Control */
581 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
582 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
583 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
584 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
585 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
586 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
587 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
588 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
589 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
590 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
592 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
593 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
595 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
596 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
598 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
599 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
601 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
602 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
604 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
605 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0,
608 /* ADC Boost Volume Control */
609 SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
610 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
612 SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
613 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
615 SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
616 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
618 SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
619 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
621 SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
622 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
627 * set_dmic_clk - Set parameter of dmic.
630 * @kcontrol: The kcontrol of this widget.
633 * Choose dmic clock between 1MHz and 3MHz.
634 * It is better for clock to approximate 3MHz.
636 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
637 struct snd_kcontrol *kcontrol, int event)
639 struct snd_soc_codec *codec = w->codec;
640 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
641 int idx = rl6231_calc_dmic_clk(rt5677->sysclk);
644 dev_err(codec->dev, "Failed to set DMIC clock\n");
646 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
647 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
651 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
652 struct snd_soc_dapm_widget *sink)
654 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
657 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
658 val &= RT5677_SCLK_SRC_MASK;
659 if (val == RT5677_SCLK_SRC_PLL1)
666 static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
667 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
668 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
669 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
670 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
673 static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
674 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
675 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
676 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
677 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
680 static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
681 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
682 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
683 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
684 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
687 static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
688 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
689 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
690 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
691 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
694 static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
695 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
696 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
697 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
698 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
701 static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
702 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
703 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
704 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
705 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
708 static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
709 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
710 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
711 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
712 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
715 static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
716 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
717 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
718 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
719 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
722 static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
723 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
724 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
725 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
726 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
729 static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
730 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
731 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
732 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
733 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
736 static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
737 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
738 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
739 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
740 RT5677_M_DAC1_L_SFT, 1, 1),
743 static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
744 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
745 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
746 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
747 RT5677_M_DAC1_R_SFT, 1, 1),
750 static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
751 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
752 RT5677_M_ST_DAC1_L_SFT, 1, 1),
753 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
754 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
755 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
756 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
757 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
758 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
761 static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
762 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
763 RT5677_M_ST_DAC1_R_SFT, 1, 1),
764 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
765 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
766 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
767 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
768 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
769 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
772 static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
773 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
774 RT5677_M_ST_DAC2_L_SFT, 1, 1),
775 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
776 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
777 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
778 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
779 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
780 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
783 static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
784 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
785 RT5677_M_ST_DAC2_R_SFT, 1, 1),
786 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
787 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
788 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
789 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
790 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
791 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
794 static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
795 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
796 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
797 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
798 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
799 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
800 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
801 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
802 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
805 static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
806 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
807 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
808 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
809 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
810 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
811 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
812 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
813 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
816 static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
817 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
818 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
819 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
820 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
821 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
822 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
823 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
824 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
827 static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
828 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
829 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
830 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
831 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
832 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
833 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
834 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
835 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
838 static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
839 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
840 RT5677_DSP_IB_01_H_SFT, 1, 1),
841 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
842 RT5677_DSP_IB_23_H_SFT, 1, 1),
843 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
844 RT5677_DSP_IB_45_H_SFT, 1, 1),
845 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
846 RT5677_DSP_IB_6_H_SFT, 1, 1),
847 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
848 RT5677_DSP_IB_7_H_SFT, 1, 1),
849 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
850 RT5677_DSP_IB_8_H_SFT, 1, 1),
851 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
852 RT5677_DSP_IB_9_H_SFT, 1, 1),
855 static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
856 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
857 RT5677_DSP_IB_01_L_SFT, 1, 1),
858 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
859 RT5677_DSP_IB_23_L_SFT, 1, 1),
860 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
861 RT5677_DSP_IB_45_L_SFT, 1, 1),
862 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
863 RT5677_DSP_IB_6_L_SFT, 1, 1),
864 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
865 RT5677_DSP_IB_7_L_SFT, 1, 1),
866 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
867 RT5677_DSP_IB_8_L_SFT, 1, 1),
868 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
869 RT5677_DSP_IB_9_L_SFT, 1, 1),
872 static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
873 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
874 RT5677_DSP_IB_01_H_SFT, 1, 1),
875 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
876 RT5677_DSP_IB_23_H_SFT, 1, 1),
877 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
878 RT5677_DSP_IB_45_H_SFT, 1, 1),
879 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
880 RT5677_DSP_IB_6_H_SFT, 1, 1),
881 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
882 RT5677_DSP_IB_7_H_SFT, 1, 1),
883 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
884 RT5677_DSP_IB_8_H_SFT, 1, 1),
885 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
886 RT5677_DSP_IB_9_H_SFT, 1, 1),
889 static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
890 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
891 RT5677_DSP_IB_01_L_SFT, 1, 1),
892 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
893 RT5677_DSP_IB_23_L_SFT, 1, 1),
894 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
895 RT5677_DSP_IB_45_L_SFT, 1, 1),
896 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
897 RT5677_DSP_IB_6_L_SFT, 1, 1),
898 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
899 RT5677_DSP_IB_7_L_SFT, 1, 1),
900 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
901 RT5677_DSP_IB_8_L_SFT, 1, 1),
902 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
903 RT5677_DSP_IB_9_L_SFT, 1, 1),
906 static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
907 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
908 RT5677_DSP_IB_01_H_SFT, 1, 1),
909 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
910 RT5677_DSP_IB_23_H_SFT, 1, 1),
911 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
912 RT5677_DSP_IB_45_H_SFT, 1, 1),
913 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
914 RT5677_DSP_IB_6_H_SFT, 1, 1),
915 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
916 RT5677_DSP_IB_7_H_SFT, 1, 1),
917 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
918 RT5677_DSP_IB_8_H_SFT, 1, 1),
919 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
920 RT5677_DSP_IB_9_H_SFT, 1, 1),
923 static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
924 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
925 RT5677_DSP_IB_01_L_SFT, 1, 1),
926 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
927 RT5677_DSP_IB_23_L_SFT, 1, 1),
928 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
929 RT5677_DSP_IB_45_L_SFT, 1, 1),
930 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
931 RT5677_DSP_IB_6_L_SFT, 1, 1),
932 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
933 RT5677_DSP_IB_7_L_SFT, 1, 1),
934 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
935 RT5677_DSP_IB_8_L_SFT, 1, 1),
936 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
937 RT5677_DSP_IB_9_L_SFT, 1, 1),
942 /* DAC1 L/R Source */ /* MX-29 [10:8] */
943 static const char * const rt5677_dac1_src[] = {
944 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
948 static SOC_ENUM_SINGLE_DECL(
949 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
950 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
952 static const struct snd_kcontrol_new rt5677_dac1_mux =
953 SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);
955 /* ADDA1 L/R Source */ /* MX-29 [1:0] */
956 static const char * const rt5677_adda1_src[] = {
957 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
960 static SOC_ENUM_SINGLE_DECL(
961 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
962 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
964 static const struct snd_kcontrol_new rt5677_adda1_mux =
965 SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);
968 /*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
969 static const char * const rt5677_dac2l_src[] = {
970 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
974 static SOC_ENUM_SINGLE_DECL(
975 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
976 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
978 static const struct snd_kcontrol_new rt5677_dac2_l_mux =
979 SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);
981 static const char * const rt5677_dac2r_src[] = {
982 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
983 "OB 3", "Haptic Generator", "VAD ADC"
986 static SOC_ENUM_SINGLE_DECL(
987 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
988 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
990 static const struct snd_kcontrol_new rt5677_dac2_r_mux =
991 SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);
993 /*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
994 static const char * const rt5677_dac3l_src[] = {
995 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
999 static SOC_ENUM_SINGLE_DECL(
1000 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1001 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1003 static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1004 SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);
1006 static const char * const rt5677_dac3r_src[] = {
1007 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1011 static SOC_ENUM_SINGLE_DECL(
1012 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1013 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1015 static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1016 SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);
1018 /*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
1019 static const char * const rt5677_dac4l_src[] = {
1020 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1024 static SOC_ENUM_SINGLE_DECL(
1025 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1026 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1028 static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1029 SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);
1031 static const char * const rt5677_dac4r_src[] = {
1032 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1036 static SOC_ENUM_SINGLE_DECL(
1037 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1038 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1040 static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1041 SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);
1043 /* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1044 static const char * const rt5677_iob_bypass_src[] = {
1045 "Bypass", "Pass SRC"
1048 static SOC_ENUM_SINGLE_DECL(
1049 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1050 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1052 static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1053 SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);
1055 static SOC_ENUM_SINGLE_DECL(
1056 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1057 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1059 static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1060 SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);
1062 static SOC_ENUM_SINGLE_DECL(
1063 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1064 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1066 static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1067 SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);
1069 static SOC_ENUM_SINGLE_DECL(
1070 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1071 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1073 static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1074 SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);
1076 static SOC_ENUM_SINGLE_DECL(
1077 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1078 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1080 static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1081 SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);
1083 /* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1084 static const char * const rt5677_stereo_adc2_src[] = {
1085 "DD MIX1", "DMIC", "Stereo DAC MIX"
1088 static SOC_ENUM_SINGLE_DECL(
1089 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1090 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1092 static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1093 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);
1095 static SOC_ENUM_SINGLE_DECL(
1096 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1097 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1099 static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1100 SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);
1102 static SOC_ENUM_SINGLE_DECL(
1103 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1104 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1106 static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1107 SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);
1109 /* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1110 static const char * const rt5677_dmic_src[] = {
1111 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1114 static SOC_ENUM_SINGLE_DECL(
1115 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1116 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1118 static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1119 SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);
1121 static SOC_ENUM_SINGLE_DECL(
1122 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1123 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1125 static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1126 SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);
1128 static SOC_ENUM_SINGLE_DECL(
1129 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1130 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1132 static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1133 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);
1135 static SOC_ENUM_SINGLE_DECL(
1136 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1137 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1139 static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1140 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);
1142 static SOC_ENUM_SINGLE_DECL(
1143 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1144 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1146 static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1147 SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);
1149 static SOC_ENUM_SINGLE_DECL(
1150 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1151 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1153 static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1154 SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);
1156 /* Stereo2 ADC Source */ /* MX-26 [0] */
1157 static const char * const rt5677_stereo2_adc_lr_src[] = {
1161 static SOC_ENUM_SINGLE_DECL(
1162 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1163 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1165 static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1166 SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);
1168 /* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1169 static const char * const rt5677_stereo_adc1_src[] = {
1170 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1173 static SOC_ENUM_SINGLE_DECL(
1174 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1175 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1177 static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1178 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);
1180 static SOC_ENUM_SINGLE_DECL(
1181 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1182 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1184 static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1185 SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);
1187 static SOC_ENUM_SINGLE_DECL(
1188 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1189 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1191 static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1192 SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);
1194 /* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
1195 static const char * const rt5677_mono_adc2_l_src[] = {
1196 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1199 static SOC_ENUM_SINGLE_DECL(
1200 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1201 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1203 static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1204 SOC_DAPM_ENUM("Mono ADC2 L Source", rt5677_mono_adc2_l_enum);
1206 /* Mono ADC Left Source 1 */ /* MX-28 [13:12] */
1207 static const char * const rt5677_mono_adc1_l_src[] = {
1208 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1211 static SOC_ENUM_SINGLE_DECL(
1212 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1213 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1215 static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1216 SOC_DAPM_ENUM("Mono ADC1 L Source", rt5677_mono_adc1_l_enum);
1218 /* Mono ADC Right Source 2 */ /* MX-28 [3:2] */
1219 static const char * const rt5677_mono_adc2_r_src[] = {
1220 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1223 static SOC_ENUM_SINGLE_DECL(
1224 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1225 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1227 static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1228 SOC_DAPM_ENUM("Mono ADC2 R Source", rt5677_mono_adc2_r_enum);
1230 /* Mono ADC Right Source 1 */ /* MX-28 [5:4] */
1231 static const char * const rt5677_mono_adc1_r_src[] = {
1232 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1235 static SOC_ENUM_SINGLE_DECL(
1236 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1237 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1239 static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1240 SOC_DAPM_ENUM("Mono ADC1 R Source", rt5677_mono_adc1_r_enum);
1242 /* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1243 static const char * const rt5677_stereo4_adc2_src[] = {
1244 "DD MIX1", "DMIC", "DD MIX2"
1247 static SOC_ENUM_SINGLE_DECL(
1248 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1249 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1251 static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1252 SOC_DAPM_ENUM("Stereo4 ADC2 Source", rt5677_stereo4_adc2_enum);
1255 /* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1256 static const char * const rt5677_stereo4_adc1_src[] = {
1257 "DD MIX1", "ADC1/2", "DD MIX2"
1260 static SOC_ENUM_SINGLE_DECL(
1261 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1262 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1264 static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1265 SOC_DAPM_ENUM("Stereo4 ADC1 Source", rt5677_stereo4_adc1_enum);
1267 /* InBound0/1 Source */ /* MX-A3 [14:12] */
1268 static const char * const rt5677_inbound01_src[] = {
1269 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1273 static SOC_ENUM_SINGLE_DECL(
1274 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1275 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1277 static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1278 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1280 /* InBound2/3 Source */ /* MX-A3 [10:8] */
1281 static const char * const rt5677_inbound23_src[] = {
1282 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1283 "DAC1 FS", "IF4 DAC"
1286 static SOC_ENUM_SINGLE_DECL(
1287 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1288 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1290 static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1291 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1293 /* InBound4/5 Source */ /* MX-A3 [6:4] */
1294 static const char * const rt5677_inbound45_src[] = {
1295 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1299 static SOC_ENUM_SINGLE_DECL(
1300 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1301 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1303 static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1304 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1306 /* InBound6 Source */ /* MX-A3 [2:0] */
1307 static const char * const rt5677_inbound6_src[] = {
1308 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1309 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1312 static SOC_ENUM_SINGLE_DECL(
1313 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1314 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1316 static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1317 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1319 /* InBound7 Source */ /* MX-A4 [14:12] */
1320 static const char * const rt5677_inbound7_src[] = {
1321 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1322 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1325 static SOC_ENUM_SINGLE_DECL(
1326 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1327 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1329 static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1330 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1332 /* InBound8 Source */ /* MX-A4 [10:8] */
1333 static const char * const rt5677_inbound8_src[] = {
1334 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1335 "MONO ADC MIX L", "DACL1 FS"
1338 static SOC_ENUM_SINGLE_DECL(
1339 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1340 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1342 static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1343 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1345 /* InBound9 Source */ /* MX-A4 [6:4] */
1346 static const char * const rt5677_inbound9_src[] = {
1347 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1348 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1351 static SOC_ENUM_SINGLE_DECL(
1352 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1353 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1355 static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1356 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1358 /* VAD Source */ /* MX-9F [6:4] */
1359 static const char * const rt5677_vad_src[] = {
1360 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1364 static SOC_ENUM_SINGLE_DECL(
1365 rt5677_vad_enum, RT5677_VAD_CTRL4,
1366 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1368 static const struct snd_kcontrol_new rt5677_vad_src_mux =
1369 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1371 /* Sidetone Source */ /* MX-13 [11:9] */
1372 static const char * const rt5677_sidetone_src[] = {
1373 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1376 static SOC_ENUM_SINGLE_DECL(
1377 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1378 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1380 static const struct snd_kcontrol_new rt5677_sidetone_mux =
1381 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1383 /* DAC1/2 Source */ /* MX-15 [1:0] */
1384 static const char * const rt5677_dac12_src[] = {
1385 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1388 static SOC_ENUM_SINGLE_DECL(
1389 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1390 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1392 static const struct snd_kcontrol_new rt5677_dac12_mux =
1393 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1395 /* DAC3 Source */ /* MX-15 [5:4] */
1396 static const char * const rt5677_dac3_src[] = {
1397 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1400 static SOC_ENUM_SINGLE_DECL(
1401 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1402 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1404 static const struct snd_kcontrol_new rt5677_dac3_mux =
1405 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1407 /* PDM channel Source */ /* MX-31 [13:12][9:8][5:4][1:0] */
1408 static const char * const rt5677_pdm_src[] = {
1409 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1412 static SOC_ENUM_SINGLE_DECL(
1413 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1414 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1416 static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1417 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_l_enum);
1419 static SOC_ENUM_SINGLE_DECL(
1420 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1421 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1423 static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1424 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_l_enum);
1426 static SOC_ENUM_SINGLE_DECL(
1427 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1428 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1430 static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1431 SOC_DAPM_ENUM("PDM1 Source", rt5677_pdm1_r_enum);
1433 static SOC_ENUM_SINGLE_DECL(
1434 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1435 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1437 static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1438 SOC_DAPM_ENUM("PDM2 Source", rt5677_pdm2_r_enum);
1440 /* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/
1441 static const char * const rt5677_if12_adc1_src[] = {
1442 "STO1 ADC MIX", "OB01", "VAD ADC"
1445 static SOC_ENUM_SINGLE_DECL(
1446 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1447 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1449 static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1450 SOC_DAPM_ENUM("IF1 ADC1 Source", rt5677_if1_adc1_enum);
1452 static SOC_ENUM_SINGLE_DECL(
1453 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1454 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1456 static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1457 SOC_DAPM_ENUM("IF2 ADC1 Source", rt5677_if2_adc1_enum);
1459 static SOC_ENUM_SINGLE_DECL(
1460 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1461 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1463 static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1464 SOC_DAPM_ENUM("SLB ADC1 Source", rt5677_slb_adc1_enum);
1466 /* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1467 static const char * const rt5677_if12_adc2_src[] = {
1468 "STO2 ADC MIX", "OB23"
1471 static SOC_ENUM_SINGLE_DECL(
1472 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1473 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1475 static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1476 SOC_DAPM_ENUM("IF1 ADC2 Source", rt5677_if1_adc2_enum);
1478 static SOC_ENUM_SINGLE_DECL(
1479 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1480 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1482 static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1483 SOC_DAPM_ENUM("IF2 ADC2 Source", rt5677_if2_adc2_enum);
1485 static SOC_ENUM_SINGLE_DECL(
1486 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1487 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1489 static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1490 SOC_DAPM_ENUM("SLB ADC2 Source", rt5677_slb_adc2_enum);
1492 /* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1493 static const char * const rt5677_if12_adc3_src[] = {
1494 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1497 static SOC_ENUM_SINGLE_DECL(
1498 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1499 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1501 static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1502 SOC_DAPM_ENUM("IF1 ADC3 Source", rt5677_if1_adc3_enum);
1504 static SOC_ENUM_SINGLE_DECL(
1505 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1506 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1508 static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1509 SOC_DAPM_ENUM("IF2 ADC3 Source", rt5677_if2_adc3_enum);
1511 static SOC_ENUM_SINGLE_DECL(
1512 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1513 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1515 static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1516 SOC_DAPM_ENUM("SLB ADC3 Source", rt5677_slb_adc3_enum);
1518 /* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1519 static const char * const rt5677_if12_adc4_src[] = {
1520 "STO4 ADC MIX", "OB67", "OB01"
1523 static SOC_ENUM_SINGLE_DECL(
1524 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1525 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1527 static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1528 SOC_DAPM_ENUM("IF1 ADC4 Source", rt5677_if1_adc4_enum);
1530 static SOC_ENUM_SINGLE_DECL(
1531 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1532 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1534 static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1535 SOC_DAPM_ENUM("IF2 ADC4 Source", rt5677_if2_adc4_enum);
1537 static SOC_ENUM_SINGLE_DECL(
1538 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1539 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1541 static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1542 SOC_DAPM_ENUM("SLB ADC4 Source", rt5677_slb_adc4_enum);
1544 /* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/
1545 static const char * const rt5677_if34_adc_src[] = {
1546 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1547 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1550 static SOC_ENUM_SINGLE_DECL(
1551 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1552 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1554 static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1555 SOC_DAPM_ENUM("IF3 ADC Source", rt5677_if3_adc_enum);
1557 static SOC_ENUM_SINGLE_DECL(
1558 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1559 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1561 static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1562 SOC_DAPM_ENUM("IF4 ADC Source", rt5677_if4_adc_enum);
1564 static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
1565 struct snd_kcontrol *kcontrol, int event)
1567 struct snd_soc_codec *codec = w->codec;
1568 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1571 case SND_SOC_DAPM_POST_PMU:
1572 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1573 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
1576 case SND_SOC_DAPM_PRE_PMD:
1577 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1578 RT5677_PWR_BST1_P, 0);
1588 static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
1589 struct snd_kcontrol *kcontrol, int event)
1591 struct snd_soc_codec *codec = w->codec;
1592 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1595 case SND_SOC_DAPM_POST_PMU:
1596 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1597 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
1600 case SND_SOC_DAPM_PRE_PMD:
1601 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1602 RT5677_PWR_BST2_P, 0);
1612 static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
1613 struct snd_kcontrol *kcontrol, int event)
1615 struct snd_soc_codec *codec = w->codec;
1616 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1619 case SND_SOC_DAPM_POST_PMU:
1620 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
1621 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
1630 static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
1631 struct snd_kcontrol *kcontrol, int event)
1633 struct snd_soc_codec *codec = w->codec;
1634 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1637 case SND_SOC_DAPM_POST_PMU:
1638 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
1639 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
1648 static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
1649 struct snd_kcontrol *kcontrol, int event)
1651 struct snd_soc_codec *codec = w->codec;
1652 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1655 case SND_SOC_DAPM_POST_PMU:
1656 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1657 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1658 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
1659 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
1662 case SND_SOC_DAPM_PRE_PMD:
1663 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1664 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1665 RT5677_PWR_CLK_MB, 0);
1675 static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1676 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
1677 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
1678 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
1679 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
1683 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
1684 0, rt5677_set_micbias1_event, SND_SOC_DAPM_PRE_PMD |
1685 SND_SOC_DAPM_POST_PMU),
1688 SND_SOC_DAPM_INPUT("DMIC L1"),
1689 SND_SOC_DAPM_INPUT("DMIC R1"),
1690 SND_SOC_DAPM_INPUT("DMIC L2"),
1691 SND_SOC_DAPM_INPUT("DMIC R2"),
1692 SND_SOC_DAPM_INPUT("DMIC L3"),
1693 SND_SOC_DAPM_INPUT("DMIC R3"),
1694 SND_SOC_DAPM_INPUT("DMIC L4"),
1695 SND_SOC_DAPM_INPUT("DMIC R4"),
1697 SND_SOC_DAPM_INPUT("IN1P"),
1698 SND_SOC_DAPM_INPUT("IN1N"),
1699 SND_SOC_DAPM_INPUT("IN2P"),
1700 SND_SOC_DAPM_INPUT("IN2N"),
1702 SND_SOC_DAPM_INPUT("Haptic Generator"),
1704 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1705 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1706 SND_SOC_DAPM_PGA("DMIC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1707 SND_SOC_DAPM_PGA("DMIC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1709 SND_SOC_DAPM_SUPPLY("DMIC1 power", RT5677_DMIC_CTRL1,
1710 RT5677_DMIC_1_EN_SFT, 0, NULL, 0),
1711 SND_SOC_DAPM_SUPPLY("DMIC2 power", RT5677_DMIC_CTRL1,
1712 RT5677_DMIC_2_EN_SFT, 0, NULL, 0),
1713 SND_SOC_DAPM_SUPPLY("DMIC3 power", RT5677_DMIC_CTRL1,
1714 RT5677_DMIC_3_EN_SFT, 0, NULL, 0),
1715 SND_SOC_DAPM_SUPPLY("DMIC4 power", RT5677_DMIC_CTRL2,
1716 RT5677_DMIC_4_EN_SFT, 0, NULL, 0),
1718 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1719 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1722 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
1723 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
1724 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1725 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
1726 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
1727 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1730 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
1732 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
1734 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
1736 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
1737 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
1738 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
1739 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
1740 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
1741 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
1742 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
1743 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
1746 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1747 &rt5677_sto1_dmic_mux),
1748 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1749 &rt5677_sto1_adc1_mux),
1750 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1751 &rt5677_sto1_adc2_mux),
1752 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
1753 &rt5677_sto2_dmic_mux),
1754 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1755 &rt5677_sto2_adc1_mux),
1756 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1757 &rt5677_sto2_adc2_mux),
1758 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
1759 &rt5677_sto2_adc_lr_mux),
1760 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
1761 &rt5677_sto3_dmic_mux),
1762 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1763 &rt5677_sto3_adc1_mux),
1764 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1765 &rt5677_sto3_adc2_mux),
1766 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
1767 &rt5677_sto4_dmic_mux),
1768 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1769 &rt5677_sto4_adc1_mux),
1770 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1771 &rt5677_sto4_adc2_mux),
1772 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1773 &rt5677_mono_dmic_l_mux),
1774 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1775 &rt5677_mono_dmic_r_mux),
1776 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
1777 &rt5677_mono_adc2_l_mux),
1778 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
1779 &rt5677_mono_adc1_l_mux),
1780 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
1781 &rt5677_mono_adc1_r_mux),
1782 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
1783 &rt5677_mono_adc2_r_mux),
1786 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
1787 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
1788 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
1789 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
1790 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
1791 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
1792 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
1793 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
1794 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1795 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
1796 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1797 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
1798 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1799 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
1800 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1801 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
1802 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
1803 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
1804 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
1805 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
1806 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
1807 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
1808 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
1809 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
1810 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
1811 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1812 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1813 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
1814 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
1815 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1816 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1817 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
1820 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1821 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1822 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1823 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1824 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1825 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1826 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1827 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1828 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1829 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1830 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1831 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1832 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1833 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1834 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1835 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1836 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1837 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1840 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
1841 &rt5677_ib9_src_mux),
1842 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
1843 &rt5677_ib8_src_mux),
1844 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
1845 &rt5677_ib7_src_mux),
1846 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
1847 &rt5677_ib6_src_mux),
1848 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
1849 &rt5677_ib45_src_mux),
1850 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
1851 &rt5677_ib23_src_mux),
1852 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
1853 &rt5677_ib01_src_mux),
1854 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
1855 &rt5677_ib45_bypass_src_mux),
1856 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1857 &rt5677_ib23_bypass_src_mux),
1858 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1859 &rt5677_ib01_bypass_src_mux),
1860 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1861 &rt5677_ob23_bypass_src_mux),
1862 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1863 &rt5677_ob01_bypass_src_mux),
1865 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
1866 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
1868 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
1869 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
1870 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
1871 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
1872 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
1873 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
1875 /* Digital Interface */
1876 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
1877 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
1878 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1879 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1880 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1881 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1882 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1883 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1884 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1885 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1886 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1887 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1888 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1889 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1890 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1891 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1892 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1893 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1895 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
1896 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
1897 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1898 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1899 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1900 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1901 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1902 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1903 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1904 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1905 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1906 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1907 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1908 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1909 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1910 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1911 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1912 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1914 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
1915 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
1916 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1917 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1918 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1919 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1920 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1921 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1923 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
1924 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
1925 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1926 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1927 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1928 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1929 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1930 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1932 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
1933 RT5677_PWR_SLB_BIT, 0, NULL, 0),
1934 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1935 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1936 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1937 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1938 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1939 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1940 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1941 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1942 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1943 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1944 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1945 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1946 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1947 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1948 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1949 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1951 /* Digital Interface Select */
1952 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1953 &rt5677_if1_adc1_mux),
1954 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1955 &rt5677_if1_adc2_mux),
1956 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1957 &rt5677_if1_adc3_mux),
1958 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1959 &rt5677_if1_adc4_mux),
1960 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1961 &rt5677_if2_adc1_mux),
1962 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1963 &rt5677_if2_adc2_mux),
1964 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1965 &rt5677_if2_adc3_mux),
1966 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1967 &rt5677_if2_adc4_mux),
1968 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
1969 &rt5677_if3_adc_mux),
1970 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
1971 &rt5677_if4_adc_mux),
1972 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
1973 &rt5677_slb_adc1_mux),
1974 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
1975 &rt5677_slb_adc2_mux),
1976 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
1977 &rt5677_slb_adc3_mux),
1978 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
1979 &rt5677_slb_adc4_mux),
1981 /* Audio Interface */
1982 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1983 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1984 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1985 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1986 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1987 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1988 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
1989 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
1990 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
1991 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
1994 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
1995 &rt5677_sidetone_mux),
1997 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
1998 &rt5677_vad_src_mux),
2001 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2002 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2003 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2004 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2005 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2006 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2007 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2008 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2009 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2010 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2011 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2012 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2013 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2016 /* DAC mixer before sound effect */
2017 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2018 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2019 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2020 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2021 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2024 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2026 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2028 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2030 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2033 /* DAC2 channel Mux */
2034 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2035 &rt5677_dac2_l_mux),
2036 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2037 &rt5677_dac2_r_mux),
2039 /* DAC3 channel Mux */
2040 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2041 &rt5677_dac3_l_mux),
2042 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2043 &rt5677_dac3_r_mux),
2045 /* DAC4 channel Mux */
2046 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2047 &rt5677_dac4_l_mux),
2048 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2049 &rt5677_dac4_r_mux),
2052 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2053 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2054 SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2,
2055 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2056 SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2,
2057 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2059 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2060 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2061 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2062 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2063 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2064 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2065 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2066 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2067 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2068 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2069 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2070 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2071 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2072 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2073 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2074 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2075 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2076 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2077 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2078 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2081 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2082 RT5677_PWR_DAC1_BIT, 0),
2083 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2084 RT5677_PWR_DAC2_BIT, 0),
2085 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2086 RT5677_PWR_DAC3_BIT, 0),
2089 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2090 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2091 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2092 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2094 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2095 1, &rt5677_pdm1_l_mux),
2096 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2097 1, &rt5677_pdm1_r_mux),
2098 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2099 1, &rt5677_pdm2_l_mux),
2100 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2101 1, &rt5677_pdm2_r_mux),
2103 SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2105 SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2107 SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2111 SND_SOC_DAPM_OUTPUT("LOUT1"),
2112 SND_SOC_DAPM_OUTPUT("LOUT2"),
2113 SND_SOC_DAPM_OUTPUT("LOUT3"),
2114 SND_SOC_DAPM_OUTPUT("PDM1L"),
2115 SND_SOC_DAPM_OUTPUT("PDM1R"),
2116 SND_SOC_DAPM_OUTPUT("PDM2L"),
2117 SND_SOC_DAPM_OUTPUT("PDM2R"),
2120 static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2121 { "DMIC1", NULL, "DMIC L1" },
2122 { "DMIC1", NULL, "DMIC R1" },
2123 { "DMIC2", NULL, "DMIC L2" },
2124 { "DMIC2", NULL, "DMIC R2" },
2125 { "DMIC3", NULL, "DMIC L3" },
2126 { "DMIC3", NULL, "DMIC R3" },
2127 { "DMIC4", NULL, "DMIC L4" },
2128 { "DMIC4", NULL, "DMIC R4" },
2130 { "DMIC L1", NULL, "DMIC CLK" },
2131 { "DMIC R1", NULL, "DMIC CLK" },
2132 { "DMIC L2", NULL, "DMIC CLK" },
2133 { "DMIC R2", NULL, "DMIC CLK" },
2134 { "DMIC L3", NULL, "DMIC CLK" },
2135 { "DMIC R3", NULL, "DMIC CLK" },
2136 { "DMIC L4", NULL, "DMIC CLK" },
2137 { "DMIC R4", NULL, "DMIC CLK" },
2139 { "DMIC L1", NULL, "DMIC1 power" },
2140 { "DMIC R1", NULL, "DMIC1 power" },
2141 { "DMIC L3", NULL, "DMIC3 power" },
2142 { "DMIC R3", NULL, "DMIC3 power" },
2143 { "DMIC L4", NULL, "DMIC4 power" },
2144 { "DMIC R4", NULL, "DMIC4 power" },
2146 { "BST1", NULL, "IN1P" },
2147 { "BST1", NULL, "IN1N" },
2148 { "BST2", NULL, "IN2P" },
2149 { "BST2", NULL, "IN2N" },
2151 { "IN1P", NULL, "micbias1" },
2152 { "IN1N", NULL, "micbias1" },
2153 { "IN2P", NULL, "micbias1" },
2154 { "IN2N", NULL, "micbias1" },
2156 { "ADC 1", NULL, "BST1" },
2157 { "ADC 1", NULL, "ADC 1 power" },
2158 { "ADC 1", NULL, "ADC1 clock" },
2159 { "ADC 2", NULL, "BST2" },
2160 { "ADC 2", NULL, "ADC 2 power" },
2161 { "ADC 2", NULL, "ADC2 clock" },
2163 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2164 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2165 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2166 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2168 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2169 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2170 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2171 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2173 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2174 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2175 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2176 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2178 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2179 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2180 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2181 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2183 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2184 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2185 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2186 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2188 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2189 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2190 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2191 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2193 { "ADC 1_2", NULL, "ADC 1" },
2194 { "ADC 1_2", NULL, "ADC 2" },
2196 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2197 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2198 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2200 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2201 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2202 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2204 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2205 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2206 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2208 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2209 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2210 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2212 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2213 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2214 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2216 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2217 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2218 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2220 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2221 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2222 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2224 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2225 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2226 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2228 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2229 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2230 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2232 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
2233 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
2234 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2236 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
2237 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
2238 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2240 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
2241 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
2242 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2244 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2245 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2246 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2247 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2249 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2250 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2251 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2253 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2254 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2255 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2257 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2258 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2260 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2261 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2262 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2263 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2265 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2266 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2268 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2269 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2271 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2272 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
2273 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2275 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2276 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
2277 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2279 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
2280 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
2282 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2283 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2284 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2285 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2287 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
2288 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
2289 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2291 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
2292 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
2293 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2295 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
2296 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
2298 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2299 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2300 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2301 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2303 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
2304 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
2305 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2307 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
2308 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
2309 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2311 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
2312 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
2314 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
2315 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
2316 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2317 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2319 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
2320 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
2321 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2322 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2324 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2325 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2327 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2328 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2329 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2330 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2331 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2333 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2334 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2335 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2337 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2338 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2340 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2341 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2342 { "IF1 ADC3 Mux", "OB45", "OB45" },
2344 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2345 { "IF1 ADC4 Mux", "OB67", "OB67" },
2346 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2348 { "AIF1TX", NULL, "I2S1" },
2349 { "AIF1TX", NULL, "IF1 ADC1 Mux" },
2350 { "AIF1TX", NULL, "IF1 ADC2 Mux" },
2351 { "AIF1TX", NULL, "IF1 ADC3 Mux" },
2352 { "AIF1TX", NULL, "IF1 ADC4 Mux" },
2354 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2355 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2356 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2358 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2359 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2361 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2362 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2363 { "IF2 ADC3 Mux", "OB45", "OB45" },
2365 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2366 { "IF2 ADC4 Mux", "OB67", "OB67" },
2367 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2369 { "AIF2TX", NULL, "I2S2" },
2370 { "AIF2TX", NULL, "IF2 ADC1 Mux" },
2371 { "AIF2TX", NULL, "IF2 ADC2 Mux" },
2372 { "AIF2TX", NULL, "IF2 ADC3 Mux" },
2373 { "AIF2TX", NULL, "IF2 ADC4 Mux" },
2375 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2376 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2377 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2378 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2379 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2380 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
2381 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
2382 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2384 { "AIF3TX", NULL, "I2S3" },
2385 { "AIF3TX", NULL, "IF3 ADC Mux" },
2387 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2388 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2389 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2390 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2391 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2392 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
2393 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
2394 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2396 { "AIF4TX", NULL, "I2S4" },
2397 { "AIF4TX", NULL, "IF4 ADC Mux" },
2399 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2400 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2401 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2403 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2404 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2406 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2407 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2408 { "SLB ADC3 Mux", "OB45", "OB45" },
2410 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2411 { "SLB ADC4 Mux", "OB67", "OB67" },
2412 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2414 { "SLBTX", NULL, "SLB" },
2415 { "SLBTX", NULL, "SLB ADC1 Mux" },
2416 { "SLBTX", NULL, "SLB ADC2 Mux" },
2417 { "SLBTX", NULL, "SLB ADC3 Mux" },
2418 { "SLBTX", NULL, "SLB ADC4 Mux" },
2420 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
2421 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
2422 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
2423 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2424 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
2426 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
2427 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
2429 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
2430 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
2431 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
2432 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2433 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
2434 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
2436 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
2437 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
2439 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
2440 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
2441 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
2442 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2443 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
2445 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
2446 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
2448 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
2449 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
2450 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
2451 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2452 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
2453 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2454 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2455 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2457 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
2458 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
2459 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
2460 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2461 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
2462 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2463 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2464 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2466 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2467 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2468 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2469 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2470 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2471 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
2473 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2474 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2475 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2476 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2477 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2478 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
2479 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
2481 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2482 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2483 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2484 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
2485 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
2486 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
2487 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
2489 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2490 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2491 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2492 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
2493 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
2494 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
2495 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
2497 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2498 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2499 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2500 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
2501 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
2502 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
2503 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
2505 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2506 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2507 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2508 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
2509 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
2510 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
2511 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
2513 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2514 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2515 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2516 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
2517 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
2518 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
2519 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
2521 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2522 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2523 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2524 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
2525 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
2526 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
2527 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
2529 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
2530 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
2531 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
2532 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
2534 { "OutBound2", NULL, "OB23 Bypass Mux" },
2535 { "OutBound3", NULL, "OB23 Bypass Mux" },
2536 { "OutBound4", NULL, "OB4 MIX" },
2537 { "OutBound5", NULL, "OB5 MIX" },
2538 { "OutBound6", NULL, "OB6 MIX" },
2539 { "OutBound7", NULL, "OB7 MIX" },
2541 { "OB45", NULL, "OutBound4" },
2542 { "OB45", NULL, "OutBound5" },
2543 { "OB67", NULL, "OutBound6" },
2544 { "OB67", NULL, "OutBound7" },
2546 { "IF1 DAC0", NULL, "AIF1RX" },
2547 { "IF1 DAC1", NULL, "AIF1RX" },
2548 { "IF1 DAC2", NULL, "AIF1RX" },
2549 { "IF1 DAC3", NULL, "AIF1RX" },
2550 { "IF1 DAC4", NULL, "AIF1RX" },
2551 { "IF1 DAC5", NULL, "AIF1RX" },
2552 { "IF1 DAC6", NULL, "AIF1RX" },
2553 { "IF1 DAC7", NULL, "AIF1RX" },
2554 { "IF1 DAC0", NULL, "I2S1" },
2555 { "IF1 DAC1", NULL, "I2S1" },
2556 { "IF1 DAC2", NULL, "I2S1" },
2557 { "IF1 DAC3", NULL, "I2S1" },
2558 { "IF1 DAC4", NULL, "I2S1" },
2559 { "IF1 DAC5", NULL, "I2S1" },
2560 { "IF1 DAC6", NULL, "I2S1" },
2561 { "IF1 DAC7", NULL, "I2S1" },
2563 { "IF1 DAC01", NULL, "IF1 DAC0" },
2564 { "IF1 DAC01", NULL, "IF1 DAC1" },
2565 { "IF1 DAC23", NULL, "IF1 DAC2" },
2566 { "IF1 DAC23", NULL, "IF1 DAC3" },
2567 { "IF1 DAC45", NULL, "IF1 DAC4" },
2568 { "IF1 DAC45", NULL, "IF1 DAC5" },
2569 { "IF1 DAC67", NULL, "IF1 DAC6" },
2570 { "IF1 DAC67", NULL, "IF1 DAC7" },
2572 { "IF2 DAC0", NULL, "AIF2RX" },
2573 { "IF2 DAC1", NULL, "AIF2RX" },
2574 { "IF2 DAC2", NULL, "AIF2RX" },
2575 { "IF2 DAC3", NULL, "AIF2RX" },
2576 { "IF2 DAC4", NULL, "AIF2RX" },
2577 { "IF2 DAC5", NULL, "AIF2RX" },
2578 { "IF2 DAC6", NULL, "AIF2RX" },
2579 { "IF2 DAC7", NULL, "AIF2RX" },
2580 { "IF2 DAC0", NULL, "I2S2" },
2581 { "IF2 DAC1", NULL, "I2S2" },
2582 { "IF2 DAC2", NULL, "I2S2" },
2583 { "IF2 DAC3", NULL, "I2S2" },
2584 { "IF2 DAC4", NULL, "I2S2" },
2585 { "IF2 DAC5", NULL, "I2S2" },
2586 { "IF2 DAC6", NULL, "I2S2" },
2587 { "IF2 DAC7", NULL, "I2S2" },
2589 { "IF2 DAC01", NULL, "IF2 DAC0" },
2590 { "IF2 DAC01", NULL, "IF2 DAC1" },
2591 { "IF2 DAC23", NULL, "IF2 DAC2" },
2592 { "IF2 DAC23", NULL, "IF2 DAC3" },
2593 { "IF2 DAC45", NULL, "IF2 DAC4" },
2594 { "IF2 DAC45", NULL, "IF2 DAC5" },
2595 { "IF2 DAC67", NULL, "IF2 DAC6" },
2596 { "IF2 DAC67", NULL, "IF2 DAC7" },
2598 { "IF3 DAC", NULL, "AIF3RX" },
2599 { "IF3 DAC", NULL, "I2S3" },
2601 { "IF4 DAC", NULL, "AIF4RX" },
2602 { "IF4 DAC", NULL, "I2S4" },
2604 { "IF3 DAC L", NULL, "IF3 DAC" },
2605 { "IF3 DAC R", NULL, "IF3 DAC" },
2607 { "IF4 DAC L", NULL, "IF4 DAC" },
2608 { "IF4 DAC R", NULL, "IF4 DAC" },
2610 { "SLB DAC0", NULL, "SLBRX" },
2611 { "SLB DAC1", NULL, "SLBRX" },
2612 { "SLB DAC2", NULL, "SLBRX" },
2613 { "SLB DAC3", NULL, "SLBRX" },
2614 { "SLB DAC4", NULL, "SLBRX" },
2615 { "SLB DAC5", NULL, "SLBRX" },
2616 { "SLB DAC6", NULL, "SLBRX" },
2617 { "SLB DAC7", NULL, "SLBRX" },
2618 { "SLB DAC0", NULL, "SLB" },
2619 { "SLB DAC1", NULL, "SLB" },
2620 { "SLB DAC2", NULL, "SLB" },
2621 { "SLB DAC3", NULL, "SLB" },
2622 { "SLB DAC4", NULL, "SLB" },
2623 { "SLB DAC5", NULL, "SLB" },
2624 { "SLB DAC6", NULL, "SLB" },
2625 { "SLB DAC7", NULL, "SLB" },
2627 { "SLB DAC01", NULL, "SLB DAC0" },
2628 { "SLB DAC01", NULL, "SLB DAC1" },
2629 { "SLB DAC23", NULL, "SLB DAC2" },
2630 { "SLB DAC23", NULL, "SLB DAC3" },
2631 { "SLB DAC45", NULL, "SLB DAC4" },
2632 { "SLB DAC45", NULL, "SLB DAC5" },
2633 { "SLB DAC67", NULL, "SLB DAC6" },
2634 { "SLB DAC67", NULL, "SLB DAC7" },
2636 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2637 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2638 { "ADDA1 Mux", "OB 67", "OB67" },
2640 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
2641 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
2642 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
2643 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
2644 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
2645 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
2647 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
2648 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
2649 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2650 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
2651 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
2652 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2654 { "DAC1 FS", NULL, "DAC1 MIXL" },
2655 { "DAC1 FS", NULL, "DAC1 MIXR" },
2657 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
2658 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
2659 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
2660 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
2661 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
2662 { "DAC2 L Mux", "OB 2", "OutBound2" },
2664 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
2665 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
2666 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
2667 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
2668 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
2669 { "DAC2 R Mux", "OB 3", "OutBound3" },
2670 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
2671 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
2673 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
2674 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
2675 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
2676 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
2677 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
2678 { "DAC3 L Mux", "OB 4", "OutBound4" },
2680 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
2681 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
2682 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
2683 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
2684 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
2685 { "DAC3 R Mux", "OB 5", "OutBound5" },
2687 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
2688 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
2689 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
2690 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
2691 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
2692 { "DAC4 L Mux", "OB 6", "OutBound6" },
2694 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
2695 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
2696 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
2697 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
2698 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
2699 { "DAC4 R Mux", "OB 7", "OutBound7" },
2701 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
2702 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
2703 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
2704 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
2705 { "Sidetone Mux", "ADC1", "ADC 1" },
2706 { "Sidetone Mux", "ADC2", "ADC 2" },
2708 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
2709 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2710 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2711 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
2712 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2713 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
2714 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2715 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2716 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
2717 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2719 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
2720 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2721 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2722 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
2723 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2724 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
2725 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2726 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2727 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
2728 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2730 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2731 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2732 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
2733 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
2734 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2735 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2736 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
2737 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
2739 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2740 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2741 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
2742 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
2743 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2744 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2745 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
2746 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
2748 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
2749 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
2750 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
2751 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
2752 { "DD1 MIX", NULL, "DD1 MIXL" },
2753 { "DD1 MIX", NULL, "DD1 MIXR" },
2754 { "DD2 MIX", NULL, "DD2 MIXL" },
2755 { "DD2 MIX", NULL, "DD2 MIXR" },
2757 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
2758 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
2759 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
2760 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
2762 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2763 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2764 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
2765 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
2767 { "DAC 1", NULL, "DAC12 SRC Mux" },
2768 { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
2769 { "DAC 2", NULL, "DAC12 SRC Mux" },
2770 { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
2771 { "DAC 3", NULL, "DAC3 SRC Mux" },
2772 { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
2774 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2775 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2776 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
2777 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
2778 { "PDM1 L Mux", NULL, "PDM1 Power" },
2779 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2780 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2781 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
2782 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
2783 { "PDM1 R Mux", NULL, "PDM1 Power" },
2784 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2785 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2786 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
2787 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
2788 { "PDM2 L Mux", NULL, "PDM2 Power" },
2789 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2790 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2791 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
2792 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
2793 { "PDM2 R Mux", NULL, "PDM2 Power" },
2795 { "LOUT1 amp", NULL, "DAC 1" },
2796 { "LOUT2 amp", NULL, "DAC 2" },
2797 { "LOUT3 amp", NULL, "DAC 3" },
2799 { "LOUT1", NULL, "LOUT1 amp" },
2800 { "LOUT2", NULL, "LOUT2 amp" },
2801 { "LOUT3", NULL, "LOUT3 amp" },
2803 { "PDM1L", NULL, "PDM1 L Mux" },
2804 { "PDM1R", NULL, "PDM1 R Mux" },
2805 { "PDM2L", NULL, "PDM2 L Mux" },
2806 { "PDM2R", NULL, "PDM2 R Mux" },
2809 static const struct snd_soc_dapm_route rt5677_dmic2_clk_1[] = {
2810 { "DMIC L2", NULL, "DMIC1 power" },
2811 { "DMIC R2", NULL, "DMIC1 power" },
2814 static const struct snd_soc_dapm_route rt5677_dmic2_clk_2[] = {
2815 { "DMIC L2", NULL, "DMIC2 power" },
2816 { "DMIC R2", NULL, "DMIC2 power" },
2819 static int rt5677_hw_params(struct snd_pcm_substream *substream,
2820 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2822 struct snd_soc_codec *codec = dai->codec;
2823 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2824 unsigned int val_len = 0, val_clk, mask_clk;
2825 int pre_div, bclk_ms, frame_size;
2827 rt5677->lrck[dai->id] = params_rate(params);
2828 pre_div = rl6231_get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
2830 dev_err(codec->dev, "Unsupported clock setting\n");
2833 frame_size = snd_soc_params_to_frame_size(params);
2834 if (frame_size < 0) {
2835 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2838 bclk_ms = frame_size > 32;
2839 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
2841 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2842 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
2843 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2844 bclk_ms, pre_div, dai->id);
2846 switch (params_width(params)) {
2850 val_len |= RT5677_I2S_DL_20;
2853 val_len |= RT5677_I2S_DL_24;
2856 val_len |= RT5677_I2S_DL_8;
2864 mask_clk = RT5677_I2S_PD1_MASK;
2865 val_clk = pre_div << RT5677_I2S_PD1_SFT;
2866 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2867 RT5677_I2S_DL_MASK, val_len);
2868 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2872 mask_clk = RT5677_I2S_PD2_MASK;
2873 val_clk = pre_div << RT5677_I2S_PD2_SFT;
2874 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2875 RT5677_I2S_DL_MASK, val_len);
2876 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2880 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
2881 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
2882 pre_div << RT5677_I2S_PD3_SFT;
2883 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2884 RT5677_I2S_DL_MASK, val_len);
2885 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2889 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
2890 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
2891 pre_div << RT5677_I2S_PD4_SFT;
2892 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2893 RT5677_I2S_DL_MASK, val_len);
2894 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2904 static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2906 struct snd_soc_codec *codec = dai->codec;
2907 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2908 unsigned int reg_val = 0;
2910 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2911 case SND_SOC_DAIFMT_CBM_CFM:
2912 rt5677->master[dai->id] = 1;
2914 case SND_SOC_DAIFMT_CBS_CFS:
2915 reg_val |= RT5677_I2S_MS_S;
2916 rt5677->master[dai->id] = 0;
2922 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2923 case SND_SOC_DAIFMT_NB_NF:
2925 case SND_SOC_DAIFMT_IB_NF:
2926 reg_val |= RT5677_I2S_BP_INV;
2932 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2933 case SND_SOC_DAIFMT_I2S:
2935 case SND_SOC_DAIFMT_LEFT_J:
2936 reg_val |= RT5677_I2S_DF_LEFT;
2938 case SND_SOC_DAIFMT_DSP_A:
2939 reg_val |= RT5677_I2S_DF_PCM_A;
2941 case SND_SOC_DAIFMT_DSP_B:
2942 reg_val |= RT5677_I2S_DF_PCM_B;
2950 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2951 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2952 RT5677_I2S_DF_MASK, reg_val);
2955 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2956 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2957 RT5677_I2S_DF_MASK, reg_val);
2960 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2961 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2962 RT5677_I2S_DF_MASK, reg_val);
2965 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2966 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2967 RT5677_I2S_DF_MASK, reg_val);
2977 static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
2978 int clk_id, unsigned int freq, int dir)
2980 struct snd_soc_codec *codec = dai->codec;
2981 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2982 unsigned int reg_val = 0;
2984 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
2988 case RT5677_SCLK_S_MCLK:
2989 reg_val |= RT5677_SCLK_SRC_MCLK;
2991 case RT5677_SCLK_S_PLL1:
2992 reg_val |= RT5677_SCLK_SRC_PLL1;
2994 case RT5677_SCLK_S_RCCLK:
2995 reg_val |= RT5677_SCLK_SRC_RCCLK;
2998 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
3001 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3002 RT5677_SCLK_SRC_MASK, reg_val);
3003 rt5677->sysclk = freq;
3004 rt5677->sysclk_src = clk_id;
3006 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3012 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3013 * @freq_in: external clock provided to codec.
3014 * @freq_out: target clock which codec works on.
3015 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3017 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3019 * Returns 0 for success or negative error code.
3021 static int rt5677_pll_calc(const unsigned int freq_in,
3022 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
3024 if (RT5677_PLL_INP_MIN > freq_in)
3027 return rl6231_pll_calc(freq_in, freq_out, pll_code);
3030 static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3031 unsigned int freq_in, unsigned int freq_out)
3033 struct snd_soc_codec *codec = dai->codec;
3034 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3035 struct rl6231_pll_code pll_code;
3038 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
3039 freq_out == rt5677->pll_out)
3042 if (!freq_in || !freq_out) {
3043 dev_dbg(codec->dev, "PLL disabled\n");
3046 rt5677->pll_out = 0;
3047 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3048 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
3053 case RT5677_PLL1_S_MCLK:
3054 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3055 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
3057 case RT5677_PLL1_S_BCLK1:
3058 case RT5677_PLL1_S_BCLK2:
3059 case RT5677_PLL1_S_BCLK3:
3060 case RT5677_PLL1_S_BCLK4:
3063 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3064 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
3067 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3068 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
3071 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3072 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
3075 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3076 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
3083 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3087 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
3089 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3093 dev_dbg(codec->dev, "m_bypass=%d m=%d n=%d k=%d\n",
3094 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3095 pll_code.n_code, pll_code.k_code);
3097 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
3098 pll_code.n_code << RT5677_PLL_N_SFT | pll_code.k_code);
3099 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
3100 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
3101 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
3103 rt5677->pll_in = freq_in;
3104 rt5677->pll_out = freq_out;
3105 rt5677->pll_src = source;
3110 static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3111 enum snd_soc_bias_level level)
3113 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3116 case SND_SOC_BIAS_ON:
3119 case SND_SOC_BIAS_PREPARE:
3120 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3121 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3122 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
3124 regmap_update_bits(rt5677->regmap,
3125 RT5677_PR_BASE + RT5677_BIAS_CUR4,
3127 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3128 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3129 RT5677_PWR_BG | RT5677_PWR_VREF2,
3130 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3131 RT5677_PWR_BG | RT5677_PWR_VREF2);
3133 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3134 RT5677_PWR_FV1 | RT5677_PWR_FV2,
3135 RT5677_PWR_FV1 | RT5677_PWR_FV2);
3136 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
3137 RT5677_PWR_CORE, RT5677_PWR_CORE);
3138 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
3143 case SND_SOC_BIAS_STANDBY:
3146 case SND_SOC_BIAS_OFF:
3147 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
3148 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
3149 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
3150 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0022);
3151 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
3152 regmap_update_bits(rt5677->regmap,
3153 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
3159 codec->dapm.bias_level = level;
3164 #ifdef CONFIG_GPIOLIB
3165 static inline struct rt5677_priv *gpio_to_rt5677(struct gpio_chip *chip)
3167 return container_of(chip, struct rt5677_priv, gpio_chip);
3170 static void rt5677_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3172 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3175 case RT5677_GPIO1 ... RT5677_GPIO5:
3176 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3177 0x1 << (offset * 3 + 1), !!value << (offset * 3 + 1));
3181 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3182 RT5677_GPIO6_OUT_MASK, !!value << RT5677_GPIO6_OUT_SFT);
3190 static int rt5677_gpio_direction_out(struct gpio_chip *chip,
3191 unsigned offset, int value)
3193 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3196 case RT5677_GPIO1 ... RT5677_GPIO5:
3197 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3198 0x3 << (offset * 3 + 1),
3199 (0x2 | !!value) << (offset * 3 + 1));
3203 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3204 RT5677_GPIO6_DIR_MASK | RT5677_GPIO6_OUT_MASK,
3205 RT5677_GPIO6_DIR_OUT | !!value << RT5677_GPIO6_OUT_SFT);
3215 static int rt5677_gpio_get(struct gpio_chip *chip, unsigned offset)
3217 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3220 ret = regmap_read(rt5677->regmap, RT5677_GPIO_ST, &value);
3224 return (value & (0x1 << offset)) >> offset;
3227 static int rt5677_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
3229 struct rt5677_priv *rt5677 = gpio_to_rt5677(chip);
3232 case RT5677_GPIO1 ... RT5677_GPIO5:
3233 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3234 0x1 << (offset * 3 + 2), 0x0);
3238 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL3,
3239 RT5677_GPIO6_DIR_MASK, RT5677_GPIO6_DIR_IN);
3249 static struct gpio_chip rt5677_template_chip = {
3251 .owner = THIS_MODULE,
3252 .direction_output = rt5677_gpio_direction_out,
3253 .set = rt5677_gpio_set,
3254 .direction_input = rt5677_gpio_direction_in,
3255 .get = rt5677_gpio_get,
3259 static void rt5677_init_gpio(struct i2c_client *i2c)
3261 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
3264 rt5677->gpio_chip = rt5677_template_chip;
3265 rt5677->gpio_chip.ngpio = RT5677_GPIO_NUM;
3266 rt5677->gpio_chip.dev = &i2c->dev;
3267 rt5677->gpio_chip.base = -1;
3269 ret = gpiochip_add(&rt5677->gpio_chip);
3271 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
3274 static void rt5677_free_gpio(struct i2c_client *i2c)
3276 struct rt5677_priv *rt5677 = i2c_get_clientdata(i2c);
3278 gpiochip_remove(&rt5677->gpio_chip);
3281 static void rt5677_init_gpio(struct i2c_client *i2c)
3285 static void rt5677_free_gpio(struct i2c_client *i2c)
3290 static int rt5677_probe(struct snd_soc_codec *codec)
3292 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3294 rt5677->codec = codec;
3296 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
3297 snd_soc_dapm_add_routes(&codec->dapm,
3299 ARRAY_SIZE(rt5677_dmic2_clk_2));
3300 } else { /*use dmic1 clock by default*/
3301 snd_soc_dapm_add_routes(&codec->dapm,
3303 ARRAY_SIZE(rt5677_dmic2_clk_1));
3306 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
3308 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
3309 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
3314 static int rt5677_remove(struct snd_soc_codec *codec)
3316 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3318 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3324 static int rt5677_suspend(struct snd_soc_codec *codec)
3326 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3328 regcache_cache_only(rt5677->regmap, true);
3329 regcache_mark_dirty(rt5677->regmap);
3334 static int rt5677_resume(struct snd_soc_codec *codec)
3336 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3338 regcache_cache_only(rt5677->regmap, false);
3339 regcache_sync(rt5677->regmap);
3344 #define rt5677_suspend NULL
3345 #define rt5677_resume NULL
3348 #define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3349 #define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3350 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3352 static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
3353 .hw_params = rt5677_hw_params,
3354 .set_fmt = rt5677_set_dai_fmt,
3355 .set_sysclk = rt5677_set_dai_sysclk,
3356 .set_pll = rt5677_set_dai_pll,
3359 static struct snd_soc_dai_driver rt5677_dai[] = {
3361 .name = "rt5677-aif1",
3364 .stream_name = "AIF1 Playback",
3367 .rates = RT5677_STEREO_RATES,
3368 .formats = RT5677_FORMATS,
3371 .stream_name = "AIF1 Capture",
3374 .rates = RT5677_STEREO_RATES,
3375 .formats = RT5677_FORMATS,
3377 .ops = &rt5677_aif_dai_ops,
3380 .name = "rt5677-aif2",
3383 .stream_name = "AIF2 Playback",
3386 .rates = RT5677_STEREO_RATES,
3387 .formats = RT5677_FORMATS,
3390 .stream_name = "AIF2 Capture",
3393 .rates = RT5677_STEREO_RATES,
3394 .formats = RT5677_FORMATS,
3396 .ops = &rt5677_aif_dai_ops,
3399 .name = "rt5677-aif3",
3402 .stream_name = "AIF3 Playback",
3405 .rates = RT5677_STEREO_RATES,
3406 .formats = RT5677_FORMATS,
3409 .stream_name = "AIF3 Capture",
3412 .rates = RT5677_STEREO_RATES,
3413 .formats = RT5677_FORMATS,
3415 .ops = &rt5677_aif_dai_ops,
3418 .name = "rt5677-aif4",
3421 .stream_name = "AIF4 Playback",
3424 .rates = RT5677_STEREO_RATES,
3425 .formats = RT5677_FORMATS,
3428 .stream_name = "AIF4 Capture",
3431 .rates = RT5677_STEREO_RATES,
3432 .formats = RT5677_FORMATS,
3434 .ops = &rt5677_aif_dai_ops,
3437 .name = "rt5677-slimbus",
3440 .stream_name = "SLIMBus Playback",
3443 .rates = RT5677_STEREO_RATES,
3444 .formats = RT5677_FORMATS,
3447 .stream_name = "SLIMBus Capture",
3450 .rates = RT5677_STEREO_RATES,
3451 .formats = RT5677_FORMATS,
3453 .ops = &rt5677_aif_dai_ops,
3457 static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
3458 .probe = rt5677_probe,
3459 .remove = rt5677_remove,
3460 .suspend = rt5677_suspend,
3461 .resume = rt5677_resume,
3462 .set_bias_level = rt5677_set_bias_level,
3463 .idle_bias_off = true,
3464 .controls = rt5677_snd_controls,
3465 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
3466 .dapm_widgets = rt5677_dapm_widgets,
3467 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
3468 .dapm_routes = rt5677_dapm_routes,
3469 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
3472 static const struct regmap_config rt5677_regmap = {
3476 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
3479 .volatile_reg = rt5677_volatile_register,
3480 .readable_reg = rt5677_readable_register,
3482 .cache_type = REGCACHE_RBTREE,
3483 .reg_defaults = rt5677_reg,
3484 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
3485 .ranges = rt5677_ranges,
3486 .num_ranges = ARRAY_SIZE(rt5677_ranges),
3489 static const struct i2c_device_id rt5677_i2c_id[] = {
3493 MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
3495 static int rt5677_i2c_probe(struct i2c_client *i2c,
3496 const struct i2c_device_id *id)
3498 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
3499 struct rt5677_priv *rt5677;
3503 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
3508 i2c_set_clientdata(i2c, rt5677);
3511 rt5677->pdata = *pdata;
3513 rt5677->regmap = devm_regmap_init_i2c(i2c, &rt5677_regmap);
3514 if (IS_ERR(rt5677->regmap)) {
3515 ret = PTR_ERR(rt5677->regmap);
3516 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3521 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
3522 if (val != RT5677_DEVICE_ID) {
3524 "Device with ID register %x is not rt5677\n", val);
3528 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3530 ret = regmap_register_patch(rt5677->regmap, init_list,
3531 ARRAY_SIZE(init_list));
3533 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3535 if (rt5677->pdata.in1_diff)
3536 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3537 RT5677_IN_DF1, RT5677_IN_DF1);
3539 if (rt5677->pdata.in2_diff)
3540 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3541 RT5677_IN_DF2, RT5677_IN_DF2);
3543 if (rt5677->pdata.dmic2_clk_pin == RT5677_DMIC_CLK2) {
3544 regmap_update_bits(rt5677->regmap, RT5677_GEN_CTRL2,
3545 RT5677_GPIO5_FUNC_MASK,
3546 RT5677_GPIO5_FUNC_DMIC);
3547 regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL2,
3548 RT5677_GPIO5_DIR_MASK,
3549 RT5677_GPIO5_DIR_OUT);
3552 rt5677_init_gpio(i2c);
3554 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
3555 rt5677_dai, ARRAY_SIZE(rt5677_dai));
3558 static int rt5677_i2c_remove(struct i2c_client *i2c)
3560 snd_soc_unregister_codec(&i2c->dev);
3561 rt5677_free_gpio(i2c);
3566 static struct i2c_driver rt5677_i2c_driver = {
3569 .owner = THIS_MODULE,
3571 .probe = rt5677_i2c_probe,
3572 .remove = rt5677_i2c_remove,
3573 .id_table = rt5677_i2c_id,
3575 module_i2c_driver(rt5677_i2c_driver);
3577 MODULE_DESCRIPTION("ASoC RT5677 driver");
3578 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
3579 MODULE_LICENSE("GPL v2");