2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/regulator/driver.h>
20 #include <linux/regulator/machine.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/of_device.h>
23 #include <sound/core.h>
24 #include <sound/tlv.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
33 #define SGTL5000_DAP_REG_OFFSET 0x0100
34 #define SGTL5000_MAX_REG_OFFSET 0x013A
36 /* default value of sgtl5000 registers */
37 static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = {
38 [SGTL5000_CHIP_CLK_CTRL] = 0x0008,
39 [SGTL5000_CHIP_I2S_CTRL] = 0x0010,
40 [SGTL5000_CHIP_SSS_CTRL] = 0x0008,
41 [SGTL5000_CHIP_DAC_VOL] = 0x3c3c,
42 [SGTL5000_CHIP_PAD_STRENGTH] = 0x015f,
43 [SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818,
44 [SGTL5000_CHIP_ANA_CTRL] = 0x0111,
45 [SGTL5000_CHIP_LINE_OUT_VOL] = 0x0404,
46 [SGTL5000_CHIP_ANA_POWER] = 0x7060,
47 [SGTL5000_CHIP_PLL_CTRL] = 0x5000,
48 [SGTL5000_DAP_BASS_ENHANCE] = 0x0040,
49 [SGTL5000_DAP_BASS_ENHANCE_CTRL] = 0x051f,
50 [SGTL5000_DAP_SURROUND] = 0x0040,
51 [SGTL5000_DAP_EQ_BASS_BAND0] = 0x002f,
52 [SGTL5000_DAP_EQ_BASS_BAND1] = 0x002f,
53 [SGTL5000_DAP_EQ_BASS_BAND2] = 0x002f,
54 [SGTL5000_DAP_EQ_BASS_BAND3] = 0x002f,
55 [SGTL5000_DAP_EQ_BASS_BAND4] = 0x002f,
56 [SGTL5000_DAP_MAIN_CHAN] = 0x8000,
57 [SGTL5000_DAP_AVC_CTRL] = 0x0510,
58 [SGTL5000_DAP_AVC_THRESHOLD] = 0x1473,
59 [SGTL5000_DAP_AVC_ATTACK] = 0x0028,
60 [SGTL5000_DAP_AVC_DECAY] = 0x0050,
63 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
64 enum sgtl5000_regulator_supplies {
71 /* vddd is optional supply */
72 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
78 #define LDO_CONSUMER_NAME "VDDD_LDO"
79 #define LDO_VOLTAGE 1200000
81 static struct regulator_consumer_supply ldo_consumer[] = {
82 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
85 static struct regulator_init_data ldo_init_data = {
89 .valid_modes_mask = REGULATOR_MODE_NORMAL,
90 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
92 .num_consumer_supplies = 1,
93 .consumer_supplies = &ldo_consumer[0],
97 * sgtl5000 internal ldo regulator,
98 * enabled when VDDD not provided
100 struct ldo_regulator {
101 struct regulator_desc desc;
102 struct regulator_dev *dev;
108 /* sgtl5000 private structure in codec */
109 struct sgtl5000_priv {
110 int sysclk; /* sysclk rate */
111 int master; /* i2s master or not */
112 int fmt; /* i2s data format */
113 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
114 struct ldo_regulator *ldo;
118 * mic_bias power on/off share the same register bits with
119 * output impedance of mic bias, when power on mic bias, we
120 * need reclaim it to impedance value.
126 static int mic_bias_event(struct snd_soc_dapm_widget *w,
127 struct snd_kcontrol *kcontrol, int event)
130 case SND_SOC_DAPM_POST_PMU:
131 /* change mic bias resistor to 4Kohm */
132 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
133 SGTL5000_BIAS_R_MASK,
134 SGTL5000_BIAS_R_4k << SGTL5000_BIAS_R_SHIFT);
137 case SND_SOC_DAPM_PRE_PMD:
138 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
139 SGTL5000_BIAS_R_MASK, 0);
146 * As manual described, ADC/DAC only works when VAG powerup,
147 * So enabled VAG before ADC/DAC up.
148 * In power down case, we need wait 400ms when vag fully ramped down.
150 static int power_vag_event(struct snd_soc_dapm_widget *w,
151 struct snd_kcontrol *kcontrol, int event)
154 case SND_SOC_DAPM_PRE_PMU:
155 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
156 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
159 case SND_SOC_DAPM_POST_PMD:
160 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
161 SGTL5000_VAG_POWERUP, 0);
171 /* input sources for ADC */
172 static const char *adc_mux_text[] = {
176 static const struct soc_enum adc_enum =
177 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 2, 2, adc_mux_text);
179 static const struct snd_kcontrol_new adc_mux =
180 SOC_DAPM_ENUM("Capture Mux", adc_enum);
182 /* input sources for DAC */
183 static const char *dac_mux_text[] = {
187 static const struct soc_enum dac_enum =
188 SOC_ENUM_SINGLE(SGTL5000_CHIP_ANA_CTRL, 6, 2, dac_mux_text);
190 static const struct snd_kcontrol_new dac_mux =
191 SOC_DAPM_ENUM("Headphone Mux", dac_enum);
193 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
194 SND_SOC_DAPM_INPUT("LINE_IN"),
195 SND_SOC_DAPM_INPUT("MIC_IN"),
197 SND_SOC_DAPM_OUTPUT("HP_OUT"),
198 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
200 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
202 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
204 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
205 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
207 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
208 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
210 /* aif for i2s input */
211 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
212 0, SGTL5000_CHIP_DIG_POWER,
215 /* aif for i2s output */
216 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
217 0, SGTL5000_CHIP_DIG_POWER,
220 SND_SOC_DAPM_SUPPLY("VAG_POWER", SGTL5000_CHIP_ANA_POWER, 7, 0,
222 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
224 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
225 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
228 /* routes for sgtl5000 */
229 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
230 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
231 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
233 {"ADC", NULL, "VAG_POWER"},
234 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
235 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
237 {"DAC", NULL, "VAG_POWER"},
238 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
239 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
240 {"LO", NULL, "DAC"}, /* dac --> line_out */
242 {"LINE_IN", NULL, "VAG_POWER"},
243 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
244 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
246 {"LINE_OUT", NULL, "LO"},
247 {"HP_OUT", NULL, "HP"},
250 /* custom function to fetch info of PCM playback volume */
251 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
252 struct snd_ctl_elem_info *uinfo)
254 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
256 uinfo->value.integer.min = 0;
257 uinfo->value.integer.max = 0xfc - 0x3c;
262 * custom function to get of PCM playback volume
264 * dac volume register
265 * 15-------------8-7--------------0
266 * | R channel vol | L channel vol |
267 * -------------------------------
269 * PCM volume with 0.5017 dB steps from 0 to -90 dB
271 * register values map to dB
272 * 0x3B and less = Reserved
276 * 0xFC and greater = Muted
278 * register value map to userspace value
280 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
281 * ------------------------------
282 * userspace value 0xc0 0
284 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
285 struct snd_ctl_elem_value *ucontrol)
287 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
292 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
294 /* get left channel volume */
295 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
297 /* get right channel volume */
298 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
300 /* make sure value fall in (0x3c,0xfc) */
301 l = clamp(l, 0x3c, 0xfc);
302 r = clamp(r, 0x3c, 0xfc);
304 /* invert it and map to userspace value */
308 ucontrol->value.integer.value[0] = l;
309 ucontrol->value.integer.value[1] = r;
315 * custom function to put of PCM playback volume
317 * dac volume register
318 * 15-------------8-7--------------0
319 * | R channel vol | L channel vol |
320 * -------------------------------
322 * PCM volume with 0.5017 dB steps from 0 to -90 dB
324 * register values map to dB
325 * 0x3B and less = Reserved
329 * 0xFC and greater = Muted
331 * userspace value map to register value
333 * userspace value 0xc0 0
334 * ------------------------------
335 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
337 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
338 struct snd_ctl_elem_value *ucontrol)
340 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
345 l = ucontrol->value.integer.value[0];
346 r = ucontrol->value.integer.value[1];
348 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
349 l = clamp(l, 0, 0xfc - 0x3c);
350 r = clamp(r, 0, 0xfc - 0x3c);
352 /* invert it, get the value can be set to register */
356 /* shift to get the register value */
357 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
358 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
360 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
365 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
367 /* tlv for mic gain, 0db 20db 30db 40db */
368 static const unsigned int mic_gain_tlv[] = {
369 TLV_DB_RANGE_HEAD(2),
370 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
371 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
374 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
375 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
377 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
378 /* SOC_DOUBLE_S8_TLV with invert */
380 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
381 .name = "PCM Playback Volume",
382 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
383 SNDRV_CTL_ELEM_ACCESS_READWRITE,
384 .info = dac_info_volsw,
385 .get = dac_get_volsw,
386 .put = dac_put_volsw,
389 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
390 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
391 SGTL5000_CHIP_ANA_ADC_CTRL,
392 8, 2, 0, capture_6db_attenuate),
393 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
395 SOC_DOUBLE_TLV("Headphone Playback Volume",
396 SGTL5000_CHIP_ANA_HP_CTRL,
400 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
403 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
404 0, 4, 0, mic_gain_tlv),
407 /* mute the codec used by alsa core */
408 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
410 struct snd_soc_codec *codec = codec_dai->codec;
411 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
413 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
414 adcdac_ctrl, mute ? adcdac_ctrl : 0);
419 /* set codec format */
420 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
422 struct snd_soc_codec *codec = codec_dai->codec;
423 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
426 sgtl5000->master = 0;
428 * i2s clock and frame master setting.
430 * - clock and frame slave,
431 * - clock and frame master
433 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
434 case SND_SOC_DAIFMT_CBS_CFS:
436 case SND_SOC_DAIFMT_CBM_CFM:
437 i2sctl |= SGTL5000_I2S_MASTER;
438 sgtl5000->master = 1;
444 /* setting i2s data format */
445 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
446 case SND_SOC_DAIFMT_DSP_A:
447 i2sctl |= SGTL5000_I2S_MODE_PCM;
449 case SND_SOC_DAIFMT_DSP_B:
450 i2sctl |= SGTL5000_I2S_MODE_PCM;
451 i2sctl |= SGTL5000_I2S_LRALIGN;
453 case SND_SOC_DAIFMT_I2S:
454 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
456 case SND_SOC_DAIFMT_RIGHT_J:
457 i2sctl |= SGTL5000_I2S_MODE_RJ;
458 i2sctl |= SGTL5000_I2S_LRPOL;
460 case SND_SOC_DAIFMT_LEFT_J:
461 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
462 i2sctl |= SGTL5000_I2S_LRALIGN;
468 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
470 /* Clock inversion */
471 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
472 case SND_SOC_DAIFMT_NB_NF:
474 case SND_SOC_DAIFMT_IB_NF:
475 i2sctl |= SGTL5000_I2S_SCLK_INV;
481 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
486 /* set codec sysclk */
487 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
488 int clk_id, unsigned int freq, int dir)
490 struct snd_soc_codec *codec = codec_dai->codec;
491 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
494 case SGTL5000_SYSCLK:
495 sgtl5000->sysclk = freq;
505 * set clock according to i2s frame clock,
506 * sgtl5000 provide 2 clock sources.
507 * 1. sys_mclk. sample freq can only configure to
508 * 1/256, 1/384, 1/512 of sys_mclk.
509 * 2. pll. can derive any audio clocks.
511 * clock setting rules:
512 * 1. in slave mode, only sys_mclk can use.
513 * 2. as constraint by sys_mclk, sample freq should
514 * set to 32k, 44.1k and above.
515 * 3. using sys_mclk prefer to pll to save power.
517 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
519 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
521 int sys_fs; /* sample freq */
524 * sample freq should be divided by frame clock,
525 * if frame clock lower than 44.1khz, sample feq should set to
528 switch (frame_rate) {
542 /* set divided factor of frame clock */
543 switch (sys_fs / frame_rate) {
545 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
548 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
551 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
557 /* set the sys_fs according to frame rate */
560 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
563 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
566 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
569 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
572 dev_err(codec->dev, "frame rate %d not supported\n",
578 * calculate the divider of mclk/sample_freq,
579 * factor of freq =96k can only be 256, since mclk in range (12m,27m)
581 switch (sgtl5000->sysclk / sys_fs) {
583 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
584 SGTL5000_MCLK_FREQ_SHIFT;
587 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
588 SGTL5000_MCLK_FREQ_SHIFT;
591 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
592 SGTL5000_MCLK_FREQ_SHIFT;
595 /* if mclk not satisify the divider, use pll */
596 if (sgtl5000->master) {
597 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
598 SGTL5000_MCLK_FREQ_SHIFT;
601 "PLL not supported in slave mode\n");
606 /* if using pll, please check manual 6.4.2 for detail */
607 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
611 unsigned int in, int_div, frac_div;
613 if (sgtl5000->sysclk > 17000000) {
615 in = sgtl5000->sysclk / 2;
618 in = sgtl5000->sysclk;
629 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
630 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
632 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
634 snd_soc_update_bits(codec,
635 SGTL5000_CHIP_CLK_TOP_CTRL,
636 SGTL5000_INPUT_FREQ_DIV2,
637 SGTL5000_INPUT_FREQ_DIV2);
639 snd_soc_update_bits(codec,
640 SGTL5000_CHIP_CLK_TOP_CTRL,
641 SGTL5000_INPUT_FREQ_DIV2,
645 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
646 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
647 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
650 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
651 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
655 /* if using pll, clk_ctrl must be set after pll power up */
656 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
662 * Set PCM DAI bit size and sample rate.
663 * input: params_rate, params_fmt
665 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
666 struct snd_pcm_hw_params *params,
667 struct snd_soc_dai *dai)
669 struct snd_soc_codec *codec = dai->codec;
670 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
671 int channels = params_channels(params);
676 /* sysclk should already set */
677 if (!sgtl5000->sysclk) {
678 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
682 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
683 stereo = SGTL5000_DAC_STEREO;
685 stereo = SGTL5000_ADC_STEREO;
687 /* set mono to save power */
688 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
689 channels == 1 ? 0 : stereo);
691 /* set codec clock base on lrclk */
692 ret = sgtl5000_set_clock(codec, params_rate(params));
696 /* set i2s data format */
697 switch (params_format(params)) {
698 case SNDRV_PCM_FORMAT_S16_LE:
699 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
701 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
702 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
703 SGTL5000_I2S_SCLKFREQ_SHIFT;
705 case SNDRV_PCM_FORMAT_S20_3LE:
706 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
707 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
708 SGTL5000_I2S_SCLKFREQ_SHIFT;
710 case SNDRV_PCM_FORMAT_S24_LE:
711 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
712 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
713 SGTL5000_I2S_SCLKFREQ_SHIFT;
715 case SNDRV_PCM_FORMAT_S32_LE:
716 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
718 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
719 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
720 SGTL5000_I2S_SCLKFREQ_SHIFT;
726 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
727 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
733 #ifdef CONFIG_REGULATOR
734 static int ldo_regulator_is_enabled(struct regulator_dev *dev)
736 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
741 static int ldo_regulator_enable(struct regulator_dev *dev)
743 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
744 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
747 if (ldo_regulator_is_enabled(dev))
750 /* set regulator value firstly */
751 reg = (1600 - ldo->voltage / 1000) / 50;
752 reg = clamp(reg, 0x0, 0xf);
754 /* amend the voltage value, unit: uV */
755 ldo->voltage = (1600 - reg * 50) * 1000;
757 /* set voltage to register */
758 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
759 SGTL5000_LINREG_VDDD_MASK, reg);
761 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
762 SGTL5000_LINEREG_D_POWERUP,
763 SGTL5000_LINEREG_D_POWERUP);
765 /* when internal ldo enabled, simple digital power can be disabled */
766 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
767 SGTL5000_LINREG_SIMPLE_POWERUP,
774 static int ldo_regulator_disable(struct regulator_dev *dev)
776 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
777 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
779 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
780 SGTL5000_LINEREG_D_POWERUP,
783 /* clear voltage info */
784 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
785 SGTL5000_LINREG_VDDD_MASK, 0);
792 static int ldo_regulator_get_voltage(struct regulator_dev *dev)
794 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
799 static struct regulator_ops ldo_regulator_ops = {
800 .is_enabled = ldo_regulator_is_enabled,
801 .enable = ldo_regulator_enable,
802 .disable = ldo_regulator_disable,
803 .get_voltage = ldo_regulator_get_voltage,
806 static int ldo_regulator_register(struct snd_soc_codec *codec,
807 struct regulator_init_data *init_data,
810 struct ldo_regulator *ldo;
811 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
812 struct regulator_config config = { };
814 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
817 dev_err(codec->dev, "failed to allocate ldo_regulator\n");
821 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
822 if (!ldo->desc.name) {
824 dev_err(codec->dev, "failed to allocate decs name memory\n");
828 ldo->desc.type = REGULATOR_VOLTAGE;
829 ldo->desc.owner = THIS_MODULE;
830 ldo->desc.ops = &ldo_regulator_ops;
831 ldo->desc.n_voltages = 1;
833 ldo->codec_data = codec;
834 ldo->voltage = voltage;
836 config.dev = codec->dev;
837 config.driver_data = ldo;
838 config.init_data = init_data;
840 ldo->dev = regulator_register(&ldo->desc, &config);
841 if (IS_ERR(ldo->dev)) {
842 int ret = PTR_ERR(ldo->dev);
844 dev_err(codec->dev, "failed to register regulator\n");
845 kfree(ldo->desc.name);
855 static int ldo_regulator_remove(struct snd_soc_codec *codec)
857 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
858 struct ldo_regulator *ldo = sgtl5000->ldo;
863 regulator_unregister(ldo->dev);
864 kfree(ldo->desc.name);
870 static int ldo_regulator_register(struct snd_soc_codec *codec,
871 struct regulator_init_data *init_data,
874 dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
878 static int ldo_regulator_remove(struct snd_soc_codec *codec)
886 * common state changes:
888 * off --> standby --> prepare --> on
889 * standby --> prepare --> on
892 * on --> prepare --> standby
894 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
895 enum snd_soc_bias_level level)
898 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
901 case SND_SOC_BIAS_ON:
902 case SND_SOC_BIAS_PREPARE:
904 case SND_SOC_BIAS_STANDBY:
905 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
906 ret = regulator_bulk_enable(
907 ARRAY_SIZE(sgtl5000->supplies),
915 case SND_SOC_BIAS_OFF:
916 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
921 codec->dapm.bias_level = level;
925 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
926 SNDRV_PCM_FMTBIT_S20_3LE |\
927 SNDRV_PCM_FMTBIT_S24_LE |\
928 SNDRV_PCM_FMTBIT_S32_LE)
930 static const struct snd_soc_dai_ops sgtl5000_ops = {
931 .hw_params = sgtl5000_pcm_hw_params,
932 .digital_mute = sgtl5000_digital_mute,
933 .set_fmt = sgtl5000_set_dai_fmt,
934 .set_sysclk = sgtl5000_set_dai_sysclk,
937 static struct snd_soc_dai_driver sgtl5000_dai = {
940 .stream_name = "Playback",
944 * only support 8~48K + 96K,
945 * TODO modify hw_param to support more
947 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
948 .formats = SGTL5000_FORMATS,
951 .stream_name = "Capture",
954 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
955 .formats = SGTL5000_FORMATS,
957 .ops = &sgtl5000_ops,
958 .symmetric_rates = 1,
961 static int sgtl5000_volatile_register(struct snd_soc_codec *codec,
965 case SGTL5000_CHIP_ID:
966 case SGTL5000_CHIP_ADCDAC_CTRL:
967 case SGTL5000_CHIP_ANA_STATUS:
974 #ifdef CONFIG_SUSPEND
975 static int sgtl5000_suspend(struct snd_soc_codec *codec)
977 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
983 * restore all sgtl5000 registers,
984 * since a big hole between dap and regular registers,
985 * we will restore them respectively.
987 static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
989 u16 *cache = codec->reg_cache;
992 /* restore regular registers */
993 for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
995 /* These regs should restore in particular order */
996 if (reg == SGTL5000_CHIP_ANA_POWER ||
997 reg == SGTL5000_CHIP_CLK_CTRL ||
998 reg == SGTL5000_CHIP_LINREG_CTRL ||
999 reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
1000 reg == SGTL5000_CHIP_REF_CTRL)
1003 snd_soc_write(codec, reg, cache[reg]);
1006 /* restore dap registers */
1007 for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
1008 snd_soc_write(codec, reg, cache[reg]);
1011 * restore these regs according to the power setting sequence in
1012 * sgtl5000_set_power_regs() and clock setting sequence in
1013 * sgtl5000_set_clock().
1015 * The order of restore is:
1016 * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after
1017 * SGTL5000_CHIP_ANA_POWER PLL bits set
1018 * 2. SGTL5000_CHIP_LINREG_CTRL should be set before
1019 * SGTL5000_CHIP_ANA_POWER LINREG_D restored
1020 * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage,
1021 * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored
1023 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
1024 cache[SGTL5000_CHIP_LINREG_CTRL]);
1026 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
1027 cache[SGTL5000_CHIP_ANA_POWER]);
1029 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
1030 cache[SGTL5000_CHIP_CLK_CTRL]);
1032 snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
1033 cache[SGTL5000_CHIP_REF_CTRL]);
1035 snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1036 cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
1040 static int sgtl5000_resume(struct snd_soc_codec *codec)
1042 /* Bring the codec back up to standby to enable regulators */
1043 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1045 /* Restore registers by cached in memory */
1046 sgtl5000_restore_regs(codec);
1050 #define sgtl5000_suspend NULL
1051 #define sgtl5000_resume NULL
1052 #endif /* CONFIG_SUSPEND */
1055 * sgtl5000 has 3 internal power supplies:
1056 * 1. VAG, normally set to vdda/2
1057 * 2. chargepump, set to different value
1058 * according to voltage of vdda and vddio
1059 * 3. line out VAG, normally set to vddio/2
1061 * and should be set according to:
1062 * 1. vddd provided by external or not
1063 * 2. vdda and vddio voltage value. > 3.1v or not
1064 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1066 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1074 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1076 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1077 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1078 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1081 vddio = vddio / 1000;
1084 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1085 dev_err(codec->dev, "regulator voltage not set correctly\n");
1090 /* according to datasheet, maximum voltage of supplies */
1091 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1093 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1100 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1101 ana_pwr |= SGTL5000_DAC_STEREO |
1102 SGTL5000_ADC_STEREO |
1103 SGTL5000_REFTOP_POWERUP;
1104 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1106 if (vddio < 3100 && vdda < 3100) {
1107 /* enable internal oscillator used for charge pump */
1108 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1109 SGTL5000_INT_OSC_EN,
1110 SGTL5000_INT_OSC_EN);
1111 /* Enable VDDC charge pump */
1112 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1113 } else if (vddio >= 3100 && vdda >= 3100) {
1115 * if vddio and vddd > 3.1v,
1116 * charge pump should be clean before set ana_pwr
1118 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1119 SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
1121 /* VDDC use VDDIO rail */
1122 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1123 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1124 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1127 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1129 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1131 /* set voltage to register */
1132 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
1133 SGTL5000_LINREG_VDDD_MASK, 0x8);
1136 * if vddd linear reg has been enabled,
1137 * simple digital supply should be clear to get
1138 * proper VDDD voltage.
1140 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1141 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1142 SGTL5000_LINREG_SIMPLE_POWERUP,
1145 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1146 SGTL5000_LINREG_SIMPLE_POWERUP |
1147 SGTL5000_STARTUP_POWERUP,
1151 * set ADC/DAC VAG to vdda / 2,
1152 * should stay in range (0.8v, 1.575v)
1155 if (vag <= SGTL5000_ANA_GND_BASE)
1157 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1158 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1159 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1161 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1163 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1164 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1166 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1168 if (vag <= SGTL5000_LINE_OUT_GND_BASE)
1170 else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
1171 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1172 vag = SGTL5000_LINE_OUT_GND_MAX;
1174 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
1175 SGTL5000_LINE_OUT_GND_STP;
1177 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1178 SGTL5000_LINE_OUT_CURRENT_MASK |
1179 SGTL5000_LINE_OUT_GND_MASK,
1180 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1181 SGTL5000_LINE_OUT_CURRENT_360u <<
1182 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1187 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1189 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1192 /* set internal ldo to 1.2v */
1193 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1196 "Failed to register vddd internal supplies: %d\n", ret);
1200 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1202 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1203 sgtl5000->supplies);
1206 ldo_regulator_remove(codec);
1207 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1211 dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1215 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1221 int external_vddd = 0;
1222 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1224 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1225 sgtl5000->supplies[i].supply = supply_names[i];
1227 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1228 sgtl5000->supplies);
1232 ret = sgtl5000_replace_vddd_with_ldo(codec);
1237 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1238 sgtl5000->supplies);
1240 goto err_regulator_free;
1242 /* wait for all power rails bring up */
1245 /* read chip information */
1246 reg = snd_soc_read(codec, SGTL5000_CHIP_ID);
1247 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1248 SGTL5000_PARTID_PART_ID) {
1250 "Device with ID register %x is not a sgtl5000\n", reg);
1252 goto err_regulator_disable;
1255 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1256 dev_info(codec->dev, "sgtl5000 revision 0x%x\n", rev);
1259 * workaround for revision 0x11 and later,
1260 * roll back to use internal LDO
1262 if (external_vddd && rev >= 0x11) {
1263 /* disable all regulator first */
1264 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1265 sgtl5000->supplies);
1266 /* free VDDD regulator */
1267 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1268 sgtl5000->supplies);
1270 ret = sgtl5000_replace_vddd_with_ldo(codec);
1274 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1275 sgtl5000->supplies);
1277 goto err_regulator_free;
1279 /* wait for all power rails bring up */
1285 err_regulator_disable:
1286 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1287 sgtl5000->supplies);
1289 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1290 sgtl5000->supplies);
1292 ldo_regulator_remove(codec);
1297 static int sgtl5000_probe(struct snd_soc_codec *codec)
1300 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1302 /* setup i2c data ops */
1303 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
1305 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1309 ret = sgtl5000_enable_regulators(codec);
1313 /* power up sgtl5000 */
1314 ret = sgtl5000_set_power_regs(codec);
1318 /* enable small pop, introduce 400ms delay in turning off */
1319 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1321 SGTL5000_SMALL_POP);
1323 /* disable short cut detector */
1324 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1327 * set i2s as default input of sound switch
1328 * TODO: add sound switch to control and dapm widge.
1330 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1331 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1332 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1333 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1335 /* enable dac volume ramp by default */
1336 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1337 SGTL5000_DAC_VOL_RAMP_EN |
1338 SGTL5000_DAC_MUTE_RIGHT |
1339 SGTL5000_DAC_MUTE_LEFT);
1341 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1343 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1344 SGTL5000_HP_ZCD_EN |
1345 SGTL5000_ADC_ZCD_EN);
1347 snd_soc_write(codec, SGTL5000_CHIP_MIC_CTRL, 0);
1352 * Enable DAP in kcontrol and dapm.
1354 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1356 /* leading to standby state */
1357 ret = sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1364 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1365 sgtl5000->supplies);
1366 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1367 sgtl5000->supplies);
1368 ldo_regulator_remove(codec);
1373 static int sgtl5000_remove(struct snd_soc_codec *codec)
1375 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1377 sgtl5000_set_bias_level(codec, SND_SOC_BIAS_OFF);
1379 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1380 sgtl5000->supplies);
1381 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1382 sgtl5000->supplies);
1383 ldo_regulator_remove(codec);
1388 static struct snd_soc_codec_driver sgtl5000_driver = {
1389 .probe = sgtl5000_probe,
1390 .remove = sgtl5000_remove,
1391 .suspend = sgtl5000_suspend,
1392 .resume = sgtl5000_resume,
1393 .set_bias_level = sgtl5000_set_bias_level,
1394 .reg_cache_size = ARRAY_SIZE(sgtl5000_regs),
1395 .reg_word_size = sizeof(u16),
1396 .reg_cache_step = 2,
1397 .reg_cache_default = sgtl5000_regs,
1398 .volatile_register = sgtl5000_volatile_register,
1399 .controls = sgtl5000_snd_controls,
1400 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1401 .dapm_widgets = sgtl5000_dapm_widgets,
1402 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1403 .dapm_routes = sgtl5000_dapm_routes,
1404 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1407 static __devinit int sgtl5000_i2c_probe(struct i2c_client *client,
1408 const struct i2c_device_id *id)
1410 struct sgtl5000_priv *sgtl5000;
1413 sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv),
1418 i2c_set_clientdata(client, sgtl5000);
1420 ret = snd_soc_register_codec(&client->dev,
1421 &sgtl5000_driver, &sgtl5000_dai, 1);
1425 static __devexit int sgtl5000_i2c_remove(struct i2c_client *client)
1427 snd_soc_unregister_codec(&client->dev);
1432 static const struct i2c_device_id sgtl5000_id[] = {
1437 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1439 static const struct of_device_id sgtl5000_dt_ids[] = {
1440 { .compatible = "fsl,sgtl5000", },
1443 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1445 static struct i2c_driver sgtl5000_i2c_driver = {
1448 .owner = THIS_MODULE,
1449 .of_match_table = sgtl5000_dt_ids,
1451 .probe = sgtl5000_i2c_probe,
1452 .remove = __devexit_p(sgtl5000_i2c_remove),
1453 .id_table = sgtl5000_id,
1456 module_i2c_driver(sgtl5000_i2c_driver);
1458 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1459 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1460 MODULE_LICENSE("GPL");