2 * sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/slab.h>
17 #include <linux/i2c.h>
18 #include <linux/clk.h>
19 #include <linux/log2.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/driver.h>
22 #include <linux/regulator/machine.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/of_device.h>
25 #include <sound/core.h>
26 #include <sound/tlv.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
35 #define SGTL5000_DAP_REG_OFFSET 0x0100
36 #define SGTL5000_MAX_REG_OFFSET 0x013A
38 /* default value of sgtl5000 registers */
39 static const struct reg_default sgtl5000_reg_defaults[] = {
40 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
41 { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
42 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
43 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
44 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
45 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
46 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
47 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
48 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
49 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
50 { SGTL5000_CHIP_LINREG_CTRL, 0x0000 },
51 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
52 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
53 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
54 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
55 { SGTL5000_CHIP_ANA_POWER, 0x7060 },
56 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
57 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
58 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
59 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
60 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
61 { SGTL5000_DAP_CTRL, 0x0000 },
62 { SGTL5000_DAP_PEQ, 0x0000 },
63 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
64 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
65 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
66 { SGTL5000_DAP_SURROUND, 0x0040 },
67 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
68 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
69 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
70 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
71 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
72 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
73 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
74 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
75 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
76 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
77 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
80 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
81 enum sgtl5000_regulator_supplies {
88 /* vddd is optional supply */
89 static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
95 #define LDO_CONSUMER_NAME "VDDD_LDO"
96 #define LDO_VOLTAGE 1200000
98 static struct regulator_consumer_supply ldo_consumer[] = {
99 REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
102 static struct regulator_init_data ldo_init_data = {
106 .valid_modes_mask = REGULATOR_MODE_NORMAL,
107 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
109 .num_consumer_supplies = 1,
110 .consumer_supplies = &ldo_consumer[0],
114 * sgtl5000 internal ldo regulator,
115 * enabled when VDDD not provided
117 struct ldo_regulator {
118 struct regulator_desc desc;
119 struct regulator_dev *dev;
125 enum sgtl5000_micbias_resistor {
126 SGTL5000_MICBIAS_OFF = 0,
127 SGTL5000_MICBIAS_2K = 2,
128 SGTL5000_MICBIAS_4K = 4,
129 SGTL5000_MICBIAS_8K = 8,
132 /* sgtl5000 private structure in codec */
133 struct sgtl5000_priv {
134 int sysclk; /* sysclk rate */
135 int master; /* i2s master or not */
136 int fmt; /* i2s data format */
137 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
138 struct ldo_regulator *ldo;
139 struct regmap *regmap;
146 * mic_bias power on/off share the same register bits with
147 * output impedance of mic bias, when power on mic bias, we
148 * need reclaim it to impedance value.
154 static int mic_bias_event(struct snd_soc_dapm_widget *w,
155 struct snd_kcontrol *kcontrol, int event)
157 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(w->codec);
160 case SND_SOC_DAPM_POST_PMU:
161 /* change mic bias resistor */
162 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
163 SGTL5000_BIAS_R_MASK,
164 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
167 case SND_SOC_DAPM_PRE_PMD:
168 snd_soc_update_bits(w->codec, SGTL5000_CHIP_MIC_CTRL,
169 SGTL5000_BIAS_R_MASK, 0);
176 * As manual described, ADC/DAC only works when VAG powerup,
177 * So enabled VAG before ADC/DAC up.
178 * In power down case, we need wait 400ms when vag fully ramped down.
180 static int power_vag_event(struct snd_soc_dapm_widget *w,
181 struct snd_kcontrol *kcontrol, int event)
183 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
186 case SND_SOC_DAPM_POST_PMU:
187 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
188 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
191 case SND_SOC_DAPM_PRE_PMD:
193 * Don't clear VAG_POWERUP, when both DAC and ADC are
194 * operational to prevent inadvertently starving the
197 if ((snd_soc_read(w->codec, SGTL5000_CHIP_ANA_POWER) &
199 snd_soc_update_bits(w->codec, SGTL5000_CHIP_ANA_POWER,
200 SGTL5000_VAG_POWERUP, 0);
211 /* input sources for ADC */
212 static const char *adc_mux_text[] = {
216 static SOC_ENUM_SINGLE_DECL(adc_enum,
217 SGTL5000_CHIP_ANA_CTRL, 2,
220 static const struct snd_kcontrol_new adc_mux =
221 SOC_DAPM_ENUM("Capture Mux", adc_enum);
223 /* input sources for DAC */
224 static const char *dac_mux_text[] = {
228 static SOC_ENUM_SINGLE_DECL(dac_enum,
229 SGTL5000_CHIP_ANA_CTRL, 6,
232 static const struct snd_kcontrol_new dac_mux =
233 SOC_DAPM_ENUM("Headphone Mux", dac_enum);
235 static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
236 SND_SOC_DAPM_INPUT("LINE_IN"),
237 SND_SOC_DAPM_INPUT("MIC_IN"),
239 SND_SOC_DAPM_OUTPUT("HP_OUT"),
240 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
242 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
244 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
246 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
247 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
249 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
250 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
252 /* aif for i2s input */
253 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
254 0, SGTL5000_CHIP_DIG_POWER,
257 /* aif for i2s output */
258 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
259 0, SGTL5000_CHIP_DIG_POWER,
262 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
263 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
265 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
266 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
269 /* routes for sgtl5000 */
270 static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
271 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
272 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
274 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
275 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
277 {"DAC", NULL, "AIFIN"}, /* i2s-->dac,skip audio mux */
278 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
279 {"LO", NULL, "DAC"}, /* dac --> line_out */
281 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
282 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
284 {"LINE_OUT", NULL, "LO"},
285 {"HP_OUT", NULL, "HP"},
288 /* custom function to fetch info of PCM playback volume */
289 static int dac_info_volsw(struct snd_kcontrol *kcontrol,
290 struct snd_ctl_elem_info *uinfo)
292 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
294 uinfo->value.integer.min = 0;
295 uinfo->value.integer.max = 0xfc - 0x3c;
300 * custom function to get of PCM playback volume
302 * dac volume register
303 * 15-------------8-7--------------0
304 * | R channel vol | L channel vol |
305 * -------------------------------
307 * PCM volume with 0.5017 dB steps from 0 to -90 dB
309 * register values map to dB
310 * 0x3B and less = Reserved
314 * 0xFC and greater = Muted
316 * register value map to userspace value
318 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
319 * ------------------------------
320 * userspace value 0xc0 0
322 static int dac_get_volsw(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
325 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
330 reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
332 /* get left channel volume */
333 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
335 /* get right channel volume */
336 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
338 /* make sure value fall in (0x3c,0xfc) */
339 l = clamp(l, 0x3c, 0xfc);
340 r = clamp(r, 0x3c, 0xfc);
342 /* invert it and map to userspace value */
346 ucontrol->value.integer.value[0] = l;
347 ucontrol->value.integer.value[1] = r;
353 * custom function to put of PCM playback volume
355 * dac volume register
356 * 15-------------8-7--------------0
357 * | R channel vol | L channel vol |
358 * -------------------------------
360 * PCM volume with 0.5017 dB steps from 0 to -90 dB
362 * register values map to dB
363 * 0x3B and less = Reserved
367 * 0xFC and greater = Muted
369 * userspace value map to register value
371 * userspace value 0xc0 0
372 * ------------------------------
373 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
375 static int dac_put_volsw(struct snd_kcontrol *kcontrol,
376 struct snd_ctl_elem_value *ucontrol)
378 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
383 l = ucontrol->value.integer.value[0];
384 r = ucontrol->value.integer.value[1];
386 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
387 l = clamp(l, 0, 0xfc - 0x3c);
388 r = clamp(r, 0, 0xfc - 0x3c);
390 /* invert it, get the value can be set to register */
394 /* shift to get the register value */
395 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
396 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
398 snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
403 static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
405 /* tlv for mic gain, 0db 20db 30db 40db */
406 static const unsigned int mic_gain_tlv[] = {
407 TLV_DB_RANGE_HEAD(2),
408 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
409 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0),
412 /* tlv for hp volume, -51.5db to 12.0db, step .5db */
413 static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
415 static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
416 /* SOC_DOUBLE_S8_TLV with invert */
418 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
419 .name = "PCM Playback Volume",
420 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
421 SNDRV_CTL_ELEM_ACCESS_READWRITE,
422 .info = dac_info_volsw,
423 .get = dac_get_volsw,
424 .put = dac_put_volsw,
427 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
428 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
429 SGTL5000_CHIP_ANA_ADC_CTRL,
430 8, 1, 0, capture_6db_attenuate),
431 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
433 SOC_DOUBLE_TLV("Headphone Playback Volume",
434 SGTL5000_CHIP_ANA_HP_CTRL,
438 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
441 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
442 0, 3, 0, mic_gain_tlv),
445 /* mute the codec used by alsa core */
446 static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
448 struct snd_soc_codec *codec = codec_dai->codec;
449 u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
451 snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
452 adcdac_ctrl, mute ? adcdac_ctrl : 0);
457 /* set codec format */
458 static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
460 struct snd_soc_codec *codec = codec_dai->codec;
461 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
464 sgtl5000->master = 0;
466 * i2s clock and frame master setting.
468 * - clock and frame slave,
469 * - clock and frame master
471 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
472 case SND_SOC_DAIFMT_CBS_CFS:
474 case SND_SOC_DAIFMT_CBM_CFM:
475 i2sctl |= SGTL5000_I2S_MASTER;
476 sgtl5000->master = 1;
482 /* setting i2s data format */
483 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
484 case SND_SOC_DAIFMT_DSP_A:
485 i2sctl |= SGTL5000_I2S_MODE_PCM;
487 case SND_SOC_DAIFMT_DSP_B:
488 i2sctl |= SGTL5000_I2S_MODE_PCM;
489 i2sctl |= SGTL5000_I2S_LRALIGN;
491 case SND_SOC_DAIFMT_I2S:
492 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
494 case SND_SOC_DAIFMT_RIGHT_J:
495 i2sctl |= SGTL5000_I2S_MODE_RJ;
496 i2sctl |= SGTL5000_I2S_LRPOL;
498 case SND_SOC_DAIFMT_LEFT_J:
499 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ;
500 i2sctl |= SGTL5000_I2S_LRALIGN;
506 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
508 /* Clock inversion */
509 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
510 case SND_SOC_DAIFMT_NB_NF:
512 case SND_SOC_DAIFMT_IB_NF:
513 i2sctl |= SGTL5000_I2S_SCLK_INV;
519 snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
524 /* set codec sysclk */
525 static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
526 int clk_id, unsigned int freq, int dir)
528 struct snd_soc_codec *codec = codec_dai->codec;
529 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
532 case SGTL5000_SYSCLK:
533 sgtl5000->sysclk = freq;
543 * set clock according to i2s frame clock,
544 * sgtl5000 provides 2 clock sources:
545 * 1. sys_mclk: sample freq can only be configured to
546 * 1/256, 1/384, 1/512 of sys_mclk.
547 * 2. pll: can derive any audio clocks.
549 * clock setting rules:
550 * 1. in slave mode, only sys_mclk can be used
551 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
553 * 3. usage of sys_mclk is preferred over pll to save power.
555 static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
557 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
559 int sys_fs; /* sample freq */
562 * sample freq should be divided by frame clock,
563 * if frame clock is lower than 44.1 kHz, sample freq should be set to
564 * 32 kHz or 44.1 kHz.
566 switch (frame_rate) {
580 /* set divided factor of frame clock */
581 switch (sys_fs / frame_rate) {
583 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
586 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
589 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
595 /* set the sys_fs according to frame rate */
598 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
601 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
604 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
607 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
610 dev_err(codec->dev, "frame rate %d not supported\n",
616 * calculate the divider of mclk/sample_freq,
617 * factor of freq = 96 kHz can only be 256, since mclk is in the range
620 switch (sgtl5000->sysclk / sys_fs) {
622 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
623 SGTL5000_MCLK_FREQ_SHIFT;
626 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
627 SGTL5000_MCLK_FREQ_SHIFT;
630 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
631 SGTL5000_MCLK_FREQ_SHIFT;
634 /* if mclk does not satisfy the divider, use pll */
635 if (sgtl5000->master) {
636 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
637 SGTL5000_MCLK_FREQ_SHIFT;
640 "PLL not supported in slave mode\n");
641 dev_err(codec->dev, "%d ratio is not supported. "
642 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
643 sgtl5000->sysclk / sys_fs);
648 /* if using pll, please check manual 6.4.2 for detail */
649 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
653 unsigned int in, int_div, frac_div;
655 if (sgtl5000->sysclk > 17000000) {
657 in = sgtl5000->sysclk / 2;
660 in = sgtl5000->sysclk;
671 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
672 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
674 snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
676 snd_soc_update_bits(codec,
677 SGTL5000_CHIP_CLK_TOP_CTRL,
678 SGTL5000_INPUT_FREQ_DIV2,
679 SGTL5000_INPUT_FREQ_DIV2);
681 snd_soc_update_bits(codec,
682 SGTL5000_CHIP_CLK_TOP_CTRL,
683 SGTL5000_INPUT_FREQ_DIV2,
687 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
688 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
689 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
691 /* if using pll, clk_ctrl must be set after pll power up */
692 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
694 /* otherwise, clk_ctrl must be set before pll power down */
695 snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
698 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
699 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
707 * Set PCM DAI bit size and sample rate.
708 * input: params_rate, params_fmt
710 static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
711 struct snd_pcm_hw_params *params,
712 struct snd_soc_dai *dai)
714 struct snd_soc_codec *codec = dai->codec;
715 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
716 int channels = params_channels(params);
721 /* sysclk should already set */
722 if (!sgtl5000->sysclk) {
723 dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
727 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
728 stereo = SGTL5000_DAC_STEREO;
730 stereo = SGTL5000_ADC_STEREO;
732 /* set mono to save power */
733 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
734 channels == 1 ? 0 : stereo);
736 /* set codec clock base on lrclk */
737 ret = sgtl5000_set_clock(codec, params_rate(params));
741 /* set i2s data format */
742 switch (params_width(params)) {
744 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
746 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
747 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
748 SGTL5000_I2S_SCLKFREQ_SHIFT;
751 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
752 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
753 SGTL5000_I2S_SCLKFREQ_SHIFT;
756 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
757 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
758 SGTL5000_I2S_SCLKFREQ_SHIFT;
761 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
763 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
764 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
765 SGTL5000_I2S_SCLKFREQ_SHIFT;
771 snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
772 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
778 #ifdef CONFIG_REGULATOR
779 static int ldo_regulator_is_enabled(struct regulator_dev *dev)
781 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
786 static int ldo_regulator_enable(struct regulator_dev *dev)
788 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
789 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
792 if (ldo_regulator_is_enabled(dev))
795 /* set regulator value firstly */
796 reg = (1600 - ldo->voltage / 1000) / 50;
797 reg = clamp(reg, 0x0, 0xf);
799 /* amend the voltage value, unit: uV */
800 ldo->voltage = (1600 - reg * 50) * 1000;
802 /* set voltage to register */
803 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
804 SGTL5000_LINREG_VDDD_MASK, reg);
806 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
807 SGTL5000_LINEREG_D_POWERUP,
808 SGTL5000_LINEREG_D_POWERUP);
810 /* when internal ldo is enabled, simple digital power can be disabled */
811 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
812 SGTL5000_LINREG_SIMPLE_POWERUP,
819 static int ldo_regulator_disable(struct regulator_dev *dev)
821 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
822 struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
824 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
825 SGTL5000_LINEREG_D_POWERUP,
828 /* clear voltage info */
829 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
830 SGTL5000_LINREG_VDDD_MASK, 0);
837 static int ldo_regulator_get_voltage(struct regulator_dev *dev)
839 struct ldo_regulator *ldo = rdev_get_drvdata(dev);
844 static struct regulator_ops ldo_regulator_ops = {
845 .is_enabled = ldo_regulator_is_enabled,
846 .enable = ldo_regulator_enable,
847 .disable = ldo_regulator_disable,
848 .get_voltage = ldo_regulator_get_voltage,
851 static int ldo_regulator_register(struct snd_soc_codec *codec,
852 struct regulator_init_data *init_data,
855 struct ldo_regulator *ldo;
856 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
857 struct regulator_config config = { };
859 ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
864 ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
865 if (!ldo->desc.name) {
867 dev_err(codec->dev, "failed to allocate decs name memory\n");
871 ldo->desc.type = REGULATOR_VOLTAGE;
872 ldo->desc.owner = THIS_MODULE;
873 ldo->desc.ops = &ldo_regulator_ops;
874 ldo->desc.n_voltages = 1;
876 ldo->codec_data = codec;
877 ldo->voltage = voltage;
879 config.dev = codec->dev;
880 config.driver_data = ldo;
881 config.init_data = init_data;
883 ldo->dev = regulator_register(&ldo->desc, &config);
884 if (IS_ERR(ldo->dev)) {
885 int ret = PTR_ERR(ldo->dev);
887 dev_err(codec->dev, "failed to register regulator\n");
888 kfree(ldo->desc.name);
898 static int ldo_regulator_remove(struct snd_soc_codec *codec)
900 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
901 struct ldo_regulator *ldo = sgtl5000->ldo;
906 regulator_unregister(ldo->dev);
907 kfree(ldo->desc.name);
913 static int ldo_regulator_register(struct snd_soc_codec *codec,
914 struct regulator_init_data *init_data,
917 dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
921 static int ldo_regulator_remove(struct snd_soc_codec *codec)
929 * common state changes:
931 * off --> standby --> prepare --> on
932 * standby --> prepare --> on
935 * on --> prepare --> standby
937 static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
938 enum snd_soc_bias_level level)
941 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
944 case SND_SOC_BIAS_ON:
945 case SND_SOC_BIAS_PREPARE:
947 case SND_SOC_BIAS_STANDBY:
948 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
949 ret = regulator_bulk_enable(
950 ARRAY_SIZE(sgtl5000->supplies),
956 regcache_cache_only(sgtl5000->regmap, false);
958 ret = regcache_sync(sgtl5000->regmap);
961 "Failed to restore cache: %d\n", ret);
963 regcache_cache_only(sgtl5000->regmap, true);
964 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
972 case SND_SOC_BIAS_OFF:
973 regcache_cache_only(sgtl5000->regmap, true);
974 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
979 codec->dapm.bias_level = level;
983 #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
984 SNDRV_PCM_FMTBIT_S20_3LE |\
985 SNDRV_PCM_FMTBIT_S24_LE |\
986 SNDRV_PCM_FMTBIT_S32_LE)
988 static const struct snd_soc_dai_ops sgtl5000_ops = {
989 .hw_params = sgtl5000_pcm_hw_params,
990 .digital_mute = sgtl5000_digital_mute,
991 .set_fmt = sgtl5000_set_dai_fmt,
992 .set_sysclk = sgtl5000_set_dai_sysclk,
995 static struct snd_soc_dai_driver sgtl5000_dai = {
998 .stream_name = "Playback",
1002 * only support 8~48K + 96K,
1003 * TODO modify hw_param to support more
1005 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1006 .formats = SGTL5000_FORMATS,
1009 .stream_name = "Capture",
1012 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1013 .formats = SGTL5000_FORMATS,
1015 .ops = &sgtl5000_ops,
1016 .symmetric_rates = 1,
1019 static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
1022 case SGTL5000_CHIP_ID:
1023 case SGTL5000_CHIP_ADCDAC_CTRL:
1024 case SGTL5000_CHIP_ANA_STATUS:
1031 static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1034 case SGTL5000_CHIP_ID:
1035 case SGTL5000_CHIP_DIG_POWER:
1036 case SGTL5000_CHIP_CLK_CTRL:
1037 case SGTL5000_CHIP_I2S_CTRL:
1038 case SGTL5000_CHIP_SSS_CTRL:
1039 case SGTL5000_CHIP_ADCDAC_CTRL:
1040 case SGTL5000_CHIP_DAC_VOL:
1041 case SGTL5000_CHIP_PAD_STRENGTH:
1042 case SGTL5000_CHIP_ANA_ADC_CTRL:
1043 case SGTL5000_CHIP_ANA_HP_CTRL:
1044 case SGTL5000_CHIP_ANA_CTRL:
1045 case SGTL5000_CHIP_LINREG_CTRL:
1046 case SGTL5000_CHIP_REF_CTRL:
1047 case SGTL5000_CHIP_MIC_CTRL:
1048 case SGTL5000_CHIP_LINE_OUT_CTRL:
1049 case SGTL5000_CHIP_LINE_OUT_VOL:
1050 case SGTL5000_CHIP_ANA_POWER:
1051 case SGTL5000_CHIP_PLL_CTRL:
1052 case SGTL5000_CHIP_CLK_TOP_CTRL:
1053 case SGTL5000_CHIP_ANA_STATUS:
1054 case SGTL5000_CHIP_SHORT_CTRL:
1055 case SGTL5000_CHIP_ANA_TEST2:
1056 case SGTL5000_DAP_CTRL:
1057 case SGTL5000_DAP_PEQ:
1058 case SGTL5000_DAP_BASS_ENHANCE:
1059 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1060 case SGTL5000_DAP_AUDIO_EQ:
1061 case SGTL5000_DAP_SURROUND:
1062 case SGTL5000_DAP_FLT_COEF_ACCESS:
1063 case SGTL5000_DAP_COEF_WR_B0_MSB:
1064 case SGTL5000_DAP_COEF_WR_B0_LSB:
1065 case SGTL5000_DAP_EQ_BASS_BAND0:
1066 case SGTL5000_DAP_EQ_BASS_BAND1:
1067 case SGTL5000_DAP_EQ_BASS_BAND2:
1068 case SGTL5000_DAP_EQ_BASS_BAND3:
1069 case SGTL5000_DAP_EQ_BASS_BAND4:
1070 case SGTL5000_DAP_MAIN_CHAN:
1071 case SGTL5000_DAP_MIX_CHAN:
1072 case SGTL5000_DAP_AVC_CTRL:
1073 case SGTL5000_DAP_AVC_THRESHOLD:
1074 case SGTL5000_DAP_AVC_ATTACK:
1075 case SGTL5000_DAP_AVC_DECAY:
1076 case SGTL5000_DAP_COEF_WR_B1_MSB:
1077 case SGTL5000_DAP_COEF_WR_B1_LSB:
1078 case SGTL5000_DAP_COEF_WR_B2_MSB:
1079 case SGTL5000_DAP_COEF_WR_B2_LSB:
1080 case SGTL5000_DAP_COEF_WR_A1_MSB:
1081 case SGTL5000_DAP_COEF_WR_A1_LSB:
1082 case SGTL5000_DAP_COEF_WR_A2_MSB:
1083 case SGTL5000_DAP_COEF_WR_A2_LSB:
1092 * sgtl5000 has 3 internal power supplies:
1093 * 1. VAG, normally set to vdda/2
1094 * 2. charge pump, set to different value
1095 * according to voltage of vdda and vddio
1096 * 3. line out VAG, normally set to vddio/2
1098 * and should be set according to:
1099 * 1. vddd provided by external or not
1100 * 2. vdda and vddio voltage value. > 3.1v or not
1101 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1103 static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1111 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1113 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1114 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1115 vddd = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1118 vddio = vddio / 1000;
1121 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1122 dev_err(codec->dev, "regulator voltage not set correctly\n");
1127 /* according to datasheet, maximum voltage of supplies */
1128 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1130 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1137 ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1138 ana_pwr |= SGTL5000_DAC_STEREO |
1139 SGTL5000_ADC_STEREO |
1140 SGTL5000_REFTOP_POWERUP;
1141 lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1143 if (vddio < 3100 && vdda < 3100) {
1144 /* enable internal oscillator used for charge pump */
1145 snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1146 SGTL5000_INT_OSC_EN,
1147 SGTL5000_INT_OSC_EN);
1148 /* Enable VDDC charge pump */
1149 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1150 } else if (vddio >= 3100 && vdda >= 3100) {
1152 * if vddio and vddd > 3.1v,
1153 * charge pump should be clean before set ana_pwr
1155 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1156 SGTL5000_VDDC_CHRGPMP_POWERUP, 0);
1158 /* VDDC use VDDIO rail */
1159 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1160 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1161 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1164 snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1166 snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1168 /* set voltage to register */
1169 snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
1170 SGTL5000_LINREG_VDDD_MASK, 0x8);
1173 * if vddd linear reg has been enabled,
1174 * simple digital supply should be clear to get
1175 * proper VDDD voltage.
1177 if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1178 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1179 SGTL5000_LINREG_SIMPLE_POWERUP,
1182 snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1183 SGTL5000_LINREG_SIMPLE_POWERUP |
1184 SGTL5000_STARTUP_POWERUP,
1188 * set ADC/DAC VAG to vdda / 2,
1189 * should stay in range (0.8v, 1.575v)
1192 if (vag <= SGTL5000_ANA_GND_BASE)
1194 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1195 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1196 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1198 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1200 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1201 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1203 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1205 if (vag <= SGTL5000_LINE_OUT_GND_BASE)
1207 else if (vag >= SGTL5000_LINE_OUT_GND_BASE +
1208 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1209 vag = SGTL5000_LINE_OUT_GND_MAX;
1211 vag = (vag - SGTL5000_LINE_OUT_GND_BASE) /
1212 SGTL5000_LINE_OUT_GND_STP;
1214 snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1215 SGTL5000_LINE_OUT_CURRENT_MASK |
1216 SGTL5000_LINE_OUT_GND_MASK,
1217 vag << SGTL5000_LINE_OUT_GND_SHIFT |
1218 SGTL5000_LINE_OUT_CURRENT_360u <<
1219 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1224 static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1226 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1229 /* set internal ldo to 1.2v */
1230 ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1233 "Failed to register vddd internal supplies: %d\n", ret);
1237 sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1239 dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1243 static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1247 int external_vddd = 0;
1248 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1249 struct regulator *vddd;
1251 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1252 sgtl5000->supplies[i].supply = supply_names[i];
1254 /* External VDDD only works before revision 0x11 */
1255 if (sgtl5000->revision < 0x11) {
1256 vddd = regulator_get_optional(codec->dev, "VDDD");
1258 /* See if it's just not registered yet */
1259 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1260 return -EPROBE_DEFER;
1263 regulator_put(vddd);
1267 if (!external_vddd) {
1268 ret = sgtl5000_replace_vddd_with_ldo(codec);
1273 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1274 sgtl5000->supplies);
1276 goto err_ldo_remove;
1278 ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1279 sgtl5000->supplies);
1281 goto err_regulator_free;
1283 /* wait for all power rails bring up */
1289 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1290 sgtl5000->supplies);
1293 ldo_regulator_remove(codec);
1298 static int sgtl5000_probe(struct snd_soc_codec *codec)
1301 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1303 ret = sgtl5000_enable_regulators(codec);
1307 /* power up sgtl5000 */
1308 ret = sgtl5000_set_power_regs(codec);
1312 /* enable small pop, introduce 400ms delay in turning off */
1313 snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1315 SGTL5000_SMALL_POP);
1317 /* disable short cut detector */
1318 snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1321 * set i2s as default input of sound switch
1322 * TODO: add sound switch to control and dapm widge.
1324 snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1325 SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1326 snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1327 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1329 /* enable dac volume ramp by default */
1330 snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1331 SGTL5000_DAC_VOL_RAMP_EN |
1332 SGTL5000_DAC_MUTE_RIGHT |
1333 SGTL5000_DAC_MUTE_LEFT);
1335 snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1337 snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1338 SGTL5000_HP_ZCD_EN |
1339 SGTL5000_ADC_ZCD_EN);
1341 snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1342 SGTL5000_BIAS_R_MASK,
1343 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
1348 * Enable DAP in kcontrol and dapm.
1350 snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1355 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1356 sgtl5000->supplies);
1357 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1358 sgtl5000->supplies);
1359 ldo_regulator_remove(codec);
1364 static int sgtl5000_remove(struct snd_soc_codec *codec)
1366 struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1368 regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1369 sgtl5000->supplies);
1370 regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1371 sgtl5000->supplies);
1372 ldo_regulator_remove(codec);
1377 static struct snd_soc_codec_driver sgtl5000_driver = {
1378 .probe = sgtl5000_probe,
1379 .remove = sgtl5000_remove,
1380 .set_bias_level = sgtl5000_set_bias_level,
1381 .suspend_bias_off = true,
1382 .controls = sgtl5000_snd_controls,
1383 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1384 .dapm_widgets = sgtl5000_dapm_widgets,
1385 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1386 .dapm_routes = sgtl5000_dapm_routes,
1387 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1390 static const struct regmap_config sgtl5000_regmap = {
1395 .max_register = SGTL5000_MAX_REG_OFFSET,
1396 .volatile_reg = sgtl5000_volatile,
1397 .readable_reg = sgtl5000_readable,
1399 .cache_type = REGCACHE_RBTREE,
1400 .reg_defaults = sgtl5000_reg_defaults,
1401 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1405 * Write all the default values from sgtl5000_reg_defaults[] array into the
1406 * sgtl5000 registers, to make sure we always start with the sane registers
1407 * values as stated in the datasheet.
1409 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1410 * we follow this approach to guarantee we always start from the default values
1411 * and avoid problems like, not being able to probe after an audio playback
1412 * followed by a system reset or a 'reboot' command in Linux
1414 static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000)
1416 int i, ret, val, index;
1418 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1419 val = sgtl5000_reg_defaults[i].def;
1420 index = sgtl5000_reg_defaults[i].reg;
1421 ret = regmap_write(sgtl5000->regmap, index, val);
1429 static int sgtl5000_i2c_probe(struct i2c_client *client,
1430 const struct i2c_device_id *id)
1432 struct sgtl5000_priv *sgtl5000;
1435 struct device_node *np = client->dev.of_node;
1438 sgtl5000 = devm_kzalloc(&client->dev, sizeof(struct sgtl5000_priv),
1443 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1444 if (IS_ERR(sgtl5000->regmap)) {
1445 ret = PTR_ERR(sgtl5000->regmap);
1446 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1450 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1451 if (IS_ERR(sgtl5000->mclk)) {
1452 ret = PTR_ERR(sgtl5000->mclk);
1453 dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
1454 /* Defer the probe to see if the clk will be provided later */
1456 return -EPROBE_DEFER;
1460 /* SGTL5000 SYS_MCLK should be between 8 and 27 MHz */
1461 mclk = clk_get_rate(sgtl5000->mclk);
1462 if (mclk < 8000000 || mclk > 27000000) {
1463 dev_err(&client->dev, "Invalid SYS_CLK frequency: %u.%03uMHz\n",
1464 mclk / 1000000, mclk / 1000 % 1000);
1468 ret = clk_prepare_enable(sgtl5000->mclk);
1472 /* read chip information */
1473 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®);
1477 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1478 SGTL5000_PARTID_PART_ID) {
1479 dev_err(&client->dev,
1480 "Device with ID register %x is not a sgtl5000\n", reg);
1485 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1486 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1487 sgtl5000->revision = rev;
1490 if (!of_property_read_u32(np,
1491 "micbias-resistor-k-ohms", &value)) {
1493 case SGTL5000_MICBIAS_OFF:
1494 sgtl5000->micbias_resistor = 0;
1496 case SGTL5000_MICBIAS_2K:
1497 sgtl5000->micbias_resistor = 1;
1499 case SGTL5000_MICBIAS_4K:
1500 sgtl5000->micbias_resistor = 2;
1502 case SGTL5000_MICBIAS_8K:
1503 sgtl5000->micbias_resistor = 3;
1506 sgtl5000->micbias_resistor = 2;
1507 dev_err(&client->dev,
1508 "Unsuitable MicBias resistor\n");
1511 /* default is 4Kohms */
1512 sgtl5000->micbias_resistor = 2;
1514 dev_err(&client->dev,
1515 "Unsuitable MicBias resistor\n");
1521 i2c_set_clientdata(client, sgtl5000);
1523 /* Ensure sgtl5000 will start with sane register values */
1524 ret = sgtl5000_fill_defaults(sgtl5000);
1528 ret = snd_soc_register_codec(&client->dev,
1529 &sgtl5000_driver, &sgtl5000_dai, 1);
1536 clk_disable_unprepare(sgtl5000->mclk);
1540 static int sgtl5000_i2c_remove(struct i2c_client *client)
1542 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1544 snd_soc_unregister_codec(&client->dev);
1545 clk_disable_unprepare(sgtl5000->mclk);
1549 static const struct i2c_device_id sgtl5000_id[] = {
1554 MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1556 static const struct of_device_id sgtl5000_dt_ids[] = {
1557 { .compatible = "fsl,sgtl5000", },
1560 MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1562 static struct i2c_driver sgtl5000_i2c_driver = {
1565 .owner = THIS_MODULE,
1566 .of_match_table = sgtl5000_dt_ids,
1568 .probe = sgtl5000_i2c_probe,
1569 .remove = sgtl5000_i2c_remove,
1570 .id_table = sgtl5000_id,
1573 module_i2c_driver(sgtl5000_i2c_driver);
1575 MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1576 MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1577 MODULE_LICENSE("GPL");