2 * ALSA SoC TLV320AIC31XX codec driver
4 * Copyright (C) 2014 Texas Instruments, Inc.
6 * Author: Jyri Sarha <jsarha@ti.com>
8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
10 * This package is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * THIS PACKAGE IS PROVIDED AS IS AND WITHOUT ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
18 * The TLV320AIC31xx series of audio codec is a low-power, highly integrated
19 * high performance codec which provides a stereo DAC, a mono ADC,
20 * and mono/stereo Class-D speaker driver.
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
28 #include <linux/i2c.h>
29 #include <linux/gpio.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/acpi.h>
33 #include <linux/of_gpio.h>
34 #include <linux/slab.h>
35 #include <sound/core.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/soc.h>
39 #include <sound/initval.h>
40 #include <sound/tlv.h>
41 #include <dt-bindings/sound/tlv320aic31xx-micbias.h>
43 #include "tlv320aic31xx.h"
45 static const struct reg_default aic31xx_reg_defaults[] = {
46 { AIC31XX_CLKMUX, 0x00 },
47 { AIC31XX_PLLPR, 0x11 },
48 { AIC31XX_PLLJ, 0x04 },
49 { AIC31XX_PLLDMSB, 0x00 },
50 { AIC31XX_PLLDLSB, 0x00 },
51 { AIC31XX_NDAC, 0x01 },
52 { AIC31XX_MDAC, 0x01 },
53 { AIC31XX_DOSRMSB, 0x00 },
54 { AIC31XX_DOSRLSB, 0x80 },
55 { AIC31XX_NADC, 0x01 },
56 { AIC31XX_MADC, 0x01 },
57 { AIC31XX_AOSR, 0x80 },
58 { AIC31XX_IFACE1, 0x00 },
59 { AIC31XX_DATA_OFFSET, 0x00 },
60 { AIC31XX_IFACE2, 0x00 },
61 { AIC31XX_BCLKN, 0x01 },
62 { AIC31XX_DACSETUP, 0x14 },
63 { AIC31XX_DACMUTE, 0x0c },
64 { AIC31XX_LDACVOL, 0x00 },
65 { AIC31XX_RDACVOL, 0x00 },
66 { AIC31XX_ADCSETUP, 0x00 },
67 { AIC31XX_ADCFGA, 0x80 },
68 { AIC31XX_ADCVOL, 0x00 },
69 { AIC31XX_HPDRIVER, 0x04 },
70 { AIC31XX_SPKAMP, 0x06 },
71 { AIC31XX_DACMIXERROUTE, 0x00 },
72 { AIC31XX_LANALOGHPL, 0x7f },
73 { AIC31XX_RANALOGHPR, 0x7f },
74 { AIC31XX_LANALOGSPL, 0x7f },
75 { AIC31XX_RANALOGSPR, 0x7f },
76 { AIC31XX_HPLGAIN, 0x02 },
77 { AIC31XX_HPRGAIN, 0x02 },
78 { AIC31XX_SPLGAIN, 0x00 },
79 { AIC31XX_SPRGAIN, 0x00 },
80 { AIC31XX_MICBIAS, 0x00 },
81 { AIC31XX_MICPGA, 0x80 },
82 { AIC31XX_MICPGAPI, 0x00 },
83 { AIC31XX_MICPGAMI, 0x00 },
86 static bool aic31xx_volatile(struct device *dev, unsigned int reg)
89 case AIC31XX_PAGECTL: /* regmap implementation requires this */
90 case AIC31XX_RESET: /* always clears after write */
93 case AIC31XX_DACFLAG1:
94 case AIC31XX_DACFLAG2:
95 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
96 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
97 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
98 case AIC31XX_INTRDACFLAG2:
99 case AIC31XX_INTRADCFLAG2:
105 static bool aic31xx_writeable(struct device *dev, unsigned int reg)
108 case AIC31XX_OT_FLAG:
109 case AIC31XX_ADCFLAG:
110 case AIC31XX_DACFLAG1:
111 case AIC31XX_DACFLAG2:
112 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
113 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
114 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
115 case AIC31XX_INTRDACFLAG2:
116 case AIC31XX_INTRADCFLAG2:
122 static const struct regmap_range_cfg aic31xx_ranges[] = {
125 .range_max = 12 * 128,
126 .selector_reg = AIC31XX_PAGECTL,
127 .selector_mask = 0xff,
134 static const struct regmap_config aic31xx_i2c_regmap = {
137 .writeable_reg = aic31xx_writeable,
138 .volatile_reg = aic31xx_volatile,
139 .reg_defaults = aic31xx_reg_defaults,
140 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),
141 .cache_type = REGCACHE_RBTREE,
142 .ranges = aic31xx_ranges,
143 .num_ranges = ARRAY_SIZE(aic31xx_ranges),
144 .max_register = 12 * 128,
147 #define AIC31XX_NUM_SUPPLIES 6
148 static const char * const aic31xx_supply_names[AIC31XX_NUM_SUPPLIES] = {
157 struct aic31xx_disable_nb {
158 struct notifier_block nb;
159 struct aic31xx_priv *aic31xx;
162 struct aic31xx_priv {
163 struct snd_soc_codec *codec;
166 struct regmap *regmap;
167 struct aic31xx_pdata pdata;
168 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
169 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
175 struct aic31xx_rate_divs {
188 /* ADC dividers can be disabled by cofiguring them to 0 */
189 static const struct aic31xx_rate_divs aic31xx_divs[] = {
190 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */
192 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2},
193 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3},
194 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2},
196 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2},
197 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3},
198 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2},
200 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2},
201 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3},
202 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2},
204 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2},
205 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3},
206 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2},
208 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2},
209 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3},
210 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2},
212 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2},
213 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3},
214 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2},
216 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2},
217 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4},
218 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2},
220 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2},
221 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3},
222 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2},
224 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2},
225 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4},
226 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2},
228 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2},
229 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3},
230 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2},
232 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2},
233 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4},
234 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2},
237 static const char * const ldac_in_text[] = {
238 "Off", "Left Data", "Right Data", "Mono"
241 static const char * const rdac_in_text[] = {
242 "Off", "Right Data", "Left Data", "Mono"
245 static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);
247 static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);
249 static const char * const mic_select_text[] = {
250 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
253 static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,
255 static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,
257 static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
260 static SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text);
261 static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
264 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
265 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
266 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
267 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
268 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
269 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
270 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
271 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
274 * controls to be exported to the user space
276 static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
277 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,
278 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
280 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,
283 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),
284 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,
285 0, -24, 40, 6, 0, adc_cgain_tlv),
287 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
288 119, 0, mic_pga_tlv),
290 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,
291 AIC31XX_HPRGAIN, 2, 1, 0),
292 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,
293 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
295 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
296 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
299 static const struct snd_kcontrol_new aic311x_snd_controls[] = {
300 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
301 AIC31XX_SPRGAIN, 2, 1, 0),
302 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
303 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
305 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
306 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
309 static const struct snd_kcontrol_new aic310x_snd_controls[] = {
310 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
312 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
313 3, 3, 0, class_D_drv_tlv),
315 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
316 0, 0x7F, 1, sp_vol_tlv),
319 static const struct snd_kcontrol_new ldac_in_control =
320 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);
322 static const struct snd_kcontrol_new rdac_in_control =
323 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);
325 static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,
326 unsigned int mask, unsigned int wbits, int sleep,
331 int ret = regmap_read(aic31xx->regmap, reg, &bits);
333 while ((bits & mask) != wbits && counter && !ret) {
334 usleep_range(sleep, sleep * 2);
335 ret = regmap_read(aic31xx->regmap, reg, &bits);
338 if ((bits & mask) != wbits) {
339 dev_err(aic31xx->dev,
340 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
341 __func__, reg, bits, wbits, ret, mask,
342 (count - counter) * sleep);
348 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
350 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
351 struct snd_kcontrol *kcontrol, int event)
353 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
354 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
355 unsigned int reg = AIC31XX_DACFLAG1;
358 switch (WIDGET_BIT(w->reg, w->shift)) {
359 case WIDGET_BIT(AIC31XX_DACSETUP, 7):
360 mask = AIC31XX_LDACPWRSTATUS_MASK;
362 case WIDGET_BIT(AIC31XX_DACSETUP, 6):
363 mask = AIC31XX_RDACPWRSTATUS_MASK;
365 case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
366 mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
368 case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
369 mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
371 case WIDGET_BIT(AIC31XX_SPKAMP, 7):
372 mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
374 case WIDGET_BIT(AIC31XX_SPKAMP, 6):
375 mask = AIC31XX_SPRDRVPWRSTATUS_MASK;
377 case WIDGET_BIT(AIC31XX_ADCSETUP, 7):
378 mask = AIC31XX_ADCPWRSTATUS_MASK;
379 reg = AIC31XX_ADCFLAG;
382 dev_err(codec->dev, "Unknown widget '%s' calling %s\n",
388 case SND_SOC_DAPM_POST_PMU:
389 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100);
390 case SND_SOC_DAPM_POST_PMD:
391 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100);
394 "Unhandled dapm widget event %d from %s\n",
400 static const struct snd_kcontrol_new left_output_switches[] = {
401 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
402 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
403 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
406 static const struct snd_kcontrol_new right_output_switches[] = {
407 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
408 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
411 static const struct snd_kcontrol_new p_term_mic1lp =
412 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
414 static const struct snd_kcontrol_new p_term_mic1rp =
415 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
417 static const struct snd_kcontrol_new p_term_mic1lm =
418 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
420 static const struct snd_kcontrol_new m_term_mic1lm =
421 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
423 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =
424 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
426 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =
427 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
429 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =
430 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
432 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =
433 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
435 static int mic_bias_event(struct snd_soc_dapm_widget *w,
436 struct snd_kcontrol *kcontrol, int event)
438 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
439 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
442 case SND_SOC_DAPM_POST_PMU:
443 /* change mic bias voltage to user defined */
444 snd_soc_update_bits(codec, AIC31XX_MICBIAS,
445 AIC31XX_MICBIAS_MASK,
446 aic31xx->pdata.micbias_vg <<
447 AIC31XX_MICBIAS_SHIFT);
448 dev_dbg(codec->dev, "%s: turned on\n", __func__);
450 case SND_SOC_DAPM_PRE_PMD:
451 /* turn mic bias off */
452 snd_soc_update_bits(codec, AIC31XX_MICBIAS,
453 AIC31XX_MICBIAS_MASK, 0);
454 dev_dbg(codec->dev, "%s: turned off\n", __func__);
460 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
461 SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0),
463 SND_SOC_DAPM_MUX("DAC Left Input",
464 SND_SOC_NOPM, 0, 0, &ldac_in_control),
465 SND_SOC_DAPM_MUX("DAC Right Input",
466 SND_SOC_NOPM, 0, 0, &rdac_in_control),
468 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
469 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
470 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
472 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
473 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
474 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
477 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
478 left_output_switches,
479 ARRAY_SIZE(left_output_switches)),
480 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
481 right_output_switches,
482 ARRAY_SIZE(right_output_switches)),
484 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
485 &aic31xx_dapm_hpl_switch),
486 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
487 &aic31xx_dapm_hpr_switch),
490 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
491 NULL, 0, aic31xx_dapm_power_event,
492 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
493 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
494 NULL, 0, aic31xx_dapm_power_event,
495 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
498 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
499 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
500 SND_SOC_DAPM_POST_PMD),
502 /* Input Selection to MIC_PGA */
503 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
505 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
507 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
510 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
512 /* Enabling & Disabling MIC Gain Ctl */
513 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,
517 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
518 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
521 SND_SOC_DAPM_OUTPUT("HPL"),
522 SND_SOC_DAPM_OUTPUT("HPR"),
525 SND_SOC_DAPM_INPUT("MIC1LP"),
526 SND_SOC_DAPM_INPUT("MIC1RP"),
527 SND_SOC_DAPM_INPUT("MIC1LM"),
530 static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {
531 /* AIC3111 and AIC3110 have stereo class-D amplifier */
532 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
533 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
534 SND_SOC_DAPM_POST_PMD),
535 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
536 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
537 SND_SOC_DAPM_POST_PMD),
538 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
539 &aic31xx_dapm_spl_switch),
540 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
541 &aic31xx_dapm_spr_switch),
542 SND_SOC_DAPM_OUTPUT("SPL"),
543 SND_SOC_DAPM_OUTPUT("SPR"),
546 /* AIC3100 and AIC3120 have only mono class-D amplifier */
547 static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {
548 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
549 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
550 SND_SOC_DAPM_POST_PMD),
551 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
552 &aic31xx_dapm_spl_switch),
553 SND_SOC_DAPM_OUTPUT("SPK"),
556 static const struct snd_soc_dapm_route
557 aic31xx_audio_map[] = {
558 /* DAC Input Routing */
559 {"DAC Left Input", "Left Data", "DAC IN"},
560 {"DAC Left Input", "Right Data", "DAC IN"},
561 {"DAC Left Input", "Mono", "DAC IN"},
562 {"DAC Right Input", "Left Data", "DAC IN"},
563 {"DAC Right Input", "Right Data", "DAC IN"},
564 {"DAC Right Input", "Mono", "DAC IN"},
565 {"DAC Left", NULL, "DAC Left Input"},
566 {"DAC Right", NULL, "DAC Right Input"},
569 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
570 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
571 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
572 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
573 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
574 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
575 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
576 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
577 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
579 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
580 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
581 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
583 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
584 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
585 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
586 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
588 {"ADC", NULL, "MIC_GAIN_CTL"},
591 {"Output Left", "From Left DAC", "DAC Left"},
592 {"Output Left", "From MIC1LP", "MIC1LP"},
593 {"Output Left", "From MIC1RP", "MIC1RP"},
596 {"Output Right", "From Right DAC", "DAC Right"},
597 {"Output Right", "From MIC1RP", "MIC1RP"},
600 {"HP Left", "Switch", "Output Left"},
601 {"HPL Driver", NULL, "HP Left"},
602 {"HPL", NULL, "HPL Driver"},
605 {"HP Right", "Switch", "Output Right"},
606 {"HPR Driver", NULL, "HP Right"},
607 {"HPR", NULL, "HPR Driver"},
610 static const struct snd_soc_dapm_route
611 aic311x_audio_map[] = {
613 {"Speaker Left", "Switch", "Output Left"},
614 {"SPL ClassD", NULL, "Speaker Left"},
615 {"SPL", NULL, "SPL ClassD"},
618 {"Speaker Right", "Switch", "Output Right"},
619 {"SPR ClassD", NULL, "Speaker Right"},
620 {"SPR", NULL, "SPR ClassD"},
623 static const struct snd_soc_dapm_route
624 aic310x_audio_map[] = {
626 {"Speaker", "Switch", "Output Left"},
627 {"SPK ClassD", NULL, "Speaker"},
628 {"SPK", NULL, "SPK ClassD"},
631 static int aic31xx_add_controls(struct snd_soc_codec *codec)
634 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
636 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT)
637 ret = snd_soc_add_codec_controls(
638 codec, aic311x_snd_controls,
639 ARRAY_SIZE(aic311x_snd_controls));
641 ret = snd_soc_add_codec_controls(
642 codec, aic310x_snd_controls,
643 ARRAY_SIZE(aic310x_snd_controls));
648 static int aic31xx_add_widgets(struct snd_soc_codec *codec)
650 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
651 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
654 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
655 ret = snd_soc_dapm_new_controls(
656 dapm, aic311x_dapm_widgets,
657 ARRAY_SIZE(aic311x_dapm_widgets));
661 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
662 ARRAY_SIZE(aic311x_audio_map));
666 ret = snd_soc_dapm_new_controls(
667 dapm, aic310x_dapm_widgets,
668 ARRAY_SIZE(aic310x_dapm_widgets));
672 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
673 ARRAY_SIZE(aic310x_audio_map));
681 static int aic31xx_setup_pll(struct snd_soc_codec *codec,
682 struct snd_pcm_hw_params *params)
684 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
685 int bclk_score = snd_soc_params_to_frame_size(params);
686 int mclk_p = aic31xx->sysclk / aic31xx->p_div;
691 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
692 snd_soc_update_bits(codec, AIC31XX_CLKMUX,
693 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
694 snd_soc_update_bits(codec, AIC31XX_IFACE2,
695 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
697 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
698 if (aic31xx_divs[i].rate == params_rate(params) &&
699 aic31xx_divs[i].mclk_p == mclk_p) {
700 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
701 snd_soc_params_to_frame_size(params);
702 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
703 snd_soc_params_to_frame_size(params);
704 if (s < bclk_score && bn > 0) {
714 "%s: Sample rate (%u) and format not supported\n",
715 __func__, params_rate(params));
716 /* See bellow for details how fix this. */
719 if (bclk_score != 0) {
720 dev_warn(codec->dev, "Can not produce exact bitclock");
721 /* This is fine if using dsp format, but if using i2s
722 there may be trouble. To fix the issue edit the
723 aic31xx_divs table for your mclk and sample
724 rate. Details can be found from:
725 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
726 Section: 5.6 CLOCK Generation and PLL
731 /* PLL configuration */
732 snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
733 (aic31xx->p_div << 4) | 0x01);
734 snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
736 snd_soc_write(codec, AIC31XX_PLLDMSB,
737 aic31xx_divs[i].pll_d >> 8);
738 snd_soc_write(codec, AIC31XX_PLLDLSB,
739 aic31xx_divs[i].pll_d & 0xff);
741 /* DAC dividers configuration */
742 snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK,
743 aic31xx_divs[i].ndac);
744 snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK,
745 aic31xx_divs[i].mdac);
747 snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
748 snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
750 /* ADC dividers configuration. Write reset value 1 if not used. */
751 snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK,
752 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
753 snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK,
754 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
756 snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr);
758 /* Bit clock divider configuration. */
759 snd_soc_update_bits(codec, AIC31XX_BCLKN,
760 AIC31XX_PLL_MASK, bclk_n);
762 aic31xx->rate_div_line = i;
765 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
766 aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d,
767 aic31xx->p_div, aic31xx_divs[i].dosr,
768 aic31xx_divs[i].ndac, aic31xx_divs[i].mdac,
769 aic31xx_divs[i].aosr, aic31xx_divs[i].nadc,
770 aic31xx_divs[i].madc, bclk_n);
775 static int aic31xx_hw_params(struct snd_pcm_substream *substream,
776 struct snd_pcm_hw_params *params,
777 struct snd_soc_dai *dai)
779 struct snd_soc_codec *codec = dai->codec;
782 dev_dbg(codec->dev, "## %s: width %d rate %d\n",
783 __func__, params_width(params),
784 params_rate(params));
786 switch (params_width(params)) {
790 data = (AIC31XX_WORD_LEN_20BITS <<
791 AIC31XX_IFACE1_DATALEN_SHIFT);
794 data = (AIC31XX_WORD_LEN_24BITS <<
795 AIC31XX_IFACE1_DATALEN_SHIFT);
798 data = (AIC31XX_WORD_LEN_32BITS <<
799 AIC31XX_IFACE1_DATALEN_SHIFT);
802 dev_err(codec->dev, "%s: Unsupported width %d\n",
803 __func__, params_width(params));
807 snd_soc_update_bits(codec, AIC31XX_IFACE1,
808 AIC31XX_IFACE1_DATALEN_MASK,
811 return aic31xx_setup_pll(codec, params);
814 static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute)
816 struct snd_soc_codec *codec = codec_dai->codec;
819 snd_soc_update_bits(codec, AIC31XX_DACMUTE,
820 AIC31XX_DACMUTE_MASK,
821 AIC31XX_DACMUTE_MASK);
823 snd_soc_update_bits(codec, AIC31XX_DACMUTE,
824 AIC31XX_DACMUTE_MASK, 0x0);
830 static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
833 struct snd_soc_codec *codec = codec_dai->codec;
838 dev_dbg(codec->dev, "## %s: fmt = 0x%x\n", __func__, fmt);
840 /* set master/slave audio interface */
841 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
842 case SND_SOC_DAIFMT_CBM_CFM:
843 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;
846 dev_alert(codec->dev, "Invalid DAI master/slave interface\n");
850 /* interface format */
851 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
852 case SND_SOC_DAIFMT_I2S:
854 case SND_SOC_DAIFMT_DSP_A:
856 case SND_SOC_DAIFMT_DSP_B:
857 /* NOTE: BCLKINV bit value 1 equas NB and 0 equals IB */
858 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
859 case SND_SOC_DAIFMT_NB_NF:
860 iface_reg2 |= AIC31XX_BCLKINV_MASK;
862 case SND_SOC_DAIFMT_IB_NF:
867 iface_reg1 |= (AIC31XX_DSP_MODE <<
868 AIC31XX_IFACE1_DATATYPE_SHIFT);
870 case SND_SOC_DAIFMT_RIGHT_J:
871 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<
872 AIC31XX_IFACE1_DATATYPE_SHIFT);
874 case SND_SOC_DAIFMT_LEFT_J:
875 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<
876 AIC31XX_IFACE1_DATATYPE_SHIFT);
879 dev_err(codec->dev, "Invalid DAI interface format\n");
883 snd_soc_update_bits(codec, AIC31XX_IFACE1,
884 AIC31XX_IFACE1_DATATYPE_MASK |
885 AIC31XX_IFACE1_MASTER_MASK,
887 snd_soc_update_bits(codec, AIC31XX_DATA_OFFSET,
888 AIC31XX_DATA_OFFSET_MASK,
890 snd_soc_update_bits(codec, AIC31XX_IFACE2,
891 AIC31XX_BCLKINV_MASK,
897 static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
898 int clk_id, unsigned int freq, int dir)
900 struct snd_soc_codec *codec = codec_dai->codec;
901 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
904 dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
905 __func__, clk_id, freq, dir);
907 for (i = 1; freq/i > 20000000 && i < 8; i++)
909 if (freq/i > 20000000) {
910 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
916 for (i = 0; i < ARRAY_SIZE(aic31xx_divs) &&
917 aic31xx_divs[i].mclk_p != freq/aic31xx->p_div; i++)
919 if (i == ARRAY_SIZE(aic31xx_divs)) {
920 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
925 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */
926 snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
927 clk_id << AIC31XX_PLL_CLKIN_SHIFT);
929 aic31xx->sysclk = freq;
933 static int aic31xx_regulator_event(struct notifier_block *nb,
934 unsigned long event, void *data)
936 struct aic31xx_disable_nb *disable_nb =
937 container_of(nb, struct aic31xx_disable_nb, nb);
938 struct aic31xx_priv *aic31xx = disable_nb->aic31xx;
940 if (event & REGULATOR_EVENT_DISABLE) {
942 * Put codec to reset and as at least one of the
943 * supplies was disabled.
945 if (gpio_is_valid(aic31xx->pdata.gpio_reset))
946 gpio_set_value(aic31xx->pdata.gpio_reset, 0);
948 regcache_mark_dirty(aic31xx->regmap);
949 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);
955 static void aic31xx_clk_on(struct snd_soc_codec *codec)
957 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
958 u8 mask = AIC31XX_PM_MASK;
959 u8 on = AIC31XX_PM_MASK;
961 dev_dbg(codec->dev, "codec clock -> on (rate %d)\n",
962 aic31xx_divs[aic31xx->rate_div_line].rate);
963 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, on);
965 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, on);
966 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, on);
967 if (aic31xx_divs[aic31xx->rate_div_line].nadc)
968 snd_soc_update_bits(codec, AIC31XX_NADC, mask, on);
969 if (aic31xx_divs[aic31xx->rate_div_line].madc)
970 snd_soc_update_bits(codec, AIC31XX_MADC, mask, on);
971 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, on);
974 static void aic31xx_clk_off(struct snd_soc_codec *codec)
976 u8 mask = AIC31XX_PM_MASK;
979 dev_dbg(codec->dev, "codec clock -> off\n");
980 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, off);
981 snd_soc_update_bits(codec, AIC31XX_MADC, mask, off);
982 snd_soc_update_bits(codec, AIC31XX_NADC, mask, off);
983 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, off);
984 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, off);
985 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, off);
988 static int aic31xx_power_on(struct snd_soc_codec *codec)
990 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
993 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
998 if (gpio_is_valid(aic31xx->pdata.gpio_reset)) {
999 gpio_set_value(aic31xx->pdata.gpio_reset, 1);
1002 regcache_cache_only(aic31xx->regmap, false);
1003 ret = regcache_sync(aic31xx->regmap);
1006 "Failed to restore cache: %d\n", ret);
1007 regcache_cache_only(aic31xx->regmap, true);
1008 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1015 static int aic31xx_power_off(struct snd_soc_codec *codec)
1017 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1020 regcache_cache_only(aic31xx->regmap, true);
1021 ret = regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1027 static int aic31xx_set_bias_level(struct snd_soc_codec *codec,
1028 enum snd_soc_bias_level level)
1030 dev_dbg(codec->dev, "## %s: %d -> %d\n", __func__,
1031 snd_soc_codec_get_bias_level(codec), level);
1034 case SND_SOC_BIAS_ON:
1036 case SND_SOC_BIAS_PREPARE:
1037 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY)
1038 aic31xx_clk_on(codec);
1040 case SND_SOC_BIAS_STANDBY:
1041 switch (snd_soc_codec_get_bias_level(codec)) {
1042 case SND_SOC_BIAS_OFF:
1043 aic31xx_power_on(codec);
1045 case SND_SOC_BIAS_PREPARE:
1046 aic31xx_clk_off(codec);
1052 case SND_SOC_BIAS_OFF:
1053 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY)
1054 aic31xx_power_off(codec);
1061 static int aic31xx_codec_probe(struct snd_soc_codec *codec)
1064 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1067 dev_dbg(aic31xx->dev, "## %s\n", __func__);
1069 aic31xx = snd_soc_codec_get_drvdata(codec);
1071 aic31xx->codec = codec;
1073 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {
1074 aic31xx->disable_nb[i].nb.notifier_call =
1075 aic31xx_regulator_event;
1076 aic31xx->disable_nb[i].aic31xx = aic31xx;
1077 ret = regulator_register_notifier(aic31xx->supplies[i].consumer,
1078 &aic31xx->disable_nb[i].nb);
1081 "Failed to request regulator notifier: %d\n",
1087 regcache_cache_only(aic31xx->regmap, true);
1088 regcache_mark_dirty(aic31xx->regmap);
1090 ret = aic31xx_add_controls(codec);
1094 ret = aic31xx_add_widgets(codec);
1099 static int aic31xx_codec_remove(struct snd_soc_codec *codec)
1101 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1104 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1105 regulator_unregister_notifier(aic31xx->supplies[i].consumer,
1106 &aic31xx->disable_nb[i].nb);
1111 static struct snd_soc_codec_driver soc_codec_driver_aic31xx = {
1112 .probe = aic31xx_codec_probe,
1113 .remove = aic31xx_codec_remove,
1114 .set_bias_level = aic31xx_set_bias_level,
1115 .suspend_bias_off = true,
1117 .component_driver = {
1118 .controls = aic31xx_snd_controls,
1119 .num_controls = ARRAY_SIZE(aic31xx_snd_controls),
1120 .dapm_widgets = aic31xx_dapm_widgets,
1121 .num_dapm_widgets = ARRAY_SIZE(aic31xx_dapm_widgets),
1122 .dapm_routes = aic31xx_audio_map,
1123 .num_dapm_routes = ARRAY_SIZE(aic31xx_audio_map),
1127 static const struct snd_soc_dai_ops aic31xx_dai_ops = {
1128 .hw_params = aic31xx_hw_params,
1129 .set_sysclk = aic31xx_set_dai_sysclk,
1130 .set_fmt = aic31xx_set_dai_fmt,
1131 .digital_mute = aic31xx_dac_mute,
1134 static struct snd_soc_dai_driver aic31xx_dai_driver[] = {
1136 .name = "tlv320aic31xx-hifi",
1138 .stream_name = "Playback",
1141 .rates = AIC31XX_RATES,
1142 .formats = AIC31XX_FORMATS,
1145 .stream_name = "Capture",
1148 .rates = AIC31XX_RATES,
1149 .formats = AIC31XX_FORMATS,
1151 .ops = &aic31xx_dai_ops,
1152 .symmetric_rates = 1,
1156 #if defined(CONFIG_OF)
1157 static const struct of_device_id tlv320aic31xx_of_match[] = {
1158 { .compatible = "ti,tlv320aic310x" },
1159 { .compatible = "ti,tlv320aic311x" },
1160 { .compatible = "ti,tlv320aic3100" },
1161 { .compatible = "ti,tlv320aic3110" },
1162 { .compatible = "ti,tlv320aic3120" },
1163 { .compatible = "ti,tlv320aic3111" },
1166 MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
1168 static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
1170 struct device_node *np = aic31xx->dev->of_node;
1171 unsigned int value = MICBIAS_2_0V;
1174 of_property_read_u32(np, "ai31xx-micbias-vg", &value);
1179 aic31xx->pdata.micbias_vg = value;
1182 dev_err(aic31xx->dev,
1183 "Bad ai31xx-micbias-vg value %d DT\n",
1185 aic31xx->pdata.micbias_vg = MICBIAS_2_0V;
1188 ret = of_get_named_gpio(np, "gpio-reset", 0);
1190 aic31xx->pdata.gpio_reset = ret;
1192 #else /* CONFIG_OF */
1193 static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
1196 #endif /* CONFIG_OF */
1198 static int aic31xx_device_init(struct aic31xx_priv *aic31xx)
1202 dev_set_drvdata(aic31xx->dev, aic31xx);
1204 if (dev_get_platdata(aic31xx->dev))
1205 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev),
1206 sizeof(aic31xx->pdata));
1207 else if (aic31xx->dev->of_node)
1208 aic31xx_pdata_from_of(aic31xx);
1210 if (aic31xx->pdata.gpio_reset) {
1211 ret = devm_gpio_request_one(aic31xx->dev,
1212 aic31xx->pdata.gpio_reset,
1213 GPIOF_OUT_INIT_HIGH,
1214 "aic31xx-reset-pin");
1216 dev_err(aic31xx->dev, "not able to acquire gpio\n");
1221 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1222 aic31xx->supplies[i].supply = aic31xx_supply_names[i];
1224 ret = devm_regulator_bulk_get(aic31xx->dev,
1225 ARRAY_SIZE(aic31xx->supplies),
1228 dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret);
1233 static int aic31xx_i2c_probe(struct i2c_client *i2c,
1234 const struct i2c_device_id *id)
1236 struct aic31xx_priv *aic31xx;
1238 const struct regmap_config *regmap_config;
1240 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,
1241 id->name, (int) id->driver_data);
1243 regmap_config = &aic31xx_i2c_regmap;
1245 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);
1246 if (aic31xx == NULL)
1249 aic31xx->regmap = devm_regmap_init_i2c(i2c, regmap_config);
1250 if (IS_ERR(aic31xx->regmap)) {
1251 ret = PTR_ERR(aic31xx->regmap);
1252 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1256 aic31xx->dev = &i2c->dev;
1258 aic31xx->pdata.codec_type = id->driver_data;
1260 ret = aic31xx_device_init(aic31xx);
1264 return snd_soc_register_codec(&i2c->dev, &soc_codec_driver_aic31xx,
1266 ARRAY_SIZE(aic31xx_dai_driver));
1269 static int aic31xx_i2c_remove(struct i2c_client *i2c)
1271 snd_soc_unregister_codec(&i2c->dev);
1275 static const struct i2c_device_id aic31xx_i2c_id[] = {
1276 { "tlv320aic310x", AIC3100 },
1277 { "tlv320aic311x", AIC3110 },
1278 { "tlv320aic3100", AIC3100 },
1279 { "tlv320aic3110", AIC3110 },
1280 { "tlv320aic3120", AIC3120 },
1281 { "tlv320aic3111", AIC3111 },
1284 MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
1287 static const struct acpi_device_id aic31xx_acpi_match[] = {
1291 MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match);
1294 static struct i2c_driver aic31xx_i2c_driver = {
1296 .name = "tlv320aic31xx-codec",
1297 .of_match_table = of_match_ptr(tlv320aic31xx_of_match),
1298 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match),
1300 .probe = aic31xx_i2c_probe,
1301 .remove = aic31xx_i2c_remove,
1302 .id_table = aic31xx_i2c_id,
1305 module_i2c_driver(aic31xx_i2c_driver);
1307 MODULE_DESCRIPTION("ASoC TLV320AIC3111 codec driver");
1308 MODULE_AUTHOR("Jyri Sarha");
1309 MODULE_LICENSE("GPL");